GitHub actions: disable-at-0 fix; man page cosmetics

- the CI/CD workflow did not defined the TBW_GHDL_OPTS environment variable,
  as consequence VHDL IEEE package warnings at t=0ms were not suppressed and
  polluted the log files
- that problem was already in .travis.yml and was carried over to ci.yml
- now fixed, and log files are not cluttered anymore with essentially
  unavoidable but harmless warnings at t=0ms.

doc/CHANGELOG.md

@@ -30,6 +30,7 @@ The full set of tests is only run for tagged releases.
 ### New features
 ### Changes
 - tools changes
+  - ci.yml: define TBW_GHDL_OPTS and suppress IEEE package warnings at t=0ms
   - **/tbrun.yml: since nexys4 not longer available switch to nexys4d
 ### Bug Fixes
 

doc/README_buildsystem_ISE.md

@@ -236,11 +236,13 @@ the FPGA. For detailed documentation see the respective man pages.
 ### <a id="artix">Note on Artix-7 based designs</a>
 
 The development for Nexys4 started in 2013 with ISE but moved to Vivado when
-it matured in 2015. The make files for the ISE build flows have been kept for
-comparison are have the name `Makefile.ise`. So for some Nexys4 designs one can
-still start with a 
+it matured 2014. The make files for the ISE build flows have been kept for
+comparison are have the name `Makefile.ise`. So for some Nexys4 designs one
+can still start with a 
 
-    make -f Makefile.ise  <target>
+      make -f Makefile.ise  <target>
+    or
+      makeise <target>
 
 an ISE based build. To be used for tool comparisons, the ISE generated bit 
 files were never tested in an FPGA.

doc/README_buildsystem_Vivado.md

@@ -274,7 +274,7 @@ only one board must connected.
 ### <a id="ise">Note on ISE</a>
 
 The development for Nexys4 started in 2013 with ISE but moved to Vivado when
-it matured in 2015. The make files for the ISE build flows have been kept for
+it matured in 2014. The make files for the ISE build flows have been kept for
 comparison are have the name `Makefile.ise`. So for some Nexys4 designs one
 can still start with a