diff --git a/doc/CHANGELOG.md b/doc/CHANGELOG.md index cf295ec7..95ea8f99 100644 --- a/doc/CHANGELOG.md +++ b/doc/CHANGELOG.md @@ -54,6 +54,7 @@ The full set of tests is only run for tagged releases. - pdp11_dmpcnt: an array of 32 counters of 32 bit width - connected to 24 signals from inside pdp11_sys70 and 8 signals from outside - dmpcntanal: analysis script +- add s7_cmt_1ce1ce: clock generator block used in many 7-Series designs - add new disk scheme ram: (with Rw11VirtDiskRam) - implements a ram-only-disk - generates create_disk compatible test patterns @@ -81,9 +82,14 @@ The full set of tests is only run for tagged releases. - use in {dcm,s6_cmt,s7_cmt}_sfs_gsim simulation models - use in rtl/bplib/*/tb/tb_* test benches - remove s7_cmt_sfs_tb +- tbcore_rlink: wait 40 cycles after CONF_DONE +- serport_master_tb: add 100 ps RXSD,TXSD delay to allow clock jitter - tools changes - xviv_msg_filter: display INFO Common 17-14 'further message disabled' + - tbrun: add --all option - viv_tools_build.tcl: increase message limits (all 200, some 5000) +- tbench changes: + - tst_sram: don't test memory controller reset anymore - backend changes - RtclRw11Unit: fix for clang: M_virt() now public - Rw11VirtDisk: keep track of disk geometry diff --git a/rtl/bplib/bpgen/bpgenlib.vhd b/rtl/bplib/bpgen/bpgenlib.vhd index d60dd34e..4661247b 100644 --- a/rtl/bplib/bpgen/bpgenlib.vhd +++ b/rtl/bplib/bpgen/bpgenlib.vhd @@ -1,4 +1,4 @@ --- $Id: bpgenlib.vhd 1038 2018-08-11 12:39:52Z mueller $ +-- $Id: bpgenlib.vhd 1086 2018-12-16 18:29:55Z mueller $ -- -- Copyright 2011-2018 by Walter F.J. Mueller -- @@ -19,6 +19,7 @@ -- Tool versions: ise 12.1-14.7; viv 2014.4-2018.2; ghdl 0.26-0.34 -- Revision History: -- Date Rev Version Comment +-- 2018-12-16 1086 1.2.3 add s7_cmt_1ce1ce -- 2018-08-11 1038 1.2.2 add rgbdrv_3x2mux -- 2017-06-05 907 1.2.1 rgbdrv_analog: add ACTLOW generic -- 2016-02-27 737 1.2 add rgbdrv entity @@ -253,4 +254,73 @@ component rgbdrv_3x2mux is -- rgbled driver: mux three 2bit inputs ); end component; +component s7_cmt_1ce1ce is -- clocking block: 2 clk+CEs + generic ( + CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns) + CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps) + STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED + CLK0_VCODIV : positive := 1; -- clk0: vco clock divide + CLK0_VCOMUL : positive := 1; -- clk0: vco clock multiply + CLK0_OUTDIV : positive := 1; -- clk0: output divide + CLK0_GENTYPE : string := "PLL"; -- clk0: PLL or MMCM + CLK0_CDUWIDTH : positive := 7; -- clk0: usec clock divider width + CLK0_USECDIV : positive := 50; -- clk0: divider ratio for usec pulse + CLK0_MSECDIV : positive := 1000; -- clk0: divider ratio for msec pulse + CLK1_VCODIV : positive := 1; -- clk1: vco clock divide + CLK1_VCOMUL : positive := 1; -- clk1: vco clock multiply + CLK1_OUTDIV : positive := 1; -- clk1: output divide + CLK1_GENTYPE : string := "MMCM"; -- clk1: PLL or MMCM + CLK1_CDUWIDTH : positive := 7; -- clk1: usec clock divider width + CLK1_USECDIV : positive := 50; -- clk1: divider ratio for usec pulse + CLK1_MSECDIV : positive := 1000); -- clk1: divider ratio for msec pulse + port ( + CLKIN : in slbit; -- clock input + CLK0 : out slbit; -- clk0: clock output + CE0_USEC : out slbit; -- clk0: usec pulse + CE0_MSEC : out slbit; -- clk0: msec pulse + CLK1 : out slbit; -- clk1: clock output + CE1_USEC : out slbit; -- clk1: usec pulse + CE1_MSEC : out slbit; -- clk1: msec pulse + LOCKED : out slbit -- all PLL/MMCM locked + ); +end component; + +component s7_cmt_1ce1ce2c is -- clocking block: 2 clk+CEs; 2 clk + generic ( + CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns) + CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps) + STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED + CLK0_VCODIV : positive := 1; -- clk0: vco clock divide + CLK0_VCOMUL : positive := 1; -- clk0: vco clock multiply + CLK0_OUTDIV : positive := 1; -- clk0: output divide + CLK0_GENTYPE : string := "PLL"; -- clk0: PLL or MMCM + CLK0_CDUWIDTH : positive := 7; -- clk0: usec clock divider width + CLK0_USECDIV : positive := 50; -- clk0: divider ratio for usec pulse + CLK0_MSECDIV : positive := 1000; -- clk0: divider ratio for msec pulse + CLK1_VCODIV : positive := 1; -- clk1: vco clock divide + CLK1_VCOMUL : positive := 1; -- clk1: vco clock multiply + CLK1_OUTDIV : positive := 1; -- clk1: output divide + CLK1_GENTYPE : string := "MMCM"; -- clk1: PLL or MMCM + CLK1_CDUWIDTH : positive := 7; -- clk1: usec clock divider width + CLK1_USECDIV : positive := 50; -- clk1: divider ratio for usec pulse + CLK1_MSECDIV : positive := 1000; -- clk1: divider ratio for msec pulse + CLK23_VCODIV : positive := 1; -- clk2+3: vco clock divide + CLK23_VCOMUL : positive := 1; -- clk2+3: vco clock multiply + CLK2_OUTDIV : positive := 1; -- clk2: output divide + CLK3_OUTDIV : positive := 1; -- clk3: output divide + CLK23_GENTYPE : string := "PLL"); -- clk2+3: PLL or MMCM + port ( + CLKIN : in slbit; -- clock input + CLK0 : out slbit; -- clk0: clock output + CE0_USEC : out slbit; -- clk0: usec pulse + CE0_MSEC : out slbit; -- clk0: msec pulse + CLK1 : out slbit; -- clk1: clock output + CE1_USEC : out slbit; -- clk1: usec pulse + CE1_MSEC : out slbit; -- clk1: msec pulse + CLK2 : out slbit; -- clk2: clock output + CLK3 : out slbit; -- clk3: clock output + LOCKED : out slbit -- all PLL/MMCM locked + ); +end component; + end package bpgenlib; diff --git a/rtl/bplib/bpgen/s7_cmt_1ce1ce.vbom b/rtl/bplib/bpgen/s7_cmt_1ce1ce.vbom new file mode 100644 index 00000000..c6294bdd --- /dev/null +++ b/rtl/bplib/bpgen/s7_cmt_1ce1ce.vbom @@ -0,0 +1,8 @@ +# libs +../../vlib/slvtypes.vhd +# components +[vsyn]../../vlib/xlib/s7_cmt_sfs_unisim.vbom +[ghdl,vsim]../../vlib/xlib/s7_cmt_sfs_gsim.vbom +../../vlib/genlib/clkdivce.vbom +# design +s7_cmt_1ce1ce.vhd diff --git a/rtl/bplib/bpgen/s7_cmt_1ce1ce.vhd b/rtl/bplib/bpgen/s7_cmt_1ce1ce.vhd new file mode 100644 index 00000000..3e9529ce --- /dev/null +++ b/rtl/bplib/bpgen/s7_cmt_1ce1ce.vhd @@ -0,0 +1,132 @@ +-- $Id: s7_cmt_1ce1ce.vhd 1086 2018-12-16 18:29:55Z mueller $ +-- +-- Copyright 2018- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 3, or (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: s7_cmt_1ce1ce - syn +-- Description: clocking block for 7-Series: 2 clk with CEs +-- +-- Dependencies: s7_cmt_sfs +-- clkdivce +-- Test bench: - +-- Target Devices: generic 7-Series +-- Tool versions: viv 2017.2; ghdl 0.34 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2018-12-16 1086 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.genlib.all; + +entity s7_cmt_1ce1ce is -- clocking block: 2 clk with CEs + generic ( + CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns) + CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps) + STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED + CLK0_VCODIV : positive := 1; -- clk0: vco clock divide + CLK0_VCOMUL : positive := 1; -- clk0: vco clock multiply + CLK0_OUTDIV : positive := 1; -- clk0: output divide + CLK0_GENTYPE : string := "PLL"; -- clk0: PLL or MMCM + CLK0_CDUWIDTH : positive := 7; -- clk0: usec clock divider width + CLK0_USECDIV : positive := 50; -- clk0: divider ratio for usec pulse + CLK0_MSECDIV : positive := 1000; -- clk0: divider ratio for msec pulse + CLK1_VCODIV : positive := 1; -- clk1: vco clock divide + CLK1_VCOMUL : positive := 1; -- clk1: vco clock multiply + CLK1_OUTDIV : positive := 1; -- clk1: output divide + CLK1_GENTYPE : string := "MMCM"; -- clk1: PLL or MMCM + CLK1_CDUWIDTH : positive := 7; -- clk1: usec clock divider width + CLK1_USECDIV : positive := 50; -- clk1: divider ratio for usec pulse + CLK1_MSECDIV : positive := 1000); -- clk1: divider ratio for msec pulse + port ( + CLKIN : in slbit; -- clock input + CLK0 : out slbit; -- clk0: clock output + CE0_USEC : out slbit; -- clk0: usec pulse + CE0_MSEC : out slbit; -- clk0: msec pulse + CLK1 : out slbit; -- clk1: clock output + CE1_USEC : out slbit; -- clk1: usec pulse + CE1_MSEC : out slbit; -- clk1: msec pulse + LOCKED : out slbit -- all PLL/MMCM locked + ); +end s7_cmt_1ce1ce; + +architecture syn of s7_cmt_1ce1ce is + + signal CLK0_L : slbit := '0'; + signal CLK1_L : slbit := '0'; + signal LOCKED0 : slbit := '0'; + signal LOCKED1 : slbit := '0'; + +begin + + GEN_CLK0 : s7_cmt_sfs -- clock generator 0 ----------------- + generic map ( + VCO_DIVIDE => CLK0_VCODIV, + VCO_MULTIPLY => CLK0_VCOMUL, + OUT_DIVIDE => CLK0_OUTDIV, + CLKIN_PERIOD => CLKIN_PERIOD, + CLKIN_JITTER => CLKIN_JITTER, + STARTUP_WAIT => STARTUP_WAIT, + GEN_TYPE => CLK0_GENTYPE) + port map ( + CLKIN => CLKIN, + CLKFX => CLK0_L, + LOCKED => LOCKED0 + ); + + DIV_CLK0 : clkdivce -- usec/msec clock divider 0 --------- + generic map ( + CDUWIDTH => CLK0_CDUWIDTH, + USECDIV => CLK0_USECDIV, + MSECDIV => CLK0_MSECDIV) + port map ( + CLK => CLK0_L, + CE_USEC => CE0_USEC, + CE_MSEC => CE0_MSEC + ); + + GEN_CLK1 : s7_cmt_sfs -- clock generator serport------------ + generic map ( + VCO_DIVIDE => CLK1_VCODIV, + VCO_MULTIPLY => CLK1_VCOMUL, + OUT_DIVIDE => CLK1_OUTDIV, + CLKIN_PERIOD => CLKIN_PERIOD, + CLKIN_JITTER => CLKIN_JITTER, + STARTUP_WAIT => STARTUP_WAIT, + GEN_TYPE => CLK1_GENTYPE) + port map ( + CLKIN => CLKIN, + CLKFX => CLK1_L, + LOCKED => LOCKED1 + ); + + DIV_CLK1 : clkdivce -- usec/msec clock divider 1 --------- + generic map ( + CDUWIDTH => CLK1_CDUWIDTH, + USECDIV => CLK1_USECDIV, + MSECDIV => CLK1_MSECDIV) + port map ( + CLK => CLK1_L, + CE_USEC => CE1_USEC, + CE_MSEC => CE1_MSEC + ); + + CLK0 <= CLK0_L; + CLK1 <= CLK1_L; + LOCKED <= LOCKED0 and LOCKED1; + +end syn; diff --git a/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop2_n4.vbom b/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop2_n4.vbom index 610a0bc8..5b9e0769 100644 --- a/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop2_n4.vbom +++ b/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop2_n4.vbom @@ -1,15 +1,12 @@ # libs ../../../vlib/slvtypes.vhd -../../../vlib/xlib/xlib.vhd ../../../vlib/genlib/genlib.vhd ../../../bplib/bpgen/bpgenlib.vbom ../tst_serlooplib.vbom ../../../vlib/serport/serportlib.vbom ${sys_conf := sys_conf2.vhd} # components -[vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom -[ghdl,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom -../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/s7_cmt_1ce1ce.vbom ../../../bplib/bpgen/bp_rs232_4line_iob.vbom ../../../bplib/bpgen/sn_humanio.vbom ../tst_serloop_hiomap.vbom diff --git a/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop2_n4.vhd b/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop2_n4.vhd index 13c3cabb..e869e6e9 100644 --- a/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop2_n4.vhd +++ b/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop2_n4.vhd @@ -1,6 +1,6 @@ --- $Id: sys_tst_serloop2_n4.vhd 984 2018-01-02 20:56:27Z mueller $ +-- $Id: sys_tst_serloop2_n4.vhd 1086 2018-12-16 18:29:55Z mueller $ -- --- Copyright 2016- by Walter F.J. Mueller +-- Copyright 2016-2018 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -12,11 +12,10 @@ -- for complete details. -- ------------------------------------------------------------------------------ --- Module Name: sys_tst_serloop1_n4 - syn --- Description: Tester serial link for nexys4 (serport_1clock case) +-- Module Name: sys_tst_serloop2_n4 - syn +-- Description: Tester serial link for nexys4 (serport_2clock case) -- --- Dependencies: vlib/xlib/s7_cmt_sfs --- vlib/genlib/clkdivce +-- Dependencies: bplib/bpgen/s7_cmt_1ce1ce -- bpgen/bp_rs232_4line_iob -- bpgen/sn_humanio -- tst_serloop_hiomap @@ -26,7 +25,7 @@ -- Test bench: - -- -- Target Devices: generic --- Tool versions: viv 2014.4-2015.4; ghdl 0.31-0.33 +-- Tool versions: viv 2014.4-2018.2; ghdl 0.31-0.34 -- -- Synthesized: -- Date Rev viv Target flop lutl lutm bram slic @@ -34,6 +33,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2018-12-16 1086 1.1 use s7_cmt_1ce1ce -- 2016-06-05 722 1.0.1 use CDUWIDTH=7 for CLKS, 120 MHz is natural choice -- 2015-02-01 641 1.0 Initial version (derived from sys_tst_serloop1_n4) ------------------------------------------------------------------------------ @@ -44,7 +44,6 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.slvtypes.all; -use work.xlib.all; use work.genlib.all; use work.bpgenlib.all; use work.tst_serlooplib.all; @@ -108,56 +107,34 @@ architecture syn of sys_tst_serloop2_n4 is begin - GEN_CLKSYS : s7_cmt_sfs -- clock generator system ------------ + GEN_CLKALL : s7_cmt_1ce1ce -- clock generator system ------------ generic map ( - VCO_DIVIDE => sys_conf_clksys_vcodivide, - VCO_MULTIPLY => sys_conf_clksys_vcomultiply, - OUT_DIVIDE => sys_conf_clksys_outdivide, CLKIN_PERIOD => 10.0, CLKIN_JITTER => 0.01, STARTUP_WAIT => false, - GEN_TYPE => sys_conf_clksys_gentype) + CLK0_VCODIV => sys_conf_clksys_vcodivide, + CLK0_VCOMUL => sys_conf_clksys_vcomultiply, + CLK0_OUTDIV => sys_conf_clksys_outdivide, + CLK0_GENTYPE => sys_conf_clksys_gentype, + CLK0_CDUWIDTH => 8, + CLK0_USECDIV => sys_conf_clksys_mhz, + CLK0_MSECDIV => sys_conf_clksys_msecdiv, + CLK1_VCODIV => sys_conf_clkser_vcodivide, + CLK1_VCOMUL => sys_conf_clkser_vcomultiply, + CLK1_OUTDIV => sys_conf_clkser_outdivide, + CLK1_GENTYPE => sys_conf_clkser_gentype, + CLK1_CDUWIDTH => 7, + CLK1_USECDIV => sys_conf_clkser_mhz, + CLK1_MSECDIV => sys_conf_clkser_msecdiv) port map ( - CLKIN => I_CLK100, - CLKFX => CLK, - LOCKED => open - ); - - CLKDIV_CLK : clkdivce - generic map ( - CDUWIDTH => 8, - USECDIV => sys_conf_clksys_mhz, - MSECDIV => sys_conf_clksys_msecdiv) - port map ( - CLK => CLK, - CE_USEC => open, - CE_MSEC => CE_MSEC - ); - - GEN_CLKSER : s7_cmt_sfs -- clock generator serport ----------- - generic map ( - VCO_DIVIDE => sys_conf_clkser_vcodivide, - VCO_MULTIPLY => sys_conf_clkser_vcomultiply, - OUT_DIVIDE => sys_conf_clkser_outdivide, - CLKIN_PERIOD => 10.0, - CLKIN_JITTER => 0.01, - STARTUP_WAIT => false, - GEN_TYPE => sys_conf_clkser_gentype) - port map ( - CLKIN => I_CLK100, - CLKFX => CLKS, - LOCKED => open - ); - - CLKDIV_CLKS : clkdivce - generic map ( - CDUWIDTH => 7, -- good up to 127 MHz - USECDIV => sys_conf_clkser_mhz, - MSECDIV => sys_conf_clkser_msecdiv) - port map ( - CLK => CLKS, - CE_USEC => open, - CE_MSEC => CES_MSEC + CLKIN => I_CLK100, + CLK0 => CLK, + CE0_USEC => CE_USEC, + CE0_MSEC => CE_MSEC, + CLK1 => CLKS, + CE1_USEC => open, + CE1_MSEC => CES_MSEC, + LOCKED => open ); HIO : sn_humanio diff --git a/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop2_n4d.vbom b/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop2_n4d.vbom index 24e4ae91..55267e03 100644 --- a/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop2_n4d.vbom +++ b/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop2_n4d.vbom @@ -1,15 +1,12 @@ # libs ../../../vlib/slvtypes.vhd -../../../vlib/xlib/xlib.vhd ../../../vlib/genlib/genlib.vhd ../../../bplib/bpgen/bpgenlib.vbom ../tst_serlooplib.vbom ../../../vlib/serport/serportlib.vbom ${sys_conf := sys_conf2.vhd} # components -[vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom -[ghdl,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom -../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/s7_cmt_1ce1ce.vbom ../../../bplib/bpgen/bp_rs232_4line_iob.vbom ../../../bplib/bpgen/sn_humanio.vbom ../tst_serloop_hiomap.vbom diff --git a/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop2_n4d.vhd b/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop2_n4d.vhd index 20a5340c..b0cdf085 100644 --- a/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop2_n4d.vhd +++ b/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop2_n4d.vhd @@ -1,6 +1,6 @@ --- $Id: sys_tst_serloop2_n4d.vhd 984 2018-01-02 20:56:27Z mueller $ +-- $Id: sys_tst_serloop2_n4d.vhd 1086 2018-12-16 18:29:55Z mueller $ -- --- Copyright 2017- by Walter F.J. Mueller +-- Copyright 2017-2018 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -12,11 +12,10 @@ -- for complete details. -- ------------------------------------------------------------------------------ --- Module Name: sys_tst_serloop1_n4d - syn --- Description: Tester serial link for nexys4d (serport_1clock case) +-- Module Name: sys_tst_serloop2_n4d - syn +-- Description: Tester serial link for nexys4d (serport_2clock case) -- --- Dependencies: vlib/xlib/s7_cmt_sfs --- vlib/genlib/clkdivce +-- Dependencies: bplib/bpgen/s7_cmt_1ce1ce -- bpgen/bp_rs232_4line_iob -- bpgen/sn_humanio -- tst_serloop_hiomap @@ -34,6 +33,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2018-12-16 1086 1.1 use s7_cmt_1ce1ce -- 2017-01-04 838 1.0 Initial version (derived from sys_tst_serloop2_n4) ------------------------------------------------------------------------------ -- @@ -43,7 +43,6 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.slvtypes.all; -use work.xlib.all; use work.genlib.all; use work.bpgenlib.all; use work.tst_serlooplib.all; @@ -107,56 +106,34 @@ architecture syn of sys_tst_serloop2_n4d is begin - GEN_CLKSYS : s7_cmt_sfs -- clock generator system ------------ + GEN_CLKALL : s7_cmt_1ce1ce -- clock generator system ------------ generic map ( - VCO_DIVIDE => sys_conf_clksys_vcodivide, - VCO_MULTIPLY => sys_conf_clksys_vcomultiply, - OUT_DIVIDE => sys_conf_clksys_outdivide, CLKIN_PERIOD => 10.0, CLKIN_JITTER => 0.01, STARTUP_WAIT => false, - GEN_TYPE => sys_conf_clksys_gentype) + CLK0_VCODIV => sys_conf_clksys_vcodivide, + CLK0_VCOMUL => sys_conf_clksys_vcomultiply, + CLK0_OUTDIV => sys_conf_clksys_outdivide, + CLK0_GENTYPE => sys_conf_clksys_gentype, + CLK0_CDUWIDTH => 8, + CLK0_USECDIV => sys_conf_clksys_mhz, + CLK0_MSECDIV => sys_conf_clksys_msecdiv, + CLK1_VCODIV => sys_conf_clkser_vcodivide, + CLK1_VCOMUL => sys_conf_clkser_vcomultiply, + CLK1_OUTDIV => sys_conf_clkser_outdivide, + CLK1_GENTYPE => sys_conf_clkser_gentype, + CLK1_CDUWIDTH => 7, + CLK1_USECDIV => sys_conf_clkser_mhz, + CLK1_MSECDIV => sys_conf_clkser_msecdiv) port map ( - CLKIN => I_CLK100, - CLKFX => CLK, - LOCKED => open - ); - - CLKDIV_CLK : clkdivce - generic map ( - CDUWIDTH => 8, - USECDIV => sys_conf_clksys_mhz, - MSECDIV => sys_conf_clksys_msecdiv) - port map ( - CLK => CLK, - CE_USEC => open, - CE_MSEC => CE_MSEC - ); - - GEN_CLKSER : s7_cmt_sfs -- clock generator serport ----------- - generic map ( - VCO_DIVIDE => sys_conf_clkser_vcodivide, - VCO_MULTIPLY => sys_conf_clkser_vcomultiply, - OUT_DIVIDE => sys_conf_clkser_outdivide, - CLKIN_PERIOD => 10.0, - CLKIN_JITTER => 0.01, - STARTUP_WAIT => false, - GEN_TYPE => sys_conf_clkser_gentype) - port map ( - CLKIN => I_CLK100, - CLKFX => CLKS, - LOCKED => open - ); - - CLKDIV_CLKS : clkdivce - generic map ( - CDUWIDTH => 7, -- good up to 127 MHz - USECDIV => sys_conf_clkser_mhz, - MSECDIV => sys_conf_clkser_msecdiv) - port map ( - CLK => CLKS, - CE_USEC => open, - CE_MSEC => CES_MSEC + CLKIN => I_CLK100, + CLK0 => CLK, + CE0_USEC => CE_USEC, + CE0_MSEC => CE_MSEC, + CLK1 => CLKS, + CE1_USEC => open, + CE1_MSEC => CES_MSEC, + LOCKED => open ); HIO : sn_humanio diff --git a/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vbom b/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vbom index d0411d39..f66c4244 100644 --- a/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vbom +++ b/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vbom @@ -1,6 +1,5 @@ # libs ../../../vlib/slvtypes.vhd -../../../vlib/xlib/xlib.vhd ../../../vlib/genlib/genlib.vhd ../../../vlib/serport/serportlib.vbom ../../../vlib/rbus/rblib.vhd @@ -12,9 +11,7 @@ ../../../bplib/cmoda7/cmoda7lib.vhd ${sys_conf := sys_conf.vhd} # components -[vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom -[ghdl,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom -../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/s7_cmt_1ce1ce.vbom ../../../bplib/bpgen/bp_rs232_2line_iob.vbom ../../../vlib/rlink/rlink_sp2c.vbom ../tst_sram.vbom diff --git a/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd b/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd index 087359e2..635923b7 100644 --- a/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd +++ b/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd @@ -1,6 +1,6 @@ --- $Id: sys_tst_sram_c7.vhd 984 2018-01-02 20:56:27Z mueller $ +-- $Id: sys_tst_sram_c7.vhd 1086 2018-12-16 18:29:55Z mueller $ -- --- Copyright 2017- by Walter F.J. Mueller +-- Copyright 2017-2018 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -15,8 +15,7 @@ -- Module Name: sys_tst_sram_c7 - syn -- Description: test of cmoda7 sram and its controller -- --- Dependencies: vlib/xlib/s7_cmt_sfs --- vlib/genlib/clkdivce +-- Dependencies: bplib/bpgen/s7_cmt_1ce1ce -- bplib/bpgen/bp_rs232_2line_iob -- vlib/rlink/rlink_sp2c -- tst_sram @@ -29,7 +28,7 @@ -- Test bench: tb/tb_tst_sram_c7 -- -- Target Devices: generic --- Tool versions: viv 2017.1; ghdl 0.34 +-- Tool versions: viv 2017.1-2018.2; ghdl 0.34 -- -- Synthesized (viv): -- Date Rev viv Target flop lutl lutm bram slic @@ -37,6 +36,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2018-12-16 1086 1.1 use s7_cmt_1ce1ce -- 2017-06-11 914 1.0 Initial version -- 2017-06-11 912 0.5 First draft (derived from sys_tst_sram_n4) ------------------------------------------------------------------------------ @@ -135,56 +135,34 @@ architecture syn of sys_tst_sram_c7 is begin - GEN_CLKSYS : s7_cmt_sfs -- clock generator system ------------ + GEN_CLKALL : s7_cmt_1ce1ce -- clock generator system ------------ generic map ( - VCO_DIVIDE => sys_conf_clksys_vcodivide, - VCO_MULTIPLY => sys_conf_clksys_vcomultiply, - OUT_DIVIDE => sys_conf_clksys_outdivide, CLKIN_PERIOD => 83.3, CLKIN_JITTER => 0.01, STARTUP_WAIT => false, - GEN_TYPE => sys_conf_clksys_gentype) + CLK0_VCODIV => sys_conf_clksys_vcodivide, + CLK0_VCOMUL => sys_conf_clksys_vcomultiply, + CLK0_OUTDIV => sys_conf_clksys_outdivide, + CLK0_GENTYPE => sys_conf_clksys_gentype, + CLK0_CDUWIDTH => 7, + CLK0_USECDIV => sys_conf_clksys_mhz, + CLK0_MSECDIV => 1000, + CLK1_VCODIV => sys_conf_clkser_vcodivide, + CLK1_VCOMUL => sys_conf_clkser_vcomultiply, + CLK1_OUTDIV => sys_conf_clkser_outdivide, + CLK1_GENTYPE => sys_conf_clkser_gentype, + CLK1_CDUWIDTH => 7, + CLK1_USECDIV => sys_conf_clkser_mhz, + CLK1_MSECDIV => 1000) port map ( - CLKIN => I_CLK12, - CLKFX => CLK, - LOCKED => open - ); - - CLKDIV_CLK : clkdivce -- usec/msec clock divider system ---- - generic map ( - CDUWIDTH => 7, -- good for up to 127 MHz ! - USECDIV => sys_conf_clksys_mhz, - MSECDIV => 1000) - port map ( - CLK => CLK, - CE_USEC => CE_USEC, - CE_MSEC => CE_MSEC - ); - - GEN_CLKSER : s7_cmt_sfs -- clock generator serport------------ - generic map ( - VCO_DIVIDE => sys_conf_clkser_vcodivide, - VCO_MULTIPLY => sys_conf_clkser_vcomultiply, - OUT_DIVIDE => sys_conf_clkser_outdivide, - CLKIN_PERIOD => 83.3, - CLKIN_JITTER => 0.01, - STARTUP_WAIT => false, - GEN_TYPE => sys_conf_clkser_gentype) - port map ( - CLKIN => I_CLK12, - CLKFX => CLKS, - LOCKED => open - ); - - CLKDIV_CLKS : clkdivce -- usec/msec clock divider serport --- - generic map ( - CDUWIDTH => 7, - USECDIV => sys_conf_clkser_mhz, - MSECDIV => 1000) - port map ( - CLK => CLKS, - CE_USEC => open, - CE_MSEC => CES_MSEC + CLKIN => I_CLK12, + CLK0 => CLK, + CE0_USEC => CE_USEC, + CE0_MSEC => CE_MSEC, + CLK1 => CLKS, + CE1_USEC => open, + CE1_MSEC => CES_MSEC, + LOCKED => open ); IOB_RS232 : bp_rs232_2line_iob diff --git a/rtl/sys_gen/tst_sram/nexys4/sys_tst_sram_n4.vbom b/rtl/sys_gen/tst_sram/nexys4/sys_tst_sram_n4.vbom index 919d87bb..a5f2ba17 100644 --- a/rtl/sys_gen/tst_sram/nexys4/sys_tst_sram_n4.vbom +++ b/rtl/sys_gen/tst_sram/nexys4/sys_tst_sram_n4.vbom @@ -1,6 +1,5 @@ # libs ../../../vlib/slvtypes.vhd -../../../vlib/xlib/xlib.vhd ../../../vlib/genlib/genlib.vhd ../../../vlib/serport/serportlib.vbom ../../../vlib/rbus/rblib.vhd @@ -12,9 +11,7 @@ ../../../bplib/nxcramlib/nxcramlib.vhd ${sys_conf := sys_conf.vbom} # components -[vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom -[ghdl,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom -../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/s7_cmt_1ce1ce.vbom ../../../bplib/bpgen/bp_rs232_4line_iob.vbom ../../../bplib/bpgen/sn_humanio.vbom ../../../vlib/rlink/rlink_sp2c.vbom diff --git a/rtl/sys_gen/tst_sram/nexys4/sys_tst_sram_n4.vhd b/rtl/sys_gen/tst_sram/nexys4/sys_tst_sram_n4.vhd index 0d837677..d5a88436 100644 --- a/rtl/sys_gen/tst_sram/nexys4/sys_tst_sram_n4.vhd +++ b/rtl/sys_gen/tst_sram/nexys4/sys_tst_sram_n4.vhd @@ -1,6 +1,6 @@ --- $Id: sys_tst_sram_n4.vhd 1073 2018-11-23 18:05:51Z mueller $ +-- $Id: sys_tst_sram_n4.vhd 1086 2018-12-16 18:29:55Z mueller $ -- --- Copyright 2013-2017 by Walter F.J. Mueller +-- Copyright 2013-2018 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -15,8 +15,7 @@ -- Module Name: sys_tst_sram_n4 - syn -- Description: test of nexys4 sram and its controller -- --- Dependencies: vlib/xlib/s7_cmt_sfs --- vlib/genlib/clkdivce +-- Dependencies: bplib/bpgen/s7_cmt_1ce1ce -- bplib/bpgen/bp_rs232_4line_iob -- bplib/bpgen/sn_humanio -- vlib/rlink/rlink_sp2c @@ -29,7 +28,7 @@ -- Test bench: tb/tb_tst_sram_n4 -- -- Target Devices: generic --- Tool versions: viv 2014.4-2017.2; ghdl 0.29-0.34 (ise 14.5-14.7 retired) +-- Tool versions: viv 2014.4-2018.2; ghdl 0.29-0.34 (ise 14.5-14.7 retired) -- -- Synthesized: -- Date Rev viv Target flop lutl lutm bram slic @@ -38,6 +37,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2018-12-16 1086 1.7 use s7_cmt_1ce1ce -- 2017-01-14 844 1.6 add sysmon_rbus -- 2016-07-10 785 1.5.1 SWI(1) now XON -- 2016-07-09 784 1.5 tst_sram with AWIDTH and 22bit support @@ -58,7 +58,6 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.slvtypes.all; -use work.xlib.all; use work.genlib.all; use work.serportlib.all; use work.rblib.all; @@ -158,56 +157,34 @@ architecture syn of sys_tst_sram_n4 is begin - GEN_CLKSYS : s7_cmt_sfs -- clock generator system ------------ + GEN_CLKALL : s7_cmt_1ce1ce -- clock generator system ------------ generic map ( - VCO_DIVIDE => sys_conf_clksys_vcodivide, - VCO_MULTIPLY => sys_conf_clksys_vcomultiply, - OUT_DIVIDE => sys_conf_clksys_outdivide, CLKIN_PERIOD => 10.0, CLKIN_JITTER => 0.01, STARTUP_WAIT => false, - GEN_TYPE => sys_conf_clksys_gentype) + CLK0_VCODIV => sys_conf_clksys_vcodivide, + CLK0_VCOMUL => sys_conf_clksys_vcomultiply, + CLK0_OUTDIV => sys_conf_clksys_outdivide, + CLK0_GENTYPE => sys_conf_clksys_gentype, + CLK0_CDUWIDTH => 7, + CLK0_USECDIV => sys_conf_clksys_mhz, + CLK0_MSECDIV => 1000, + CLK1_VCODIV => sys_conf_clkser_vcodivide, + CLK1_VCOMUL => sys_conf_clkser_vcomultiply, + CLK1_OUTDIV => sys_conf_clkser_outdivide, + CLK1_GENTYPE => sys_conf_clkser_gentype, + CLK1_CDUWIDTH => 7, + CLK1_USECDIV => sys_conf_clkser_mhz, + CLK1_MSECDIV => 1000) port map ( - CLKIN => I_CLK100, - CLKFX => CLK, - LOCKED => open - ); - - CLKDIV_CLK : clkdivce -- usec/msec clock divider system ---- - generic map ( - CDUWIDTH => 7, -- good for up to 127 MHz ! - USECDIV => sys_conf_clksys_mhz, - MSECDIV => 1000) - port map ( - CLK => CLK, - CE_USEC => CE_USEC, - CE_MSEC => CE_MSEC - ); - - GEN_CLKSER : s7_cmt_sfs -- clock generator serport------------ - generic map ( - VCO_DIVIDE => sys_conf_clkser_vcodivide, - VCO_MULTIPLY => sys_conf_clkser_vcomultiply, - OUT_DIVIDE => sys_conf_clkser_outdivide, - CLKIN_PERIOD => 10.0, - CLKIN_JITTER => 0.01, - STARTUP_WAIT => false, - GEN_TYPE => sys_conf_clkser_gentype) - port map ( - CLKIN => I_CLK100, - CLKFX => CLKS, - LOCKED => open - ); - - CLKDIV_CLKS : clkdivce -- usec/msec clock divider serport --- - generic map ( - CDUWIDTH => 7, - USECDIV => sys_conf_clkser_mhz, - MSECDIV => 1000) - port map ( - CLK => CLKS, - CE_USEC => open, - CE_MSEC => CES_MSEC + CLKIN => I_CLK100, + CLK0 => CLK, + CE0_USEC => CE_USEC, + CE0_MSEC => CE_MSEC, + CLK1 => CLKS, + CE1_USEC => open, + CE1_MSEC => CES_MSEC, + LOCKED => open ); IOB_RS232 : bp_rs232_4line_iob diff --git a/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vbom b/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vbom index d8958a43..9437c302 100644 --- a/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vbom +++ b/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vbom @@ -1,6 +1,5 @@ # libs ../../../vlib/slvtypes.vhd -../../../vlib/xlib/xlib.vhd ../../../vlib/genlib/genlib.vhd ../../../vlib/serport/serportlib.vbom ../../../vlib/rbus/rblib.vhd @@ -13,9 +12,7 @@ ../../../w11a/pdp11.vhd ${sys_conf := sys_conf.vhd} # components -[vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom -[ghdl,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom -../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/s7_cmt_1ce1ce.vbom ../../../bplib/bpgen/bp_rs232_2line_iob.vbom ../../../vlib/rlink/rlink_sp2c.vbom ../../../w11a/pdp11_sys70.vbom diff --git a/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vhd b/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vhd index 0b192246..e1cb904d 100644 --- a/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vhd +++ b/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vhd @@ -1,4 +1,4 @@ --- $Id: sys_w11a_br_arty.vhd 1056 2018-10-13 16:01:17Z mueller $ +-- $Id: sys_w11a_br_arty.vhd 1086 2018-12-16 18:29:55Z mueller $ -- -- Copyright 2016-2018 by Walter F.J. Mueller -- @@ -15,8 +15,7 @@ -- Module Name: sys_w11a_br_arty - syn -- Description: w11a test design for arty -- --- Dependencies: vlib/xlib/s7_cmt_sfs --- vlib/genlib/clkdivce +-- Dependencies: bplib/bpgen/s7_cmt_1ce1ce -- bplib/bpgen/bp_rs232_2line_iob -- vlib/rlink/rlink_sp2c -- w11a/pdp11_sys70 @@ -54,6 +53,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2018-12-16 1086 1.4 use s7_cmt_1ce1ce -- 2018-10-13 1055 1.3 use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT -- 2016-04-02 758 1.2.1 add rbd_usracc (bitfile+jtag timestamp access) -- 2016-03-28 755 1.2 use serport_2clock2 @@ -111,7 +111,6 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.slvtypes.all; -use work.xlib.all; use work.genlib.all; use work.serportlib.all; use work.rblib.all; @@ -219,56 +218,34 @@ begin report "assert sys_conf_clksys on MHz grid" severity failure; - GEN_CLKSYS : s7_cmt_sfs -- clock generator system ------------ + GEN_CLKALL : s7_cmt_1ce1ce -- clock generator system ------------ generic map ( - VCO_DIVIDE => sys_conf_clksys_vcodivide, - VCO_MULTIPLY => sys_conf_clksys_vcomultiply, - OUT_DIVIDE => sys_conf_clksys_outdivide, CLKIN_PERIOD => 10.0, CLKIN_JITTER => 0.01, STARTUP_WAIT => false, - GEN_TYPE => sys_conf_clksys_gentype) + CLK0_VCODIV => sys_conf_clksys_vcodivide, + CLK0_VCOMUL => sys_conf_clksys_vcomultiply, + CLK0_OUTDIV => sys_conf_clksys_outdivide, + CLK0_GENTYPE => sys_conf_clksys_gentype, + CLK0_CDUWIDTH => 7, + CLK0_USECDIV => sys_conf_clksys_mhz, + CLK0_MSECDIV => 1000, + CLK1_VCODIV => sys_conf_clkser_vcodivide, + CLK1_VCOMUL => sys_conf_clkser_vcomultiply, + CLK1_OUTDIV => sys_conf_clkser_outdivide, + CLK1_GENTYPE => sys_conf_clkser_gentype, + CLK1_CDUWIDTH => 7, + CLK1_USECDIV => sys_conf_clkser_mhz, + CLK1_MSECDIV => 1000) port map ( - CLKIN => I_CLK100, - CLKFX => CLK, - LOCKED => open - ); - - CLKDIV_CLK : clkdivce -- usec/msec clock divider system ---- - generic map ( - CDUWIDTH => 7, - USECDIV => sys_conf_clksys_mhz, - MSECDIV => 1000) - port map ( - CLK => CLK, - CE_USEC => CE_USEC, - CE_MSEC => CE_MSEC - ); - - GEN_CLKSER : s7_cmt_sfs -- clock generator serport------------ - generic map ( - VCO_DIVIDE => sys_conf_clkser_vcodivide, - VCO_MULTIPLY => sys_conf_clkser_vcomultiply, - OUT_DIVIDE => sys_conf_clkser_outdivide, - CLKIN_PERIOD => 10.0, - CLKIN_JITTER => 0.01, - STARTUP_WAIT => false, - GEN_TYPE => sys_conf_clkser_gentype) - port map ( - CLKIN => I_CLK100, - CLKFX => CLKS, - LOCKED => open - ); - - CLKDIV_CLKS : clkdivce -- usec/msec clock divider serport --- - generic map ( - CDUWIDTH => 7, - USECDIV => sys_conf_clkser_mhz, - MSECDIV => 1000) - port map ( - CLK => CLKS, - CE_USEC => open, - CE_MSEC => CES_MSEC + CLKIN => I_CLK100, + CLK0 => CLK, + CE0_USEC => CE_USEC, + CE0_MSEC => CE_MSEC, + CLK1 => CLKS, + CE1_USEC => open, + CE1_MSEC => CES_MSEC, + LOCKED => open ); IOB_RS232 : bp_rs232_2line_iob -- serport iob ---------------------- diff --git a/rtl/sys_gen/w11a/artys7_bram/sys_w11a_br_as7.vbom b/rtl/sys_gen/w11a/artys7_bram/sys_w11a_br_as7.vbom index fc9fca32..4a2533a6 100644 --- a/rtl/sys_gen/w11a/artys7_bram/sys_w11a_br_as7.vbom +++ b/rtl/sys_gen/w11a/artys7_bram/sys_w11a_br_as7.vbom @@ -1,6 +1,5 @@ # libs ../../../vlib/slvtypes.vhd -../../../vlib/xlib/xlib.vhd ../../../vlib/genlib/genlib.vhd ../../../vlib/serport/serportlib.vbom ../../../vlib/rbus/rblib.vhd @@ -13,9 +12,7 @@ ../../../w11a/pdp11.vhd ${sys_conf := sys_conf.vhd} # components -[vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom -[ghdl,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom -../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/s7_cmt_1ce1ce.vbom ../../../bplib/bpgen/bp_rs232_2line_iob.vbom ../../../vlib/rlink/rlink_sp2c.vbom ../../../w11a/pdp11_sys70.vbom diff --git a/rtl/sys_gen/w11a/artys7_bram/sys_w11a_br_as7.vhd b/rtl/sys_gen/w11a/artys7_bram/sys_w11a_br_as7.vhd index d3649cb9..cc0f506b 100644 --- a/rtl/sys_gen/w11a/artys7_bram/sys_w11a_br_as7.vhd +++ b/rtl/sys_gen/w11a/artys7_bram/sys_w11a_br_as7.vhd @@ -1,4 +1,4 @@ --- $Id: sys_w11a_br_as7.vhd 1056 2018-10-13 16:01:17Z mueller $ +-- $Id: sys_w11a_br_as7.vhd 1086 2018-12-16 18:29:55Z mueller $ -- -- Copyright 2018- by Walter F.J. Mueller -- @@ -15,8 +15,7 @@ -- Module Name: sys_w11a_br_as7 - syn -- Description: w11a test design for as7 -- --- Dependencies: vlib/xlib/s7_cmt_sfs --- vlib/genlib/clkdivce +-- Dependencies: bplib/bpgen/s7_cmt_1ce1ce -- bplib/bpgen/bp_rs232_2line_iob -- vlib/rlink/rlink_sp2c -- w11a/pdp11_sys70 @@ -45,6 +44,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2018-12-16 1086 1.2 use s7_cmt_1ce1ce -- 2018-10-13 1055 1.1 use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT -- 2018-08-11 1038 1.0 Initial version (derived from sys_w11a_aa7) ------------------------------------------------------------------------------ @@ -93,7 +93,6 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.slvtypes.all; -use work.xlib.all; use work.genlib.all; use work.serportlib.all; use work.rblib.all; @@ -197,56 +196,34 @@ begin report "assert sys_conf_clksys on MHz grid" severity failure; - GEN_CLKSYS : s7_cmt_sfs -- clock generator system ------------ + GEN_CLKALL : s7_cmt_1ce1ce -- clock generator system ------------ generic map ( - VCO_DIVIDE => sys_conf_clksys_vcodivide, - VCO_MULTIPLY => sys_conf_clksys_vcomultiply, - OUT_DIVIDE => sys_conf_clksys_outdivide, CLKIN_PERIOD => 10.0, CLKIN_JITTER => 0.01, STARTUP_WAIT => false, - GEN_TYPE => sys_conf_clksys_gentype) + CLK0_VCODIV => sys_conf_clksys_vcodivide, + CLK0_VCOMUL => sys_conf_clksys_vcomultiply, + CLK0_OUTDIV => sys_conf_clksys_outdivide, + CLK0_GENTYPE => sys_conf_clksys_gentype, + CLK0_CDUWIDTH => 7, + CLK0_USECDIV => sys_conf_clksys_mhz, + CLK0_MSECDIV => 1000, + CLK1_VCODIV => sys_conf_clkser_vcodivide, + CLK1_VCOMUL => sys_conf_clkser_vcomultiply, + CLK1_OUTDIV => sys_conf_clkser_outdivide, + CLK1_GENTYPE => sys_conf_clkser_gentype, + CLK1_CDUWIDTH => 7, + CLK1_USECDIV => sys_conf_clkser_mhz, + CLK1_MSECDIV => 1000) port map ( - CLKIN => I_CLK100, - CLKFX => CLK, - LOCKED => open - ); - - CLKDIV_CLK : clkdivce -- usec/msec clock divider system ---- - generic map ( - CDUWIDTH => 7, - USECDIV => sys_conf_clksys_mhz, - MSECDIV => 1000) - port map ( - CLK => CLK, - CE_USEC => CE_USEC, - CE_MSEC => CE_MSEC - ); - - GEN_CLKSER : s7_cmt_sfs -- clock generator serport------------ - generic map ( - VCO_DIVIDE => sys_conf_clkser_vcodivide, - VCO_MULTIPLY => sys_conf_clkser_vcomultiply, - OUT_DIVIDE => sys_conf_clkser_outdivide, - CLKIN_PERIOD => 10.0, - CLKIN_JITTER => 0.01, - STARTUP_WAIT => false, - GEN_TYPE => sys_conf_clkser_gentype) - port map ( - CLKIN => I_CLK100, - CLKFX => CLKS, - LOCKED => open - ); - - CLKDIV_CLKS : clkdivce -- usec/msec clock divider serport --- - generic map ( - CDUWIDTH => 7, - USECDIV => sys_conf_clkser_mhz, - MSECDIV => 1000) - port map ( - CLK => CLKS, - CE_USEC => open, - CE_MSEC => CES_MSEC + CLKIN => I_CLK100, + CLK0 => CLK, + CE0_USEC => CE_USEC, + CE0_MSEC => CE_MSEC, + CLK1 => CLKS, + CE1_USEC => open, + CE1_MSEC => CES_MSEC, + LOCKED => open ); IOB_RS232 : bp_rs232_2line_iob -- serport iob ---------------------- diff --git a/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vbom b/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vbom index 34e6c182..5f398928 100644 --- a/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vbom +++ b/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vbom @@ -1,6 +1,5 @@ # libs ../../../vlib/slvtypes.vhd -../../../vlib/xlib/xlib.vhd ../../../vlib/genlib/genlib.vhd ../../../vlib/serport/serportlib.vbom ../../../vlib/rbus/rblib.vhd @@ -14,9 +13,7 @@ ../../../w11a/pdp11.vhd ${sys_conf := sys_conf.vhd} # components -[vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom -[ghdl,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom -../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/s7_cmt_1ce1ce.vbom ../../../bplib/bpgen/bp_rs232_2line_iob.vbom ../../../vlib/rlink/rlink_sp2c.vbom ../../../w11a/pdp11_sys70.vbom diff --git a/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd b/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd index 853ce130..4714b521 100644 --- a/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd +++ b/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd @@ -1,4 +1,4 @@ --- $Id: sys_w11a_b3.vhd 1056 2018-10-13 16:01:17Z mueller $ +-- $Id: sys_w11a_b3.vhd 1086 2018-12-16 18:29:55Z mueller $ -- -- Copyright 2015-2018 by Walter F.J. Mueller -- @@ -15,8 +15,7 @@ -- Module Name: sys_w11a_b3 - syn -- Description: w11a test design for basys3 -- --- Dependencies: vlib/xlib/s7_cmt_sfs --- vlib/genlib/clkdivce +-- Dependencies: bplib/bpgen/s7_cmt_1ce1ce -- bplib/bpgen/bp_rs232_2line_iob -- vlib/rlink/rlink_sp2c -- w11a/pdp11_sys70 @@ -51,6 +50,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2018-12-16 1086 1.5 use s7_cmt_1ce1ce -- 2018-10-13 1055 2.4 use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT -- 2016-04-02 758 2.3.1 add rbd_usracc (bitfile+jtag timestamp access) -- 2016-03-28 755 2.3 use serport_2clock2 @@ -113,7 +113,6 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.slvtypes.all; -use work.xlib.all; use work.genlib.all; use work.serportlib.all; use work.rblib.all; @@ -217,56 +216,34 @@ begin report "assert sys_conf_clksys on MHz grid" severity failure; - GEN_CLKSYS : s7_cmt_sfs -- clock generator system ------------ + GEN_CLKALL : s7_cmt_1ce1ce -- clock generator system ------------ generic map ( - VCO_DIVIDE => sys_conf_clksys_vcodivide, - VCO_MULTIPLY => sys_conf_clksys_vcomultiply, - OUT_DIVIDE => sys_conf_clksys_outdivide, CLKIN_PERIOD => 10.0, CLKIN_JITTER => 0.01, STARTUP_WAIT => false, - GEN_TYPE => sys_conf_clksys_gentype) + CLK0_VCODIV => sys_conf_clksys_vcodivide, + CLK0_VCOMUL => sys_conf_clksys_vcomultiply, + CLK0_OUTDIV => sys_conf_clksys_outdivide, + CLK0_GENTYPE => sys_conf_clksys_gentype, + CLK0_CDUWIDTH => 7, + CLK0_USECDIV => sys_conf_clksys_mhz, + CLK0_MSECDIV => 1000, + CLK1_VCODIV => sys_conf_clkser_vcodivide, + CLK1_VCOMUL => sys_conf_clkser_vcomultiply, + CLK1_OUTDIV => sys_conf_clkser_outdivide, + CLK1_GENTYPE => sys_conf_clkser_gentype, + CLK1_CDUWIDTH => 7, + CLK1_USECDIV => sys_conf_clkser_mhz, + CLK1_MSECDIV => 1000) port map ( - CLKIN => I_CLK100, - CLKFX => CLK, - LOCKED => open - ); - - CLKDIV_CLK : clkdivce -- usec/msec clock divider system ---- - generic map ( - CDUWIDTH => 7, - USECDIV => sys_conf_clksys_mhz, - MSECDIV => 1000) - port map ( - CLK => CLK, - CE_USEC => CE_USEC, - CE_MSEC => CE_MSEC - ); - - GEN_CLKSER : s7_cmt_sfs -- clock generator serport------------ - generic map ( - VCO_DIVIDE => sys_conf_clkser_vcodivide, - VCO_MULTIPLY => sys_conf_clkser_vcomultiply, - OUT_DIVIDE => sys_conf_clkser_outdivide, - CLKIN_PERIOD => 10.0, - CLKIN_JITTER => 0.01, - STARTUP_WAIT => false, - GEN_TYPE => sys_conf_clkser_gentype) - port map ( - CLKIN => I_CLK100, - CLKFX => CLKS, - LOCKED => open - ); - - CLKDIV_CLKS : clkdivce -- usec/msec clock divider serport --- - generic map ( - CDUWIDTH => 7, - USECDIV => sys_conf_clkser_mhz, - MSECDIV => 1000) - port map ( - CLK => CLKS, - CE_USEC => open, - CE_MSEC => CES_MSEC + CLKIN => I_CLK100, + CLK0 => CLK, + CE0_USEC => CE_USEC, + CE0_MSEC => CE_MSEC, + CLK1 => CLKS, + CE1_USEC => open, + CE1_MSEC => CES_MSEC, + LOCKED => open ); IOB_RS232 : bp_rs232_2line_iob -- serport iob ---------------------- diff --git a/rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vbom b/rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vbom index af3d437c..813f90ec 100644 --- a/rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vbom +++ b/rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vbom @@ -15,9 +15,7 @@ ../../../w11a/pdp11.vhd ${sys_conf := sys_conf.vhd} # components -[vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom -[ghdl,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom -../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/s7_cmt_1ce1ce.vbom ../../../bplib/bpgen/bp_rs232_2line_iob.vbom ../../../vlib/rlink/rlink_sp2c.vbom ../../../w11a/pdp11_sys70.vbom diff --git a/rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vhd b/rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vhd index c398dd5a..c1df8500 100644 --- a/rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vhd +++ b/rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vhd @@ -1,4 +1,4 @@ --- $Id: sys_w11a_c7.vhd 1056 2018-10-13 16:01:17Z mueller $ +-- $Id: sys_w11a_c7.vhd 1086 2018-12-16 18:29:55Z mueller $ -- -- Copyright 2017-2018 by Walter F.J. Mueller -- @@ -15,8 +15,7 @@ -- Module Name: sys_w11a_c7 - syn -- Description: w11a test design for Cmod A7 -- --- Dependencies: vlib/xlib/s7_cmt_sfs --- vlib/genlib/clkdivce +-- Dependencies: bplib/bpgen/s7_cmt_1ce1ce -- bplib/bpgen/bp_rs232_2line_iob -- vlib/rlink/rlink_sp2c -- w11a/pdp11_sys70 @@ -46,6 +45,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2018-12-16 1086 1.3 use s7_cmt_1ce1ce -- 2018-10-13 1055 1.2 use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT -- 2017-06-27 918 1.1.1 use 16 kB cache (all BRAM's used up) -- 2017-06-25 916 1.1 add bram_memctl for 672 kB total memory @@ -189,56 +189,34 @@ begin report "assert sys_conf_clksys on MHz grid" severity failure; - GEN_CLKSYS : s7_cmt_sfs -- clock generator system ------------ + GEN_CLKALL : s7_cmt_1ce1ce -- clock generator system ------------ generic map ( - VCO_DIVIDE => sys_conf_clksys_vcodivide, - VCO_MULTIPLY => sys_conf_clksys_vcomultiply, - OUT_DIVIDE => sys_conf_clksys_outdivide, CLKIN_PERIOD => 83.3, CLKIN_JITTER => 0.01, STARTUP_WAIT => false, - GEN_TYPE => sys_conf_clksys_gentype) + CLK0_VCODIV => sys_conf_clksys_vcodivide, + CLK0_VCOMUL => sys_conf_clksys_vcomultiply, + CLK0_OUTDIV => sys_conf_clksys_outdivide, + CLK0_GENTYPE => sys_conf_clksys_gentype, + CLK0_CDUWIDTH => 7, + CLK0_USECDIV => sys_conf_clksys_mhz, + CLK0_MSECDIV => 1000, + CLK1_VCODIV => sys_conf_clkser_vcodivide, + CLK1_VCOMUL => sys_conf_clkser_vcomultiply, + CLK1_OUTDIV => sys_conf_clkser_outdivide, + CLK1_GENTYPE => sys_conf_clkser_gentype, + CLK1_CDUWIDTH => 7, + CLK1_USECDIV => sys_conf_clkser_mhz, + CLK1_MSECDIV => 1000) port map ( - CLKIN => I_CLK12, - CLKFX => CLK, - LOCKED => open - ); - - CLKDIV_CLK : clkdivce -- usec/msec clock divider system ---- - generic map ( - CDUWIDTH => 7, - USECDIV => sys_conf_clksys_mhz, - MSECDIV => 1000) - port map ( - CLK => CLK, - CE_USEC => CE_USEC, - CE_MSEC => CE_MSEC - ); - - GEN_CLKSER : s7_cmt_sfs -- clock generator serport------------ - generic map ( - VCO_DIVIDE => sys_conf_clkser_vcodivide, - VCO_MULTIPLY => sys_conf_clkser_vcomultiply, - OUT_DIVIDE => sys_conf_clkser_outdivide, - CLKIN_PERIOD => 83.3, - CLKIN_JITTER => 0.01, - STARTUP_WAIT => false, - GEN_TYPE => sys_conf_clkser_gentype) - port map ( - CLKIN => I_CLK12, - CLKFX => CLKS, - LOCKED => open - ); - - CLKDIV_CLKS : clkdivce -- usec/msec clock divider serport --- - generic map ( - CDUWIDTH => 7, - USECDIV => sys_conf_clkser_mhz, - MSECDIV => 1000) - port map ( - CLK => CLKS, - CE_USEC => open, - CE_MSEC => CES_MSEC + CLKIN => I_CLK12, + CLK0 => CLK, + CE0_USEC => CE_USEC, + CE0_MSEC => CE_MSEC, + CLK1 => CLKS, + CE1_USEC => open, + CE1_MSEC => CES_MSEC, + LOCKED => open ); IOB_RS232 : bp_rs232_2line_iob -- serport iob ---------------------- diff --git a/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vbom b/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vbom index 746b547d..a10574ca 100644 --- a/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vbom +++ b/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vbom @@ -1,6 +1,5 @@ # libs ../../../vlib/slvtypes.vhd -../../../vlib/xlib/xlib.vhd ../../../vlib/genlib/genlib.vhd ../../../vlib/serport/serportlib.vbom ../../../vlib/rbus/rblib.vhd @@ -15,9 +14,7 @@ ../../../w11a/pdp11.vhd ${sys_conf := sys_conf.vbom} # components -[vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom -[ghdl,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom -../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/s7_cmt_1ce1ce.vbom ../../../bplib/bpgen/bp_rs232_4line_iob.vbom ../../../vlib/rlink/rlink_sp2c.vbom ../../../w11a/pdp11_sys70.vbom diff --git a/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vhd b/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vhd index d36756b0..a577eb78 100644 --- a/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vhd +++ b/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vhd @@ -1,4 +1,4 @@ --- $Id: sys_w11a_n4.vhd 1073 2018-11-23 18:05:51Z mueller $ +-- $Id: sys_w11a_n4.vhd 1086 2018-12-16 18:29:55Z mueller $ -- -- Copyright 2013-2018 by Walter F.J. Mueller -- @@ -15,8 +15,7 @@ -- Module Name: sys_w11a_n4 - syn -- Description: w11a test design for nexys4 -- --- Dependencies: vlib/xlib/s7_cmt_sfs --- vlib/genlib/clkdivce +-- Dependencies: bplib/bpgen/s7_cmt_1ce1ce -- bplib/bpgen/bp_rs232_4line_iob -- vlib/rlink/rlink_sp2c -- w11a/pdp11_sys70 @@ -54,6 +53,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2018-12-16 1086 2.5 use s7_cmt_1ce1ce -- 2018-10-13 1055 2.4 use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT -- 2016-04-02 758 2.3.1 add rbd_usracc (bitfile+jtag timestamp access) -- 2016-03-28 755 2.3 use serport_2clock2 @@ -124,7 +124,6 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.slvtypes.all; -use work.xlib.all; use work.genlib.all; use work.serportlib.all; use work.rblib.all; @@ -249,56 +248,34 @@ begin report "assert sys_conf_clksys on MHz grid" severity failure; - GEN_CLKSYS : s7_cmt_sfs -- clock generator system ------------ + GEN_CLKALL : s7_cmt_1ce1ce -- clock generator system ------------ generic map ( - VCO_DIVIDE => sys_conf_clksys_vcodivide, - VCO_MULTIPLY => sys_conf_clksys_vcomultiply, - OUT_DIVIDE => sys_conf_clksys_outdivide, CLKIN_PERIOD => 10.0, CLKIN_JITTER => 0.01, STARTUP_WAIT => false, - GEN_TYPE => sys_conf_clksys_gentype) + CLK0_VCODIV => sys_conf_clksys_vcodivide, + CLK0_VCOMUL => sys_conf_clksys_vcomultiply, + CLK0_OUTDIV => sys_conf_clksys_outdivide, + CLK0_GENTYPE => sys_conf_clksys_gentype, + CLK0_CDUWIDTH => 7, + CLK0_USECDIV => sys_conf_clksys_mhz, + CLK0_MSECDIV => 1000, + CLK1_VCODIV => sys_conf_clkser_vcodivide, + CLK1_VCOMUL => sys_conf_clkser_vcomultiply, + CLK1_OUTDIV => sys_conf_clkser_outdivide, + CLK1_GENTYPE => sys_conf_clkser_gentype, + CLK1_CDUWIDTH => 7, + CLK1_USECDIV => sys_conf_clkser_mhz, + CLK1_MSECDIV => 1000) port map ( - CLKIN => I_CLK100, - CLKFX => CLK, - LOCKED => open - ); - - CLKDIV_CLK : clkdivce -- usec/msec clock divider system ---- - generic map ( - CDUWIDTH => 7, - USECDIV => sys_conf_clksys_mhz, - MSECDIV => 1000) - port map ( - CLK => CLK, - CE_USEC => CE_USEC, - CE_MSEC => CE_MSEC - ); - - GEN_CLKSER : s7_cmt_sfs -- clock generator serport------------ - generic map ( - VCO_DIVIDE => sys_conf_clkser_vcodivide, - VCO_MULTIPLY => sys_conf_clkser_vcomultiply, - OUT_DIVIDE => sys_conf_clkser_outdivide, - CLKIN_PERIOD => 10.0, - CLKIN_JITTER => 0.01, - STARTUP_WAIT => false, - GEN_TYPE => sys_conf_clkser_gentype) - port map ( - CLKIN => I_CLK100, - CLKFX => CLKS, - LOCKED => open - ); - - CLKDIV_CLKS : clkdivce -- usec/msec clock divider serport --- - generic map ( - CDUWIDTH => 7, - USECDIV => sys_conf_clkser_mhz, - MSECDIV => 1000) - port map ( - CLK => CLKS, - CE_USEC => open, - CE_MSEC => CES_MSEC + CLKIN => I_CLK100, + CLK0 => CLK, + CE0_USEC => CE_USEC, + CE0_MSEC => CE_MSEC, + CLK1 => CLKS, + CE1_USEC => open, + CE1_MSEC => CES_MSEC, + LOCKED => open ); IOB_RS232 : bp_rs232_4line_iob -- serport iob ---------------------- diff --git a/rtl/sys_gen/w11a/nexys4d_bram/sys_w11a_br_n4d.vbom b/rtl/sys_gen/w11a/nexys4d_bram/sys_w11a_br_n4d.vbom index dbdf6c2a..addca912 100644 --- a/rtl/sys_gen/w11a/nexys4d_bram/sys_w11a_br_n4d.vbom +++ b/rtl/sys_gen/w11a/nexys4d_bram/sys_w11a_br_n4d.vbom @@ -1,6 +1,5 @@ # libs ../../../vlib/slvtypes.vhd -../../../vlib/xlib/xlib.vhd ../../../vlib/genlib/genlib.vhd ../../../vlib/serport/serportlib.vbom ../../../vlib/rbus/rblib.vhd @@ -15,9 +14,7 @@ ../../../w11a/pdp11.vhd ${sys_conf := sys_conf.vhd} # components -[vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom -[ghdl,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom -../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/s7_cmt_1ce1ce.vbom ../../../bplib/bpgen/bp_rs232_4line_iob.vbom ../../../vlib/rlink/rlink_sp2c.vbom ../../../w11a/pdp11_sys70.vbom diff --git a/rtl/sys_gen/w11a/nexys4d_bram/sys_w11a_br_n4d.vhd b/rtl/sys_gen/w11a/nexys4d_bram/sys_w11a_br_n4d.vhd index afce3d6a..c8d1a9ee 100644 --- a/rtl/sys_gen/w11a/nexys4d_bram/sys_w11a_br_n4d.vhd +++ b/rtl/sys_gen/w11a/nexys4d_bram/sys_w11a_br_n4d.vhd @@ -1,4 +1,4 @@ --- $Id: sys_w11a_br_n4d.vhd 1056 2018-10-13 16:01:17Z mueller $ +-- $Id: sys_w11a_br_n4d.vhd 1086 2018-12-16 18:29:55Z mueller $ -- -- Copyright 2017-2018 by Walter F.J. Mueller -- @@ -15,8 +15,7 @@ -- Module Name: sys_w11a_br_n4d - syn -- Description: w11a test design for nexys4d (bram only) -- --- Dependencies: vlib/xlib/s7_cmt_sfs --- vlib/genlib/clkdivce +-- Dependencies: bplib/bpgen/s7_cmt_1ce1ce -- bplib/bpgen/bp_rs232_4line_iob -- vlib/rlink/rlink_sp2c -- w11a/pdp11_sys70 @@ -42,6 +41,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2018-12-16 1086 1.2 use s7_cmt_1ce1ce -- 2018-10-13 1055 1.1 use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT -- 2017-01-04 838 1.0 Initial version (derived from sys_w11a_br_n4) ------------------------------------------------------------------------------ @@ -96,7 +96,6 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.slvtypes.all; -use work.xlib.all; use work.genlib.all; use work.serportlib.all; use work.rblib.all; @@ -208,56 +207,34 @@ begin report "assert sys_conf_clksys on MHz grid" severity failure; - GEN_CLKSYS : s7_cmt_sfs -- clock generator system ------------ + GEN_CLKALL : s7_cmt_1ce1ce -- clock generator system ------------ generic map ( - VCO_DIVIDE => sys_conf_clksys_vcodivide, - VCO_MULTIPLY => sys_conf_clksys_vcomultiply, - OUT_DIVIDE => sys_conf_clksys_outdivide, CLKIN_PERIOD => 10.0, CLKIN_JITTER => 0.01, STARTUP_WAIT => false, - GEN_TYPE => sys_conf_clksys_gentype) + CLK0_VCODIV => sys_conf_clksys_vcodivide, + CLK0_VCOMUL => sys_conf_clksys_vcomultiply, + CLK0_OUTDIV => sys_conf_clksys_outdivide, + CLK0_GENTYPE => sys_conf_clksys_gentype, + CLK0_CDUWIDTH => 7, + CLK0_USECDIV => sys_conf_clksys_mhz, + CLK0_MSECDIV => 1000, + CLK1_VCODIV => sys_conf_clkser_vcodivide, + CLK1_VCOMUL => sys_conf_clkser_vcomultiply, + CLK1_OUTDIV => sys_conf_clkser_outdivide, + CLK1_GENTYPE => sys_conf_clkser_gentype, + CLK1_CDUWIDTH => 7, + CLK1_USECDIV => sys_conf_clkser_mhz, + CLK1_MSECDIV => 1000) port map ( - CLKIN => I_CLK100, - CLKFX => CLK, - LOCKED => open - ); - - CLKDIV_CLK : clkdivce -- usec/msec clock divider system ---- - generic map ( - CDUWIDTH => 7, - USECDIV => sys_conf_clksys_mhz, - MSECDIV => 1000) - port map ( - CLK => CLK, - CE_USEC => CE_USEC, - CE_MSEC => CE_MSEC - ); - - GEN_CLKSER : s7_cmt_sfs -- clock generator serport------------ - generic map ( - VCO_DIVIDE => sys_conf_clkser_vcodivide, - VCO_MULTIPLY => sys_conf_clkser_vcomultiply, - OUT_DIVIDE => sys_conf_clkser_outdivide, - CLKIN_PERIOD => 10.0, - CLKIN_JITTER => 0.01, - STARTUP_WAIT => false, - GEN_TYPE => sys_conf_clkser_gentype) - port map ( - CLKIN => I_CLK100, - CLKFX => CLKS, - LOCKED => open - ); - - CLKDIV_CLKS : clkdivce -- usec/msec clock divider serport --- - generic map ( - CDUWIDTH => 7, - USECDIV => sys_conf_clkser_mhz, - MSECDIV => 1000) - port map ( - CLK => CLKS, - CE_USEC => open, - CE_MSEC => CES_MSEC + CLKIN => I_CLK100, + CLK0 => CLK, + CE0_USEC => CE_USEC, + CE0_MSEC => CE_MSEC, + CLK1 => CLKS, + CE1_USEC => open, + CE1_MSEC => CES_MSEC, + LOCKED => open ); IOB_RS232 : bp_rs232_4line_iob -- serport iob ---------------------- diff --git a/rtl/vlib/rlink/tbcore/tbcore_rlink.vhd b/rtl/vlib/rlink/tbcore/tbcore_rlink.vhd index aba77599..5fbe6e2b 100644 --- a/rtl/vlib/rlink/tbcore/tbcore_rlink.vhd +++ b/rtl/vlib/rlink/tbcore/tbcore_rlink.vhd @@ -1,6 +1,6 @@ --- $Id: tbcore_rlink.vhd 984 2018-01-02 20:56:27Z mueller $ +-- $Id: tbcore_rlink.vhd 1074 2018-11-25 21:38:59Z mueller $ -- --- Copyright 2010-2016 by Walter F.J. Mueller +-- Copyright 2010-2018 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -21,9 +21,10 @@ -- To test: generic, any rlink_cext based target -- -- Target Devices: generic --- Tool versions: ghdl 0.26-0.33 +-- Tool versions: ghdl 0.26-0.34 -- Revision History: -- Date Rev Version Comment +-- 2018-11-25 1074 3.3 wait 40 cycles after CONF_DONE -- 2016-09-17 807 3.2.2 conf: .sinit -> .sdata; finite length SB_VAL pulse -- 2016-09-02 805 3.2.1 conf: add .wait and CONF_DONE; drop CLK_STOP -- 2016-02-07 729 3.2 use rlink_cext_iface (allow VHPI and DPI backend) @@ -212,13 +213,13 @@ begin CEXT_RXHOLD <= '1'; - -- wait for CONF_DONE, but at least 10 clock cycles (conf+design run up) - for i in 0 to 9 loop - wait until rising_edge(CLK); - end loop; -- i + -- wait for CONF_DONE, plus addional 40 clock cycles (conf+design run up) while CONF_DONE = '0' loop wait until rising_edge(CLK); end loop; + for i in 0 to 39 loop + wait until rising_edge(CLK); + end loop; -- i writetimestamp(oline, CLK_CYCLE, ": START"); writeline(output, oline); diff --git a/rtl/vlib/serport/tb/serport_master_tb.vhd b/rtl/vlib/serport/tb/serport_master_tb.vhd index 1a164a58..9d550b5c 100644 --- a/rtl/vlib/serport/tb/serport_master_tb.vhd +++ b/rtl/vlib/serport/tb/serport_master_tb.vhd @@ -1,6 +1,6 @@ --- $Id: serport_master_tb.vhd 984 2018-01-02 20:56:27Z mueller $ +-- $Id: serport_master_tb.vhd 1087 2018-12-17 08:25:37Z mueller $ -- --- Copyright 2015-2016 by Walter F.J. Mueller +-- Copyright 2015-2018 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -20,10 +20,11 @@ -- serport_xontx_tb -- Test bench: - -- Target Devices: generic --- Tool versions: ghdl 0.31 +-- Tool versions: ghdl 0.31-0.34 -- -- Revision History: -- Date Rev Version Comment +-- 2018-12-16 1087 1.1 add 100 ps RXSD,TXSD delay to allow clock jitter -- 2016-01-03 724 1.0 Initial version (copied from serport_master) ------------------------------------------------------------------------------ @@ -61,14 +62,17 @@ end serport_master_tb; architecture sim of serport_master_tb is signal UART_RXDATA : slv8 := (others=>'0'); - signal UART_RXVAL : slbit := '0'; + signal UART_RXVAL : slbit := '0'; signal UART_TXDATA : slv8 := (others=>'0'); - signal UART_TXENA : slbit := '0'; + signal UART_TXENA : slbit := '0'; signal UART_TXBUSY : slbit := '0'; - signal XONTX_TXENA : slbit := '0'; + signal XONTX_TXENA : slbit := '0'; signal XONTX_TXBUSY : slbit := '0'; + signal UART_RXSD : slbit := '0'; + signal UART_TXSD : slbit := '0'; + signal TXOK : slbit := '0'; begin @@ -80,17 +84,24 @@ begin CLK => CLK, RESET => RESET, CLKDIV => CLKDIV, - RXSD => RXSD, + RXSD => UART_RXSD, RXDATA => UART_RXDATA, RXVAL => UART_RXVAL, RXERR => RXERR, RXACT => open, - TXSD => TXSD, + TXSD => UART_TXSD, TXDATA => UART_TXDATA, TXENA => UART_TXENA, TXBUSY => UART_TXBUSY ); + -- add some minor (100 ps) delay in the serial data path. + -- this makes transmission immune against small clock jitter between test + -- bench and UUT (e.g. from sfs re-phasing done differently in tb and UUT). + + TXSD <= UART_TXSD after 100 ps; + UART_RXSD <= RXSD after 100 ps; + XONRX : entity work.serport_xonrx_tb -- xon/xoff logic rx path port map ( CLK => CLK,