From 6b3aced4da3ce3db61b3f27d9184ca89af362216 Mon Sep 17 00:00:00 2001 From: wfjm Date: Fri, 15 Jul 2022 07:44:16 +0200 Subject: [PATCH] add test_w11a_inst_quick.tcl, cpu_selftest.mac --- rtl/w11a/tb/tb_pdp11core_stim.dat | 40 ++- tools/tbench/w11a/test_w11a_cpuerr.tcl | 4 +- tools/tbench/w11a/test_w11a_inst_quick.tcl | 338 +++++++++++++++++++++ tools/tbench/w11a/w11a_all.dat | 4 +- tools/tcode/cpu_all.dat | 3 +- tools/tcode/cpu_selftest.mac | 215 +++++++++++++ 6 files changed, 586 insertions(+), 18 deletions(-) create mode 100644 tools/tbench/w11a/test_w11a_inst_quick.tcl create mode 100644 tools/tcode/cpu_selftest.mac diff --git a/rtl/w11a/tb/tb_pdp11core_stim.dat b/rtl/w11a/tb/tb_pdp11core_stim.dat index e1e77b0f..4fb78584 100644 --- a/rtl/w11a/tb/tb_pdp11core_stim.dat +++ b/rtl/w11a/tb/tb_pdp11core_stim.dat @@ -1,4 +1,4 @@ -# $Id: tb_pdp11core_stim.dat 1253 2022-07-12 06:32:22Z mueller $ +# $Id: tb_pdp11core_stim.dat 1254 2022-07-13 06:16:19Z mueller $ # SPDX-License-Identifier: GPL-3.0-or-later # Copyright 2007-2016 by Walter F.J. Mueller # @@ -349,6 +349,7 @@ bwm 8 177600 -- 177600 (map to I/O page) #----------------------------------------------------------------------------- C Setup code 1 [base 2100] (very basics: cont,start; 'simple' instructions) +# ==> obsolete, covered by test_cp_cpubasics.tcl (2) others # wal 002100 -- code test 1: (sec+clc+halt) bwm 3 @@ -502,6 +503,7 @@ bwm 2 000000 -- PS:0 #----------------------------------------------------------------------------- C Setup code 5 [base 2500] (srcr modes: mov xxx,rn: (r0),(r0)+,-(r0),@(r0)) +# ==> now tested with test_w11a_srcr_word_flow.tcl # wal 002500 -- code: bwm 6 @@ -543,6 +545,7 @@ rsp d=001400 -- ! sp rpc d=002514 -- ! pc #----------------------------------------------------------------------------- C Setup code 6 [base 2600] (srcr modes: mov xxx,rn: x(r0),@x(r0), pc modes) +# ==> now tested with test_w11a_srcr_word_flow.tcl # wal 002600 -- code: bwm 11 @@ -581,6 +584,7 @@ rsp d=001400 -- ! sp rpc d=002626 -- ! pc #----------------------------------------------------------------------------- C Setup code 7 [base 2700] (dstw modes: mov rn,xxx: all non-r modes) +# ==> now test_w11a_dstw_word_flow.tcl # wal 002700 -- code: bwm 18 @@ -644,6 +648,7 @@ wal 001376 rmi d=000666 -- ! mem(sp)=666 #----------------------------------------------------------------------------- C Setup code 10 [base 3000] (dstm modes: inc xxx: all non-r modes) +# ==> now tested with test_w11a_dstm_word_flow.tcl # wal 003000 -- code: bwm 10 @@ -702,6 +707,7 @@ brm 7 d=000171 -- ! mem(3064)=171 #----------------------------------------------------------------------------- C Setup code 11 [base 3100; use 31-32] (dsta modes: jsr pc,xxx: all non-r modes) +# ==> now tested with test_w11a_dsta_flow.tcl # wal 003100 -- code: bwm 10 @@ -1124,6 +1130,7 @@ wal 177572 -- SSR0 rmi d=000000 -- ! cleared by CRESET #----------------------------------------------------------------------------- C Setup code 17 [base 4100; use 41-46] (basic instruction and cc test) +# ==> now tested with w11a/test_w11a_inst_quick.tcl # wal 004100 -- code: (length 70) bwm 32 @@ -1306,6 +1313,7 @@ bwm 2 000000 -- PS:0 #----------------------------------------------------------------------------- C Setup code 20 [base 4700] (check CPUERR and error handling) +# !! test_w11a_cpuerr.tcl --> only partial implementation !! #[[off]] wal 004700 -- code (to be single stepped...) bwm 11 @@ -2317,6 +2325,7 @@ brm 3 # #----------------------------------------------------------------------------- C Setup code 25 [base 6500; use 65-66] (basic byte instruction and cc test) +# ==> now tested with w11a/test_w11a_inst_quick.tcl # wal 006500 -- code: bwm 22 @@ -2394,25 +2403,25 @@ rpc d=006554 -- ! pc=6554 wal 006600 brm 11 d=155523 -- ! mem(6600)=123; movb r1,(r4)+ (#123, #333) -# ! mem(6601)=333; cmpb r1,(r4)+ (#123, #333) +# ! mem(6601)=333; cmpb r1,(r4)+ (#123, #333) d=051511 -- ! mem(6602)=111; cmpb r1,(r4)+ (#321, #111) -# ! mem(6603)=123; cmpb r1,(r4)+ (#123, #123) +# ! mem(6603)=123; cmpb r1,(r4)+ (#123, #123) d=044000 -- ! mem(6604)=000; clrb (r4)+ (#333) -# ! mem(6605)=011; bitb r1,(r4)+ (#123, #11) +# ! mem(6605)=011; bitb r1,(r4)+ (#123, #11) d=104044 -- ! mem(6606)=044; bitb r1,(r4)+ (#123, #44) -# ! mem(6607)=210; bicb r1,(r4)+ (#123, #333) +# ! mem(6607)=210; bicb r1,(r4)+ (#123, #333) d=027133 -- ! mem(6610)=133; bisb r1,(r4)+ (#123, #111) -# ! mem(6611)=056; comb (r4)+ (#321) +# ! mem(6611)=056; comb (r4)+ (#321) d=150322 -- ! mem(6612)=322; incb (r4)+ (#321) -# ! mem(6613)=320; decb (r4)+ (#321) +# ! mem(6613)=320; decb (r4)+ (#321) d=150457 -- ! mem(6614)=057; negb (r4)+ (#321) -# ! mem(6615)=321; tstb (r4)+ (#321) +# ! mem(6615)=321; tstb (r4)+ (#321) d=104100 -- ! mem(6616)=100; rorb (r4)+ (#201) Cout=1 -# ! mem(6617)=210; rorb (r4)+ (#021) Cout=1 +# ! mem(6617)=210; rorb (r4)+ (#021) Cout=1 d=004021 -- ! mem(6620)=021; rolb (r4)+ (#210) Cout=1 -# ! mem(6621)=010; asrb (r4)+ (#020) +# ! mem(6621)=010; asrb (r4)+ (#020) d=020310 -- ! mem(6622)=310; asrb (r4)+ (#220) -# ! mem(6623)=040; aslb (r4)+ (#020) +# ! mem(6623)=040; aslb (r4)+ (#020) d=000040 -- ! mem(6624)=040; aslb (r4)+ (#220) # wal 006626 -- NZVC @@ -3474,6 +3483,7 @@ brm 6 d=000777 -- ! mem(11377)=000000 #----------------------------------------------------------------------------- C Setup code 34 [base 11400; use 114-115] (11/34 self test code) +# ==> now tested with cpu_selftest.mac:A1 # code adapted from M9312 23-248F1 console PROM, the 11/04-34 Diagnostic PROM # wal 011400 -- code: @@ -3507,7 +3517,7 @@ bwm 51 #11460 056203 -- bis 12(r2),r3 ; r2=011560 r3=011566 000012 - 037203 -- bis @12(r2),r3 ; r2=011560 r3=011566 + 037203 -- bit @12(r2),r3 ; r2=011560 r3=011566 000012 001001 -- bne .+1 ; 000000 -- halt ; @@ -3560,6 +3570,7 @@ rr4 d=011565 -- ! r4 rpc d=011546 -- ! pc #----------------------------------------------------------------------------- C Setup code 35 [base 11600; use 116-121] (11/70 self test code) +# ==> now tested with cpu_selftest.mac:A2 # code adapted from M9312 23-616F1 console PROM, the 11/60-70 Diagnostic PROM # wal 011600 -- code: @@ -3571,7 +3582,7 @@ bwm 117 002401 -- blt L3 ; 101401 -- blos L4 ; 000000 -- L3: halt ; - 005306 -- L3: dec sp ; sp=177777 + 005306 -- L4: dec sp ; sp=177777 #11620 100003 -- bpl L5 ; 001402 -- beq L5 ; @@ -3623,7 +3634,7 @@ bwm 117 101401 -- blos L16 ; 000000 -- halt ; 040001 -- L16: bic r0,r1 ; r1=125252 - 060101 -- L16: add r1,r1 ; r1=052524 c=1 + 060101 -- add r1,r1 ; r1=052524 c=1 003001 -- bgt L17 ; 003401 -- ble L18 ; #11760 @@ -3715,6 +3726,7 @@ bwm 2 # result data: 037000 (512 byte area) #----------------------------------------------------------------------------- C Setup code 36 [base 12200] (systematic CMP test) +# ==> now tested with cpu_basic.mac:C5.* (redundant with 46.17wr) # wal 012200 -- code: bwm 7 diff --git a/tools/tbench/w11a/test_w11a_cpuerr.tcl b/tools/tbench/w11a/test_w11a_cpuerr.tcl index 53aad654..366e1d49 100644 --- a/tools/tbench/w11a/test_w11a_cpuerr.tcl +++ b/tools/tbench/w11a/test_w11a_cpuerr.tcl @@ -1,4 +1,4 @@ -# $Id: test_w11a_cpuerr.tcl 1178 2019-06-30 12:39:40Z mueller $ +# $Id: test_w11a_cpuerr.tcl 1254 2022-07-13 06:16:19Z mueller $ # SPDX-License-Identifier: GPL-3.0-or-later # Copyright 2016- by Walter F.J. Mueller # @@ -50,7 +50,7 @@ t.002: ; ; test 004: non-existent memory abort, will set bit cp.nxm ------------------- ; -; The address space jusr below the I/O page is never accessible in the +; The address space just below the I/O page is never accessible in the ; w11 (the 11/70 has ubmap window in this addess space). ; So setup MMU kernel I space AR(6) to point to the 8 kbyte below I/O page ; don't clear CPUERR at end of test ! diff --git a/tools/tbench/w11a/test_w11a_inst_quick.tcl b/tools/tbench/w11a/test_w11a_inst_quick.tcl new file mode 100644 index 00000000..44510bc2 --- /dev/null +++ b/tools/tbench/w11a/test_w11a_inst_quick.tcl @@ -0,0 +1,338 @@ +# $Id: test_w11a_inst_quick.tcl 1254 2022-07-13 06:16:19Z mueller $ +# SPDX-License-Identifier: GPL-3.0-or-later +# Copyright 2022- by Walter F.J. Mueller +# +# Revision History: +# Date Rev Version Comment +# 2022-07-12 1254 1.0 Initial version +# +# Quick instruction test. +# Most arithmetic instructions are used, usully for a single value +# Full testing with all corner cases is done in tcode cpu_basics.mac +# + +# ---------------------------------------------------------------------------- +rlc log "test_w11a_inst_quick: quick instruction test ------------------------" + +# -- Section A --------------------------------------------------------------- +rlc log " Word instructions -----------------------------------------" +# derived from tb_pdp11core_stim.dat code 17 +# r3 points to data, each instruction reads or modifies one value +# r4 points to check data, the values after instruction +# r5 points to check psw, the psw values after instruction + +$cpu ldasm -lst lst -sym sym { + .include |lib/defs_cpu.mac| + .include |lib/vec_cpucatch.mac| +; +; setup bpt vector + . = 000014 + .word vh.bpt + .word 0 +; + . = 1000 +stack: +; +; bpt vector handler +vh.bpt: cmp -2(r3),(r4)+ ; check modified data + beq 1$ + halt +1$: cmp 2(sp),(r5)+ ; check psw saved on stack + beq 2$ + halt +2$: rtt ; ensure next instruction is executed + +; main code +start: mov r1,(r3)+ ; (#4711, #123456) + cmp r1,(r3)+ ; (#4711, #123456) + cmp r2,(r3)+ ; (#123456,#4711) + cmp r1,(r3)+ ; (#4711, #4711) + clr (r3)+ ; (#123456) + bit r1,(r3)+ ; (#4711, #11) + bit r1,(r3)+ ; (#4711, #66) + bic r1,(r3)+ ; (#4711, #123456) + bis r1,(r3)+ ; (#4711, #123456) + add r1,(r3)+ ; (#4711, #123456) + sub r1,(r3)+ ; (#4711, #123456) + com (r3)+ ; (#123456) + inc (r3)+ ; (#123456) + dec (r3)+ ; (#123456) + neg (r3)+ ; (#123456) + tst (r3)+ ; (#123456) + ror (r3)+ ; (#100201) Cin=0; Cout=1 + ror (r3)+ ; (#002201) Cin=1; Cout=1 + rol (r3)+ ; (#100200) Cin=1; Cout=1 + asr (r3)+ ; (#200) + asr (r3)+ ; (#100200) + asl (r3)+ ; (#200) + asl (r3)+ ; (#100200) + add r1,(r3)+ ; (#4711, #077777) + adc (r3)+ ; (#200) + sub r1,(r3)+ ; (#4711, #4700) + sbc (r3)+ ; (#200) + swab (r3)+ ; (#111000) + sxt (r3)+ ; (#111111 with N=1) + xor r1,(r3)+ ; (#070707,#4711) + sxt (r3)+ ; (#111111 with N=0) + halt +stop: + +; input data for code +data: .word 123456 ; mov r1,(r3)+ (#4711, #123456) + .word 123456 ; cmp r1,(r3)+ (#4711, #123456) + .word 004711 ; cmp r1,(r3)+ (#123456,#4711) + .word 004711 ; cmp r1,(r3)+ (#4711, #4711) + .word 123456 ; clr (r3)+ (#123456) + .word 000011 ; bit r1,(r3)+ (#4711, #11) + .word 000066 ; bit r1,(r3)+ (#4711, #66) + .word 123456 ; bic r1,(r3)+ (#4711, #123456) + .word 123456 ; bis r1,(r3)+ (#4711, #123456) + .word 123456 ; add r1,(r3)+ (#4711, #123456) + .word 123456 ; sub r1,(r3)+ (#4711, #123456) + .word 123456 ; com (r3)+ (#123456) + .word 123456 ; inc (r3)+ (#123456) + .word 123456 ; dec (r3)+ (#123456) + .word 123456 ; neg (r3)+ (#123456) + .word 123456 ; tst (r3)+ (#123456) + .word 100201 ; ror (r3)+ (#100201) + .word 002201 ; ror (r3)+ (#002201) + .word 100200 ; rol (r3)+ (#100200) + .word 000200 ; asr (r3)+ (#200) + .word 100200 ; asr (r3)+ (#100200) + .word 000200 ; asl (r3)+ (#200) + .word 100200 ; asl (r3)+ (#100200) + .word 177000 ; add r1,(r3)+ (#4711, ,#177000) + .word 000200 ; adc (r3)+ (#200) + .word 004701 ; sub r1,(r3)+ (#4711, #4701) + .word 000200 ; sbc (r3)+ (#200) + .word 111000 ; swab (r3)+ (#111000) + .word 111111 ; sxt (r3)+ (#111111) + .word 070707 ; xor r1,(r3)+ (#070707) + .word 111111 ; sxt (r3)+ (#111111) +; +; data check, values after instruction +chkdat: .word 004711 ; mov r1,(r3)+ (#4711, #123456) + .word 123456 ; cmp r1,(r3)+ (#4711, #123456) + .word 004711 ; cmp r1,(r3)+ (#123456,#4711) + .word 004711 ; cmp r1,(r3)+ (#4711, #4711) + .word 000000 ; clr (r3)+ (#123456) + .word 000011 ; bit r1,(r3)+ (#4711, #11) + .word 000066 ; bit r1,(r3)+ (#4711, #66) + .word 123046 ; bic r1,(r3)+ (#4711, #123456) + .word 127757 ; bis r1,(r3)+ (#4711, #123456) + .word 130367 ; add r1,(r3)+ (#4711, #123456) + .word 116545 ; sub r1,(r3)+ (#4711, #123456) + .word 054321 ; com (r3)+ (#123456) + .word 123457 ; inc (r3)+ (#123456) + .word 123455 ; dec (r3)+ (#123456) + .word 054322 ; neg (r3)+ (#123456) + .word 123456 ; tst (r3)+ (#123456) + .word 040100 ; ror (r3)+ (#100201) + .word 101100 ; ror (r3)+ (#002201) + .word 000401 ; rol (r3)+ (#100200) + .word 000100 ; asr (r3)+ (#200) + .word 140100 ; asr (r3)+ (#100200) + .word 000400 ; asl (r3)+ (#200) + .word 000400 ; asl (r3)+ (#100200) + .word 003711 ; add r1,(r3)+ (#4711, ,#177000) + .word 000201 ; adc (r3)+ (#200) + .word 177770 ; sub r1,(r3)+ (#4711, #4701) + .word 000177 ; sbc (r3)+ (#200) + .word 000222 ; swab (r3)+ (#111000) + .word 177777 ; sxt (r3)+ (#111111) + .word 074016 ; xor r1,(r3)+ (#070707) + .word 000000 ; sxt (r3)+ (#111111) +; +; psw check, condition codes after instruction (Note: T bit always set !) +chkcc: .word 000020 ; 0000; mov r1,(r3)+ (#4711, #123456) + .word 000021 ; 000C; cmp r1,(r3)+ (#4711, #123456) + .word 000030 ; N000; cmp r1,(r3)+ (#123456,#4711) + .word 000024 ; 0Z00; cmp r1,(r3)+ (#4711, #4711) + .word 000024 ; 0Z00; clr (r3)+ (#123456) + .word 000020 ; 0000; bit r1,(r3)+ (#4711, #11) + .word 000024 ; 0Z00; bit r1,(r3)+ (#4711, #66) + .word 000030 ; N000; bic r1,(r3)+ (#4711, #123456) + .word 000030 ; N000; bis r1,(r3)+ (#4711, #123456) + .word 000030 ; N000; add r1,(r3)+ (#4711, #123456) + .word 000030 ; N000; sub r1,(r3)+ (#4711, #123456) + .word 000021 ; 000C; com (r3)+ (#123456) + .word 000031 ; N00C; inc (r3)+ (#123456) keep C! + .word 000031 ; N00C; dec (r3)+ (#123456) keep C! + .word 000021 ; 000C; neg (r3)+ (#123456) + .word 000030 ; N000; tst (r3)+ (#123456) + .word 000023 ; 00VC; ror (r3)+ (#100201) + .word 000031 ; N00C; ror (r3)+ (#002201) + .word 000023 ; 00VC; rol (r3)+ (#100200) + .word 000020 ; 0000; asr (r3)+ (#200) + .word 000032 ; N0V0; asr (r3)+ (#100200) + .word 000020 ; 0000; asl (r3)+ (#200) + .word 000023 ; 00VC; asl (r3)+ (#100200) + .word 000021 ; 000C; add r1,(r3)+ (#4711, ,#177000) + .word 000020 ; 0000; adc (r3)+ (#200) + .word 000031 ; N00C; sub r1,(r3)+ (#4711, #4701) + .word 000020 ; 0000; sbc (r3)+ (#200) + .word 000030 ; N000; swab (r3)+ (#111000) + .word 000030 ; N000; sxt (r3)+ (#111111 with N=1) + .word 000020 ; 0000; xor r1,(r3)+ (#4711, #070707) + .word 000024 ; 0Z00; sxt (r3)+ (#111111 with N=0) +} + +rw11::asmrun $cpu sym r0 0 \ + r1 0004711 \ + r2 0123456 \ + r3 $sym(data) \ + r4 $sym(chkdat) \ + r5 $sym(chkcc) \ + sp $sym(stack) \ + pc $sym(start) \ + ps 020 +rw11::asmwait $cpu sym +rw11::asmtreg $cpu r1 0004711 \ + r2 0123456 \ + r3 [expr $sym(data)+2*31] \ + r4 [expr $sym(chkdat)+2*31] \ + r5 [expr $sym(chkcc)+2*31] \ + sp $sym(stack) +; +# -- Section B --------------------------------------------------------------- +rlc log " Byte instructions -----------------------------------------" +# derived from tb_pdp11core_stim.dat code 25 +# r3 points to data, each instruction reads or modifies one value +# r4 points to check data, the values after instruction +# r5 points to check psw, the psw values after instruction + +$cpu ldasm -lst lst -sym sym { + .include |lib/defs_cpu.mac| + .include |lib/vec_cpucatch.mac| +; +; setup bpt vector + . = 000014 + .word vh.bpt + .word 0 +; + . = 1000 +stack: +; +; bpt vector handler +vh.bpt: cmpb -1(r3),(r4)+ ; check modified data + beq 1$ + halt +1$: cmp 2(sp),(r5)+ ; check psw saved on stack + beq 2$ + halt +2$: rtt ; ensure next instruction is executed + +; main code +start: movb r1,(r3)+ ; (#123, #333) + cmpb r1,(r3)+ ; (#123, #333) + cmpb r2,(r3)+ ; (#321, #111) + cmpb r1,(r3)+ ; (#123, #123) + clrb (r3)+ ; (#333) + bitb r1,(r3)+ ; (#123, #11) + bitb r1,(r3)+ ; (#123, #44) + bicb r1,(r3)+ ; (#123, #333) + bisb r1,(r3)+ ; (#123, #111) + comb (r3)+ ; (#321) + incb (r3)+ ; (#321) + decb (r3)+ ; (#321) + negb (r3)+ ; (#321) + tstb (r3)+ ; (#321) + rorb (r3)+ ; (#201) Cin=0; Cout=1 + rorb (r3)+ ; (#021) Cin=1; Cout=1 + rolb (r3)+ ; (#210) Cin=1; Cout=1 + asrb (r3)+ ; (#020) + asrb (r3)+ ; (#220) + aslb (r3)+ ; (#020) + aslb (r3)+ ; (#220) + halt +stop: + +; input data for code +data: .byte 333 ; movb r1,(r3)+ (#123, #333) + .byte 333 ; cmpb r1,(r3)+ (#123, #333) + .byte 111 ; cmpb r2,(r3)+ (#321, #111) + .byte 123 ; cmpb r1,(r3)+ (#123, #123) + .byte 333 ; clrb (r3)+ (#333) + .byte 011 ; bitb r1,(r3)+ (#123, #11) + .byte 044 ; bitb r1,(r3)+ (#123, #44) + .byte 333 ; bicb r1,(r3)+ (#123, #333) + .byte 111 ; bisb r1,(r3)+ (#123, #111) + .byte 321 ; comb (r3)+ (#321) + .byte 321 ; incb (r3)+ (#321) + .byte 321 ; decb (r3)+ (#321) + .byte 321 ; negb (r3)+ (#321) + .byte 321 ; tstb (r3)+ (#321) + .byte 201 ; rorb (r3)+ (#201) Cin=0; Cout=1 + .byte 021 ; rorb (r3)+ (#021) Cin=1; Cout=1 + .byte 210 ; rolb (r3)+ (#210) Cin=1; Cout=1 + .byte 020 ; asrb (r3)+ (#020) + .byte 220 ; asrb (r3)+ (#220) + .byte 020 ; aslb (r3)+ (#020) + .byte 220 ; aslb (r3)+ (#220) + .even +; +; data check, values after instruction +chkdat: .byte 123 ; movb r1,(r3)+ (#123, #333) + .byte 333 ; cmpb r1,(r3)+ (#123, #333) + .byte 111 ; cmpb r2,(r3)+ (#321, #111) + .byte 123 ; cmpb r1,(r3)+ (#123, #123) + .byte 000 ; clrb (r3)+ (#333) + .byte 011 ; bitb r1,(r3)+ (#123, #11) + .byte 044 ; bitb r1,(r3)+ (#123, #44) + .byte 210 ; bicb r1,(r3)+ (#123, #333) + .byte 133 ; bisb r1,(r3)+ (#123, #111) + .byte 056 ; comb (r3)+ (#321) + .byte 322 ; incb (r3)+ (#321) + .byte 320 ; decb (r3)+ (#321) + .byte 057 ; negb (r3)+ (#321) + .byte 321 ; tstb (r3)+ (#321) + .byte 100 ; rorb (r3)+ (#201) Cin=0; Cout=1 + .byte 210 ; rorb (r3)+ (#021) Cin=1; Cout=1 + .byte 021 ; rolb (r3)+ (#210) Cin=1; Cout=1 + .byte 010 ; asrb (r3)+ (#020) + .byte 310 ; asrb (r3)+ (#220) + .byte 040 ; aslb (r3)+ (#020) + .byte 040 ; aslb (r3)+ (#220) + .even +; +; psw check, condition codes after instruction (Note: T bit always set !) +chkcc: + .word 000020 ; 0000; movb r1,(r3)+ (#123, #333) + .word 000021 ; 000C; cmpb r1,(r3)+ (#123, #333) + .word 000030 ; N000; cmpb r1,(r3)+ (#321, #111) + .word 000024 ; 0Z00; cmpb r1,(r3)+ (#123, #123) + .word 000024 ; 0Z00; clrb (r3)+ (#333) + .word 000020 ; 0000; bitb r1,(r3)+ (#123, #11) + .word 000024 ; 0Z00; bitb r1,(r3)+ (#123, #44) + .word 000030 ; N000; bicb r1,(r3)+ (#123, #333) + .word 000020 ; 0000; bisb r1,(r3)+ (#123, #111) + .word 000021 ; 000C; comb (r3)+ (#321) + .word 000031 ; N00C; incb (r3)+ (#321) keep C! + .word 000031 ; N00C; decb (r3)+ (#321) keep C! + .word 000021 ; 000C; negb (r3)+ (#321) + .word 000030 ; N000; tstb (r3)+ (#321) + .word 000023 ; 00VC; rorb (r3)+ (#201) + .word 000031 ; N00C; rorb (r3)+ (#021) + .word 000023 ; 00VC; rolb (r3)+ (#210) + .word 000020 ; 0000; asrb (r3)+ (#020) + .word 000032 ; N0V0; asrb (r3)+ (#220) + .word 000020 ; 0000; aslb (r3)+ (#020) + .word 000023 ; 00VC; aslb (r3)+ (#220) +} + +rw11::asmrun $cpu sym r0 0 \ + r1 0000123 \ + r2 0000321 \ + r3 $sym(data) \ + r4 $sym(chkdat) \ + r5 $sym(chkcc) \ + sp $sym(stack) \ + pc $sym(start) \ + ps 020 +rw11::asmwait $cpu sym +rw11::asmtreg $cpu r1 0000123 \ + r2 0000321 \ + r3 [expr $sym(data)+1*21] \ + r4 [expr $sym(chkdat)+1*21] \ + r5 [expr $sym(chkcc)+2*21] \ + sp $sym(stack) diff --git a/tools/tbench/w11a/w11a_all.dat b/tools/tbench/w11a/w11a_all.dat index 2884415e..0fa0ecfb 100644 --- a/tools/tbench/w11a/w11a_all.dat +++ b/tools/tbench/w11a/w11a_all.dat @@ -1,4 +1,4 @@ -# $Id: w11a_all.dat 1250 2022-07-10 10:21:03Z mueller $ +# $Id: w11a_all.dat 1254 2022-07-13 06:16:19Z mueller $ # ## steering file for all w11a tests # @@ -10,6 +10,8 @@ test_w11a_srcr_word_flow.tcl test_w11a_dstw_word_flow.tcl test_w11a_dstm_word_flow.tcl test_w11a_dsta_flow.tcl +# +test_w11a_inst_quick.tcl test_w11a_inst_traps.tcl # test_w11a_cpuerr.tcl diff --git a/tools/tcode/cpu_all.dat b/tools/tcode/cpu_all.dat index d418a3ac..63f85453 100644 --- a/tools/tcode/cpu_all.dat +++ b/tools/tcode/cpu_all.dat @@ -1,6 +1,7 @@ -# $Id: cpu_all.dat 1250 2022-07-10 10:21:03Z mueller $ +# $Id: cpu_all.dat 1254 2022-07-13 06:16:19Z mueller $ # ## steering file for all cpu tests # cpu_basics.mac cpu_eis.mac +cpu_selftest.mac diff --git a/tools/tcode/cpu_selftest.mac b/tools/tcode/cpu_selftest.mac new file mode 100644 index 00000000..65755a6a --- /dev/null +++ b/tools/tcode/cpu_selftest.mac @@ -0,0 +1,215 @@ +; $Id: cpu_selftest.mac 1254 2022-07-13 06:16:19Z mueller $ +; SPDX-License-Identifier: GPL-3.0-or-later +; Copyright 2022- by Walter F.J. Mueller +; +; Revision History: +; Date Rev Version Comment +; 2022-07-12 1254 1.0 Initial version +; +; Test CPU basics +; + .include |lib/tcode_std_base.mac| +; +; Section A: Self-Test codes +; +; Test A1 -- 11/34 self test ++++++++++++++++++++++++++++++++++++++++++ +; adopted from tb_pdp11core_stim.dat code 34 +; heavily inspired from 23-248F1, the 11/04-34 Diagnostic PROM +; +ta0101: clr r0 ; r0=000000 c=0 + inc r0 ; r0=000001 c=0 + com r0 ; r0=177776 c=1 + asr r0 ; r0=177777 c=0 + asl r0 ; r0=177776 c=1 + ror r0 ; r0=177777 c=0 + tst r0 ; r0=177777 c=0 ?impact unclear? + neg r0 ; r0=000001 c=1 + dec r0 ; r0=000000 c=1 + sbc r0 ; r0=177777 c=1 + rol r0 ; r0=177777 c=1 + adc r0 ; r0=000000 c=1 + swab r0 ; r0=000000 c=0 + beq 1$ + halt +1$: mov #300$,r2 ; r2=300$ + mov (r2),r3 ; r2=300$ r3=300$ + cmp (r2)+,r3 ; r2=300$+2 r3=300$ + beq 2$ + halt +2$: add @(r2)+,r3 ; r2=300$+4 r3=<2*300$> + sub @-(r2),r3 ; r2=300$+2 r3=300$ + bic -(r2),r3 ; r2=300$ r3=000000 + bis 12(r2),r3 ; r2=300$ r3=003122 + bit @12(r2),r3 ; r2=300$ r3=003122 + bne 3$ + halt +3$: mov pc,r1 ; r1 points to jmp + jmp (r1)+ ; jumps 1st to itself, 2nd to next instruction + mov #102$,r1 + jmp @(r1)+ ; jump to next jmp +101$: jmp (r1) ; jump to instruction after 102$ +102$: .word 101$ + tstb 301$ + beq 4$ + halt +4$: mov r2,r4 + cmp (r4)+,(r4)+ ; r4=011564 + tstb (r4)+ ; r4=011565 (r4)+=000 + beq 5$ + halt +5$: tstb (r4) ; r4=011565 (r4)=200 + bmi 6$ + halt +6$: mov #302$,r5 ; r5=302$ + mov #400$,r2 ; r2=400$ + mov (r5),r3 ; r3=177777 + clr (r2) ; 400$[0] = 0 + movb (r5)+,(r2) ; 400$[0] = 377; r5=302$+1 + inc r2 ; r2=400$+1 + movb (r5)+,(r2) ; 400$[1] = 377; r5=302$+2 + dec r2 ; r2=400$ + cmp @(r5)+,(r2) ; 302$[0] == 400$[0]; r5=302$+4 + beq 7$ + halt +7$: inc r2 ; r2=400$+1 + bicb @(r5)+,(r2)+ ; 400$[1] = 0; r2=400$+2; r5=302$+6 + cmp -(r5),-(r2) ; r2=400$; r5=302$+4 + bicb @(r5)+,(r2)+ ; 400$[0] = 0; r2=400$+1; r5=302$+6 + beq 8$ + halt +8$: mov r5,r2 ; r2=302$+6 + mov -6(r5),r5 ; r5=177777 + movb r5,@(r2)+ ; 400$[0] = 377; r2=302$+10 + bisb r5,@0(r2) ; 400$[1] = 377 + cmp r3,@-(r2) ; r2=302$+6 + beq 9$ + halt +9$: jmp 9999$ +; +300$: .word 300$ ; 300$ + 0 + .word 300$ ; + 2 +301$: .byte 000,200 ; + 4 +302$: .word 177777 ; + 6; 302$ + 0 + .word 302$ ; +10 + 2 + .word 302$ ; +12 + 4 + .word 400$ ; + 6 + .word 400$+1 ; +10 +400$: .word 0,0 +; +9999$: iot ; end of test A1 +; +; Test A2 -- 11/70 self test ++++++++++++++++++++++++++++++++++++++++++ +; adopted from tb_pdp11core_stim.dat code 35 +; heavily inspired from 23-616F1, the 11/60-70 Diagnostic PROM +; +ta0201: + clr sp ; sp=000000 + bmi 1$ + bvs 1$ + bhi 1$ + blt 1$ + blos 2$ +1$: halt +2$: dec sp ; sp=177777 + bpl 3$ + beq 3$ + bge 3$ + ble 4$ +3$: halt +4$: ror sp ; sp=077777 + bvc 5$ + bcc 5$ + bne 6$ +5$: halt +6$: mov #125252,sp ; sp=125252 + mov sp,r0 ; r0=125252 + mov r0,r1 ; r1=125252 + mov r1,r2 ; r2=125252 + mov r2,r3 ; r3=125252 + mov r3,r4 ; r4=125252 + mov r4,r5 ; r5=125252 + sub r5,r1 ; r1=00000 + blt 7$ + beq 8$ +7$: halt +8$: rol r2 ; r2=052524 c=1 + bcc 9$ + blt 10$ +9$: halt +10$: add r2,r3 ; r3=177776 (125252+052524) + inc r3 ; r3=177777 + com r3 ; r3=000000 + add r3,r1 ; r1=000000 c=0 + bcs 11$ + ble 12$ +11$: halt +12$: ror r4 ; r4=052525 + bis r4,r3 ; r3=052525 (r3 was 0) + add r5,r3 ; r3=177777 c=0 (125252+052525) + inc r3 ; r3=000000 c=0 (kept) + bcs 13$ + dec r1 ; r1=177777 + blt 14$ +13$: halt +14$: com r0 ; r0=052525 + blos 16$ + halt +16$: bic r0,r1 ; r1=125252 + add r1,r1 ; r1=052524 c=1 + bgt 17$ + ble 18$ +17$: halt +18$: swab r1 ; r1=052125 + cmp r1,#052125 + bne 19$ + bit r4,r5 + bgt 19$ + com r5 ; r5=052525 + bne 20$ +19$: halt +20$: movb #177401,r0 ; r0=000001 + bpl 22$ +21$: halt +22$: sob r0,21$ ; r0=1 so sob falls through; r0=000000 + sec ; c=1 + rol r0 ; r0=000001 + rol r0 ; r0=000002 + rol r0 ; r0=000004 + mov r0,r1 ; r1=000004 + neg r1 ; r1=177774 +24$: inc r1 + sob r0,24$ ; sob will do 4 iterations + tst r0 ; here r0=0; r1=0 + bne 25$ + tst r1 + beq 26$ +25$: halt +26$: mov #stack,sp ; sp=002000 + jsr pc,100$ +27$: halt +100$: cmp #27$,(sp) ; check return address + beq 101$ + halt +101$: mov #200$,(sp) ; set new return + rts pc ; and rts to 200$ + halt +200$: clr -(sp) ; setup vector return + mov #300$,-(sp) ; + rti ; and rti to 300$ + halt +300$: jmp @#400$ + halt +400$: mov #160000,r5 ; r5=160000 + mov #500$,v..iit ; setup iit vector + clr v..iit+2 + mov #stack,sp ; sp=002000 + tst (r5) ; will fail, first word of I/O page + halt +500$: mov #v..iit+2,v..iit ; restore iit catcher + clr v..iit+2 +; +9999$: iot ; end of test A2 +; +; END OF ALL TESTS - loop closure -------------------------------------------- +; + jmp loop