diff --git a/rtl/w11a/pdp11.vhd b/rtl/w11a/pdp11.vhd index ed523978..eba96e9c 100644 --- a/rtl/w11a/pdp11.vhd +++ b/rtl/w11a/pdp11.vhd @@ -1,16 +1,17 @@ --- $Id: pdp11.vhd 1181 2019-07-08 17:00:50Z mueller $ +-- $Id: pdp11.vhd 1279 2022-08-14 08:02:21Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later --- Copyright 2006-2019 by Walter F.J. Mueller +-- Copyright 2006-2022 by Walter F.J. Mueller -- ------------------------------------------------------------------------------ -- Package Name: pdp11 -- Description: Definitions for pdp11 components -- -- Dependencies: - --- Tool versions: ise 8.2-14.7; viv 2016.2-2019.1; ghdl 0.18-0.35 +-- Tool versions: ise 8.2-14.7; viv 2016.2-2022.1; ghdl 0.18-2.0.0 -- -- Revision History: -- Date Rev Version Comment +-- 2022-08-13 1279 1.6.13 ssr->mmr rename -- 2019-06-02 1159 1.6.12 add rbaddr_ constants -- 2019-03-01 1116 1.6.11 define c_init_rbf_greset -- 2018-10-07 1054 1.6.10 add DM_STAT_EXP; add DM_STAT_SE.itimer @@ -144,16 +145,16 @@ package pdp11 is constant psw_ibf_tflag: integer := 4; subtype psw_ibf_cc is integer range 3 downto 0; - type sarsdr_type is record -- combined SAR/SDR MMU status - saf : slv16; -- segment address field - slf : slv7; -- segment length field + type parpdr_type is record -- combined PAR/PDR MMU status + paf : slv16; -- page address field + plf : slv7; -- page length field ed : slbit; -- expansion direction acf : slv3; -- access control field - end record sarsdr_type; + end record parpdr_type; - constant sarsdr_init : sarsdr_type := ( - (others=>'0'), -- saf - "0000000",'0',"000" -- slf, ed, acf + constant parpdr_init : parpdr_type := ( + (others=>'0'), -- paf + "0000000",'0',"000" -- plf, ed, acf ); type dpath_cntl_type is record -- data path control @@ -413,7 +414,7 @@ package pdp11 is kstack : slbit; -- access through kernel stack intrsv : slbit; -- active rsv interrupt sequence mode : slv2; -- mode - trap_done : slbit; -- mmu trap taken (to set ssr0 bit) + trap_done : slbit; -- mmu trap taken (to set mmr0 bit) end record vm_cntl_type; constant vm_cntl_init : vm_cntl_type := ( @@ -469,7 +470,7 @@ package pdp11 is cacc : slbit; -- console access (bypass mmu) dspace : slbit; -- dspace access mode : slv2; -- processor mode - trap_done : slbit; -- mmu trap taken (set ssr0 bit) + trap_done : slbit; -- mmu trap taken (set mmr0 bit) end record mmu_cntl_type; constant mmu_cntl_init : mmu_cntl_type := ( @@ -480,9 +481,9 @@ package pdp11 is type mmu_stat_type is record -- mmu status port vaok : slbit; -- virtual address valid trap : slbit; -- mmu trap request - ena_mmu : slbit; -- mmu enable (ssr0 bit 0) - ena_22bit : slbit; -- mmu in 22 bit mode (ssr3 bit 4) - ena_ubmap : slbit; -- ubmap enable (ssr3 bit 5) + ena_mmu : slbit; -- mmu enable (mmr0 bit 0) + ena_22bit : slbit; -- mmu in 22 bit mode (mmr3 bit 4) + ena_ubmap : slbit; -- ubmap enable (mmr3 bit 5) end record mmu_stat_type; constant mmu_stat_init : mmu_stat_type := (others=>'0'); @@ -495,7 +496,7 @@ package pdp11 is regnum : slv3; -- register number delta : slv4; -- register offset isdec : slbit; -- offset to be subtracted - trace_prev : slbit; -- use ssr12 trace state of prev. state + trace_prev : slbit; -- use mmr12 trace state of prev. state end record mmu_moni_type; constant mmu_moni_init : mmu_moni_type := ( @@ -504,46 +505,46 @@ package pdp11 is '0','0' -- isdec, trace_prev ); - type mmu_ssr0_type is record -- MMU ssr0 + type mmu_mmr0_type is record -- MMU mmr0 abo_nonres : slbit; -- abort non resident - abo_length : slbit; -- abort segment length + abo_length : slbit; -- abort page length abo_rdonly : slbit; -- abort read-only trap_mmu : slbit; -- trap management ena_trap : slbit; -- enable traps inst_compl : slbit; -- instruction complete - seg_mode : slv2; -- segement mode + page_mode : slv2; -- page mode dspace : slbit; -- address space (D=1, I=0) - seg_num : slv3; -- segment number + page_num : slv3; -- page number ena_mmu : slbit; -- enable memory management - trace_prev : slbit; -- ssr12 trace status in prev. state - end record mmu_ssr0_type; + trace_prev : slbit; -- mmr12 trace status in prev. state + end record mmu_mmr0_type; - constant mmu_ssr0_init : mmu_ssr0_type := ( - inst_compl=>'0', seg_mode=>"00", seg_num=>"000", + constant mmu_mmr0_init : mmu_mmr0_type := ( + inst_compl=>'0', page_mode=>"00", page_num=>"000", others=>'0' ); - type mmu_ssr1_type is record -- MMU ssr1 + type mmu_mmr1_type is record -- MMU mmr1 rb_delta : slv5; -- RB: amount change rb_num : slv3; -- RB: register number ra_delta : slv5; -- RA: amount change ra_num : slv3; -- RA: register number - end record mmu_ssr1_type; + end record mmu_mmr1_type; - constant mmu_ssr1_init : mmu_ssr1_type := ( + constant mmu_mmr1_init : mmu_mmr1_type := ( "00000","000", -- rb_... "00000","000" -- ra_... ); - type mmu_ssr3_type is record -- MMU ssr3 + type mmu_mmr3_type is record -- MMU mmr3 ena_ubmap : slbit; -- enable unibus mapping ena_22bit : slbit; -- enable 22 bit mapping dspace_km : slbit; -- enable dspace kernel dspace_sm : slbit; -- enable dspace supervisor dspace_um : slbit; -- enable dspace user - end record mmu_ssr3_type; + end record mmu_mmr3_type; - constant mmu_ssr3_init : mmu_ssr3_type := (others=>'0'); + constant mmu_mmr3_init : mmu_mmr3_type := (others=>'0'); -- control port definitions -------------------------------------------------- @@ -932,21 +933,21 @@ constant c_munit_func_div : slv2 := "01"; -- DIV constant c_munit_func_ash : slv2 := "10"; -- ASH constant c_munit_func_ashc : slv2 := "11"; -- ASHC -component pdp11_mmu_sadr is -- mmu SAR/SDR register set +component pdp11_mmu_padr is -- mmu PAR/PDR register set port ( CLK : in slbit; -- clock MODE : in slv2; -- mode - ASN : in slv4; -- augmented segment number (1+3 bit) + APN : in slv4; -- augmented page number (1+3 bit) AIB_WE : in slbit; -- update AIB AIB_SETA : in slbit; -- set access AIB AIB_SETW : in slbit; -- set write AIB - SARSDR : out sarsdr_type; -- combined SAR/SDR + PARPDR : out parpdr_type; -- combined PAR/PDR IB_MREQ : in ib_mreq_type; -- ibus request IB_SRES : out ib_sres_type -- ibus response ); end component; -component pdp11_mmu_ssr12 is -- mmu register ssr1 and ssr2 +component pdp11_mmu_mmr12 is -- mmu register mmr1 and mmr2 port ( CLK : in slbit; -- clock CRESET : in slbit; -- cpu reset diff --git a/rtl/w11a/pdp11_mmu.vhd b/rtl/w11a/pdp11_mmu.vhd index 1d9dc082..7530953d 100644 --- a/rtl/w11a/pdp11_mmu.vhd +++ b/rtl/w11a/pdp11_mmu.vhd @@ -1,32 +1,33 @@ --- $Id: pdp11_mmu.vhd 1181 2019-07-08 17:00:50Z mueller $ +-- $Id: pdp11_mmu.vhd 1279 2022-08-14 08:02:21Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later --- Copyright 2006-2011 by Walter F.J. Mueller +-- Copyright 2006-2022 by Walter F.J. Mueller -- ------------------------------------------------------------------------------ -- Module Name: pdp11_mmu - syn -- Description: pdp11: mmu - memory management unit -- --- Dependencies: pdp11_mmu_sadr --- pdp11_mmu_ssr12 +-- Dependencies: pdp11_mmu_padr +-- pdp11_mmu_mmr12 -- ibus/ib_sres_or_3 -- ibus/ib_sel -- -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 +-- Tool versions: ise 8.2-14.7; viv 2014.4-2022.1; ghdl 0.18-2.0.0 -- --- Revision History: +-- Revision History: -- Date Rev Version Comment +-- 2022-08-13 1279 1.4.3 ssr->mmr rename -- 2011-11-18 427 1.4.2 now numeric_std clean -- 2010-10-23 335 1.4.1 use ib_sel -- 2010-10-17 333 1.4 use ibus V2 interface -- 2010-06-20 307 1.3.7 rename cpacc to cacc in mmu_cntl_type -- 2009-05-30 220 1.3.6 final removal of snoopers (were already commented) -- 2009-05-09 213 1.3.5 BUGFIX: tie inst_compl permanentely '0' --- BUGFIX: set ssr0 trap_mmu even when traps disabled +-- BUGFIX: set mmr0 trap_mmu even when traps disabled -- 2008-08-22 161 1.3.4 rename pdp11_ibres_ -> ib_sres_, ubf_ -> ibf_ --- 2008-04-27 139 1.3.3 allow ssr1/2 tracing even with mmu_ena=0 --- 2008-04-25 138 1.3.2 add BRESET port, clear ssr0/3 with BRESET +-- 2008-04-27 139 1.3.3 allow mmr1/2 tracing even with mmu_ena=0 +-- 2008-04-25 138 1.3.2 add BRESET port, clear mmr0/3 with BRESET -- 2008-03-02 121 1.3.1 remove snoopers -- 2008-02-24 119 1.3 return always mapped address in PADDRH; remove -- cpacc handling; PADDR generation now on _vmbox @@ -36,7 +37,7 @@ -- 2007-12-31 108 1.1.1 remove SADR memory address mux (-> _mmu_regfile) -- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now -- 2007-06-14 56 1.0.1 Use slvtypes.all --- 2007-05-12 26 1.0 Initial version +-- 2007-05-12 26 1.0 Initial version ------------------------------------------------------------------------------ library ieee; @@ -66,218 +67,218 @@ end pdp11_mmu; architecture syn of pdp11_mmu is - constant ibaddr_ssr0 : slv16 := slv(to_unsigned(8#177572#,16)); - constant ibaddr_ssr3 : slv16 := slv(to_unsigned(8#172516#,16)); + constant ibaddr_mmr0 : slv16 := slv(to_unsigned(8#177572#,16)); + constant ibaddr_mmr3 : slv16 := slv(to_unsigned(8#172516#,16)); - constant ssr0_ibf_abo_nonres : integer := 15; - constant ssr0_ibf_abo_length : integer := 14; - constant ssr0_ibf_abo_rdonly : integer := 13; - constant ssr0_ibf_trap_mmu : integer := 12; - constant ssr0_ibf_ena_trap : integer := 9; - constant ssr0_ibf_inst_compl : integer := 7; - subtype ssr0_ibf_seg_mode is integer range 6 downto 5; - constant ssr0_ibf_dspace : integer := 4; - subtype ssr0_ibf_seg_num is integer range 3 downto 1; - constant ssr0_ibf_ena_mmu : integer := 0; + constant mmr0_ibf_abo_nonres : integer := 15; + constant mmr0_ibf_abo_length : integer := 14; + constant mmr0_ibf_abo_rdonly : integer := 13; + constant mmr0_ibf_trap_mmu : integer := 12; + constant mmr0_ibf_ena_trap : integer := 9; + constant mmr0_ibf_inst_compl : integer := 7; + subtype mmr0_ibf_page_mode is integer range 6 downto 5; + constant mmr0_ibf_dspace : integer := 4; + subtype mmr0_ibf_page_num is integer range 3 downto 1; + constant mmr0_ibf_ena_mmu : integer := 0; - constant ssr3_ibf_ena_ubmap : integer := 5; - constant ssr3_ibf_ena_22bit : integer := 4; - constant ssr3_ibf_dspace_km : integer := 2; - constant ssr3_ibf_dspace_sm : integer := 1; - constant ssr3_ibf_dspace_um : integer := 0; + constant mmr3_ibf_ena_ubmap : integer := 5; + constant mmr3_ibf_ena_22bit : integer := 4; + constant mmr3_ibf_dspace_km : integer := 2; + constant mmr3_ibf_dspace_sm : integer := 1; + constant mmr3_ibf_dspace_um : integer := 0; - signal IBSEL_SSR0 : slbit := '0'; -- ibus select SSR0 - signal IBSEL_SSR3 : slbit := '0'; -- ibus select SSR3 + signal IBSEL_MMR0 : slbit := '0'; -- ibus select MMR0 + signal IBSEL_MMR3 : slbit := '0'; -- ibus select MMR3 - signal R_SSR0 : mmu_ssr0_type := mmu_ssr0_init; - signal N_SSR0 : mmu_ssr0_type := mmu_ssr0_init; + signal R_MMR0 : mmu_mmr0_type := mmu_mmr0_init; + signal N_MMR0 : mmu_mmr0_type := mmu_mmr0_init; - signal R_SSR3 : mmu_ssr3_type := mmu_ssr3_init; + signal R_MMR3 : mmu_mmr3_type := mmu_mmr3_init; - signal ASN : slv4 := "0000"; -- augmented segment number (1+3 bit) + signal APN : slv4 := "0000"; -- augmented page number (1+3 bit) signal AIB_WE : slbit := '0'; -- update AIB signal AIB_SETA : slbit := '0'; -- set A bit in access information bits signal AIB_SETW : slbit := '0'; -- set W bit in access information bits - signal TRACE : slbit := '0'; -- enable tracing in ssr1/2 + signal TRACE : slbit := '0'; -- enable tracing in mmr1/2 signal DSPACE : slbit := '0'; -- use dspace - signal IB_SRES_SADR : ib_sres_type := ib_sres_init; - signal IB_SRES_SSR12 : ib_sres_type := ib_sres_init; - signal IB_SRES_SSR03 : ib_sres_type := ib_sres_init; + signal IB_SRES_PADR : ib_sres_type := ib_sres_init; + signal IB_SRES_MMR12 : ib_sres_type := ib_sres_init; + signal IB_SRES_MMR03 : ib_sres_type := ib_sres_init; - signal SARSDR : sarsdr_type := sarsdr_init; + signal PARPDR : parpdr_type := parpdr_init; begin - SADR : pdp11_mmu_sadr port map ( + PADR : pdp11_mmu_padr port map ( CLK => CLK, MODE => CNTL.mode, - ASN => ASN, + APN => APN, AIB_WE => AIB_WE, AIB_SETA => AIB_SETA, AIB_SETW => AIB_SETW, - SARSDR => SARSDR, + PARPDR => PARPDR, IB_MREQ => IB_MREQ, - IB_SRES => IB_SRES_SADR); + IB_SRES => IB_SRES_PADR); - SSR12 : pdp11_mmu_ssr12 port map ( + MMR12 : pdp11_mmu_mmr12 port map ( CLK => CLK, CRESET => CRESET, TRACE => TRACE, MONI => MONI, IB_MREQ => IB_MREQ, - IB_SRES => IB_SRES_SSR12); + IB_SRES => IB_SRES_MMR12); SRES_OR : ib_sres_or_3 port map ( - IB_SRES_1 => IB_SRES_SADR, - IB_SRES_2 => IB_SRES_SSR12, - IB_SRES_3 => IB_SRES_SSR03, + IB_SRES_1 => IB_SRES_PADR, + IB_SRES_2 => IB_SRES_MMR12, + IB_SRES_3 => IB_SRES_MMR03, IB_SRES_OR => IB_SRES); - SEL_SSR0 : ib_sel + SEL_MMR0 : ib_sel generic map ( - IB_ADDR => ibaddr_ssr0) + IB_ADDR => ibaddr_mmr0) port map ( CLK => CLK, IB_MREQ => IB_MREQ, - SEL => IBSEL_SSR0 + SEL => IBSEL_MMR0 ); - SEL_SSR3 : ib_sel + SEL_MMR3 : ib_sel generic map ( - IB_ADDR => ibaddr_ssr3) + IB_ADDR => ibaddr_mmr3) port map ( CLK => CLK, IB_MREQ => IB_MREQ, - SEL => IBSEL_SSR3 + SEL => IBSEL_MMR3 ); - proc_ibres : process (IBSEL_SSR0, IBSEL_SSR3, IB_MREQ, R_SSR0, R_SSR3) + proc_ibres : process (IBSEL_MMR0, IBSEL_MMR3, IB_MREQ, R_MMR0, R_MMR3) - variable ssr0out : slv16 := (others=>'0'); - variable ssr3out : slv16 := (others=>'0'); + variable mmr0out : slv16 := (others=>'0'); + variable mmr3out : slv16 := (others=>'0'); begin - ssr0out := (others=>'0'); - if IBSEL_SSR0 = '1' then - ssr0out(ssr0_ibf_abo_nonres) := R_SSR0.abo_nonres; - ssr0out(ssr0_ibf_abo_length) := R_SSR0.abo_length; - ssr0out(ssr0_ibf_abo_rdonly) := R_SSR0.abo_rdonly; - ssr0out(ssr0_ibf_trap_mmu) := R_SSR0.trap_mmu; - ssr0out(ssr0_ibf_ena_trap) := R_SSR0.ena_trap; - ssr0out(ssr0_ibf_inst_compl) := R_SSR0.inst_compl; - ssr0out(ssr0_ibf_seg_mode) := R_SSR0.seg_mode; - ssr0out(ssr0_ibf_dspace) := R_SSR0.dspace; - ssr0out(ssr0_ibf_seg_num) := R_SSR0.seg_num; - ssr0out(ssr0_ibf_ena_mmu) := R_SSR0.ena_mmu; + mmr0out := (others=>'0'); + if IBSEL_MMR0 = '1' then + mmr0out(mmr0_ibf_abo_nonres) := R_MMR0.abo_nonres; + mmr0out(mmr0_ibf_abo_length) := R_MMR0.abo_length; + mmr0out(mmr0_ibf_abo_rdonly) := R_MMR0.abo_rdonly; + mmr0out(mmr0_ibf_trap_mmu) := R_MMR0.trap_mmu; + mmr0out(mmr0_ibf_ena_trap) := R_MMR0.ena_trap; + mmr0out(mmr0_ibf_inst_compl) := R_MMR0.inst_compl; + mmr0out(mmr0_ibf_page_mode) := R_MMR0.page_mode; + mmr0out(mmr0_ibf_dspace) := R_MMR0.dspace; + mmr0out(mmr0_ibf_page_num) := R_MMR0.page_num; + mmr0out(mmr0_ibf_ena_mmu) := R_MMR0.ena_mmu; end if; - ssr3out := (others=>'0'); - if IBSEL_SSR3 = '1' then - ssr3out(ssr3_ibf_ena_ubmap) := R_SSR3.ena_ubmap; - ssr3out(ssr3_ibf_ena_22bit) := R_SSR3.ena_22bit; - ssr3out(ssr3_ibf_dspace_km) := R_SSR3.dspace_km; - ssr3out(ssr3_ibf_dspace_sm) := R_SSR3.dspace_sm; - ssr3out(ssr3_ibf_dspace_um) := R_SSR3.dspace_um; + mmr3out := (others=>'0'); + if IBSEL_MMR3 = '1' then + mmr3out(mmr3_ibf_ena_ubmap) := R_MMR3.ena_ubmap; + mmr3out(mmr3_ibf_ena_22bit) := R_MMR3.ena_22bit; + mmr3out(mmr3_ibf_dspace_km) := R_MMR3.dspace_km; + mmr3out(mmr3_ibf_dspace_sm) := R_MMR3.dspace_sm; + mmr3out(mmr3_ibf_dspace_um) := R_MMR3.dspace_um; end if; - IB_SRES_SSR03.dout <= ssr0out or ssr3out; - IB_SRES_SSR03.ack <= (IBSEL_SSR0 or IBSEL_SSR3) and + IB_SRES_MMR03.dout <= mmr0out or mmr3out; + IB_SRES_MMR03.ack <= (IBSEL_MMR0 or IBSEL_MMR3) and (IB_MREQ.re or IB_MREQ.we); -- ack all - IB_SRES_SSR03.busy <= '0'; + IB_SRES_MMR03.busy <= '0'; end process proc_ibres; - proc_ssr0 : process (CLK) + proc_mmr0 : process (CLK) begin if rising_edge(CLK) then if BRESET = '1' then - R_SSR0 <= mmu_ssr0_init; + R_MMR0 <= mmu_mmr0_init; else - R_SSR0 <= N_SSR0; + R_MMR0 <= N_MMR0; end if; end if; - end process proc_ssr0; + end process proc_mmr0; - proc_ssr3 : process (CLK) + proc_mmr3 : process (CLK) begin if rising_edge(CLK) then if BRESET = '1' then - R_SSR3 <= mmu_ssr3_init; - elsif IBSEL_SSR3='1' and IB_MREQ.we='1' then + R_MMR3 <= mmu_mmr3_init; + elsif IBSEL_MMR3='1' and IB_MREQ.we='1' then if IB_MREQ.be0 = '1' then - R_SSR3.ena_ubmap <= IB_MREQ.din(ssr3_ibf_ena_ubmap); - R_SSR3.ena_22bit <= IB_MREQ.din(ssr3_ibf_ena_22bit); - R_SSR3.dspace_km <= IB_MREQ.din(ssr3_ibf_dspace_km); - R_SSR3.dspace_sm <= IB_MREQ.din(ssr3_ibf_dspace_sm); - R_SSR3.dspace_um <= IB_MREQ.din(ssr3_ibf_dspace_um); + R_MMR3.ena_ubmap <= IB_MREQ.din(mmr3_ibf_ena_ubmap); + R_MMR3.ena_22bit <= IB_MREQ.din(mmr3_ibf_ena_22bit); + R_MMR3.dspace_km <= IB_MREQ.din(mmr3_ibf_dspace_km); + R_MMR3.dspace_sm <= IB_MREQ.din(mmr3_ibf_dspace_sm); + R_MMR3.dspace_um <= IB_MREQ.din(mmr3_ibf_dspace_um); end if; end if; end if; - end process proc_ssr3; + end process proc_mmr3; - proc_paddr : process (R_SSR0, R_SSR3, CNTL, SARSDR, VADDR) + proc_paddr : process (R_MMR0, R_MMR3, CNTL, PARPDR, VADDR) variable ipaddrh : slv16 := (others=>'0'); variable dspace_ok : slbit := '0'; variable dspace_en : slbit := '0'; - variable asf : slv3 := (others=>'0'); -- va: active segment field + variable apf : slv3 := (others=>'0'); -- va: active page field variable bn : slv7 := (others=>'0'); -- va: block number - variable iasn : slv4 := (others=>'0');-- augmented segment number + variable iapn : slv4 := (others=>'0');-- augmented page number begin - asf := VADDR(15 downto 13); + apf := VADDR(15 downto 13); bn := VADDR(12 downto 6); dspace_en := '0'; case CNTL.mode is - when "00" => dspace_en := R_SSR3.dspace_km; - when "01" => dspace_en := R_SSR3.dspace_sm; - when "11" => dspace_en := R_SSR3.dspace_um; + when "00" => dspace_en := R_MMR3.dspace_km; + when "01" => dspace_en := R_MMR3.dspace_sm; + when "11" => dspace_en := R_MMR3.dspace_um; when others => null; end case; dspace_ok := CNTL.dspace and dspace_en; - iasn(3) := dspace_ok; - iasn(2 downto 0) := asf; + iapn(3) := dspace_ok; + iapn(2 downto 0) := apf; - ipaddrh := slv(unsigned("000000000"&bn) + unsigned(SARSDR.saf)); + ipaddrh := slv(unsigned("000000000"&bn) + unsigned(PARPDR.paf)); DSPACE <= dspace_ok; - ASN <= iasn; + APN <= iapn; PADDRH <= ipaddrh; end process proc_paddr; - proc_nssr0 : process (R_SSR0, R_SSR3, IB_MREQ, IBSEL_SSR0, DSPACE, - CNTL, MONI, SARSDR, VADDR) + proc_nmmr0 : process (R_MMR0, R_MMR3, IB_MREQ, IBSEL_MMR0, DSPACE, + CNTL, MONI, PARPDR, VADDR) - variable nssr0 : mmu_ssr0_type := mmu_ssr0_init; - variable asf : slv3 := (others=>'0'); - variable bn : slv7 := (others=>'0'); + variable nmmr0 : mmu_mmr0_type := mmu_mmr0_init; + variable apf : slv3 := (others=>'0'); + variable bn : slv7 := (others=>'0'); variable abo_nonres : slbit := '0'; variable abo_length : slbit := '0'; variable abo_rdonly : slbit := '0'; - variable ssr_freeze : slbit := '0'; + variable mmr_freeze : slbit := '0'; variable doabort : slbit := '0'; variable dotrap : slbit := '0'; variable dotrace : slbit := '0'; begin - nssr0 := R_SSR0; + nmmr0 := R_MMR0; AIB_WE <= '0'; AIB_SETA <= '0'; AIB_SETW <= '0'; - ssr_freeze := R_SSR0.abo_nonres or R_SSR0.abo_length or R_SSR0.abo_rdonly; - dotrace := not(CNTL.cacc or ssr_freeze); + mmr_freeze := R_MMR0.abo_nonres or R_MMR0.abo_length or R_MMR0.abo_rdonly; + dotrace := not(CNTL.cacc or mmr_freeze); - asf := VADDR(15 downto 13); + apf := VADDR(15 downto 13); bn := VADDR(12 downto 6); abo_nonres := '0'; @@ -286,19 +287,19 @@ begin doabort := '0'; dotrap := '0'; - if SARSDR.ed = '0' then -- ed=0: upward expansion - if unsigned(bn) > unsigned(SARSDR.slf) then + if PARPDR.ed = '0' then -- ed=0: upward expansion + if unsigned(bn) > unsigned(PARPDR.plf) then abo_length := '1'; end if; else -- ed=0: downward expansion - if unsigned(bn) < unsigned(SARSDR.slf) then + if unsigned(bn) < unsigned(PARPDR.plf) then abo_length := '1'; end if; end if; - case SARSDR.acf is -- evaluate accecc control field + case PARPDR.acf is -- evaluate accecc control field - when "000" => -- segment non-resident + when "000" => -- page non-resident abo_nonres := '1'; when "001" => -- read-only; trap on read @@ -324,35 +325,35 @@ begin abo_nonres := '1'; end case; - if IBSEL_SSR0='1' and IB_MREQ.we='1' then + if IBSEL_MMR0='1' and IB_MREQ.we='1' then if IB_MREQ.be1 = '1' then - nssr0.abo_nonres := IB_MREQ.din(ssr0_ibf_abo_nonres); - nssr0.abo_length := IB_MREQ.din(ssr0_ibf_abo_length); - nssr0.abo_rdonly := IB_MREQ.din(ssr0_ibf_abo_rdonly); - nssr0.trap_mmu := IB_MREQ.din(ssr0_ibf_trap_mmu); - nssr0.ena_trap := IB_MREQ.din(ssr0_ibf_ena_trap); + nmmr0.abo_nonres := IB_MREQ.din(mmr0_ibf_abo_nonres); + nmmr0.abo_length := IB_MREQ.din(mmr0_ibf_abo_length); + nmmr0.abo_rdonly := IB_MREQ.din(mmr0_ibf_abo_rdonly); + nmmr0.trap_mmu := IB_MREQ.din(mmr0_ibf_trap_mmu); + nmmr0.ena_trap := IB_MREQ.din(mmr0_ibf_ena_trap); end if; if IB_MREQ.be0 = '1' then - nssr0.ena_mmu := IB_MREQ.din(ssr0_ibf_ena_mmu); - end if; + nmmr0.ena_mmu := IB_MREQ.din(mmr0_ibf_ena_mmu); + end if; - elsif nssr0.ena_mmu='1' and CNTL.cacc='0' then + elsif nmmr0.ena_mmu='1' and CNTL.cacc='0' then if dotrace = '1' then if MONI.istart = '1' then - nssr0.inst_compl := '0'; + nmmr0.inst_compl := '0'; elsif MONI.idone = '1' then - nssr0.inst_compl := '0'; -- disable instr.compl logic + nmmr0.inst_compl := '0'; -- disable instr.compl logic end if; end if; - if CNTL.req = '1' then - AIB_WE <= '1'; - if ssr_freeze = '0' then - nssr0.abo_nonres := abo_nonres; - nssr0.abo_length := abo_length; - nssr0.abo_rdonly := abo_rdonly; + if CNTL.req = '1' then + AIB_WE <= '1'; + if mmr_freeze = '0' then + nmmr0.abo_nonres := abo_nonres; + nmmr0.abo_length := abo_length; + nmmr0.abo_rdonly := abo_rdonly; end if; doabort := abo_nonres or abo_length or abo_rdonly; @@ -361,46 +362,46 @@ begin AIB_SETW <= CNTL.wacc or CNTL.macc; end if; - if ssr_freeze = '0' then - nssr0.dspace := DSPACE; - nssr0.seg_num := asf; - nssr0.seg_mode := CNTL.mode; + if mmr_freeze = '0' then + nmmr0.dspace := DSPACE; + nmmr0.page_num := apf; + nmmr0.page_mode := CNTL.mode; end if; end if; end if; - if CNTL.req='1' and R_SSR0.ena_mmu='1' and CNTL.cacc='0' and + if CNTL.req='1' and R_MMR0.ena_mmu='1' and CNTL.cacc='0' and dotrap='1' then - nssr0.trap_mmu := '1'; + nmmr0.trap_mmu := '1'; end if; - nssr0.trace_prev := dotrace; + nmmr0.trace_prev := dotrace; if MONI.trace_prev = '0' then TRACE <= dotrace; else - TRACE <= R_SSR0.trace_prev; + TRACE <= R_MMR0.trace_prev; end if; - N_SSR0 <= nssr0; + N_MMR0 <= nmmr0; - if R_SSR0.ena_mmu='1' and CNTL.cacc='0' then + if R_MMR0.ena_mmu='1' and CNTL.cacc='0' then STAT.vaok <= not doabort; else STAT.vaok <= '1'; end if; - if R_SSR0.ena_mmu='1' and CNTL.cacc='0' and doabort='0' and - R_SSR0.ena_trap='1' and R_SSR0.trap_mmu='0' and dotrap='1' then + if R_MMR0.ena_mmu='1' and CNTL.cacc='0' and doabort='0' and + R_MMR0.ena_trap='1' and R_MMR0.trap_mmu='0' and dotrap='1' then STAT.trap <= '1'; else STAT.trap <= '0'; end if; - STAT.ena_mmu <= R_SSR0.ena_mmu; - STAT.ena_22bit <= R_SSR3.ena_22bit; - STAT.ena_ubmap <= R_SSR3.ena_ubmap; + STAT.ena_mmu <= R_MMR0.ena_mmu; + STAT.ena_22bit <= R_MMR3.ena_22bit; + STAT.ena_ubmap <= R_MMR3.ena_ubmap; - end process proc_nssr0; + end process proc_nmmr0; end syn; diff --git a/rtl/w11a/pdp11_mmu_mmr12.vhd b/rtl/w11a/pdp11_mmu_mmr12.vhd index 7cc9e121..e21e33c5 100644 --- a/rtl/w11a/pdp11_mmu_mmr12.vhd +++ b/rtl/w11a/pdp11_mmu_mmr12.vhd @@ -1,18 +1,19 @@ --- $Id: pdp11_mmu_ssr12.vhd 1181 2019-07-08 17:00:50Z mueller $ +-- $Id: pdp11_mmu_mmr12.vhd 1279 2022-08-14 08:02:21Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later --- Copyright 2006-2011 by Walter F.J. Mueller +-- Copyright 2006-2022 by Walter F.J. Mueller -- ------------------------------------------------------------------------------ --- Module Name: pdp11_mmu_ssr12 - syn --- Description: pdp11: mmu register ssr1 and ssr2 +-- Module Name: pdp11_mmu_mmr12 - syn +-- Description: pdp11: mmu register mmr1 and mmr2 -- -- Dependencies: ib_sel -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 +-- Tool versions: ise 8.2-14.7; viv 2014.4-2022.1; ghdl 0.18-2.0.0 -- --- Revision History: +-- Revision History: -- Date Rev Version Comment +-- 2022-08-13 1279 1.2.3 ssr->mmr rename -- 2011-11-18 427 1.2.2 now numeric_std clean -- 2010-10-23 335 1.2.1 use ib_sel -- 2010-10-17 333 1.2 use ibus V2 interface @@ -22,7 +23,7 @@ -- 2008-01-05 110 1.1.1 rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy) -- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now -- 2007-06-14 56 1.0.1 Use slvtypes.all --- 2007-05-12 26 1.0 Initial version +-- 2007-05-12 26 1.0 Initial version ------------------------------------------------------------------------------ library ieee; @@ -35,7 +36,7 @@ use work.pdp11.all; -- ---------------------------------------------------------------------------- -entity pdp11_mmu_ssr12 is -- mmu register ssr1 and ssr2 +entity pdp11_mmu_mmr12 is -- mmu register mmr1 and mmr2 port ( CLK : in slbit; -- clock CRESET : in slbit; -- cpu reset @@ -44,64 +45,64 @@ entity pdp11_mmu_ssr12 is -- mmu register ssr1 and ssr2 IB_MREQ : in ib_mreq_type; -- ibus request IB_SRES : out ib_sres_type -- ibus response ); -end pdp11_mmu_ssr12; +end pdp11_mmu_mmr12; -architecture syn of pdp11_mmu_ssr12 is +architecture syn of pdp11_mmu_mmr12 is - constant ibaddr_ssr1 : slv16 := slv(to_unsigned(8#177574#,16)); - constant ibaddr_ssr2 : slv16 := slv(to_unsigned(8#177576#,16)); + constant ibaddr_mmr1 : slv16 := slv(to_unsigned(8#177574#,16)); + constant ibaddr_mmr2 : slv16 := slv(to_unsigned(8#177576#,16)); - subtype ssr1_ibf_rb_delta is integer range 15 downto 11; - subtype ssr1_ibf_rb_num is integer range 10 downto 8; - subtype ssr1_ibf_ra_delta is integer range 7 downto 3; - subtype ssr1_ibf_ra_num is integer range 2 downto 0; + subtype mmr1_ibf_rb_delta is integer range 15 downto 11; + subtype mmr1_ibf_rb_num is integer range 10 downto 8; + subtype mmr1_ibf_ra_delta is integer range 7 downto 3; + subtype mmr1_ibf_ra_num is integer range 2 downto 0; - signal IBSEL_SSR1 : slbit := '0'; - signal IBSEL_SSR2 : slbit := '0'; - signal R_SSR1 : mmu_ssr1_type := mmu_ssr1_init; - signal R_SSR2 : slv16 := (others=>'0'); - signal N_SSR1 : mmu_ssr1_type := mmu_ssr1_init; - signal N_SSR2 : slv16 := (others=>'0'); + signal IBSEL_MMR1 : slbit := '0'; + signal IBSEL_MMR2 : slbit := '0'; + signal R_MMR1 : mmu_mmr1_type := mmu_mmr1_init; + signal R_MMR2 : slv16 := (others=>'0'); + signal N_MMR1 : mmu_mmr1_type := mmu_mmr1_init; + signal N_MMR2 : slv16 := (others=>'0'); begin - SEL_SSR1 : ib_sel + SEL_MMR1 : ib_sel generic map ( - IB_ADDR => ibaddr_ssr1) + IB_ADDR => ibaddr_mmr1) port map ( CLK => CLK, IB_MREQ => IB_MREQ, - SEL => IBSEL_SSR1 + SEL => IBSEL_MMR1 ); - SEL_SSR2 : ib_sel + SEL_MMR2 : ib_sel generic map ( - IB_ADDR => ibaddr_ssr2) + IB_ADDR => ibaddr_mmr2) port map ( CLK => CLK, IB_MREQ => IB_MREQ, - SEL => IBSEL_SSR2 + SEL => IBSEL_MMR2 ); - proc_ibres : process (IBSEL_SSR1, IBSEL_SSR2, IB_MREQ, R_SSR1, R_SSR2) - variable ssr1out : slv16 := (others=>'0'); - variable ssr2out : slv16 := (others=>'0'); + proc_ibres : process (IBSEL_MMR1, IBSEL_MMR2, IB_MREQ, R_MMR1, R_MMR2) + variable mmr1out : slv16 := (others=>'0'); + variable mmr2out : slv16 := (others=>'0'); begin - ssr1out := (others=>'0'); - if IBSEL_SSR1 = '1' then - ssr1out(ssr1_ibf_rb_delta) := R_SSR1.rb_delta; - ssr1out(ssr1_ibf_rb_num) := R_SSR1.rb_num; - ssr1out(ssr1_ibf_ra_delta) := R_SSR1.ra_delta; - ssr1out(ssr1_ibf_ra_num) := R_SSR1.ra_num; + mmr1out := (others=>'0'); + if IBSEL_MMR1 = '1' then + mmr1out(mmr1_ibf_rb_delta) := R_MMR1.rb_delta; + mmr1out(mmr1_ibf_rb_num) := R_MMR1.rb_num; + mmr1out(mmr1_ibf_ra_delta) := R_MMR1.ra_delta; + mmr1out(mmr1_ibf_ra_num) := R_MMR1.ra_num; end if; - ssr2out := (others=>'0'); - if IBSEL_SSR2 = '1' then - ssr2out := R_SSR2; + mmr2out := (others=>'0'); + if IBSEL_MMR2 = '1' then + mmr2out := R_MMR2; end if; - IB_SRES.dout <= ssr1out or ssr2out; - IB_SRES.ack <= (IBSEL_SSR1 or IBSEL_SSR2) and + IB_SRES.dout <= mmr1out or mmr2out; + IB_SRES.ack <= (IBSEL_MMR1 or IBSEL_MMR2) and (IB_MREQ.re or IB_MREQ.we); -- ack all IB_SRES.busy <= '0'; @@ -110,74 +111,74 @@ begin proc_regs : process (CLK) begin if rising_edge(CLK) then - R_SSR1 <= N_SSR1; - R_SSR2 <= N_SSR2; + R_MMR1 <= N_MMR1; + R_MMR2 <= N_MMR2; end if; end process proc_regs; - proc_comb : process (CRESET, IBSEL_SSR1, IB_MREQ, - R_SSR1, R_SSR2, TRACE, MONI) + proc_comb : process (CRESET, IBSEL_MMR1, IB_MREQ, + R_MMR1, R_MMR2, TRACE, MONI) - variable nssr1 : mmu_ssr1_type := mmu_ssr1_init; - variable nssr2 : slv16 := (others=>'0'); + variable nmmr1 : mmu_mmr1_type := mmu_mmr1_init; + variable nmmr2 : slv16 := (others=>'0'); variable delta : slv5 := (others=>'0'); variable use_rb : slbit := '0'; begin - nssr1 := R_SSR1; - nssr2 := R_SSR2; + nmmr1 := R_MMR1; + nmmr2 := R_MMR2; delta := "0" & MONI.delta; use_rb := '0'; - if MONI.regnum/=nssr1.ra_num and unsigned(nssr1.ra_delta)/=0 then + if MONI.regnum/=nmmr1.ra_num and unsigned(nmmr1.ra_delta)/=0 then use_rb := '1'; end if; if CRESET = '1' then - nssr1 := mmu_ssr1_init; - nssr2 := (others=>'0'); + nmmr1 := mmu_mmr1_init; + nmmr2 := (others=>'0'); - elsif IBSEL_SSR1='1' and IB_MREQ.we='1' then + elsif IBSEL_MMR1='1' and IB_MREQ.we='1' then if IB_MREQ.be1 = '1' then - nssr1.rb_delta := IB_MREQ.din(ssr1_ibf_rb_delta); - nssr1.rb_num := IB_MREQ.din(ssr1_ibf_rb_num); + nmmr1.rb_delta := IB_MREQ.din(mmr1_ibf_rb_delta); + nmmr1.rb_num := IB_MREQ.din(mmr1_ibf_rb_num); end if; if IB_MREQ.be0 = '1' then - nssr1.ra_delta := IB_MREQ.din(ssr1_ibf_ra_delta); - nssr1.ra_num := IB_MREQ.din(ssr1_ibf_ra_num); + nmmr1.ra_delta := IB_MREQ.din(mmr1_ibf_ra_delta); + nmmr1.ra_num := IB_MREQ.din(mmr1_ibf_ra_num); end if; elsif TRACE = '1' then if MONI.istart = '1' then - nssr1 := mmu_ssr1_init; - nssr2 := MONI.pc; + nmmr1 := mmu_mmr1_init; + nmmr2 := MONI.pc; elsif MONI.regmod = '1' then if use_rb = '0' then - nssr1.ra_num := MONI.regnum; + nmmr1.ra_num := MONI.regnum; if MONI.isdec = '0' then - nssr1.ra_delta := slv(signed(nssr1.ra_delta) + signed(delta)); + nmmr1.ra_delta := slv(signed(nmmr1.ra_delta) + signed(delta)); else - nssr1.ra_delta := slv(signed(nssr1.ra_delta) - signed(delta)); + nmmr1.ra_delta := slv(signed(nmmr1.ra_delta) - signed(delta)); end if; else - nssr1.rb_num := MONI.regnum; + nmmr1.rb_num := MONI.regnum; if MONI.isdec = '0' then - nssr1.rb_delta := slv(signed(nssr1.rb_delta) + signed(delta)); + nmmr1.rb_delta := slv(signed(nmmr1.rb_delta) + signed(delta)); else - nssr1.rb_delta := slv(signed(nssr1.rb_delta) - signed(delta)); + nmmr1.rb_delta := slv(signed(nmmr1.rb_delta) - signed(delta)); end if; end if; end if; end if; - N_SSR1 <= nssr1; - N_SSR2 <= nssr2; + N_MMR1 <= nmmr1; + N_MMR2 <= nmmr2; - end process proc_comb; + end process proc_comb; end syn; diff --git a/rtl/w11a/pdp11_mmu_padr.vhd b/rtl/w11a/pdp11_mmu_padr.vhd index 37c32222..dc3b1da4 100644 --- a/rtl/w11a/pdp11_mmu_padr.vhd +++ b/rtl/w11a/pdp11_mmu_padr.vhd @@ -1,19 +1,20 @@ --- $Id: pdp11_mmu_sadr.vhd 1181 2019-07-08 17:00:50Z mueller $ +-- $Id: pdp11_mmu_padr.vhd 1279 2022-08-14 08:02:21Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later --- Copyright 2006-2011 by Walter F.J. Mueller +-- Copyright 2006-2022 by Walter F.J. Mueller -- ------------------------------------------------------------------------------ -- Module Name: pdp11_mmu_sadr - syn --- Description: pdp11: mmu SAR/SDR register set +-- Description: pdp11: mmu PAR/PDR register set -- -- Dependencies: memlib/ram_1swar_gen -- -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 +-- Tool versions: ise 8.2-14.7; viv 2014.4-2022.1; ghdl 0.18-2.0.0 -- --- Revision History: +-- Revision History: -- Date Rev Version Comment +-- 2022-08-13 1279 1.3.4 ssr->mmr rename -- 2011-11-18 427 1.3.3 now numeric_std clean -- 2010-12-30 351 1.3.2 BUGFIX: fix sensitivity list of proc_eaddr -- 2010-10-23 335 1.3.1 change proc_eaddr logic, shorten logic path @@ -27,7 +28,7 @@ -- 2007-12-30 108 1.1.1 use ubf_byte[01]; move SADR memory address mux here -- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now -- 2007-06-14 56 1.0.1 Use slvtypes.all --- 2007-05-12 26 1.0 Initial version +-- 2007-05-12 26 1.0 Initial version ------------------------------------------------------------------------------ library ieee; @@ -41,21 +42,21 @@ use work.pdp11.all; -- ---------------------------------------------------------------------------- -entity pdp11_mmu_sadr is -- mmu SAR/SDR register set +entity pdp11_mmu_padr is -- mmu PAR/PDR register set port ( CLK : in slbit; -- clock MODE : in slv2; -- mode - ASN : in slv4; -- augmented segment number (1+3 bit) + APN : in slv4; -- augmented page number (1+3 bit) AIB_WE : in slbit; -- update AIB AIB_SETA : in slbit; -- set access AIB AIB_SETW : in slbit; -- set write AIB - SARSDR : out sarsdr_type; -- combined SAR/SDR + PARPDR : out parpdr_type; -- combined PAR/PDR IB_MREQ : in ib_mreq_type; -- ibus request IB_SRES : out ib_sres_type -- ibus response ); -end pdp11_mmu_sadr; +end pdp11_mmu_padr; -architecture syn of pdp11_mmu_sadr is +architecture syn of pdp11_mmu_padr is -- bit 1 111 1 -- bit 5 432 109 876 543 210 @@ -73,85 +74,85 @@ architecture syn of pdp11_mmu_sadr is constant ibaddr_smdar : slv16 := slv(to_unsigned(8#172200#,16)); constant ibaddr_umdar : slv16 := slv(to_unsigned(8#177600#,16)); - subtype sdr_ibf_slf is integer range 14 downto 8; - subtype sdr_ibf_aib is integer range 7 downto 6; - subtype sdr_ibf_acf is integer range 3 downto 0; + subtype pdr_ibf_plf is integer range 14 downto 8; + subtype pdr_ibf_aib is integer range 7 downto 6; + subtype pdr_ibf_acf is integer range 3 downto 0; - signal SADR_ADDR : slv6 := (others=>'0'); -- address (from mmu or ibus) + signal PADR_ADDR : slv6 := (others=>'0'); -- address (from mmu or ibus) - signal SAR_HIGH_WE : slbit := '0'; -- write enables - signal SAR_LOW_WE : slbit := '0'; -- ... - signal SDR_SLF_WE : slbit := '0'; -- ... - signal SDR_AIB_WE : slbit := '0'; -- ... - signal SDR_LOW_WE : slbit := '0'; -- ... + signal PAR_HIGH_WE : slbit := '0'; -- write enables + signal PAR_LOW_WE : slbit := '0'; -- ... + signal PDR_PLF_WE : slbit := '0'; -- ... + signal PDR_AIB_WE : slbit := '0'; -- ... + signal PDR_LOW_WE : slbit := '0'; -- ... signal R_IBSEL_DR : slbit := '0'; -- DR's selected from ibus signal R_IBSEL_AR : slbit := '0'; -- AR's selected from ibus - signal SAF : slv16 := (others=>'0'); -- current SAF - signal SLF : slv7 := (others=>'0'); -- current SLF + signal PAF : slv16 := (others=>'0'); -- current PAF + signal PLF : slv7 := (others=>'0'); -- current PLF signal AIB : slv2 := "00"; -- current AIB flags signal N_AIB : slv2 := "00"; -- next AIB flags signal ED_ACF : slv4 := "0000"; -- current ED & ACF begin - SAR_HIGH : ram_1swar_gen + PAR_HIGH : ram_1swar_gen generic map ( AWIDTH => 6, DWIDTH => 8) port map ( CLK => CLK, - WE => SAR_HIGH_WE, - ADDR => SADR_ADDR, + WE => PAR_HIGH_WE, + ADDR => PADR_ADDR, DI => IB_MREQ.din(ibf_byte1), - DO => SAF(ibf_byte1)); + DO => PAF(ibf_byte1)); - SAR_LOW : ram_1swar_gen + PAR_LOW : ram_1swar_gen generic map ( AWIDTH => 6, DWIDTH => 8) port map ( CLK => CLK, - WE => SAR_LOW_WE, - ADDR => SADR_ADDR, + WE => PAR_LOW_WE, + ADDR => PADR_ADDR, DI => IB_MREQ.din(ibf_byte0), - DO => SAF(ibf_byte0)); + DO => PAF(ibf_byte0)); - SDR_SLF : ram_1swar_gen + PDR_PLF : ram_1swar_gen generic map ( AWIDTH => 6, DWIDTH => 7) port map ( CLK => CLK, - WE => SDR_SLF_WE, - ADDR => SADR_ADDR, - DI => IB_MREQ.din(sdr_ibf_slf), - DO => SLF); + WE => PDR_PLF_WE, + ADDR => PADR_ADDR, + DI => IB_MREQ.din(pdr_ibf_plf), + DO => PLF); - SDR_AIB : ram_1swar_gen + PDR_AIB : ram_1swar_gen generic map ( AWIDTH => 6, DWIDTH => 2) port map ( CLK => CLK, - WE => SDR_AIB_WE, - ADDR => SADR_ADDR, + WE => PDR_AIB_WE, + ADDR => PADR_ADDR, DI => N_AIB, DO => AIB); - SDR_LOW : ram_1swar_gen + PDR_LOW : ram_1swar_gen generic map ( AWIDTH => 6, DWIDTH => 4) port map ( CLK => CLK, - WE => SDR_LOW_WE, - ADDR => SADR_ADDR, - DI => IB_MREQ.din(sdr_ibf_acf), + WE => PDR_LOW_WE, + ADDR => PADR_ADDR, + DI => IB_MREQ.din(pdr_ibf_acf), DO => ED_ACF); - -- determine IBSEL's and the address for accessing the SADR's + -- determine IBSEL's and the address for accessing the PADR's proc_ibsel: process (CLK) variable ibsel_dr : slbit := '0'; @@ -176,24 +177,24 @@ begin end if; end process proc_ibsel; - proc_ibres : process (R_IBSEL_DR, R_IBSEL_AR, IB_MREQ, SAF, SLF, AIB, ED_ACF) - variable sarout : slv16 := (others=>'0'); -- IB sar out - variable sdrout : slv16 := (others=>'0'); -- IB sdr out + proc_ibres : process (R_IBSEL_DR, R_IBSEL_AR, IB_MREQ, PAF, PLF, AIB, ED_ACF) + variable parout : slv16 := (others=>'0'); -- IB par out + variable pdrout : slv16 := (others=>'0'); -- IB pdr out begin - sarout := (others=>'0'); + parout := (others=>'0'); if R_IBSEL_AR = '1' then - sarout := SAF; + parout := PAF; end if; - sdrout := (others=>'0'); + pdrout := (others=>'0'); if R_IBSEL_DR = '1' then - sdrout(sdr_ibf_slf) := SLF; - sdrout(sdr_ibf_aib) := AIB; - sdrout(sdr_ibf_acf) := ED_ACF; + pdrout(pdr_ibf_plf) := PLF; + pdrout(pdr_ibf_aib) := AIB; + pdrout(pdr_ibf_acf) := ED_ACF; end if; - IB_SRES.dout <= sarout or sdrout; + IB_SRES.dout <= parout or pdrout; IB_SRES.ack <= (R_IBSEL_DR or R_IBSEL_AR) and (IB_MREQ.re or IB_MREQ.we); -- ack all IB_SRES.busy <= '0'; @@ -206,13 +207,13 @@ begin -- and reduce the eaddr mux to a 4-input LUT. Last resort is a 2 cycle ibus -- access with a state flop marking the 2nd cycle of a re/we transaction. - proc_eaddr: process (IB_MREQ, MODE, ASN, R_IBSEL_DR, R_IBSEL_AR) + proc_eaddr: process (IB_MREQ, MODE, APN, R_IBSEL_DR, R_IBSEL_AR) variable eaddr : slv6 := (others=>'0'); variable idr : slbit := '0'; variable iar : slbit := '0'; begin - eaddr := MODE & ASN; + eaddr := MODE & APN; if (R_IBSEL_DR='1' or R_IBSEL_AR='1') and (IB_MREQ.re='1' or IB_MREQ.we='1') then @@ -221,57 +222,57 @@ begin eaddr(3 downto 0) := IB_MREQ.addr(4 downto 1); end if; - SADR_ADDR <= eaddr; + PADR_ADDR <= eaddr; end process proc_eaddr; proc_comb : process (R_IBSEL_AR, R_IBSEL_DR, IB_MREQ, AIB_WE, AIB_SETA, AIB_SETW, - SAF, SLF, AIB, ED_ACF) - begin + PAF, PLF, AIB, ED_ACF) + begin N_AIB <= "00"; - SAR_HIGH_WE <= '0'; - SAR_LOW_WE <= '0'; - SDR_SLF_WE <= '0'; - SDR_AIB_WE <= '0'; - SDR_LOW_WE <= '0'; + PAR_HIGH_WE <= '0'; + PAR_LOW_WE <= '0'; + PDR_PLF_WE <= '0'; + PDR_AIB_WE <= '0'; + PDR_LOW_WE <= '0'; if IB_MREQ.we = '1' then if R_IBSEL_AR = '1' then if IB_MREQ.be1 = '1' then - SAR_HIGH_WE <= '1'; + PAR_HIGH_WE <= '1'; end if; if IB_MREQ.be0 = '1' then - SAR_LOW_WE <= '1'; + PAR_LOW_WE <= '1'; end if; end if; if R_IBSEL_DR = '1' then if IB_MREQ.be1 = '1' then - SDR_SLF_WE <= '1'; + PDR_PLF_WE <= '1'; end if; if IB_MREQ.be0 = '1' then - SDR_LOW_WE <= '1'; + PDR_LOW_WE <= '1'; end if; end if; if (R_IBSEL_AR or R_IBSEL_DR)='1' then N_AIB <= "00"; - SDR_AIB_WE <= '1'; + PDR_AIB_WE <= '1'; end if; end if; if AIB_WE = '1' then N_AIB(0) <= AIB(0) or AIB_SETW; N_AIB(1) <= AIB(1) or AIB_SETA; - SDR_AIB_WE <= '1'; + PDR_AIB_WE <= '1'; end if; - SARSDR.saf <= SAF; - SARSDR.slf <= SLF; - SARSDR.ed <= ED_ACF(3); - SARSDR.acf <= ED_ACF(2 downto 0); + PARPDR.paf <= PAF; + PARPDR.plf <= PLF; + PARPDR.ed <= ED_ACF(3); + PARPDR.acf <= ED_ACF(2 downto 0); end process proc_comb; diff --git a/rtl/w11a/pdp11_sequencer.vhd b/rtl/w11a/pdp11_sequencer.vhd index c2439159..06e1b3b6 100644 --- a/rtl/w11a/pdp11_sequencer.vhd +++ b/rtl/w11a/pdp11_sequencer.vhd @@ -1,6 +1,6 @@ --- $Id: pdp11_sequencer.vhd 1203 2019-08-19 21:41:03Z mueller $ +-- $Id: pdp11_sequencer.vhd 1279 2022-08-14 08:02:21Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later --- Copyright 2006-2019 by Walter F.J. Mueller +-- Copyright 2006-2022 by Walter F.J. Mueller -- ------------------------------------------------------------------------------ -- Module Name: pdp11_sequencer - syn @@ -9,10 +9,11 @@ -- Dependencies: ib_sel -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: ise 8.2-14.7; viv 2014.4-2019.1; ghdl 0.18-0.36 +-- Tool versions: ise 8.2-14.7; viv 2014.4-2022.1; ghdl 0.18-2.0.0 -- -- Revision History: -- Date Rev Version Comment +-- 2022-08-13 1279 1.6.13 ssr->mmr rename -- 2019-08-17 1203 1.6.12 fix for ghdl V0.36 -Whide warnings -- 2018-10-07 1054 1.6.11 drop ITIMER, use DM_STAT_SE.itimer -- 2018-10-06 1053 1.6.10 add DM_STAT_SE.(cpbusy,idec,pcload) @@ -1375,7 +1376,7 @@ begin if R_STATUS.do_gprwe = '1' then nmmumoni.regmod := '1'; nmmumoni.isdec := '0'; - nmmumoni.trace_prev := '1'; -- ssr freeze of prev state + nmmumoni.trace_prev := '1'; -- mmr freeze of prev state ndpcntl.gpr_we := '1'; -- update DST reg end if; nstatus.do_gprwe := '0'; @@ -2144,7 +2145,7 @@ begin when s_trap_disp => -- ----------------------------------- if R_STATUS.trap_mmu = '1' then - nvmcntl.trap_done := '1'; -- mmu trap taken: set ssr0 trap bit + nvmcntl.trap_done := '1'; -- mmu trap taken: set mmr0 trap bit lvector := "0101010"; -- mmu trap: vector (250) elsif R_STATUS.trap_ysv = '1' then lvector := "0000001"; -- ysv trap: vector (4)