mirror of
https://github.com/wfjm/w11.git
synced 2026-05-03 22:59:46 +00:00
tcode: add CPUERR tests; minor changes
- cpu_details.mac: add section A2.* (cpuerr tests) - tcode_exec.scmd: use 3M config; set STOP_SPA to 0
This commit is contained in:
wfjm
@@ -1,5 +1,5 @@
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#!/usr/bin/perl -w
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# $Id: tmuconv 1283 2022-08-22 10:07:58Z mueller $
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# $Id: tmuconv 1303 2022-10-17 17:55:51Z mueller $
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# SPDX-License-Identifier: GPL-3.0-or-later
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# Copyright 2008-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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#
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@@ -1002,7 +1002,7 @@ sub print_help {
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print " --t_id trace instruction decodes\n";
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print " --t_ru trace register updates\n";
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print " --t_em trace em transactions\n";
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print " --t_vf trace onfy vector fetch em transactions\n";
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print " --t_vf trace only vector fetch em transactions\n";
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print " --t_ib trace ib transactions\n";
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print " --t_all trace id,ru,em, and ib transactions\n";
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}
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@@ -1,4 +1,4 @@
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; $Id: cpu_details.mac 1264 2022-07-30 07:42:17Z mueller $
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; $Id: cpu_details.mac 1303 2022-10-17 17:55:51Z mueller $
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; SPDX-License-Identifier: GPL-3.0-or-later
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; Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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;
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@@ -13,6 +13,35 @@
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; Section C: 11/70 specifics
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;
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.include |lib/tcode_std_base.mac|
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.include |lib/defs_mmu.mac|
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;
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; Preface: set up MMU for kernel mode (for some tests) =======================
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;
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mov #kipdr,r0
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mov #<127.*md.plf>!md.arw,r1 ; plf=127; ed=0(up); acf=6(w/r)
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mov r1,(r0)+ ; kipdr0
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mov r1,(r0)+ ; kipdr1
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mov r1,(r0)+ ; kipdr2
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mov r1,(r0)+ ; kipdr3
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mov r1,(r0)+ ; kipdr4
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mov r1,(r0)+ ; kipdr5
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mov r1,(r0)+ ; kipdr6
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mov r1,(r0)+ ; kipdr7
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mov #kipar,r0
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mov #000000,(r0)+ ; kipar0 000000 base
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mov #000200,(r0)+ ; kipar1 020000 base
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mov #000400,(r0)+ ; kipar2 040000 base
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mov #000600,(r0)+ ; kipar3 060000 base
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mov #001000,(r0)+ ; kipar4 100000 base
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mov #001200,(r0)+ ; kipar5 120000 base
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mov #001400,(r0)+ ; kipar6 140000 base
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mov #177600,(r0)+ ; kipar7 (map I/O page)
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;
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; some useful definitions
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kipdr5 = kipdr+12
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kipdr6 = kipdr+14
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kipar6 = kipar+14
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p6base = <6*20000> ; page 6
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;
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; Section A: CPU registers ===================================================
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;
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@@ -114,6 +143,218 @@ ta0101: mov #1000$,v..pir ; setup handler
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;
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9999$: iot ; end of test A1.1
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;
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; Test A2: CPUERR +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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; This sub-section verifies operation of CPUERR register
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;
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; setup for all A2.* tests
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mov #cp.err,r0 ; ptr tp CPUERR
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mov #vhugen,v..iit ; set iit handler
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clr v..iit+2 ; pr0 kernel
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;
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; Test A2.1 -- CPUERR cp.hlt +++++++++++++++++++++++++++++++++++++++++
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; Test cp.hlt: halt in non-kernel mode
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;
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ta0201: mov #177777,(r0) ; clear CPUERR (any write should)
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hcmpeq (r0),#0 ; ensure that CPUERR is zero
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;
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mov #4000$,r2 ; mode list (user,supervisor)
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mov #2,r3 ; number of modes
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;
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1000$: clr r1 ; clear tracer
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mov #3000$,vhustp ; continuation address
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push (r2)+ ; frame: psw
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push #2000$ ; frame: address
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rti ; start user mode code
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halt
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;
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2000$: inc r1 ; proof of execution
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halt ; that will abort
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inc r1
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tst @#001 ; that must abort
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;
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3000$: hcmpeq r1,#1 ; check tracer
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hcmpeq (r0),#cp.hlt ; check CPUERR
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mov #cp.rsv,(r0) ; clear CPUERR (any write should)
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hcmpeq (r0),#0 ; check CPUERR
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;
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sob r3,1000$ ; go for next mode
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;
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br 9999$
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;
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4000$: .word <cp.cmu!cp.pmu> ; user mode
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.word <cp.cms!cp.pms> ; supervisor mode
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;
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9999$: iot ; end of test A2.1
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;
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; Test A2.2 -- CPUERR cp.aer +++++++++++++++++++++++++++++++++++++++++
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; Test cp.aer: address error abort
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;
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ta0202: mov #1000$,vhustp ; continuation address
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tst @#001 ; odd address access
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halt
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1000$: hcmpeq (r0),#cp.aer ; check CPUERR
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clr (r0) ; clear CPUERR (any write should)
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hcmpeq (r0),#0 ; check CPUERR
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;
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9999$: iot ; end of test A2.2
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;
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; Test A2.3 -- CPUERR cp.nxm +++++++++++++++++++++++++++++++++++++++++
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; Test cp.nxm: non-existent memory abort
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; Use unibus map address space (248kB) below the I/O page, the w11
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; will return a non-existent memory abort even in a maximum memory
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; configuration.
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;
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ta0203: cmp systyp,#sy.e11 ; e11 V7.3 return wrong CPUERR value
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beq 9999$
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push kipar6 ; save kipar6
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mov #177400,kipar6
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mov #m3.e22,mmr3 ; 22-bit mode
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mov #m0.ena,mmr0 ; enable mmu ;! MMU 22
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;
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mov #1000$,vhustp ; continuation address
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tst p6base ; access non-existing memory
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halt
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1000$: hcmpeq (r0),#cp.nxm ; check CPUERR
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com (r0) ; clear CPUERR (any write should)
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hcmpeq (r0),#0 ; check CPUERR
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;
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reset ; disable mmu ;! MMU off
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pop kipar6 ; restore kipar6
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9999$: iot ; end of test A2.3
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;
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; Test A2.4 -- CPUERR cp.ito +++++++++++++++++++++++++++++++++++++++++
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; Test cp.ito: unibus timeout abort
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; Use first address in I/O page (160000), always unused in w11
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;
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ta0204: mov #1000$,vhustp ; continuation address
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tst @#160000 ; access non-existing unibus device
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halt
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1000$: hcmpeq (r0),#cp.ito ; check CPUERR
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clr (r0) ; clear CPUERR (any write should)
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hcmpeq (r0),#0 ; check CPUERR
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;
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9999$: iot ; end of test A2.4
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;
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; Test A2.5 -- CPUERR cp.ysv +++++++++++++++++++++++++++++++++++++++++
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; Test cp.ysv: yellow stack trap
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; Since stack is still usable after the trap, the vhugen handler can be used.
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;
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ta0205: cmp systyp,#sy.e11 ; e11 V7.3 doesnt trap, runs on hold
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beq 9999$
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mov #1000$,vhustp ; continuation address
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mov #400,sp
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clr -(sp) ; should trap (not abort)
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halt ; not executed, handler continues at 1000$
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1000$: hcmpeq (r0),#cp.ysv ; check CPUERR
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clr (r0) ; clear CPUERR (any write should)
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hcmpeq (r0),#0 ; check CPUERR
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;
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mov #stack,sp
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9999$: iot ; end of test A2.5
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;
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; Test A2.6 -- CPUERR cp.rsv +++++++++++++++++++++++++++++++++++++++++
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; Test cp.rsv: red stack trap - simple low stack case
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;
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ta0206: cmp systyp,#sy.e11 ; e11 V7.3 doesnt abort, runs on hold
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beq 9999$
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mov #1000$,v..iit ; setup direct iit handler
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mov #340,sp
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clr -(sp) ; should abort (not trap)
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halt
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1000$: mov #stack,sp ; direct iit handler
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hcmpeq (r0),#cp.rsv ; check CPUERR
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clr (r0) ; clear CPUERR (any write should)
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hcmpeq (r0),#0 ; check CPUERR
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;
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9999$: iot ; end of test A2.6
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;
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; Test A2.7 -- CPUERR cp.rsv+cp.aer (odd address) ++++++++++++++++++++
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; Test cp.rsv: red stack escalation after odd stack
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;
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ta0207: cmp systyp,#sy.e11 ; e11 V7.3 pushes to odd stack, abort after halt
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beq 9999$
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mov #1000$,v..iit ; setup direct iit handler
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mov #stack-1,sp
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clr -(sp) ; odd-address abort, escalated to red stack
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halt
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1000$: mov #stack,sp ; direct iit handler
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hcmpeq (r0),#<cp.rsv+cp.aer> ; check CPUERR
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clr (r0) ; clear CPUERR (any write should)
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hcmpeq (r0),#0 ; check CPUERR
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;
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9999$: iot ; end of test A2.7
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;
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; Test A2.8 -- CPUERR cp.rsv+cp.nxm ++++++++++++++++++++++++++++++++++
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; Test cp.rsv: red stack escalation after non-existent memory abort
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; Setup like in A2.3, put stack at p6base+4
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;
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ta0208: cmp systyp,#sy.e11 ; e11 V7.3 pushes to bad stack, abort after halt
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beq 9999$
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mov #1000$,v..iit ; setup direct iit handler
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mov #177400,kipar6
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mov #m3.e22,mmr3 ; 22-bit mode
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mov #m0.ena,mmr0 ; enable mmu ;! MMU 22
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;
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mov #p6base+4,sp ; stack in non-existing memory
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clr -(sp) ; non-existing memory, escalated to red stack
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halt
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1000$: mov #stack,sp ; direct iit handler
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hcmpeq (r0),#<cp.rsv+cp.nxm> ; check CPUERR
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clr (r0) ; clear CPUERR (any write should)
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hcmpeq (r0),#0 ; check CPUERR
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;
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reset ;! MMU off
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mov #001400,kipar6 ; restore kipar6
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;
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9999$: iot ; end of test A2.8
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;
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; Test A2.9 -- CPUERR cp.rsv+cp.ito ++++++++++++++++++++++++++++++++++
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; Test cp.rsv: red stack escalation after unibus timeout
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; Setup like in A2.4, put stack at 160004
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;
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ta0209: cmp systyp,#sy.e11 ; e11 V7.3 pushes to bad stack, abort after halt
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beq 9999$
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mov #1000$,v..iit ; setup direct iit handler
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mov #160004,sp ; stack at non-existing unibus device
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clr -(sp) ; non-existing memory, escalated to red stack
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halt
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1000$: mov #stack,sp ; direct iit handler
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hcmpeq (r0),#<cp.rsv+cp.ito> ; check CPUERR
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clr (r0) ; clear CPUERR (any write should)
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hcmpeq (r0),#0 ; check CPUERR
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;
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9999$: iot ; end of test A2.9
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;
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; Test A2.10 -- CPUERR cp.rsv+cp.aer (mmu abort) +++++++++++++++++++++
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; Test cp.rsv: red stack escalation after mmu timeout
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; Set kernel I page 6 to non-resident
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;
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ta0210: cmp systyp,#sy.sih ; this red stack escalation fails in SimH
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beq 9999$
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cmp systyp,#sy.e11 ; e11 V7.3 pushes to bad stack, does MMU 250
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beq 9999$
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mov #1000$,v..iit ; setup direct iit handler
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clr kipdr6 ; set non-resident
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mov #m3.e22,mmr3 ; 22-bit mode
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mov #m0.ena,mmr0 ; enable mmu ;! MMU 22
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;
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mov #p6base+4,sp ; stack in non-resident memory
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clr -(sp) ; MMU abort, escalated to red stack
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halt
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1000$: mov #stack,sp ; direct iit handler
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hcmpeq (r0),#<cp.rsv+cp.aer> ; check CPUERR
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clr (r0) ; clear CPUERR (any write should)
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hcmpeq (r0),#0 ; check CPUERR
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;
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reset ;! MMU off
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mov kipdr5,kipdr6 ; restore kipdr6 (default kipdr are identical)
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;
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9999$: iot ; end of test A2.10
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;
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; -----------------------------------------------
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; end of A2.* tests, restore iit handler
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mov v..iit+2,v..iit ; restore iit handler
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;
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; Section B: Stress tests ====================================================
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;
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; Test B1: address mode torture tests +++++++++++++++++++++++++++++++++++++++
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@@ -273,8 +514,22 @@ tb0202: mov #2,r5
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; END OF ALL TESTS - loop closure ============================================
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;
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mov tstno,r0 ; hack, for easy monitoring ...
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hcmpeq tstno,#6. ; all tests done ?
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hcmpeq tstno,#16. ; all tests done ?
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;
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jmp loop
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;
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; kernel handlers ============================================================
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;
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; vhugen - generic handler for expected traps/abort ++++++++++++++++++++++++++
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; the kernel continution address must be written to vhustp
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; execution will reset vhustp to a catcher value
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; --> vhustp must be set for each execution
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;
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vhugen: tst (sp)+ ; discard one word of vector push
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mov vhustp,(sp) ; set up kernel return address
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mov #vhuhlt,vhustp ; reset stop address by catcher
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rts pc ; end return to continuation address
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vhustp: .word vhuhlt
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vhuhlt: halt
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;
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.end start
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@@ -1,4 +1,4 @@
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; $Id: cpu_mmu.mac 1301 2022-10-06 08:53:46Z mueller $
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; $Id: cpu_mmu.mac 1303 2022-10-17 17:55:51Z mueller $
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; SPDX-License-Identifier: GPL-3.0-or-later
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; Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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;
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@@ -260,18 +260,18 @@ tb0102: mov #mmr3,r0 ; ptr to mmr3
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tb0201: mov #123456,1000$
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; enable mmu in 18bit mode
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clr mmr3 ; no d dspace, no 22bit
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mov #m0.ena,mmr0 ; enable mmu
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hbitne #m0.ena,mmr0 ; test bit ;! MMU 18
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mov #m0.ena,mmr0 ; enable mmu ;! MMU 18
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hbitne #m0.ena,mmr0 ; test bit
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hcmpeq 1000$,#123456 ; check marker
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; verify I/O page mapping in 18bit mode (007600 must be OK)
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mov #kipar7,r0 ; ptr to kipar7
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bic #170000,(r0) ; clear to 4 bits in kipar7
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hcmpeq (r0),#007600 ; kipar7 still seen ???
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hcmpeq (r0),#007600 ; kipar7 still seen ?
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bis #170000,(r0) ; restore kipar7
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hcmpeq (r0),#177600
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; enable mmu in 22bit mode; check that mmr3 still seen
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mov #m3.e22,mmr3
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hcmpeq mmr3,#m3.e22 ; test mmr3 stll seen ??? ;! MMU 22
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hcmpeq mmr3,#m3.e22 ; test mmr3 still seen ? ;! MMU 22
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; test RESET
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reset ; should clear mmr0 and mmr3
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htsteq mmr0 ; check mmr0 cleared ;! MMU off
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@@ -1,14 +1,16 @@
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; $Id: tcode_exec.scmd 1283 2022-08-22 10:07:58Z mueller $
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; $Id: tcode_exec.scmd 1303 2022-10-17 17:55:51Z mueller $
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; SPDX-License-Identifier: GPL-3.0-or-later
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; Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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;
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; setup w11 like processor configuration
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; like ../simh/setup_w11a_max.scmd
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; but only cpu, devices are all default
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; and 3M memory to ensure that the is NXM gap below I/O page
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; Note: a 4M memory config of a 11/70 gives memory up to I/O page (as on J11)
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;
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set cpu 11/70
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set cpu nofpp
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set cpu 4m
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set cpu 3m
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set cpu oct
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set cpu idle
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; set sysid, leading '1' indicates simulator, next '1' SimH
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@@ -17,6 +19,7 @@ dep sysid 110234
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; disable simulator stop conditions, especially "read stack trap"
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;
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dep STOP_TRAPS 0
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dep STOP_SPA 0
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;
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dep pc 0200
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load %1.lda
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Block a user