mirror of
https://github.com/wfjm/w11.git
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add rk11perf.tcl; asm.tcl and shell.tcl updates
- tools/ - mcode/rk11/rk11perf.tcl: added, RK11 performance tested - tcl/rw11/asm.tcl: asmrun: re-organize -stop -creset handling - tcl/rw11/shell.tcl: add rw11::shell_attnmuted to mute CPU attn messages
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wfjm
10
tools/mcode/rk11/Makefile
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10
tools/mcode/rk11/Makefile
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# $Id: Makefile 1176 2019-06-30 07:16:06Z mueller $
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# SPDX-License-Identifier: GPL-3.0-or-later
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# Copyright 2019- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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#
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# Revision History:
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# Date Rev Version Comment
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# 2019-05-07 1147 1.0 Initial version
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#---
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#
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include ${RETROBASE}/tools/make/generic_asm11_def.mk
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5
tools/mcode/rk11/README.md
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tools/mcode/rk11/README.md
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This directory tree contains **RK11 test codes** and contains
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| File | Docu | Comments |
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| --------- | --------- | ------- |
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| [rk11perf.tcl](rk11perf.tcl) | - | performance tester for RK11 |
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295
tools/mcode/rk11/rk11perf.tcl
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295
tools/mcode/rk11/rk11perf.tcl
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# $Id: rk11perf.tcl 1362 2023-01-31 18:16:17Z mueller $
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# SPDX-License-Identifier: GPL-3.0-or-later
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# Copyright 2017-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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#
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# Revision History:
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# Date Rev Version Comment
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# 2023-01-31 1362 1.1 add more usage modes; mute CPU attn messages
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# 2019-03-09 1120 1.0.1 use -wal
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# 2017-05-07 895 1.0 Initial version
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#
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# Simple rk11 I/O performance tester
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#
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# Usage:
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# ti_rri --cuff --logl=2 --int --pack=rw11 -- rw11::setup_sys
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#
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# source rk11perf.tcl
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# rk11perf cpu0 1000; # full mode,nblk,code scan
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# rk11perf cpu0 1000 1; # single run with nblk=1
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# rk11perf cpu0 -1; # print code and quit
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proc rk11perf {{cpu cpu0} {tmax 1000} {nblk 0} {mode 0} {code 0}} {
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# mute shell CPU attention messages
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if {[info exists rw11::shell_attnhdl_muted]} {
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set rw11::shell_attnhdl_muted 1
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}
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# stop CPU and attach RAM disk image
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$cpu cp -stop
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${cpu}rka0 att {ram:?pat=test}
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# compile and load code
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$cpu ldasm -lst lst -sym sym [rk11perf_asmcode]
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# if tmax == 0 quit, if <0 just print listing and quit
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if {$tmax == 0} { return}
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if {$tmax < 0} {
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puts $lst
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return
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}
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# if nblk defined > 0, do a single run
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if {$nblk > 0} {
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set res [rk11perf_run $cpu sym $code $mode $nblk $tmax]
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set dt [lindex $res 0]
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set kb [lindex $res 1]
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set cnt [lindex $res 2]
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puts [format " dt: %5.2f req/s: %5.0f KB/s: %5.0f" \
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$dt [expr {double($cnt)/$dt}] [expr {$kb/$dt}]]
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return
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}
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# otherwise, loop over mode,nblk,code and print table
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puts " code= 'wait' 'inc r1' 'ashc ...' 'mov ...'"
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puts " nblk req/s KB/s req/s KB/s req/s KB/s req/s KB/s"
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foreach mode {0 1} {
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puts [expr { $mode ? "write" : "read" }]
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foreach nblk {1 2 4 6 8 12 16 24 32} {
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set line [format " %4d" $nblk]
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foreach code {0 1 2 3} {
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set res [rk11perf_run $cpu sym $code $mode $nblk $tmax]
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set dt [lindex $res 0]
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set kb [lindex $res 1]
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set cnt [lindex $res 2]
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append line [format " %5.0f %5.0f" \
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[expr {double($cnt)/$dt}] [expr {$kb/$dt}]]
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}
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puts $line
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}
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}
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$cpu cp -stop
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return
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}
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proc rk11perf_run {cpu symName {code 0} {mode 0} {nblk 1} {tmax 1000}} {
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upvar 1 $symName sym
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set tbeg [clock milliseconds]
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rw11::asmrun $cpu sym r0 $code r1 $mode r2 $nblk
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after $tmax
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$cpu cp -wal $sym(t.stop) -wm 1
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$cpu wtcpu [expr $tmax/10.]
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set trun [expr {[clock milliseconds] - $tbeg}]
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$cpu cp -rpc rpc -wal $sym(t.stat) -rm rstat
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if {$rpc != $sym(stop) || $rstat != 0 } {
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error [format "rk11perf-E: abort at pc=%6.6o stat=%6.6o" $rpc $rstat]
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}
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$cpu cp -stop
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$cpu cp -wal $sym(t.tcnt) -rmi rtcnt
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set dt [expr { double($trun)/1000. } ]
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set kb [expr { double(512.*$nblk*$rtcnt) / 1024. }]
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return [list $dt $kb $rtcnt]
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}
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#
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# w11 test code for rk11perf test
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#
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proc rk11perf_asmcode {} {
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return {
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;
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; definitions ----------------------------------------------
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;
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.include |lib/defs_cpu.mac|
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.include |lib/defs_rk.mac|
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;
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; vector area ----------------------------------------------
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;
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.include |lib/vec_cpucatch.mac|
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.include |lib/vec_devcatch.mac|
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. = v..rk
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.word vh.rk
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.word cp.ars+cp.pr7 ; PR7 and use alternate registers
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;
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; stack area -----------------------------------------------
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;
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. = 1000
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stack:
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;
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; data area ------------------------------------------------
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;
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t.code: .word 0 ; background code
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t.mode: .word 0 ; mode (0=read, 1=write)
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t.nblk: .word 1 ; number of blocks
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t.stop: .word 0 ; stop word
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t.stat: .word 0 ; return status
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t.tcnt: .word 0,0 ; transfer counter
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;
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dach: .word 0 ; cyc/hd disk address
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;
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ctbl: .word code0
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.word code1
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.word code2
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.word code3
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ctble:
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cstart: .word 0
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;
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; code area ------------------------------------------------
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;
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. = 2000
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start: spl 7 ; lockout interrupts
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mov r0,t.code ; setup code
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mov r1,t.mode ; setup mode
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mov r2,t.nblk ; setup nblk
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clr t.stop ; clear stop word
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clr t.stat ; clear return status
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clr t.tcnt ; clear transfer counter
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clr t.tcnt+2
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mov #177777,@#cp.dsr ; sdreg: start phase marker
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tstb @#rk.cs ; is controller ready
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bmi 1$
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mov #1,t.stat ; if not, halt with stat = 1
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halt
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1$: mov #rk.go,@#rk.cs ; do control reset
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2$: tstb rk.cs
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bpl 2$
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mov #0,@#rk.da ; select drive 0
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tstb @#rk.ds ; is drive ready ?
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bmi 3$
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mov #2,t.stat ; if not, halt with stat = 2
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halt
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3$: clr dach
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call rkstrt ; start 1st transfer
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clr @#cp.dsr ; sdreg: end of start phase
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mov t.code,r0 ; determine background code
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cmp r0,#<ctble-ctbl>/2
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blo 4$
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mov #3,t.stat ; if not, halt with stat = 3
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halt
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4$: asl r0
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mov ctbl(r0),cstart
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spl 0 ; allow interrupts
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jmp @cstart ; and start background
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;
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; rk11 interrupt vector handler ----------------------------
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;
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vh.rk: tst @#rk.er ; test drive error
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beq 1$
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mov #4,t.stat ; if any bit set, halt with stat = 4
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halt
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1$: tst t.stop ; test stop flag set ?
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bne 99$ ; if yes, stop (with stat = 0)
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inc dach ; increment cyl/hdr address
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cmp dach,#620 ; beyond end of disk ?
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; last cyl/hd is 0625, to allow 32 block I/Os
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; covering 3 cyl (with 12 sec) stop at 0620
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blos 2$ ; restart from beginning
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clr dach
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2$: call rkstrt
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rti
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99$: halt
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stop: halt
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;
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; start next rk11 io ---------------------------------------
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;
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rkstrt: mov dach,r0 ; get cyl/hdr disk address
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ash #4,r0 ; convert to chs (use sector = 0)
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mov r0,@#rk.da
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mov #bufdma,@#rk.ba
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mov t.nblk,r0 ; get number of blocks
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ash #8.,r0 ; -> word count
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neg r0 ; 2's complement
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mov r0,rk.wc
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mov #rk.ie+rk.go,r0 ; prepare command
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tst t.mode
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bne 1$
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bis #rk.frd,r0 ; mode==0: use read
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br 2$
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1$: bis #rk.fwr,r0 ; mode!=0: use write
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2$: mov r0,@#rk.cs ; start request
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add #1,t.tcnt ; inc transfer count
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adc t.tcnt+2
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mov t.tcnt,@#cp.dsr ; show transfer count in display register
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return
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;
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; code 0 - wait endless loop -------------------------------
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;
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nwait: .word 0
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;
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code0: clr nwait
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1$: wait
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inc nwait
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br 1$
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;
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; code 1 - short instruction endless loop ------------------
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;
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code1: mov #cp.cmu,@#cp.psw ; switch user mode PRI=0
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1$: inc r1
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inc r1
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inc r1
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inc r1
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inc r1
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inc r1
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inc r1
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inc r1
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br 1$
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;
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; code 2 - long instruction endless loop -------------------
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;
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pscnt: .word scnt
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scnt: .word 31.
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;
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code2: mov #cp.cmu,@#cp.psw ; switch user mode PRI=0
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1$: ashc @pscnt,r2
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ashc @pscnt,r2
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ashc @pscnt,r2
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ashc @pscnt,r2
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ashc @pscnt,r2
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ashc @pscnt,r2
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ashc @pscnt,r2
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ashc @pscnt,r2
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br 1$
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;
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; code 3 - buffer copy endless loop ------------------------
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; constanty copies from bufdma to bufcpy
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;
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code3: mov #cp.cmu,@#cp.psw ; switch user mode PRI=0
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1$: mov #bufdma,r2
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mov #bufcpy,r3
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mov t.nblk,r4 ; get number of blocks
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ash #6.,r4 ; -> word count / 4 !!
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2$: mov (r2)+,(r3)+
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mov (r2)+,(r3)+
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mov (r2)+,(r3)+
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mov (r2)+,(r3)+
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sob r4,2$
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br 1$
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;
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; buffers --------------------------------------------------
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; Notes on buffer placement
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; - w11a cache size is 8k bytes (020000)
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; - the buffers are 16k bytes (040000) --> allow up to 32 block transfers
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; - the dma buffer start on 044000 to avoid cache conflicts with code which
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; resides in first 004000 bytes
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; - the dma and cpy buffer are separated by 16k to cause maximal cache conflict
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;
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. = 044000
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bufdma: .blkb 040000
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bufcpy: .blkb 040000
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bufend:
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}
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}
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