diff --git a/.travis.yml b/.travis.yml index ba0c62da..15663d4a 100644 --- a/.travis.yml +++ b/.travis.yml @@ -78,8 +78,10 @@ script: -tag default,sys_tst_mig,base \ -tag default,sys_tst_sram,base \ -tag default,sys_tst_sram,n4 \ + -tag default,sys_tst_sram,arty \ -tag default,sys_w11a,stim1 \ - -tag default,sys_w11a,n4 + -tag default,sys_w11a,n4 \ + -tag default,sys_w11a,arty - tbfilt -all -sum -comp # - .travis/deploy.sh diff --git a/doc/CHANGELOG.md b/doc/CHANGELOG.md index 73467d98..610c74a3 100644 --- a/doc/CHANGELOG.md +++ b/doc/CHANGELOG.md @@ -50,6 +50,8 @@ The full set of tests is only run for tagged releases. - viv_tools_build.tcl - export log and rpt generated in OOC synthesis runs - downgrade SSN critical warnings to warnings + - tbrun: add --list option + - ti_w11: add add -ar,-n4d (ddr versions) - firmware changes - cdc_vector_s0: add ENA port (now used in cdc_pulse) diff --git a/rtl/bplib/arty/tb/tb_arty_dram.vhd b/rtl/bplib/arty/tb/tb_arty_dram.vhd index b2fae8d8..70b46701 100644 --- a/rtl/bplib/arty/tb/tb_arty_dram.vhd +++ b/rtl/bplib/arty/tb/tb_arty_dram.vhd @@ -1,4 +1,4 @@ --- $Id: tb_arty_dram.vhd 1069 2018-11-16 17:11:30Z mueller $ +-- $Id: tb_arty_dram.vhd 1105 2019-01-12 19:52:45Z mueller $ -- -- Copyright 2018- by Walter F.J. Mueller -- @@ -19,7 +19,7 @@ -- simlib/simclkcnt -- rlink/tbcore/tbcore_rlink -- xlib/sfs_gsim_core --- tb_basys3_core +-- tb_arty_core -- serport/tb/serport_master_tb -- arty_dram_aif [UUT] -- diff --git a/rtl/sys_gen/w11a/arty/sys_w11a_arty.vhd b/rtl/sys_gen/w11a/arty/sys_w11a_arty.vhd index 3cc7fdc6..39686538 100644 --- a/rtl/sys_gen/w11a/arty/sys_w11a_arty.vhd +++ b/rtl/sys_gen/w11a/arty/sys_w11a_arty.vhd @@ -1,4 +1,4 @@ --- $Id: sys_w11a_arty.vhd 1101 2019-01-02 21:22:37Z mueller $ +-- $Id: sys_w11a_arty.vhd 1105 2019-01-12 19:52:45Z mueller $ -- -- Copyright 2018-2019 by Walter F.J. Mueller -- @@ -13,7 +13,7 @@ -- ------------------------------------------------------------------------------ -- Module Name: sys_w11a_arty - syn --- Description: w11a test design for arty (with dram via mig) +-- Description: w11a design for arty (with dram via mig) -- -- Dependencies: bplib/bpgen/s7_cmt_1ce1ce2c -- cdclib/cdc_signal_s1_as @@ -115,7 +115,7 @@ use unisim.vcomponents.ALL; -- ---------------------------------------------------------------------------- entity sys_w11a_arty is -- top level - -- implements arty_aif + -- implements arty_dram_aif port ( I_CLK100 : in slbit; -- 100 MHz clock I_RXD : in slbit; -- receive data (board view) diff --git a/tools/bin/tbrun b/tools/bin/tbrun index 72675d16..ae9120e6 100755 --- a/tools/bin/tbrun +++ b/tools/bin/tbrun @@ -1,7 +1,7 @@ #!/usr/bin/perl -w -# $Id: tbrun 1097 2018-12-29 11:20:14Z mueller $ +# $Id: tbrun 1103 2019-01-04 13:18:54Z mueller $ # -# Copyright 2016-2018 by Walter F.J. Mueller +# Copyright 2016-2019 by Walter F.J. Mueller # # This program is free software; you may redistribute and/or modify it under # the terms of the GNU General Public License as published by the Free @@ -14,6 +14,7 @@ # # Revision History: # Date Rev Version Comment +# 2019-01-04 1103 1.1.3 add --list option # 2018-12-29 1097 1.1.2 show correct 'found count' in summary message # 2018-11-16 1069 1.1.1 add --all # 2018-11-09 1066 1.1 add and use bailout; update exit code usage @@ -35,7 +36,7 @@ use Time::HiRes qw(gettimeofday); my %opts = (); GetOptions(\%opts, "tag=s@", "exclude=s@", "mode=s", "all", - "jobs=i", "tee=s", "tmax=i", "dry", "trace", + "jobs=i", "tee=s", "tmax=i", "dry", "list", "trace", "nomake", "norun", "rlmon", "rbmon", "bwait=i", "swait=i", "help" @@ -119,6 +120,12 @@ unless ($ntest) { exit 1; } +if (defined $opts{list}) { + foreach my $titem (@tlist) { tpr("$titem->{tmsg}\n"); } + tpr(sprintf "#tbrun-I: %d tests found, %d selected\n", $nseen,$ntest); + exit 0; +} + if (defined $opts{jobs}) { run_tests_multi(); } else { diff --git a/tools/bin/ti_w11 b/tools/bin/ti_w11 index b47ebcf3..67c9fa17 100755 --- a/tools/bin/ti_w11 +++ b/tools/bin/ti_w11 @@ -1,11 +1,12 @@ #!/usr/bin/perl -w -# $Id: ti_w11 1089 2018-12-19 10:45:41Z mueller $ +# $Id: ti_w11 1103 2019-01-04 13:18:54Z mueller $ # -# Copyright 2013-2017 by Walter F.J. Mueller +# Copyright 2013-2019 by Walter F.J. Mueller # License disclaimer see License.txt in $RETROBASE directory # # Revision History: # Date Rev Version Comment +# 2019-01-04 1103 1.4.3 add -ar,-n4d (ddr versions) # 2017-06-25 916 1.4.2 add -c7 (cmoda7 support) # 2017-01-08 843 1.4.1 allow -tuD,.... for Digilent autodetect; add -bn4d # 2016-12-31 834 1.4 use rw11::shell by default; add -ns to suppress it @@ -51,7 +52,9 @@ my $val_tb_b3 = "tbw $sysbase/basys3/tb/tb_w11a_b3 -fifo"; my $val_tb_n4 = "tbw $sysbase/nexys4/tb/tb_w11a_n4 -fifo"; my $val_tb_bn4 = "tbw $sysbase/nexys4_bram/tb/tb_w11a_br_n4 -fifo"; my $val_tb_bn4d = "tbw $sysbase/nexys4d_bram/tb/tb_w11a_br_n4d -fifo"; +my $val_tb_n4d = "tbw $sysbase/nexys4d/tb/tb_w11a_n4d -fifo"; my $val_tb_bar = "tbw $sysbase/arty_bram/tb/tb_w11a_br_arty -fifo"; +my $val_tb_ar = "tbw $sysbase/arty/tb/tb_w11a_arty -fifo"; my $val_tb_c7 = "tbw $sysbase/cmoda7/tb/tb_w11a_c7 -fifo"; my $val_tb; my $val_e; @@ -120,18 +123,30 @@ while (scalar(@ARGV)) { $val_tb = $val_tb_bn4; shift @ARGV; - } elsif ($curarg =~ m{^-bn4s$} ) { # -bn4d (prim serport fine) + } elsif ($curarg =~ m{^-bn4d$} ) { # -bn4d (prim serport fine) $opt_io = 'f'; $opt_f = '1'; $val_tb = $val_tb_bn4d; shift @ARGV; + } elsif ($curarg =~ m{^-n4d$} ) { # -n4d (prim serport fine) + $opt_io = 'f'; + $opt_f = '1'; + $val_tb = $val_tb_n4d; + shift @ARGV; + } elsif ($curarg =~ m{^-bar$} ) { # -bar (use -fx by default) $opt_io = 'f'; $opt_f = 'x'; $val_tb = $val_tb_bar; shift @ARGV; + } elsif ($curarg =~ m{^-ar$} ) { # -ar (use -fx by default) + $opt_io = 'f'; + $opt_f = 'x'; + $val_tb = $val_tb_ar; + shift @ARGV; + } elsif ($curarg =~ m{^-c7$} ) { # -c7 (use -fx by default) $opt_io = 'f'; $opt_f = 'x'; diff --git a/tools/man/man1/tbrun.1 b/tools/man/man1/tbrun.1 index 8ca265e1..751c1bb5 100644 --- a/tools/man/man1/tbrun.1 +++ b/tools/man/man1/tbrun.1 @@ -1,11 +1,11 @@ .\" -*- nroff -*- -.\" $Id: tbrun.1 1069 2018-11-16 17:11:30Z mueller $ +.\" $Id: tbrun.1 1102 2019-01-03 08:46:04Z mueller $ .\" -.\" Copyright 2016-2018 by Walter F.J. Mueller +.\" Copyright 2016-2019 by Walter F.J. Mueller .\" .\" ------------------------------------------------------------------ . -.TH TBRUN 1 2018-11-16 "Retro Project" "Retro Project Manual" +.TH TBRUN 1 2019-01-03 "Retro Project" "Retro Project Manual" .\" ------------------------------------------------------------------ .SH NAME tbrun \- test bench driver @@ -173,6 +173,10 @@ device. Using shell pipes and \fBtee\fP(1) will therefore prevent progress lines, use the \fB\-\-tee\fP instead to save the output into a file. . +.\" -- --list ------------------------------------ +.IP \fB\-\-list\fP +list selected tags and quit. +. .\" -- --dry ------------------------------------- .IP \fB\-\-dry\fP dry run, prints the generated commands, but doesn't execute. diff --git a/tools/man/man1/ti_w11.1 b/tools/man/man1/ti_w11.1 index b50ea033..2514e44f 100644 --- a/tools/man/man1/ti_w11.1 +++ b/tools/man/man1/ti_w11.1 @@ -1,11 +1,11 @@ .\" -*- nroff -*- -.\" $Id: ti_w11.1 916 2017-06-25 13:30:07Z mueller $ +.\" $Id: ti_w11.1 1103 2019-01-04 13:18:54Z mueller $ .\" -.\" Copyright 2013-2017 by Walter F.J. Mueller +.\" Copyright 2013-2019 by Walter F.J. Mueller .\" .\" ------------------------------------------------------------------ . -.TH TI_W11 1 2017-06-25 "Retro Project" "Retro Project Manual" +.TH TI_W11 1 2019-01-04 "Retro Project" "Retro Project Manual" .\" ------------------------------------------------------------------ .SH NAME ti_w11 \- Quick starter for \fBti_rri\fP with \fBw11\fP CPU designs @@ -61,12 +61,10 @@ start \fItb_w11a_c7\fP simulation (Cmod A7, default \fB-fx\fP) start \fItb_w11a_b3\fP simulation (Basys3, default \fB-fx\fP) .IP \fB-n4\fP start \fItb_w11a_n4\fP simulation (Nexys4) -.IP \fB-bn4\fP -start \fItb_w11a_br_n4\fP simulation (Nexys4, BRAM only) -.IP \fB-bn4d\fP -start \fItb_w11a_br_n4d\fP simulation (Nexys4 DDR, BRAM only) -.IP \fB-bar\fP -start \fItb_w11a_br_arty\fP simulation (Arty, BRAM only, default \fB-fx\fP) +.IP \fB-n4d\fP +start \fItb_w11a_n4d\fP simulation (Nexys4 DDR) +.IP \fB-ar\fP +start \fItb_w11a_arty\fP simulation (Arty, default \fB-fx\fP) .IP \fB-n3\fP start \fItb_w11a_n3\fP simulation (Nexys3, default \fB-fc\fP) .IP \fB-n2\fP @@ -74,6 +72,14 @@ start \fItb_w11a_n2\fP simulation (Nexys2, default \fB-fc\fP) .IP \fB-s3\fP start \fItb_w11a_s3\fP simulation (S3board, default \fB-f2\fP) .PD +.IP \fB-bn4\fP +start \fItb_w11a_br_n4\fP simulation (Nexys4, BRAM only) +.PD 0 +.IP \fB-bn4d\fP +start \fItb_w11a_br_n4d\fP simulation (Nexys4 DDR, BRAM only) +.IP \fB-bar\fP +start \fItb_w11a_br_arty\fP simulation (Arty, BRAM only, default \fB-fx\fP) +.PD .IP \fB-f\fIm\fR select communication mode for simulation. The \fB-f\fIm\fR can be used after the \fB-b3\fP,...,\fB-s3\fP options to overwrite the default. Valid values diff --git a/tools/tcl/tst_mig/test_mem.tcl b/tools/tcl/tst_mig/test_mem.tcl index a6fe9127..e5b784d2 100644 --- a/tools/tcl/tst_mig/test_mem.tcl +++ b/tools/tcl/tst_mig/test_mem.tcl @@ -1,6 +1,6 @@ -# $Id: test_mem.tcl 1096 2018-12-29 07:54:17Z mueller $ +# $Id: test_mem.tcl 1103 2019-01-04 13:18:54Z mueller $ # -# Copyright 2018- by Walter F.J. Mueller +# Copyright 2018-2019 by Walter F.J. Mueller # # This program is free software; you may redistribute and/or modify it under # the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ # # Revision History: # Date Rev Version Comment +# 2019-01-04 1103 1.1 add very basic low level interface tests # 2018-12-28 1096 1.0 Initial version # @@ -94,6 +95,37 @@ namespace eval tst_mig { -rreg mt.xwait calwait rlc log [format " # rwait: %2d refwait: %2d calwait: %2d" \ $rwait $refwait $calwait] + # + #------------------------------------------------------------------------- + rlc log " test 5: CMD function - low level write/read" + rlc exec \ + -wreg mt.mask 0x0000 \ + -wreg mt.addrh 0x0000 \ + -wreg mt.addrl 0x4400 \ + -wreg mt.datwr0 0x4400 \ + -wreg mt.datwr1 0x4401 \ + -wreg mt.datwr2 0x4402 \ + -wreg mt.datwr3 0x4403 \ + -wreg mt.cntl [regbld tst_mig::CNTL wren {cmd "WR"} {func "CMD"}] \ + -wreg mt.addrl 0x4500 \ + -wreg mt.datwr0 0x4500 \ + -wreg mt.datwr1 0x4501 \ + -wreg mt.datwr2 0x4502 \ + -wreg mt.datwr3 0x4503 \ + -wreg mt.cntl [regbld tst_mig::CNTL wren {cmd "WR"} {func "CMD"}] + rlc exec \ + -wreg mt.addrl 0x4400 \ + -wreg mt.cntl [regbld tst_mig::CNTL {cmd "RD"} {func "CMD"}] \ + -rreg mt.datrd0 -edata 0x4400 \ + -rreg mt.datrd1 -edata 0x4401 \ + -rreg mt.datrd2 -edata 0x4402 \ + -rreg mt.datrd3 -edata 0x4403 \ + -wreg mt.addrl 0x4500 \ + -wreg mt.cntl [regbld tst_mig::CNTL {cmd "RD"} {func "CMD"}] \ + -rreg mt.datrd0 -edata 0x4500 \ + -rreg mt.datrd1 -edata 0x4501 \ + -rreg mt.datrd2 -edata 0x4502 \ + -rreg mt.datrd3 -edata 0x4503 # #------------------------------------------------------------------------- diff --git a/tools/tcl/tst_mig/util.tcl b/tools/tcl/tst_mig/util.tcl index b20b1164..4ebc22df 100644 --- a/tools/tcl/tst_mig/util.tcl +++ b/tools/tcl/tst_mig/util.tcl @@ -1,6 +1,6 @@ -# $Id: util.tcl 1101 2019-01-02 21:22:37Z mueller $ +# $Id: util.tcl 1103 2019-01-04 13:18:54Z mueller $ # -# Copyright 2018- by Walter F.J. Mueller +# Copyright 2018-2019 by Walter F.J. Mueller # # This program is free software; you may redistribute and/or modify it under # the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ # # Revision History: # Date Rev Version Comment +# 2019-01-04 1103 1.0.2 add defs for CNTL cmd field # 2019-01-02 1101 1.0.1 test_rwait: add optional lena argument # 2018-12-28 1096 1.0 Initial version # 2018-12-24 1093 0.1 First draft @@ -34,7 +35,8 @@ namespace eval tst_mig { # # setup register descriptions for tst_mig core design ---------------------- # - regdsc CNTL {cmd 15 3} {wren 12} {dwend 11} \ + regdsc CNTL {cmd 15 3 "s:WR:RD:F2:F3:F4:F5:F6:F7"} \ + {wren 12} {dwend 11} \ {func 3 4 \ "s:NOOP:RD:WR:PAT:REF:CAL:CMD:WREN:F8:F9:F10:F11:F12:F13:F14:F15"} regdsc STAT {zqpend 6} {refpend 5} {rdend 4} \