diff --git a/doc/CHANGELOG.md b/doc/CHANGELOG.md index d6506c36..05632b43 100644 --- a/doc/CHANGELOG.md +++ b/doc/CHANGELOG.md @@ -30,7 +30,7 @@ The full set of tests is only run for tagged releases. - add ostest support for rsx11m-31_rk, rsx11m-40_rk and rsx11mp-30_rp oskits - all actively used commands have now a man page - Doxygen support now for V1.9.4; remove discontinued Tcl support -- build flow Vivado 2022.1 ready; handle synth 8-3331 -> 8-7129 transition) +- build flow Vivado 2022.1 ready; handle synth 8-3331 -> 8-7129 transition ### New features ### Changes - tools changes @@ -41,6 +41,8 @@ The full set of tests is only run for tagged releases. - tools/dox - w11_(cpp|vhd_all).Doxyfile: for Doxygen V1.9.4 - w11_tcl.Doxyfile: removed, Tcl support removed in Doxygen V1.8.18 +- firmware changes + - vlib/xlib/bufg_unisim: added, encapulate unisim BUFG ### Bug Fixes - tools/mcode - m9312/bootw11.mac: proper init of unit number in getnam diff --git a/rtl/sys_gen/tst_mig/arty/sys_tst_mig_arty.vbom b/rtl/sys_gen/tst_mig/arty/sys_tst_mig_arty.vbom index f9f8d4dc..d3c925a4 100644 --- a/rtl/sys_gen/tst_mig/arty/sys_tst_mig_arty.vbom +++ b/rtl/sys_gen/tst_mig/arty/sys_tst_mig_arty.vbom @@ -1,5 +1,6 @@ # libs ../../../vlib/slvtypes.vhd +../../../vlib/xlib/xlib.vhd ../../../vlib/cdclib/cdclib.vhd ../../../vlib/serport/serportlib.vbom ../../../vlib/rbus/rblib.vhd @@ -9,8 +10,8 @@ ../../../bplib/sysmon/sysmonrbuslib.vbom ../../../bplib/arty/miglib_arty.vbom ${sys_conf := sys_conf.vhd} -@lib:unisim # components +../../../vlib/xlib/bufg_unisim.vbom ../../../bplib/bpgen/s7_cmt_1ce1ce2c.vbom ../../../vlib/cdclib/cdc_pulse.vbom ../../../vlib/cdclib/cdc_signal_s1_as.vbom diff --git a/rtl/sys_gen/tst_mig/arty/sys_tst_mig_arty.vhd b/rtl/sys_gen/tst_mig/arty/sys_tst_mig_arty.vhd index 7ef492c5..1758b741 100644 --- a/rtl/sys_gen/tst_mig/arty/sys_tst_mig_arty.vhd +++ b/rtl/sys_gen/tst_mig/arty/sys_tst_mig_arty.vhd @@ -1,12 +1,13 @@ --- $Id: sys_tst_mig_arty.vhd 1181 2019-07-08 17:00:50Z mueller $ +-- $Id: sys_tst_mig_arty.vhd 1247 2022-07-06 07:04:33Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later --- Copyright 2018-2019 by Walter F.J. Mueller +-- Copyright 2018-2022 by Walter F.J. Mueller -- ------------------------------------------------------------------------------ -- Module Name: sys_tst_mig_arty - syn -- Description: test of arty ddr and its mig controller -- --- Dependencies: bplib/bpgen/s7_cmt_1ce1ce2c +-- Dependencies: vlib/xlib/bufg_unisim +-- bplib/bpgen/s7_cmt_1ce1ce2c -- cdclib/cdc_signal_s1_as -- cdclib/cdc_pulse -- bplib/bpgen/bp_rs232_2line_iob @@ -20,16 +21,18 @@ -- Test bench: tb/tb_tst_mig_arty -- -- Target Devices: generic --- Tool versions: viv 2017.2-2018.3; ghdl 0.34-0.35 +-- Tool versions: viv 2017.2-2022.1; ghdl 0.34-2.0.0 -- -- Synthesized (viv): -- Date Rev viv Target flop lutl lutm bram slic +-- 2022-07-05 1247 2022.1 xc7a35t-1l 4325 4197 415 1 1699 -- 2019-02-02 1108 2018.3 xc7a35t-1l 4323 4537 444 1 1874 -- 2019-02-02 1108 2017.2 xc7a35t-1l 4330 4773 444 1 1774 -- 2019-01-02 1101 2017.2 xc7a35t-1l 4320 4773 462 1 1770 -- -- Revision History: -- Date Rev Version Comment +-- 2022-07-05 1247 1.0.1 use bufg_unisim -- 2018-12-26 1094 1.0 Initial version -- 2018-12-23 1092 0.1 First draft ------------------------------------------------------------------------------ @@ -39,6 +42,7 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.slvtypes.all; +use work.xlib.all; use work.cdclib.all; use work.serportlib.all; use work.rblib.all; @@ -49,9 +53,6 @@ use work.sysmonrbuslib.all; use work.miglib_arty.all; use work.sys_conf.all; -library unisim; -use unisim.vcomponents.ALL; - -- ---------------------------------------------------------------------------- entity sys_tst_mig_arty is -- top level @@ -170,7 +171,7 @@ architecture syn of sys_tst_mig_arty is begin - CLK100_BUFG: bufg + CLK100_BUFG: bufg_unisim port map ( I => I_CLK100, O => CLK100_BUF diff --git a/rtl/sys_gen/tst_mig/nexys4d/sys_tst_mig_n4d.vbom b/rtl/sys_gen/tst_mig/nexys4d/sys_tst_mig_n4d.vbom index b1160dbc..e099f122 100644 --- a/rtl/sys_gen/tst_mig/nexys4d/sys_tst_mig_n4d.vbom +++ b/rtl/sys_gen/tst_mig/nexys4d/sys_tst_mig_n4d.vbom @@ -1,5 +1,6 @@ # libs ../../../vlib/slvtypes.vhd +../../../vlib/xlib/xlib.vhd ../../../vlib/cdclib/cdclib.vhd ../../../vlib/serport/serportlib.vbom ../../../vlib/rbus/rblib.vhd @@ -9,8 +10,8 @@ ../../../bplib/sysmon/sysmonrbuslib.vbom ../../../bplib/nexys4d/miglib_nexys4d.vbom ${sys_conf := sys_conf.vhd} -@lib:unisim # components +../../../vlib/xlib/bufg_unisim.vbom ../../../bplib/bpgen/s7_cmt_1ce1ce2c.vbom ../../../vlib/cdclib/cdc_pulse.vbom ../../../vlib/cdclib/cdc_signal_s1_as.vbom diff --git a/rtl/sys_gen/tst_mig/nexys4d/sys_tst_mig_n4d.vhd b/rtl/sys_gen/tst_mig/nexys4d/sys_tst_mig_n4d.vhd index f32af33a..edfa9be2 100644 --- a/rtl/sys_gen/tst_mig/nexys4d/sys_tst_mig_n4d.vhd +++ b/rtl/sys_gen/tst_mig/nexys4d/sys_tst_mig_n4d.vhd @@ -1,12 +1,13 @@ --- $Id: sys_tst_mig_n4d.vhd 1201 2019-08-10 16:51:22Z mueller $ +-- $Id: sys_tst_mig_n4d.vhd 1247 2022-07-06 07:04:33Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later --- Copyright 2018-2019 by Walter F.J. Mueller +-- Copyright 2018-2022 by Walter F.J. Mueller -- ------------------------------------------------------------------------------ -- Module Name: sys_tst_mig_n4d - syn -- Description: test of nexyx4d ddr and its mig controller -- --- Dependencies: bplib/bpgen/s7_cmt_1ce1ce2c +-- Dependencies: vlib/xlib/bufg_unisim +-- bplib/bpgen/s7_cmt_1ce1ce2c -- cdclib/cdc_signal_s1_as -- cdclib/cdc_pulse -- bplib/bpgen/bp_rs232_4line_iob @@ -20,10 +21,11 @@ -- Test bench: tb/tb_tst_mig_n4d -- -- Target Devices: generic --- Tool versions: viv 2017.2-2019.1; ghdl 0.34-0.35 +-- Tool versions: viv 2017.2-2022.1; ghdl 0.34-2.0.0 -- -- Synthesized (viv): -- Date Rev viv Target flop lutl lutm bram slic +-- 2022-07-05 1247 2022.1 xc7a100t-1l 4216 3821 412 1 1726 -- 2019-08-10 1201 2019.1 xc7a100t-1l 4217 4173 440 1 1709 +clkmon -- 2019-02-02 1108 2018.3 xc7a100t-1l 4106 4145 440 1 1689 -- 2019-02-02 1108 2017.2 xc7a100t-1l 4097 4310 440 1 1767 @@ -31,6 +33,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2022-07-05 1247 1.1.1 use bufg_unisim -- 2019-08-10 1201 1.1 use 100 MHz MIG SYS_CLK; add clock monitor -- 2018-12-30 1099 1.0 Initial version ------------------------------------------------------------------------------ @@ -69,6 +72,7 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.slvtypes.all; +use work.xlib.all; use work.cdclib.all; use work.serportlib.all; use work.rblib.all; @@ -79,9 +83,6 @@ use work.sysmonrbuslib.all; use work.miglib_nexys4d.all; use work.sys_conf.all; -library unisim; -use unisim.vcomponents.ALL; - -- ---------------------------------------------------------------------------- entity sys_tst_mig_n4d is -- top level @@ -204,7 +205,7 @@ architecture syn of sys_tst_mig_n4d is begin - CLK100_BUFG: bufg + CLK100_BUFG: bufg_unisim port map ( I => I_CLK100, O => CLK100_BUF diff --git a/rtl/sys_gen/tst_rlink/arty/sys_tst_rlink_arty.vhd b/rtl/sys_gen/tst_rlink/arty/sys_tst_rlink_arty.vhd index d3674d50..4e76d122 100644 --- a/rtl/sys_gen/tst_rlink/arty/sys_tst_rlink_arty.vhd +++ b/rtl/sys_gen/tst_rlink/arty/sys_tst_rlink_arty.vhd @@ -1,6 +1,6 @@ --- $Id: sys_tst_rlink_arty.vhd 1181 2019-07-08 17:00:50Z mueller $ +-- $Id: sys_tst_rlink_arty.vhd 1247 2022-07-06 07:04:33Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later --- Copyright 2016-2019 by Walter F.J. Mueller +-- Copyright 2016-2022 by Walter F.J. Mueller -- ------------------------------------------------------------------------------ -- Module Name: sys_tst_rlink_arty - syn @@ -21,10 +21,11 @@ -- Test bench: tb/tb_tst_rlink_arty -- -- Target Devices: generic --- Tool versions: viv 2015.4-2018.3; ghdl 0.33-0.35 +-- Tool versions: viv 2015.4-2022.1; ghdl 0.33-2.0.0 -- -- Synthesized (viv): -- Date Rev viv Target flop lutl lutm bram slic +-- 2022-07-05 1247 2022.1 xc7a35t-1L 1033 1528 34 3.0 543 -- 2019-02-02 1108 2018.3 xc7a35t-1L 1034 1613 36 3.0 550 -- 2019-02-02 1108 2017.2 xc7a35t-1L 1036 1678 36 3.0 557 -- 2017-06-05 907 2016.4 xc7a35t-1L 1033 1658 36 3.0 544 diff --git a/rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vhd b/rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vhd index 48890bf5..a12bc13f 100644 --- a/rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vhd +++ b/rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vhd @@ -1,6 +1,6 @@ --- $Id: sys_tst_rlink_b3.vhd 1181 2019-07-08 17:00:50Z mueller $ +-- $Id: sys_tst_rlink_b3.vhd 1247 2022-07-06 07:04:33Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later --- Copyright 2015-2019 by Walter F.J. Mueller +-- Copyright 2015-2022 by Walter F.J. Mueller -- ------------------------------------------------------------------------------ -- Module Name: sys_tst_rlink_b3 - syn @@ -19,10 +19,11 @@ -- Test bench: tb/tb_tst_rlink_b3 -- -- Target Devices: generic --- Tool versions: viv 2014.4-2018.3; ghdl 0.31-0.35 +-- Tool versions: viv 2014.4-2022.1; ghdl 0.31-2.0.0 -- -- Synthesized (viv): -- Date Rev viv Target flop lutl lutm bram slic +-- 2022-07-05 1247 2022.1 xc7a35t-1 1039 1492 34 3.0 527 -- 2019-02-02 1108 2018.3 xc7a35t-1 1040 1594 36 3.0 546 -- 2019-02-02 1108 2017.2 xc7a35t-1 1040 1682 36 3.0 587 -- 2016-03-27 753 2015.4 xc7a35t-1 986 1352 36 3.0 473 meminf diff --git a/rtl/sys_gen/tst_rlink/cmoda7/sys_tst_rlink_c7.vhd b/rtl/sys_gen/tst_rlink/cmoda7/sys_tst_rlink_c7.vhd index bfae4f11..d944c2a3 100644 --- a/rtl/sys_gen/tst_rlink/cmoda7/sys_tst_rlink_c7.vhd +++ b/rtl/sys_gen/tst_rlink/cmoda7/sys_tst_rlink_c7.vhd @@ -1,6 +1,6 @@ --- $Id: sys_tst_rlink_c7.vhd 1181 2019-07-08 17:00:50Z mueller $ +-- $Id: sys_tst_rlink_c7.vhd 1247 2022-07-06 07:04:33Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later --- Copyright 2017-2019 by Walter F.J. Mueller +-- Copyright 2017-2022 by Walter F.J. Mueller -- ------------------------------------------------------------------------------ -- Module Name: sys_tst_rlink_c7 - syn @@ -21,10 +21,11 @@ -- Test bench: tb/tb_tst_rlink_c7 -- -- Target Devices: generic --- Tool versions: viv 2016.4-2018.3; ghdl 0.34-0.35 +-- Tool versions: viv 2016.4-2022.1; ghdl 0.34-2.0.0 -- -- Synthesized (viv): -- Date Rev viv Target flop lutl lutm bram slic +-- 2022-07-05 1247 2022.1 xc7a35t-1 913 1402 34 3.0 494 -- 2019-02-02 1108 2018.3 xc7a35t-1 913 1494 36 3.0 496 -- 2019-02-02 1108 2017.2 xc7a35t-1 914 1581 36 3.0 510 -- 2017-06-05 907 2016.4 xc7a35t-1 913 1556 36 3.0 513 diff --git a/rtl/sys_gen/tst_rlink/nexys4d/sys_tst_rlink_n4d.vhd b/rtl/sys_gen/tst_rlink/nexys4d/sys_tst_rlink_n4d.vhd index 7248dbb6..678276f9 100644 --- a/rtl/sys_gen/tst_rlink/nexys4d/sys_tst_rlink_n4d.vhd +++ b/rtl/sys_gen/tst_rlink/nexys4d/sys_tst_rlink_n4d.vhd @@ -1,6 +1,6 @@ --- $Id: sys_tst_rlink_n4d.vhd 1181 2019-07-08 17:00:50Z mueller $ +-- $Id: sys_tst_rlink_n4d.vhd 1247 2022-07-06 07:04:33Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later --- Copyright 2017-2019 by Walter F.J. Mueller +-- Copyright 2017-2022 by Walter F.J. Mueller -- ------------------------------------------------------------------------------ -- Module Name: sys_tst_rlink_n4d - syn @@ -22,10 +22,11 @@ -- Test bench: tb/tb_tst_rlink_n4d -- -- Target Devices: generic --- Tool versions: viv 2014.4-2018.3; ghdl 0.29-0.35 +-- Tool versions: viv 2014.4-2022.1; ghdl 0.29-2.0.0 -- -- Synthesized: -- Date Rev viv Target flop lutl lutm bram slic +-- 2022-07-05 1247 2022.1 xc7a100t-1 1181 1611 34 3.0 581 -- 2019-02-02 1108 2018.3 xc7a100t-1 1179 1721 36 3.0 597 -- 2019-02-02 1108 2017.2 xc7a100t-1 1179 1802 36 3.0 619 -- 2016-04-02 758 2015.4 xc7a100t-1 1113 1461 36 3.0 528 usracc diff --git a/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop1_n4d.vhd b/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop1_n4d.vhd index 7aa69b53..a1e6cd85 100644 --- a/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop1_n4d.vhd +++ b/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop1_n4d.vhd @@ -1,6 +1,6 @@ --- $Id: sys_tst_serloop1_n4d.vhd 1181 2019-07-08 17:00:50Z mueller $ +-- $Id: sys_tst_serloop1_n4d.vhd 1247 2022-07-06 07:04:33Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later --- Copyright 2017-2019 by Walter F.J. Mueller +-- Copyright 2017-2022 by Walter F.J. Mueller -- ------------------------------------------------------------------------------ -- Module Name: sys_tst_serloop1_n4d - syn @@ -17,10 +17,11 @@ -- Test bench: - -- -- Target Devices: generic --- Tool versions: viv 2016.2-2018.3; ghdl 0.33-0.35 +-- Tool versions: viv 2016.2-2022.1; ghdl 0.33-2.0.0 -- -- Synthesized: -- Date Rev viv Target flop lutl lutm bram slic +-- 2022-07-05 1247 2022.1 xc7a100t-1 409 421 12 0 189 -- 2019-02-02 1108 2018.3 xc7a100t-1 409 456 16 0 200 -- 2019-02-02 1108 2017.2 xc7a100t-1 409 446 16 0 186 -- diff --git a/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop2_n4d.vhd b/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop2_n4d.vhd index ab7b3c59..4372726f 100644 --- a/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop2_n4d.vhd +++ b/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop2_n4d.vhd @@ -1,6 +1,6 @@ --- $Id: sys_tst_serloop2_n4d.vhd 1181 2019-07-08 17:00:50Z mueller $ +-- $Id: sys_tst_serloop2_n4d.vhd 1247 2022-07-06 07:04:33Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later --- Copyright 2017-2019 by Walter F.J. Mueller +-- Copyright 2017-2022 by Walter F.J. Mueller -- ------------------------------------------------------------------------------ -- Module Name: sys_tst_serloop2_n4d - syn @@ -16,10 +16,11 @@ -- Test bench: - -- -- Target Devices: generic --- Tool versions: viv 2016.2-2018.3; ghdl 0.33-0.35 +-- Tool versions: viv 2016.2-2022.1; ghdl 0.33-2.0.0 -- -- Synthesized: -- Date Rev viv Target flop lutl lutm bram slic +-- 2022-07-05 1247 2022.1 xc7a100t-1 537 482 12 0 238 -- 2019-02-02 1108 2018.3 xc7a100t-1 537 510 16 0 232 -- 2019-02-02 1108 2017.2 xc7a100t-1 537 552 16 0 238 -- diff --git a/rtl/sys_gen/tst_snhumanio/basys3/sys_tst_snhumanio_b3.vhd b/rtl/sys_gen/tst_snhumanio/basys3/sys_tst_snhumanio_b3.vhd index 1f768672..0c86fe69 100644 --- a/rtl/sys_gen/tst_snhumanio/basys3/sys_tst_snhumanio_b3.vhd +++ b/rtl/sys_gen/tst_snhumanio/basys3/sys_tst_snhumanio_b3.vhd @@ -1,6 +1,6 @@ --- $Id: sys_tst_snhumanio_b3.vhd 1181 2019-07-08 17:00:50Z mueller $ +-- $Id: sys_tst_snhumanio_b3.vhd 1247 2022-07-06 07:04:33Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later --- Copyright 2015-2019 by Walter F.J. Mueller +-- Copyright 2015-2022 by Walter F.J. Mueller -- ------------------------------------------------------------------------------ -- Module Name: sys_tst_snhumanio_b3 - syn @@ -13,10 +13,11 @@ -- Test bench: - -- -- Target Devices: generic --- Tool versions: viv 2014.4-2018.3; ghdl 0.31-0.35 +-- Tool versions: viv 2014.4-2022.1; ghdl 0.31-2.0.0 -- -- Synthesized (viv): -- Date Rev viv Target flop lutl lutm bram slic +-- 2022--7-05 1247 2022.1 xc7a35t-1 154 161 0 0 67 -- 2019-02-02 1108 2018.3 xc7a35t-1 154 187 0 0 75 -- 2019-02-02 1108 2017.2 xc7a35t-1 154 184 0 0 69 -- 2015-01-30 636 2014.4 xc7a35t-1 154 133 0 0 63 diff --git a/rtl/sys_gen/tst_snhumanio/nexys4d/sys_tst_snhumanio_n4d.vhd b/rtl/sys_gen/tst_snhumanio/nexys4d/sys_tst_snhumanio_n4d.vhd index 0336df97..533e47b7 100644 --- a/rtl/sys_gen/tst_snhumanio/nexys4d/sys_tst_snhumanio_n4d.vhd +++ b/rtl/sys_gen/tst_snhumanio/nexys4d/sys_tst_snhumanio_n4d.vhd @@ -1,6 +1,6 @@ --- $Id: sys_tst_snhumanio_n4d.vhd 1181 2019-07-08 17:00:50Z mueller $ +-- $Id: sys_tst_snhumanio_n4d.vhd 1247 2022-07-06 07:04:33Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later --- Copyright 2017-2019 by Walter F.J. Mueller +-- Copyright 2017-2022 by Walter F.J. Mueller -- ------------------------------------------------------------------------------ -- Module Name: sys_tst_snhumanio_n4d - syn @@ -13,10 +13,11 @@ -- Test bench: - -- -- Target Devices: generic --- Tool versions: viv 2016.2-2018.3; ghdl 0.31-0.35 +-- Tool versions: viv 2016.2-2022.1; ghdl 0.31-2.0.0 -- -- Synthesized: -- Date Rev viv Target flop lutl lutm bram slic +-- 2022-07-05 1247 2022.1 xc7a100t-1 154 164 0 0 67 -- 2019-02-02 1108 2018.3 xc7a100t-1 154 187 0 0 74 -- 2019-02-02 1108 2017.2 xc7a100t-1 154 185 0 0 68 -- diff --git a/rtl/sys_gen/tst_sram/arty/sys_tst_sram_arty.vbom b/rtl/sys_gen/tst_sram/arty/sys_tst_sram_arty.vbom index ceb5f0c7..27bd85f9 100644 --- a/rtl/sys_gen/tst_sram/arty/sys_tst_sram_arty.vbom +++ b/rtl/sys_gen/tst_sram/arty/sys_tst_sram_arty.vbom @@ -1,5 +1,6 @@ # libs ../../../vlib/slvtypes.vhd +../../../vlib/xlib/xlib.vhd ../../../vlib/cdclib/cdclib.vhd ../../../vlib/serport/serportlib.vbom ../../../vlib/rbus/rblib.vhd @@ -11,8 +12,8 @@ ../../../bplib/mig/miglib.vbom ../../../bplib/arty/miglib_arty.vbom ${sys_conf := sys_conf.vhd} -@lib:unisim # components +../../../vlib/xlib/bufg_unisim.vbom ../../../bplib/bpgen/s7_cmt_1ce1ce2c.vbom ../../../vlib/cdclib/cdc_signal_s1_as.vbom ../../../bplib/bpgen/bp_rs232_2line_iob.vbom diff --git a/rtl/sys_gen/tst_sram/arty/sys_tst_sram_arty.vhd b/rtl/sys_gen/tst_sram/arty/sys_tst_sram_arty.vhd index a48d292d..a711d035 100644 --- a/rtl/sys_gen/tst_sram/arty/sys_tst_sram_arty.vhd +++ b/rtl/sys_gen/tst_sram/arty/sys_tst_sram_arty.vhd @@ -1,12 +1,13 @@ --- $Id: sys_tst_sram_arty.vhd 1181 2019-07-08 17:00:50Z mueller $ +-- $Id: sys_tst_sram_arty.vhd 1247 2022-07-06 07:04:33Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later --- Copyright 2018-2019 by Walter F.J. Mueller +-- Copyright 2018-2022 by Walter F.J. Mueller -- ------------------------------------------------------------------------------ -- Module Name: sys_tst_sram_arty - syn -- Description: test of arty ddr and its mig controller -- --- Dependencies: bplib/bpgen/s7_cmt_1ce1ce2c +-- Dependencies: vlib/xlib/bufg_unisim +-- bplib/bpgen/s7_cmt_1ce1ce2c -- cdclib/cdc_signal_s1_as -- bplib/bpgen/bp_rs232_2line_iob -- rlink/rlink_sp2c @@ -20,16 +21,18 @@ -- Test bench: tb/tb_tst_sram_arty -- -- Target Devices: generic --- Tool versions: viv 2017.2-2018.3; ghdl 0.34-0.35 +-- Tool versions: viv 2017.2-2022.1; ghdl 0.34-2.0.0 -- -- Synthesized (viv): -- Date Rev viv Target flop lutl lutm bram slic +-- 2022-07-05 1247 2022.1 xc7a35t-1l 4648 4594 611 5 1849 -- 2019-02-02 1108 2018.3 xc7a35t-1l 4648 4968 644 5 1983 -- 2019-02-02 1108 2017.2 xc7a35t-1l 4643 5334 644 5 1929 -- 2019-01-02 1101 2017.2 xc7a35t-1l 4643 5334 644 5 1929 -- -- Revision History: -- Date Rev Version Comment +-- 2022-07-05 1247 1.0.1 use bufg_unisim -- 2018-12-20 1090 1.0 Initial version -- 2018-11-17 1071 0.1 First draft (derived from sys_tst_sram_c7) ------------------------------------------------------------------------------ @@ -39,6 +42,7 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.slvtypes.all; +use work.xlib.all; use work.cdclib.all; use work.serportlib.all; use work.rblib.all; @@ -51,9 +55,6 @@ use work.miglib.all; use work.miglib_arty.all; use work.sys_conf.all; -library unisim; -use unisim.vcomponents.ALL; - -- ---------------------------------------------------------------------------- entity sys_tst_sram_arty is -- top level @@ -161,7 +162,7 @@ architecture syn of sys_tst_sram_arty is begin - CLK100_BUFG: bufg + CLK100_BUFG: bufg_unisim port map ( I => I_CLK100, O => CLK100_BUF diff --git a/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd b/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd index b74bd9bc..58b33385 100644 --- a/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd +++ b/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd @@ -1,6 +1,6 @@ --- $Id: sys_tst_sram_c7.vhd 1181 2019-07-08 17:00:50Z mueller $ +-- $Id: sys_tst_sram_c7.vhd 1247 2022-07-06 07:04:33Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later --- Copyright 2017-2019 by Walter F.J. Mueller +-- Copyright 2017-2022 by Walter F.J. Mueller -- ------------------------------------------------------------------------------ -- Module Name: sys_tst_sram_c7 - syn @@ -19,10 +19,11 @@ -- Test bench: tb/tb_tst_sram_c7 -- -- Target Devices: generic --- Tool versions: viv 2017.1-2018.3; ghdl 0.34-0.35 +-- Tool versions: viv 2017.1-2022.1; ghdl 0.34-2.0.0 -- -- Synthesized (viv): -- Date Rev viv Target flop lutl lutm bram slic +-- 2022-07-05 1247 2022.1 xc7a35t-1 1045 1355 18 5.0 469 -- 2019-02-02 1108 2018.3 xc7a35t-1 1045 1537 24 5.0 490 -- 2019-02-02 1108 2017.2 xc7a35t-1 1042 1541 24 5.0 494 -- diff --git a/rtl/sys_gen/tst_sram/nexys4d/sys_tst_sram_n4d.vbom b/rtl/sys_gen/tst_sram/nexys4d/sys_tst_sram_n4d.vbom index 6b8ba198..0999a79d 100644 --- a/rtl/sys_gen/tst_sram/nexys4d/sys_tst_sram_n4d.vbom +++ b/rtl/sys_gen/tst_sram/nexys4d/sys_tst_sram_n4d.vbom @@ -1,5 +1,6 @@ # libs ../../../vlib/slvtypes.vhd +../../../vlib/xlib/xlib.vhd ../../../vlib/cdclib/cdclib.vhd ../../../vlib/serport/serportlib.vbom ../../../vlib/rbus/rblib.vhd @@ -12,6 +13,7 @@ ../../../bplib/nexys4d/miglib_nexys4d.vbom ${sys_conf := sys_conf.vhd} # components +../../../vlib/xlib/bufg_unisim.vbom ../../../bplib/bpgen/s7_cmt_1ce1ce2c.vbom ../../../vlib/cdclib/cdc_signal_s1_as.vbom ../../../bplib/bpgen/bp_rs232_4line_iob.vbom diff --git a/rtl/sys_gen/tst_sram/nexys4d/sys_tst_sram_n4d.vhd b/rtl/sys_gen/tst_sram/nexys4d/sys_tst_sram_n4d.vhd index ff26b797..e56b3a1c 100644 --- a/rtl/sys_gen/tst_sram/nexys4d/sys_tst_sram_n4d.vhd +++ b/rtl/sys_gen/tst_sram/nexys4d/sys_tst_sram_n4d.vhd @@ -1,12 +1,13 @@ --- $Id: sys_tst_sram_n4d.vhd 1201 2019-08-10 16:51:22Z mueller $ +-- $Id: sys_tst_sram_n4d.vhd 1247 2022-07-06 07:04:33Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later --- Copyright 2018-2019 by Walter F.J. Mueller +-- Copyright 2018-2022 by Walter F.J. Mueller -- ------------------------------------------------------------------------------ -- Module Name: sys_tst_sram_n4d - syn -- Description: test of nexys4d ddr and its mig controller -- --- Dependencies: bplib/bpgen/s7_cmt_1ce1ce2c +-- Dependencies: vlib/xlib/bufg_unisim +-- bplib/bpgen/s7_cmt_1ce1ce2c -- cdclib/cdc_signal_s1_as -- bplib/bpgen/bp_rs232_4line_iob -- bplib/bpgen/sn_humanio @@ -20,10 +21,11 @@ -- Test bench: tb/tb_tst_sram_n4d -- -- Target Devices: generic --- Tool versions: viv 2017.2-2019.1; ghdl 0.34-0.35 +-- Tool versions: viv 2017.2-2022.1; ghdl 0.34-2.0.0 -- -- Synthesized: -- Date Rev viv Target flop lutl lutm bram slic +-- 2022-07-05 1247 2022.1 xc7a100t-1 4408 4197 608 5 1761 -- 2019-08-10 1201 2019.1 xc7a100t-1 4409 4606 656 5 1875 -- 2019-02-02 1108 2018.3 xc7a100t-1 4408 4606 656 5 1895 -- 2019-02-02 1108 2017.2 xc7a100t-1 4403 4900 657 5 1983 @@ -31,6 +33,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2022-07-05 1247 1.1.1 use bufg_unisim -- 2019-08-10 1201 1.1 use 100 MHz MIG SYS_CLK -- 2019-01-02 1101 1.0 Initial version -- 2018-12-30 1099 0.1 First draft (derived from sys_tst_sram_n4/arty) @@ -41,6 +44,7 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.slvtypes.all; +use work.xlib.all; use work.cdclib.all; use work.serportlib.all; use work.rblib.all; @@ -53,9 +57,6 @@ use work.miglib.all; use work.miglib_nexys4d.all; use work.sys_conf.all; -library unisim; -use unisim.vcomponents.ALL; - -- ---------------------------------------------------------------------------- entity sys_tst_sram_n4d is -- top level @@ -158,7 +159,7 @@ architecture syn of sys_tst_sram_n4d is begin - CLK100_BUFG: bufg + CLK100_BUFG: bufg_unisim port map ( I => I_CLK100, O => CLK100_BUF diff --git a/rtl/sys_gen/w11a/arty/sys_w11a_arty.vbom b/rtl/sys_gen/w11a/arty/sys_w11a_arty.vbom index 44545b17..aa6240dd 100644 --- a/rtl/sys_gen/w11a/arty/sys_w11a_arty.vbom +++ b/rtl/sys_gen/w11a/arty/sys_w11a_arty.vbom @@ -1,5 +1,6 @@ # libs ../../../vlib/slvtypes.vhd +../../../vlib/xlib/xlib.vhd ../../../vlib/cdclib/cdclib.vhd ../../../vlib/serport/serportlib.vbom ../../../vlib/rbus/rblib.vhd @@ -13,8 +14,8 @@ ../../../ibus/ibdlib.vhd ../../../w11a/pdp11.vhd ${sys_conf := sys_conf.vhd} -@lib:unisim # components +../../../vlib/xlib/bufg_unisim.vbom ../../../bplib/bpgen/s7_cmt_1ce1ce2c.vbom ../../../vlib/cdclib/cdc_signal_s1_as.vbom ../../../bplib/bpgen/bp_rs232_2line_iob.vbom diff --git a/rtl/sys_gen/w11a/arty/sys_w11a_arty.vhd b/rtl/sys_gen/w11a/arty/sys_w11a_arty.vhd index 2e8ddfe4..98216f57 100644 --- a/rtl/sys_gen/w11a/arty/sys_w11a_arty.vhd +++ b/rtl/sys_gen/w11a/arty/sys_w11a_arty.vhd @@ -1,12 +1,13 @@ --- $Id: sys_w11a_arty.vhd 1211 2021-08-28 11:20:34Z mueller $ +-- $Id: sys_w11a_arty.vhd 1247 2022-07-06 07:04:33Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later --- Copyright 2018-2019 by Walter F.J. Mueller +-- Copyright 2018-2022 by Walter F.J. Mueller -- ------------------------------------------------------------------------------ -- Module Name: sys_w11a_arty - syn -- Description: w11a design for arty (with dram via mig) -- --- Dependencies: bplib/bpgen/s7_cmt_1ce1ce2c +-- Dependencies: vlib/xlib/bufg_unisim +-- bplib/bpgen/s7_cmt_1ce1ce2c -- cdclib/cdc_signal_s1_as -- bplib/bpgen/bp_rs232_2line_iob -- vlib/rlink/rlink_sp2c @@ -24,10 +25,11 @@ -- Test bench: tb/tb_sys_w11a_arty -- -- Target Devices: generic --- Tool versions: viv 2017.2-2018.3; ghdl 0.34-0.35 +-- Tool versions: viv 2017.2-2022.1; ghdl 0.34-2.0.0 -- -- Synthesized: -- Date Rev viv Target flop lutl lutm bram slic +-- 2022-07-05 1247 2022.1 xc7a35t-1l 6842 9218 872 17.5 3210 -- 2019-05-19 1150 2017.2 xc7a35t-1l 6838 10574 923 17.5 3392 +dz11 -- 2019-04-27 1140 2017.2 xc7a35t-1l 6706 10249 898 17.0 3380 +*buf -- 2019-03-02 1116 2017.2 xc7a35t-1l 6625 10705 836 17.0 3218 @@ -36,6 +38,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2022-07-05 1247 1.1.2 use bufg_unisim -- 2018-12-28 1096 1.1.1 setup reset for sramif_mig_arty -- 2018-12-16 1086 1.1 use s7_cmt_1ce1ce2c -- 2018-11-18 1072 1.0 Initial version @@ -90,6 +93,7 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.slvtypes.all; +use work.xlib.all; use work.cdclib.all; use work.serportlib.all; use work.rblib.all; @@ -104,9 +108,6 @@ use work.ibdlib.all; use work.pdp11.all; use work.sys_conf.all; -library unisim; -use unisim.vcomponents.ALL; - -- ---------------------------------------------------------------------------- entity sys_w11a_arty is -- top level @@ -230,7 +231,7 @@ begin report "assert sys_conf_clksys on MHz grid" severity failure; - CLK100_BUFG: bufg + CLK100_BUFG: bufg_unisim port map ( I => I_CLK100, O => CLK100_BUF diff --git a/rtl/sys_gen/w11a/artys7/sys_w11a_as7.vbom b/rtl/sys_gen/w11a/artys7/sys_w11a_as7.vbom index c99c892a..46182267 100644 --- a/rtl/sys_gen/w11a/artys7/sys_w11a_as7.vbom +++ b/rtl/sys_gen/w11a/artys7/sys_w11a_as7.vbom @@ -1,5 +1,6 @@ # libs ../../../vlib/slvtypes.vhd +../../../vlib/xlib/xlib.vhd ../../../vlib/cdclib/cdclib.vhd ../../../vlib/serport/serportlib.vbom ../../../vlib/rbus/rblib.vhd @@ -14,6 +15,7 @@ ../../../w11a/pdp11.vhd ${sys_conf := sys_conf.vhd} # components +../../../vlib/xlib/bufg_unisim.vbom ../../../bplib/bpgen/s7_cmt_1ce1ce2c.vbom ../../../vlib/cdclib/cdc_signal_s1_as.vbom ../../../bplib/bpgen/bp_rs232_2line_iob.vbom diff --git a/rtl/sys_gen/w11a/artys7/sys_w11a_as7.vhd b/rtl/sys_gen/w11a/artys7/sys_w11a_as7.vhd index 358bb714..a6f61bb9 100644 --- a/rtl/sys_gen/w11a/artys7/sys_w11a_as7.vhd +++ b/rtl/sys_gen/w11a/artys7/sys_w11a_as7.vhd @@ -1,12 +1,13 @@ --- $Id: sys_w11a_as7.vhd 1211 2021-08-28 11:20:34Z mueller $ +-- $Id: sys_w11a_as7.vhd 1247 2022-07-06 07:04:33Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later --- Copyright 2019- by Walter F.J. Mueller +-- Copyright 2019-2022 by Walter F.J. Mueller -- ------------------------------------------------------------------------------ -- Module Name: sys_w11a_br_as7 - syn -- Description: w11a design for as7 (with dram via mig) -- --- Dependencies: bplib/bpgen/s7_cmt_1ce1ce2c +-- Dependencies: vlib/xlib/bufg_unisim +-- bplib/bpgen/s7_cmt_1ce1ce2c -- cdclib/cdc_signal_s1_as -- bplib/bpgen/bp_rs232_2line_iob -- vlib/rlink/rlink_sp2c @@ -24,15 +25,17 @@ -- Test bench: tb/tb_sys_w11a_as7 -- -- Target Devices: generic --- Tool versions: viv 2018.3; ghdl 0.35 +-- Tool versions: viv 2018.3-2022.1; ghdl 0.35-2.0.0 -- -- Synthesized: -- Date Rev viv Target flop lutl lutm bram slic +-- 2022-07-05 1247 2022.1 xc7s50 6843 9162 878 17.5 3184 -- 2019-05-19 1150 2018.3 xc7s50 6843 10554 926 17.5 3425 +dz11 -- 2019-01-12 1105 2018.3 xc7s50 6585 9837 806 17.0 3250 -- -- Revision History: -- Date Rev Version Comment +-- 2022-07-05 1247 1.0.1 use bufg_unisim -- 2019-01-12 1105 1.0 Initial version (derived from sys_w11a_arty/br_as7) ------------------------------------------------------------------------------ -- @@ -80,6 +83,7 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.slvtypes.all; +use work.xlib.all; use work.cdclib.all; use work.serportlib.all; use work.rblib.all; @@ -94,9 +98,6 @@ use work.ibdlib.all; use work.pdp11.all; use work.sys_conf.all; -library unisim; -use unisim.vcomponents.ALL; - -- ---------------------------------------------------------------------------- entity sys_w11a_as7 is -- top level @@ -216,7 +217,7 @@ begin report "assert sys_conf_clksys on MHz grid" severity failure; - CLK100_BUFG: bufg + CLK100_BUFG: bufg_unisim port map ( I => I_CLK100, O => CLK100_BUF diff --git a/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd b/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd index bfebe296..9c906562 100644 --- a/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd +++ b/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd @@ -1,6 +1,6 @@ --- $Id: sys_w11a_b3.vhd 1181 2019-07-08 17:00:50Z mueller $ +-- $Id: sys_w11a_b3.vhd 1247 2022-07-06 07:04:33Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later --- Copyright 2015-2019 by Walter F.J. Mueller +-- Copyright 2015-2022 by Walter F.J. Mueller -- ------------------------------------------------------------------------------ -- Module Name: sys_w11a_b3 - syn @@ -22,10 +22,11 @@ -- Test bench: tb/tb_sys_w11a_b3 -- -- Target Devices: generic --- Tool versions: viv 2014.4-2018.3; ghdl 0.31-0.35 +-- Tool versions: viv 2014.4-2022.1; ghdl 0.31-2.0.0 -- -- Synthesized: -- Date Rev viv Target flop lutl lutm bram slic +-- 2022-07-05 1247 2022.1 xc7a35t-1 3011 5669 267 48.0 1906 -- 2019-05-19 1150 2017.2 xc7a35t-1 2968 6360 273 48.0 1963 +dz11 -- 2019-04-27 1140 2017.2 xc7a35t-1 2835 6032 248 47.5 1879 +*buf -- 2019-03-02 1116 2017.2 xc7a35t-1 2748 5725 186 47.5 1811 +ibtst diff --git a/rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vhd b/rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vhd index 4fb118bb..44e2ef84 100644 --- a/rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vhd +++ b/rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vhd @@ -1,6 +1,6 @@ --- $Id: sys_w11a_c7.vhd 1211 2021-08-28 11:20:34Z mueller $ +-- $Id: sys_w11a_c7.vhd 1247 2022-07-06 07:04:33Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later --- Copyright 2017-2019 by Walter F.J. Mueller +-- Copyright 2017-2022 by Walter F.J. Mueller -- ------------------------------------------------------------------------------ -- Module Name: sys_w11a_c7 - syn @@ -24,10 +24,11 @@ -- Test bench: tb/tb_sys_w11a_c7 -- -- Target Devices: generic --- Tool versions: viv 2017.2-2018.3; ghdl 0.34-0.35 +-- Tool versions: viv 2017.2-2022.1; ghdl 0.34-2.0.0 -- -- Synthesized: -- Date Rev viv Target flop lutl lutm bram slic +-- 2022-07-05 1247 2022.1 xc7a35t-1 3411 6189 279 50.0 2021 -- 2019-05-19 1150 2017.2 xc7a35t-1 3369 6994 285 50.0 2099 +dz11 -- 2019-04-27 1140 2017.2 xc7a35t-1 3243 6618 260 50.0 2009 +ibtst -- 2019-03-02 1116 2017.2 xc7a35t-1 3156 6332 198 50.0 1918 +ibtst diff --git a/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vhd b/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vhd index 1179fb68..19697a19 100644 --- a/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vhd +++ b/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vhd @@ -1,6 +1,6 @@ --- $Id: sys_w11a_n4.vhd 1181 2019-07-08 17:00:50Z mueller $ +-- $Id: sys_w11a_n4.vhd 1247 2022-07-06 07:04:33Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later --- Copyright 2013-2019 by Walter F.J. Mueller +-- Copyright 2013-2022 by Walter F.J. Mueller -- ------------------------------------------------------------------------------ -- Module Name: sys_w11a_n4 - syn @@ -22,10 +22,11 @@ -- Test bench: tb/tb_sys_w11a_n4 -- -- Target Devices: generic --- Tool versions: viv 2014.4-2018.3; ghdl 0.29-0.35 (ise 14.5-14.7 retired) +-- Tool versions: viv 2014.4-2022.1; ghdl 0.29-2.0.0 (ise 14.5-14.7 retired) -- -- Synthesized: -- Date Rev viv Target flop lutl lutm bram slic MHz +-- 2022-07-05 1247 2022.1 xc7a100t-1 3455 6137 279 17.5 2100 80 -- 2019-05-19 1150 2017.2 xc7a100t-1 3418 7272 285 17.5 2234 80 +dz11 -- 2019-05-01 1143 2017.2 xc7a100t-1 3295 6597 260 17.5 2107 80 +m9312 -- 2019-04-27 1140 2017.2 xc7a100t-1 3288 6574 260 17.0 2132 80 +dlbuf diff --git a/rtl/sys_gen/w11a/nexys4d/sys_w11a_n4d.vbom b/rtl/sys_gen/w11a/nexys4d/sys_w11a_n4d.vbom index e1525196..0d1154bf 100644 --- a/rtl/sys_gen/w11a/nexys4d/sys_w11a_n4d.vbom +++ b/rtl/sys_gen/w11a/nexys4d/sys_w11a_n4d.vbom @@ -1,5 +1,6 @@ # libs ../../../vlib/slvtypes.vhd +../../../vlib/xlib/xlib.vhd ../../../vlib/cdclib/cdclib.vhd ../../../vlib/serport/serportlib.vbom ../../../vlib/rbus/rblib.vhd @@ -14,8 +15,8 @@ ../../../ibus/ibdlib.vhd ../../../w11a/pdp11.vhd ${sys_conf := sys_conf.vhd} -@lib:unisim # components +../../../vlib/xlib/bufg_unisim.vbom ../../../bplib/bpgen/s7_cmt_1ce1ce2c.vbom ../../../vlib/cdclib/cdc_signal_s1_as.vbom ../../../bplib/bpgen/bp_rs232_4line_iob.vbom diff --git a/rtl/sys_gen/w11a/nexys4d/sys_w11a_n4d.vhd b/rtl/sys_gen/w11a/nexys4d/sys_w11a_n4d.vhd index b4926f8f..9e7515ab 100644 --- a/rtl/sys_gen/w11a/nexys4d/sys_w11a_n4d.vhd +++ b/rtl/sys_gen/w11a/nexys4d/sys_w11a_n4d.vhd @@ -1,12 +1,13 @@ --- $Id: sys_w11a_n4d.vhd 1201 2019-08-10 16:51:22Z mueller $ +-- $Id: sys_w11a_n4d.vhd 1247 2022-07-06 07:04:33Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later --- Copyright 2019- by Walter F.J. Mueller +-- Copyright 2019-2022 by Walter F.J. Mueller -- ------------------------------------------------------------------------------ -- Module Name: sys_w11a_n4d - syn -- Description: w11a design for nexys4 DDR (with dram via mig) -- --- Dependencies: bplib/bpgen/s7_cmt_1ce1ce +-- Dependencies: vlib/xlib/bufg_unisim +-- bplib/bpgen/s7_cmt_1ce1ce -- cdclib/cdc_signal_s1_as -- bplib/bpgen/bp_rs232_4line_iob -- vlib/rlink/rlink_sp2c @@ -23,10 +24,11 @@ -- Test bench: tb/tb_sys_w11a_n4d -- -- Target Devices: generic --- Tool versions: viv 2017.2-2018.3; ghdl 0.34-0.35 +-- Tool versions: viv 2017.2-2022.1; ghdl 0.34-2.0.0 -- -- Synthesized: -- Date Rev viv Target flop lutl lutm bram slic MHz +-- 2022-07-05 1247 2022.1 xc7a100t-1 6805 8961 869 17.5 3282 80 -- 2019-08-10 1201 2019.1 xc7a100t-1 6850 10258 901 17.5 3563 80 -- 2019-05-19 1150 2017.2 xc7a100t-1 6811 10322 901 17.5 3496 80 +dz11 -- 2019-02-02 1108 2018.3 xc7a100t-1 6558 9537 814 17.0 3443 80 @@ -34,6 +36,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2022-07-05 1247 1.1.1 use bufg_unisim -- 2019-08-10 1201 1.1 use 100 MHz MIG SYS_CLK -- 2019-01-02 1101 1.0 Initial version (derived from sys_w11a_n4 and arty) ------------------------------------------------------------------------------ @@ -88,6 +91,7 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.slvtypes.all; +use work.xlib.all; use work.cdclib.all; use work.serportlib.all; use work.rblib.all; @@ -103,9 +107,6 @@ use work.ibdlib.all; use work.pdp11.all; use work.sys_conf.all; -library unisim; -use unisim.vcomponents.ALL; - -- ---------------------------------------------------------------------------- entity sys_w11a_n4d is -- top level @@ -231,7 +232,7 @@ begin report "assert sys_conf_clksys on MHz grid" severity failure; - CLK100_BUFG: bufg + CLK100_BUFG: bufg_unisim port map ( I => I_CLK100, O => CLK100_BUF diff --git a/rtl/sys_gen/w11a/nexys4d_bram/sys_w11a_br_n4d.vhd b/rtl/sys_gen/w11a/nexys4d_bram/sys_w11a_br_n4d.vhd index d26b224b..66b94c3b 100644 --- a/rtl/sys_gen/w11a/nexys4d_bram/sys_w11a_br_n4d.vhd +++ b/rtl/sys_gen/w11a/nexys4d_bram/sys_w11a_br_n4d.vhd @@ -1,6 +1,6 @@ --- $Id: sys_w11a_br_n4d.vhd 1181 2019-07-08 17:00:50Z mueller $ +-- $Id: sys_w11a_br_n4d.vhd 1247 2022-07-06 07:04:33Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later --- Copyright 2017-2019 by Walter F.J. Mueller +-- Copyright 2017-2022 by Walter F.J. Mueller -- ------------------------------------------------------------------------------ -- Module Name: sys_w11a_br_n4d - syn @@ -22,10 +22,11 @@ -- Test bench: tb/tb_sys_w11a_br_n4d -- -- Target Devices: generic --- Tool versions: viv 2016.2-2018.3; ghdl 0.34-0.35 +-- Tool versions: viv 2016.2-2022.1; ghdl 0.34-2.0.0 -- -- Synthesized: -- Date Rev viv Target flop lutl lutm bram slic +-- 2022-07-05 1247 2022.1 xc7a100t-1 3099 5842 267 132.0 1957 -- 2019-05-19 1150 2017.2 xc7a100t-1 3097 6562 273 132.0 2110 +dz11 -- 2019-02-02 1108 2018.3 xc7a100t-1 2837 6083 170 131.5 1957 -- 2019-02-02 1108 2017.2 xc7a100t-1 2825 5843 170 131.5 1824 +dmpcnt diff --git a/rtl/vlib/xlib/bufg_unisim.vbom b/rtl/vlib/xlib/bufg_unisim.vbom new file mode 100644 index 00000000..34e73a8a --- /dev/null +++ b/rtl/vlib/xlib/bufg_unisim.vbom @@ -0,0 +1,4 @@ +# libs +@lib:unisim +# design +bufg_unisim.vhd diff --git a/rtl/vlib/xlib/bufg_unisim.vhd b/rtl/vlib/xlib/bufg_unisim.vhd new file mode 100644 index 00000000..117d45f5 --- /dev/null +++ b/rtl/vlib/xlib/bufg_unisim.vhd @@ -0,0 +1,42 @@ +-- $Id: bufg_unisim.vhd 1247 2022-07-06 07:04:33Z mueller $ +-- SPDX-License-Identifier: GPL-3.0-or-later +-- Copyright 2022- by Walter F.J. Mueller +-- +------------------------------------------------------------------------------ +-- Module Name: bufg_unisim - syn +-- Description: Wrapper for BUFG entity +-- +-- Dependencies: - +-- Test bench: - +-- Target Devices: generic Series-7 +-- Tool versions: viv 2022.1; ghdl 2.0.0 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2022-07-05 1247 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +library unisim; +use unisim.vcomponents.ALL; + +entity bufg_unisim is -- wrapper for BUFG + port ( + O : out std_ulogic; -- input + I : in std_ulogic -- output + ); +end bufg_unisim; + + +architecture syn of bufg_unisim is +begin + + BUF : BUFG + port map ( + O => O, + I => I + ); + +end syn; diff --git a/rtl/vlib/xlib/xlib.vhd b/rtl/vlib/xlib/xlib.vhd index 70447729..6d54aff9 100644 --- a/rtl/vlib/xlib/xlib.vhd +++ b/rtl/vlib/xlib/xlib.vhd @@ -1,15 +1,16 @@ --- $Id: xlib.vhd 1181 2019-07-08 17:00:50Z mueller $ +-- $Id: xlib.vhd 1247 2022-07-06 07:04:33Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later --- Copyright 2007-2018 by Walter F.J. Mueller +-- Copyright 2007-2022 by Walter F.J. Mueller -- ------------------------------------------------------------------------------ -- Package Name: xlib -- Description: Xilinx specific components -- -- Dependencies: - --- Tool versions: ise 8.2-14.7; viv 2014.4-2018.2; ghdl 0.18-0.34 +-- Tool versions: ise 8.2-14.7; viv 2014.4-2022.1; ghdl 0.18-2.0.0 -- Revision History: -- Date Rev Version Comment +-- 2022-07-05 1247 1.1.2 add bufg_unisim -- 2018-11-18 1072 1.1.1 add s7_cmt_sfs_3 and s7_cmt_sfs_2 -- 2018-11-03 1064 1.1 add sfs_gsim_core -- 2016-04-02 758 1.0.11 add usr_access_unisim @@ -264,4 +265,11 @@ component usr_access_unisim is -- wrapper for USR_ACCESS family ); end component; +component bufg_unisim is -- wrapper for bufg + port ( + O : out std_ulogic; -- input + I : in std_ulogic -- output + ); +end component; + end package xlib;