diff --git a/rtl/sys_gen/README.md b/rtl/sys_gen/README.md index 53e4780d..e158444c 100644 --- a/rtl/sys_gen/README.md +++ b/rtl/sys_gen/README.md @@ -1,12 +1,12 @@ This directory sub-tree contains **HDL sources for top level designs** and is organized in -| Directory | Content | -| --------- | ------- | -| [tst_mig](tst_mig) | MIG core tester | -| [tst_rlink](tst_rlink) | rlink tester (over serial links) | -| [tst_rlink_cuff](tst_rlink_cuff) | rlink tester (over Cypress FX2 USB) | -| [tst_serloop](tst_serloop) | serial port loop back tester | -| [tst_snhumanio](tst_snhumanio) | Digilent board human IO tester | -| [tst_sram](tst_sram) | memory tester (SRAM or CRAM) | -| [w11a](w11a) | w11a systems | +| Directory | Content | s3 | n2 | n3 |atl| n4 | n4d| arty| as7| b3 | c7 | +| -------------------------------- | -------------------------------- |:--:|:--:|:--:|:-:|:--:|:--:|:---:|:--:|:--:|:--:| +| [tst_mig](tst_mig) | MIG core tester | - | - | - | - | - | y | y | - | - | - | +| [tst_rlink](tst_rlink) | rlink tester (over serial links) | y | y | y | - | y | y | y | - | y | y | +| [tst_rlink_cuff](tst_rlink_cuff) | rlink tester (over Cypress FX2) | - | y | y | y | - | - | - | - | - | - | +| [tst_serloop](tst_serloop) | serial port loop back tester | y | y | y | - | y | y | - | - | - | - | +| [tst_snhumanio](tst_snhumanio) | Digilent board human IO tester | y | y | y | y | y | y | - | - | y | - | +| [tst_sram](tst_sram) | memory tester | y | y | y | - | y | y | y | - | - | y | +| [w11a](w11a) | w11a systems | y | y | y | - | y | y | y | y | y | y | diff --git a/rtl/sys_gen/tst_mig/README.md b/rtl/sys_gen/tst_mig/README.md new file mode 100644 index 00000000..f4f4d5fa --- /dev/null +++ b/rtl/sys_gen/tst_mig/README.md @@ -0,0 +1,7 @@ +This directory sub-tree contains **MIG core tester systems** +and is organized in + +| Directory | Content | +| --------- | ------- | +| [arty](arty) | design for Digilent Arty A7-35 | +| [nexys4d](nexys4d) | design for Digilent Nexys4 DDR _!! only sim-tested !!_ | diff --git a/rtl/sys_gen/tst_rlink/README.md b/rtl/sys_gen/tst_rlink/README.md new file mode 100644 index 00000000..7eca259b --- /dev/null +++ b/rtl/sys_gen/tst_rlink/README.md @@ -0,0 +1,13 @@ +This directory sub-tree contains **rlink over serial link tester systems** +and is organized in + +| Directory | Content | +| --------- | ------- | +| [arty](arty) | design for Digilent Arty A7-35 | +| [basys3](basys3) | design for Digilent Basys3 | +| [cmoda7](cmoda7) | design for Digilent Cmod A7 (35 die size) | +| [nexys2](nexys2) | design for Digilent Nexys2 | +| [nexys3](nexys3) | design for Digilent Nexys3 | +| [nexys4](nexys4) | design for Digilent Nexys4 (old CRAM version) | +| [nexys4d](nexys4d) | design for Digilent Nexys4 DDR _!! only sim-tested !!_ | +| [s3board](s3board) | design for Digilent S3BOARD | diff --git a/rtl/sys_gen/tst_rlink_cuff/README.md b/rtl/sys_gen/tst_rlink_cuff/README.md new file mode 100644 index 00000000..8e5a93de --- /dev/null +++ b/rtl/sys_gen/tst_rlink_cuff/README.md @@ -0,0 +1,8 @@ +This directory sub-tree contains **rlink over Cypress FX2 tester systems** +and is organized in + +| Directory | Content | +| --------- | ------- | +| [atlys](atlys) | design for Digilent Atlys | +| [nexys2](nexys2) | design for Digilent Nexys2 | +| [nexys3](nexys3) | design for Digilent Nexys3 | diff --git a/rtl/sys_gen/tst_serloop/README.md b/rtl/sys_gen/tst_serloop/README.md new file mode 100644 index 00000000..1fa2d8f7 --- /dev/null +++ b/rtl/sys_gen/tst_serloop/README.md @@ -0,0 +1,10 @@ +This directory sub-tree contains **serial port loop back tester systems** +and is organized in + +| Directory | Content | +| --------- | ------- | +| [nexys2](nexys2) | design for Digilent Nexys2 | +| [nexys3](nexys3) | design for Digilent Nexys3 | +| [nexys4](nexys4) | design for Digilent Nexys4 (old CRAM version) | +| [nexys4d](nexys4d) | design for Digilent Nexys4 DDR _!! only sim-tested !!_ | +| [s3board](s3board) | design for Digilent S3BOARD | diff --git a/rtl/sys_gen/tst_snhumanio/README.md b/rtl/sys_gen/tst_snhumanio/README.md new file mode 100644 index 00000000..9a26c41e --- /dev/null +++ b/rtl/sys_gen/tst_snhumanio/README.md @@ -0,0 +1,12 @@ +This directory sub-tree contains **Digilent board human IO tester systems** +and is organized in + +| Directory | Content | +| --------- | ------- | +| [atlys](atlys) | design for Digilent Atlys | +| [basys3](basys3) | design for Digilent Basys3 | +| [nexys2](nexys2) | design for Digilent Nexys2 | +| [nexys3](nexys3) | design for Digilent Nexys3 | +| [nexys4](nexys4) | design for Digilent Nexys4 (old CRAM version) | +| [nexys4d](nexys4d) | design for Digilent Nexys4 DDR _!! only sim-tested !!_ | +| [s3board](s3board) | design for Digilent S3BOARD | diff --git a/rtl/sys_gen/tst_sram/README.md b/rtl/sys_gen/tst_sram/README.md new file mode 100644 index 00000000..7a0b4d64 --- /dev/null +++ b/rtl/sys_gen/tst_sram/README.md @@ -0,0 +1,12 @@ +This directory sub-tree contains **memory tester systems** +and is organized in + +| Directory | Content | +| --------- | ------- | +| [arty](arty) | design for Digilent Arty A7-35 | +| [cmoda7](cmoda7) | design for Digilent Cmod A7 (35 die size) | +| [nexys2](nexys2) | design for Digilent Nexys2 | +| [nexys3](nexys3) | design for Digilent Nexys3 | +| [nexys4](nexys4) | design for Digilent Nexys4 (old CRAM version) | +| [nexys4d](nexys4d) | design for Digilent Nexys4 DDR _!! only sim-tested !!_ | +| [s3board](s3board) | design for Digilent S3BOARD |