diff --git a/doc/CHANGELOG.md b/doc/CHANGELOG.md index 04bfa9f3..a611c350 100644 --- a/doc/CHANGELOG.md +++ b/doc/CHANGELOG.md @@ -34,6 +34,7 @@ The full set of tests is only run for tagged releases. - tmuconv: add -t_ru06 and -t_flow - tools/tcode - cpu_details.mac: significantly expanded + - cpu_mmu.mac: significantly expanded - firmware changes - pdp11.vhd: rename, eg srv->ser; drop trap_done; add in_vecysv - pdp11_vmbox.vhd: rename some rsv->ser; remove obsolete trap_done @@ -44,6 +45,7 @@ The full set of tests is only run for tagged releases. - pdp11_sequencer: - BUGFIX: use is_kstackdst1246 also in dstr flow - BUGFIX: correct ysv flow implementation + - BUGFIX: correct mmu trap handing in s_idecode - pdp11_vmbox: BUGFIX: correct red/yellow zone boundary diff --git a/rtl/w11a/pdp11.vhd b/rtl/w11a/pdp11.vhd index 0dc0e2a8..8c262fe2 100644 --- a/rtl/w11a/pdp11.vhd +++ b/rtl/w11a/pdp11.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11.vhd 1320 2022-11-22 18:52:59Z mueller $ +-- $Id: pdp11.vhd 1321 2022-11-24 15:06:47Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later -- Copyright 2006-2022 by Walter F.J. Mueller -- @@ -11,6 +11,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2022-11-24 1321 1.5.17 add cpustat_type intpend -- 2022-11-21 1320 1.6.16 rename some rsv->ser and cpustat_type trap_->treq_; -- remove vm_cntl_type.trap_done; add in_vecysv; -- 2022-10-25 1309 1.6.15 rename _gpr -> _gr @@ -377,6 +378,7 @@ package pdp11 is creset : slbit; -- CRESET pulse breset : slbit; -- BRESET pulse intack : slbit; -- INT_ACK pulse + intpend : slbit; -- interrupt pending intvect : slv9_2; -- current interrupt vector treq_mmu : slbit; -- mmu trap requested treq_ysv : slbit; -- ysv trap requested @@ -393,7 +395,7 @@ package pdp11 is '0','0', -- suspint,suspext "00000","000", -- cpfunc, cprnum '0', -- waitsusp - '0','0','0','0', -- itimer,creset,breset,intack + '0','0','0','0','0', -- itimer,creset,breset,intack,intpend (others=>'0'), -- intvect '0','0','0', -- treq_(mmu|ysv), prefdone '0','0','0' -- do_grwe, in_vec(ser|ysv) diff --git a/rtl/w11a/pdp11_sequencer.vhd b/rtl/w11a/pdp11_sequencer.vhd index ebf4a90a..1c77d2dc 100644 --- a/rtl/w11a/pdp11_sequencer.vhd +++ b/rtl/w11a/pdp11_sequencer.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11_sequencer.vhd 1320 2022-11-22 18:52:59Z mueller $ +-- $Id: pdp11_sequencer.vhd 1321 2022-11-24 15:06:47Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later -- Copyright 2006-2022 by Walter F.J. Mueller -- @@ -13,6 +13,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2022-11-24 1321 1.6.20 BUGFIX: correct mmu trap handing in s_idecode -- 2022-11-21 1320 1.6.19 rename some rsv->ser and cpustat_type trap_->treq_; -- remove vm_cntl_type.trap_done; -- BUGFIX: correct ysv flow implementation @@ -626,6 +627,7 @@ begin if unsigned(INT_PRI) > unsigned(PSW.pri) then int_pending := '1'; end if; + nstatus.intpend := int_pending; idm_idle := '0'; idm_cpbusy := '0'; @@ -934,11 +936,21 @@ begin nvmcntl.dspace := '0'; ndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC - - if ID_STAT.do_pref_dec='1' and PSW.tflag='0' and int_pending='0' and - R_STATUS.cpugo='1' and R_STATUS.cpususp='0' and - not R_STATUS.cmdbusy='1' - then + + -- The prefetch decision path can be critical (and was on s3). + -- It uses R_STATUS.intpend instead of int_pending, using the status + -- latched at the previous state is OK. It uses R_STATUS.treq_mmu + -- because no MMU trap can occur during this state (only in *_w states). + -- It does not check treq_ysv because pipelined instructions can't + -- trigger ysv traps, in contrast to MMU traps. + if ID_STAT.do_pref_dec='1' and -- prefetch possible + PSW.tflag='0' and -- no tbit traps + R_STATUS.intpend='0' and -- no interrupts + R_STATUS.treq_mmu='0' and -- no MMU trap request + R_STATUS.cpugo='1' and -- CPU on go + R_STATUS.cpususp='0' and -- CPU not suspended + not R_STATUS.cmdbusy='1' -- and no command pending + then -- then go for prefetch nvmcntl.req := '1'; ndpcntl.gr_pcinc := '1'; -- (pc)++ nmmumoni.istart := '1'; diff --git a/tools/tbench/rhrp/test_rhrp_int.tcl b/tools/tbench/rhrp/test_rhrp_int.tcl index 05a2a8da..61debaab 100644 --- a/tools/tbench/rhrp/test_rhrp_int.tcl +++ b/tools/tbench/rhrp/test_rhrp_int.tcl @@ -1,9 +1,10 @@ -# $Id: test_rhrp_int.tcl 1178 2019-06-30 12:39:40Z mueller $ +# $Id: test_rhrp_int.tcl 1321 2022-11-24 15:06:47Z mueller $ # SPDX-License-Identifier: GPL-3.0-or-later -# Copyright 2015-2019 by Walter F.J. Mueller +# Copyright 2015-2022 by Walter F.J. Mueller # # Revision History: # Date Rev Version Comment +# 2022-11-24 1321 1.1.4 increase expected interrupt latency (_seq change) # 2019-03-09 1120 1.1.3 add proper device check # 2015-07-25 704 1.1.2 tmpproc_dotest: use args rather opts # 2015-06-20 692 1.1.1 de-configure all drives at begin @@ -97,7 +98,9 @@ start: spl 7 ; lock out interrupts mov (r0)+,@#rp.cs1 ; cs1 spl 0 ; allow interrupts ; - inc r5 ; time int delay, up to 10 instructions + inc r5 ; time int delay, up to 12 instructions + inc r5 + inc r5 inc r5 inc r5 inc r5 @@ -192,7 +195,7 @@ proc tmpproc_dotest {cpu symName args} { o.er1 0 \ o.ds 0 \ o.as 0 \ - o.itim 10 \ + o.itim 12 \ o.icnt 0 \ o.pcnt 1 \ or.cs1 0 \ @@ -428,7 +431,7 @@ tmpproc_dotest $cpu sym \ o.er1 0 \ o.ds [regbld ibd_rhrp::DS ata mol dpr dry vv] \ o.as [regbld ibd_rhrp::AS u0] \ - o.itim 3 + o.itim 4 rlc log " A3.5 search function, valid da,dc, idly=8 ----------" @@ -444,7 +447,7 @@ tmpproc_dotest $cpu sym \ o.er1 0 \ o.ds [regbld ibd_rhrp::DS ata mol dpr dry vv] \ o.as [regbld ibd_rhrp::AS u0] \ - o.itim 9 + o.itim 10 rlc log " A3.5 search function, invalid sa, idly=8 -----------" # Note: idly is 8, but error ata's come immediately !! diff --git a/tools/tcode/cpu_mmu.mac b/tools/tcode/cpu_mmu.mac index 119f870f..472e7f81 100644 --- a/tools/tcode/cpu_mmu.mac +++ b/tools/tcode/cpu_mmu.mac @@ -1,4 +1,4 @@ -; $Id: cpu_mmu.mac 1313 2022-11-04 14:01:08Z mueller $ +; $Id: cpu_mmu.mac 1321 2022-11-24 15:06:47Z mueller $ ; SPDX-License-Identifier: GPL-3.0-or-later ; Copyright 2022- by Walter F.J. Mueller ; @@ -14,6 +14,16 @@ ; Section D: mmr2+mmr1+mmr0 register, abort recovery ; Section E: traps and pdr aia and aiw bits ; Section F: miscellaneous +; +; Overall usage of pages in kernel mode +; page 0 main code +; page 1 main code +; page 2 +; page 3 +; page 4 code mapped in user/super space; test E1.4 code +; page 5 code for test E1.4 +; page 6 data test target +; page 7 iopage ; .include |lib/tcode_std_base.mac| .include |lib/defs_mmu.mac| @@ -34,6 +44,7 @@ kipdr0 = kipdr+ 0 kdpdr0 = kdpdr+ 0 + kipdr5 = kipdr+12 kipdr6 = kipdr+14 kipar6 = kipar+14 kdpdr6 = kdpdr+14 @@ -1684,6 +1695,78 @@ te0102: mov #vhmmut,v..mmu ; setup MMU trap handler clr v..mmu+2 9999$: iot ; end of test E1.2 ; +; Test E1.3 -- test trap request logic (trap on non-last access) +++++ +; Test cases where an instruction does multiple memory accesses and the +; trap condition is not met on the last one. This verifies that the trap +; request is properly recorded and handled at end of instruction execution. +; Page 6 has traps enabled (afc=4), all others not. +; +te0103: mov #mmr0,r2 ; ptr to mmr0 + mov #p6base,r3 ; ptr to page6 (MMU traps enabled) + mov #1500$,r4 ; ptr to page0 (MMU traps disabled) + mov r4,(r3) ; p6base holds ptr to 1500$ + clr (r4) ; clear target location + clr 2(r4) + mov #<127.*md.plf>!md.att,kipdr6 ; enable traps (afc=4) + mov #m0.ent!m0.ena,mmr0 ; enable mmu with traps ;! MMU 18 +; + mov #vhmmut,v..mmu ; setup MMU trap handler + mov #1010$,vhvmmu + mov (r3),r5 ; check r(p6) - trival case + halt +; +1010$: mov #1020$,vhvmmu + bic #m0.trp,(r2) ; clear trp + mov (r3),(r4) ; check r(p6),w(p0) + halt +; +1020$: mov #1030$,vhvmmu + bic #m0.trp,(r2) ; clear trp + mov @(r3)+,2(r4) ; check r(p6),r(p0),r(p0),w(p0) + halt +; +1030$: mov #1040$,vhvmmu + bic #m0.trp,(r2) ; clear trp + inc @-(r3) ; check r(p6),rm(p0),wm(p0) + halt +; +1040$: hcmpeq #1500$+1,1500$ ; check proper values in target + hcmpeq #1500$,1500$+2 ; as internal consistency check + br 2000$ +; +1500$: .word 0 + .word 0 +; +2000$: reset ; mmu off ;! MMU off + mov #<127.*md.plf>!md.arw,kipdr6 ; reset kipdr6 + mov #v..mmu+2,v..mmu +; +9999$: iot ; end of test E1.3 +; +; Test E1.4 -- test trap request after prefetched instructions +++++++ +; The w11 starts a prefetch of the next instruction when the decode step +; detects a register-only operate instruction (as the 11/70 does). +; This test checks whether MMU traps are properly detected. +; Page 5 has traps enabled (afc=4). A sequence of 'inc r2' instructions is +; executed which start in page 4 and continue in page 5. The first in page 5 +; should cause an MMU trap. +; +te0104: mov #<127.*md.plf>!md.att,kipdr5 ; enable traps (afc=4) + mov #m0.ent!m0.ena,mmr0 ; enable mmu with traps ;! MMU 18 + clr r2 ; clear counter + mov #1000$,r3 ; ptr to failed landing + mov #vhmmut,v..mmu ; setup MMU trap handler + mov #1100$,vhvmmu + jmp @#p5base-6 ; start test code +; +1000$: nop ; lands here if no trap + halt +1100$: hcmpeq #4.,r2 ; check counter +; + reset ; mmu off ;! MMU off + mov #<127.*md.plf>!md.arw,kipdr5 ; reset kipdr5 + mov #v..mmu+2,v..mmu +; ; Section F: miscellaneous =================================================== ; ; Test F1: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ @@ -1797,7 +1880,7 @@ tf0102: mov #154345,@#p6base ; inititialize target ;; END OF ALL TESTS - loop closure ============================================ ; mov tstno,r0 ; hack, for easy monitoring ... - hcmpeq tstno,#19. ; all tests done ? + hcmpeq tstno,#20. ; all tests done ? ; jmp loop ; @@ -1857,8 +1940,8 @@ vhustp: .word vhuhlt vhuhlt: halt ; ; Test codes that will be mapped in user or supervisor mode ================== -; They are located at 100000 and above and are position-independent code. -; That allows to assemble and load them together with the main code. +; They are located in page 4 at 100000 and above and are position-independent +; code. That allows to assemble and load them together with the main code. ; ; vc0 - simple code ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ; uses jsr, has stack below 1000 (no problem in user/supervisor mode) @@ -1925,5 +2008,19 @@ vc2dat: .word 010111 .word 010222 .word 010333 .word 010444 +; +; Test E1.4 test code +; located at border of page 4 and page 5 (touching both) +; started via @#p5base-6, therefore no explicit label +; + . = p5base-6 + inc r2 ; @117772; r2=1 + inc r2 ; @117774; r2=2 + inc r2 ; @117776; r2=3 + inc r2 ; @120000; r2=4 <-- should trap here + inc r2 ; @120002; r2=5 + inc r2 ; @120004; r2=6 + inc r2 ; @120006; r2=7 + jmp (r3) ; return to main code ; .end start