diff --git a/doc/CHANGELOG.md b/doc/CHANGELOG.md index cac2269b..470b9f77 100644 --- a/doc/CHANGELOG.md +++ b/doc/CHANGELOG.md @@ -30,7 +30,10 @@ The full set of tests is only run for tagged releases. ### Summary - Doxygen support now for V1.9.6 ### New features -- tools/mcode: added folders rk11 and rlink +- new systems + - rtl/sys_gen/tst_serloop/basys3 - serport loop tester for Basys3 +- new tools + - tools/mcode: added folders rk11 and rlink ### Changes - tools changes - tools/bin @@ -75,8 +78,9 @@ The full set of tests is only run for tagged releases. - xxdp run scripts added for w11a and SimH - Doxygen support now for V1.9.5 ### New features -- gwstart: gtkwave starter -- tools/xxdp: add directory with xxdp setup and patch scripts +- new tools + - gwstart: gtkwave starter + - tools/xxdp: add directory with xxdp setup and patch scripts ### Changes - tools changes - tools/asm-11/lib/push_pop.mac: add push2 diff --git a/rtl/sys_gen/tst_serloop/README.md b/rtl/sys_gen/tst_serloop/README.md index 95e3341c..a8c232d9 100644 --- a/rtl/sys_gen/tst_serloop/README.md +++ b/rtl/sys_gen/tst_serloop/README.md @@ -3,6 +3,7 @@ and is organized in | Directory | Content | | --------- | ------- | +| [basys3](basys3) | design for Digilent Basys3 | | [nexys2](nexys2) | design for Digilent Nexys2 | | [nexys3](nexys3) | design for Digilent Nexys3 | | [nexys4](nexys4) | design for Digilent Nexys4 (old CRAM version) | diff --git a/rtl/sys_gen/tst_serloop/basys3/Makefile b/rtl/sys_gen/tst_serloop/basys3/Makefile new file mode 100644 index 00000000..b179f1b5 --- /dev/null +++ b/rtl/sys_gen/tst_serloop/basys3/Makefile @@ -0,0 +1,27 @@ +# $Id: Makefile 1369 2023-02-08 18:59:50Z mueller $ +# SPDX-License-Identifier: GPL-3.0-or-later +# Copyright 2023- by Walter F.J. Mueller +# +# Revision History: +# Date Rev Version Comment +# 2023-02-07 1369 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +include ${RETROBASE}/rtl/make_viv/viv_default_basys3.mk +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : viv_clean +# +#---- +# +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +endif +# diff --git a/rtl/sys_gen/tst_serloop/basys3/sys_conf1.vhd b/rtl/sys_gen/tst_serloop/basys3/sys_conf1.vhd new file mode 100644 index 00000000..96285758 --- /dev/null +++ b/rtl/sys_gen/tst_serloop/basys3/sys_conf1.vhd @@ -0,0 +1,47 @@ +-- $Id: sys_conf1.vhd 1369 2023-02-08 18:59:50Z mueller $ +-- SPDX-License-Identifier: GPL-3.0-or-later +-- Copyright 2023- by Walter F.J. Mueller +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_serloop1_b3 (for synthesis) +-- +-- Dependencies: - +-- Tool versions: viv 2022.1; ghdl 2.0.0 +-- Revision History: +-- Date Rev Version Comment +-- 2023-02-07 1369 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + -- configure clocks -------------------------------------------------------- + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 12; -- vco 1200 MHz + constant sys_conf_clksys_outdivide : positive := 10; -- sys 120 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + + constant sys_conf_clkdiv_usecdiv : integer := 100; -- default usec + constant sys_conf_clkdiv_msecdiv : integer := 1000; -- default msec + + -- configure hio interfaces ----------------------------------------------- + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + + -- configure serport ------------------------------------------------------ + constant sys_conf_uart_defbaud : integer := 115200; -- default 115k baud + + -- derived constants ======================================================= + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_uart_cdinit : integer := + (sys_conf_clksys/sys_conf_uart_defbaud)-1; + +end package sys_conf; diff --git a/rtl/sys_gen/tst_serloop/basys3/sys_conf2.vhd b/rtl/sys_gen/tst_serloop/basys3/sys_conf2.vhd new file mode 100644 index 00000000..f5457012 --- /dev/null +++ b/rtl/sys_gen/tst_serloop/basys3/sys_conf2.vhd @@ -0,0 +1,58 @@ +-- $Id: sys_conf2.vhd 1369 2023-02-08 18:59:50Z mueller $ +-- SPDX-License-Identifier: GPL-3.0-or-later +-- Copyright 2023- by Walter F.J. Mueller +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_serloop2_b3 (for synthesis) +-- +-- Dependencies: - +-- Tool versions: viv 2022.1; ghdl 2.0.0 +-- Revision History: +-- Date Rev Version Comment +-- 2023-02-07 1369 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + -- configure clocks -------------------------------------------------------- + constant sys_conf_clksys_vcodivide : positive := 5; -- f 20 Mhz + constant sys_conf_clksys_vcomultiply : positive := 36; -- vco 720 MHz + constant sys_conf_clksys_outdivide : positive := 10; -- sys 72 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + + constant sys_conf_clksys_msecdiv : integer := 1000; -- default msec + + constant sys_conf_clkser_vcodivide : positive := 1; + constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz + constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz + constant sys_conf_clkser_gentype : string := "PLL"; + + constant sys_conf_clkser_msecdiv : integer := 1000; -- default msec + + -- configure hio interfaces ----------------------------------------------- + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + + -- configure serport ------------------------------------------------------ + constant sys_conf_uart_defbaud : integer := 115200; -- default 115k baud + + -- derived constants ======================================================= + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_clkser : integer := + ((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) / + sys_conf_clkser_outdivide; + constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000; + + constant sys_conf_uart_cdinit : integer := + (sys_conf_clkser/sys_conf_uart_defbaud)-1; + +end package sys_conf; diff --git a/rtl/sys_gen/tst_serloop/basys3/sys_tst_serloop1_b3.vbom b/rtl/sys_gen/tst_serloop/basys3/sys_tst_serloop1_b3.vbom new file mode 100644 index 00000000..530caee6 --- /dev/null +++ b/rtl/sys_gen/tst_serloop/basys3/sys_tst_serloop1_b3.vbom @@ -0,0 +1,21 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/xlib/xlib.vhd +../../../vlib/genlib/genlib.vhd +../../../bplib/bpgen/bpgenlib.vbom +../tst_serlooplib.vbom +../../../vlib/serport/serportlib.vbom +${sys_conf := sys_conf1.vhd} +# components +[vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom +[ghdl,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/bp_rs232_2line_iob.vbom +../../../bplib/bpgen/sn_humanio.vbom +../tst_serloop_hiomap.vbom +../../../vlib/serport/serport_1clock.vbom +../tst_serloop.vbom +# design +sys_tst_serloop1_b3.vhd +@xdc:../../../bplib/basys3/basys3_pclk.xdc +@xdc:../../../bplib/basys3/basys3_pins.xdc diff --git a/rtl/sys_gen/tst_serloop/basys3/sys_tst_serloop1_b3.vhd b/rtl/sys_gen/tst_serloop/basys3/sys_tst_serloop1_b3.vhd new file mode 100644 index 00000000..44cd371d --- /dev/null +++ b/rtl/sys_gen/tst_serloop/basys3/sys_tst_serloop1_b3.vhd @@ -0,0 +1,205 @@ +-- $Id: sys_tst_serloop1_b3.vhd 1369 2023-02-08 18:59:50Z mueller $ +-- SPDX-License-Identifier: GPL-3.0-or-later +-- Copyright 2023- by Walter F.J. Mueller +-- +------------------------------------------------------------------------------ +-- Module Name: sys_tst_serloop1_b3 - syn +-- Description: Serial link tester design for basys3 (serport_1clock case) +-- +-- Dependencies: vlib/xlib/s7_cmt_sfs +-- vlib/genlib/clkdivce +-- bpgen/bp_rs232_2line_iob +-- bpgen/sn_humanio +-- tst_serloop_hiomap +-- vlib/serport/serport_1clock +-- tst_serloop +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: viv 2022.1; ghdl 2.0.0 +-- +-- Synthesized (viv): +-- Date Rev viv Target flop lutl lutm bram slic +-- 2023-02-07 1369 2022.1 xc7a35t-1 408 406 12 0.0 179 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2023-02-07 1369 1.0 Initial version (derived from sys_tst_serloop1_n4) +------------------------------------------------------------------------------ +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.genlib.all; +use work.bpgenlib.all; +use work.tst_serlooplib.all; +use work.serportlib.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_tst_serloop1_b3 is -- top level + -- implements basys3_aif + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv16; -- b3 switches + I_BTN : in slv5; -- b3 buttons + O_LED : out slv16; -- b3 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8 -- 7 segment disp: segments (act.low) + ); +end sys_tst_serloop1_b3; + +architecture syn of sys_tst_serloop1_b3 is + + signal CLK : slbit := '0'; + signal RESET : slbit := '0'; + + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal RXD : slbit := '0'; + signal TXD : slbit := '0'; + + signal SWI : slv16 := (others=>'0'); + signal BTN : slv5 := (others=>'0'); + signal LED : slv16 := (others=>'0'); + signal DSP_DAT : slv16 := (others=>'0'); + signal DSP_DP : slv4 := (others=>'0'); + + signal HIO_CNTL : hio_cntl_type := hio_cntl_init; + signal HIO_STAT : hio_stat_type := hio_stat_init; + + signal RXDATA : slv8 := (others=>'0'); + signal RXVAL : slbit := '0'; + signal RXHOLD : slbit := '0'; + signal TXDATA : slv8 := (others=>'0'); + signal TXENA : slbit := '0'; + signal TXBUSY : slbit := '0'; + + signal SER_MONI : serport_moni_type := serport_moni_init; + +begin + + GEN_CLKSYS : s7_cmt_sfs -- clock generator ------------------- + generic map ( + VCO_DIVIDE => sys_conf_clksys_vcodivide, + VCO_MULTIPLY => sys_conf_clksys_vcomultiply, + OUT_DIVIDE => sys_conf_clksys_outdivide, + CLKIN_PERIOD => 10.0, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clksys_gentype) + port map ( + CLKIN => I_CLK100, + CLKFX => CLK, + LOCKED => open + ); + + CLKDIV : clkdivce + generic map ( + CDUWIDTH => 7, + USECDIV => sys_conf_clksys_mhz, + MSECDIV => sys_conf_clkdiv_msecdiv) + port map ( + CLK => CLK, + CE_USEC => open, + CE_MSEC => CE_MSEC + ); + + HIO : sn_humanio + generic map ( + SWIDTH => 16, + BWIDTH => 5, + LWIDTH => 16, + DEBOUNCE => sys_conf_hio_debounce) + port map ( + CLK => CLK, + RESET => '0', + CE_MSEC => CE_MSEC, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + RESET <= BTN(0); -- BTN(0) will reset tester !! + + HIOMAP : tst_serloop_hiomap + port map ( + CLK => CLK, + RESET => RESET, + HIO_CNTL => HIO_CNTL, + HIO_STAT => HIO_STAT, + SER_MONI => SER_MONI, + SWI => SWI(7 downto 0), + BTN => BTN(3 downto 0), + LED => LED(7 downto 0), + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP + ); + + IOB_RS232 : bp_rs232_2line_iob + port map ( + CLK => CLK, + RXD => RXD, + TXD => TXD, + I_RXD => I_RXD, + O_TXD => O_TXD + ); + + SERPORT : serport_1clock + generic map ( + CDWIDTH => 12, + CDINIT => sys_conf_uart_cdinit, + RXFAWIDTH => 5, + TXFAWIDTH => 5) + port map ( + CLK => CLK, + CE_MSEC => CE_MSEC, + RESET => RESET, + ENAXON => HIO_CNTL.enaxon, + ENAESC => HIO_CNTL.enaesc, + RXDATA => RXDATA, + RXVAL => RXVAL, + RXHOLD => RXHOLD, + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY, + MONI => SER_MONI, + RXSD => RXD, + TXSD => TXD, + RXRTS_N => open, + TXCTS_N => '0' + ); + + TESTER : tst_serloop + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + HIO_CNTL => HIO_CNTL, + HIO_STAT => HIO_STAT, + SER_MONI => SER_MONI, + RXDATA => RXDATA, + RXVAL => RXVAL, + RXHOLD => RXHOLD, + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY + ); + +end syn; diff --git a/rtl/sys_gen/tst_serloop/basys3/sys_tst_serloop1_b3.vmfset b/rtl/sys_gen/tst_serloop/basys3/sys_tst_serloop1_b3.vmfset new file mode 100644 index 00000000..fa657975 --- /dev/null +++ b/rtl/sys_gen/tst_serloop/basys3/sys_tst_serloop1_b3.vmfset @@ -0,0 +1,62 @@ +# $Id: sys_tst_serloop1_b3.vmfset 1369 2023-02-08 18:59:50Z mueller $ +# +# Validated code/tool version combinations +# Date rev viv +# 2023-02-08 1369 2022.1 +# +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[syn] + +# general issues ----------------------------------------------- +{2018.2:} +# stupid new warning, Xilinx suggests to safely ingnore +I [Constraints 18-5210] # generic +{2022.1:} +# new warning on 'Parallel synthesis criteria is not met', safe tp ignore +I [Synth 8-7080] +{:} + +# +++# port driven by constant -------------------------------------- +# --> upper 8 LEDs unused # OK 2023-02-08 +i [Synth 8-3917] O_LED[(8|9)] +i [Synth 8-3917] O_LED[1\d] + +# tying undriven pin to constant ------------------------------- +# upper 8 LEDs unused # OK 2023-02-08 +i [Synth 8-3295] HIO:LED[\d*] + +# unconnected ports -------------------------------------------- +{:2019.2} +# --> unused SWI and BTN # OK 2023-02-08 +i [Synth 8-3331] tst_serloop_hiomap.*SWI[\d] +i [Synth 8-3331] tst_serloop_hiomap.*BTN[\d] +# --> clkdiv isn't displayed # OK 2023-02-08 +i [Synth 8-3331] SER_MONI[abclkdiv.*][\d*] +# --> other unused fields which aren't visualized # OK 2023-02-08 +i [Synth 8-3331] SER_MONI[(rxact|txact|abdone|rxerr|rxovr)] +i [Synth 8-3331] HIO_CNTL[enaftdi] +{2022.1:} +# --> unused SWI and BTN # OK 2023-02-08 +i [Synth 8-7129] SWI[\d] .* tst_serloop_hiomap +i [Synth 8-7129] BTN[\d] .* tst_serloop_hiomap +# --> clkdiv isn't displayed # OK 2023-02-08 +i [Synth 8-7129] SER_MONI[abclkdiv.*][\d*] +# --> other unused fields which aren't visualized # OK 2023-02-08 +i [Synth 8-7129] SER_MONI[(rxact|txact|abdone|rxerr|rxovr)] +i [Synth 8-7129] HIO_CNTL[enaftdi] +{:} + +# sequential element removed (2017.1 nonsense) ----------------- +I [Synth 8-6014] _reg # generic + +# unused sequential element ------------------------------------ +{2017.2:2018.2} +# --> many HIO pins not used # OK 2023-02-08 +i [Synth 8-3332] HIO/IOB_(SWI|BTN)/R_DI_reg[\d*] +i [Synth 8-3332] HIO/DEB.DEB_(SWI|BTN)/R_REGS_reg[(dref|dout|dchange)][\d*] +{:} + +# +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[imp] +I [Vivado 12-2489] # multiple of 1 ps +I [Physopt 32-742] # BRAM Flop Optimization diff --git a/rtl/sys_gen/tst_serloop/basys3/sys_tst_serloop2_b3.vbom b/rtl/sys_gen/tst_serloop/basys3/sys_tst_serloop2_b3.vbom new file mode 100644 index 00000000..7a608104 --- /dev/null +++ b/rtl/sys_gen/tst_serloop/basys3/sys_tst_serloop2_b3.vbom @@ -0,0 +1,17 @@ +# libs +../../../vlib/slvtypes.vhd +../../../bplib/bpgen/bpgenlib.vbom +../tst_serlooplib.vbom +../../../vlib/serport/serportlib.vbom +${sys_conf := sys_conf2.vhd} +# components +../../../bplib/bpgen/s7_cmt_1ce1ce.vbom +../../../bplib/bpgen/bp_rs232_2line_iob.vbom +../../../bplib/bpgen/sn_humanio.vbom +../tst_serloop_hiomap.vbom +../../../vlib/serport/serport_2clock2.vbom +../tst_serloop.vbom +# design +sys_tst_serloop2_b3.vhd +@xdc:../../../bplib/basys3/basys3_pclk.xdc +@xdc:../../../bplib/basys3/basys3_pins.xdc diff --git a/rtl/sys_gen/tst_serloop/basys3/sys_tst_serloop2_b3.vhd b/rtl/sys_gen/tst_serloop/basys3/sys_tst_serloop2_b3.vhd new file mode 100644 index 00000000..a6de1f1d --- /dev/null +++ b/rtl/sys_gen/tst_serloop/basys3/sys_tst_serloop2_b3.vhd @@ -0,0 +1,210 @@ +-- $Id: sys_tst_serloop2_b3.vhd 1369 2023-02-08 18:59:50Z mueller $ +-- SPDX-License-Identifier: GPL-3.0-or-later +-- Copyright 2023- by Walter F.J. Mueller +-- +------------------------------------------------------------------------------ +-- Module Name: sys_tst_serloop2_b3 - syn +-- Description: Serial link tester design for basys3 (serport_2clock case) +-- +-- Dependencies: bpgen/s7_cmt_1ce1ce +-- bpgen/bp_rs232_2line_iob +-- bpgen/sn_humanio +-- tst_serloop_hiomap +-- vlib/serport/serport_2clock2 +-- tst_serloop +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: viv 2022.1; ghdl 2.0.0 +-- +-- Synthesized (viv): +-- Date Rev viv Target flop lutl lutm bram slic +-- 2023-02-07 1369 2022.1 xc7a35t-1 533 472 12 0.0 228 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2023-02-07 1369 1.0 Initial version (derived from sys_tst_serloop1_b3) +------------------------------------------------------------------------------ +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.bpgenlib.all; +use work.tst_serlooplib.all; +use work.serportlib.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_tst_serloop2_b3 is -- top level + -- implements basys3_aif + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv16; -- b3 switches + I_BTN : in slv5; -- b3 buttons + O_LED : out slv16; -- b3 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8 -- 7 segment disp: segments (act.low) + ); +end sys_tst_serloop2_b3; + +architecture syn of sys_tst_serloop2_b3 is + + signal CLK : slbit := '0'; + signal RESET : slbit := '0'; + + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal CLKS : slbit := '0'; + signal CES_MSEC : slbit := '0'; + + signal RXD : slbit := '0'; + signal TXD : slbit := '0'; + + signal SWI : slv16 := (others=>'0'); + signal BTN : slv5 := (others=>'0'); + signal LED : slv16 := (others=>'0'); + signal DSP_DAT : slv16 := (others=>'0'); + signal DSP_DP : slv4 := (others=>'0'); + + signal HIO_CNTL : hio_cntl_type := hio_cntl_init; + signal HIO_STAT : hio_stat_type := hio_stat_init; + + signal RXDATA : slv8 := (others=>'0'); + signal RXVAL : slbit := '0'; + signal RXHOLD : slbit := '0'; + signal TXDATA : slv8 := (others=>'0'); + signal TXENA : slbit := '0'; + signal TXBUSY : slbit := '0'; + + signal SER_MONI : serport_moni_type := serport_moni_init; + +begin + + GEN_CLKALL : s7_cmt_1ce1ce -- clock generator system ------------ + generic map ( + CLKIN_PERIOD => 10.0, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + CLK0_VCODIV => sys_conf_clksys_vcodivide, + CLK0_VCOMUL => sys_conf_clksys_vcomultiply, + CLK0_OUTDIV => sys_conf_clksys_outdivide, + CLK0_GENTYPE => sys_conf_clksys_gentype, + CLK0_CDUWIDTH => 8, + CLK0_USECDIV => sys_conf_clksys_mhz, + CLK0_MSECDIV => sys_conf_clksys_msecdiv, + CLK1_VCODIV => sys_conf_clkser_vcodivide, + CLK1_VCOMUL => sys_conf_clkser_vcomultiply, + CLK1_OUTDIV => sys_conf_clkser_outdivide, + CLK1_GENTYPE => sys_conf_clkser_gentype, + CLK1_CDUWIDTH => 7, + CLK1_USECDIV => sys_conf_clkser_mhz, + CLK1_MSECDIV => sys_conf_clkser_msecdiv) + port map ( + CLKIN => I_CLK100, + CLK0 => CLK, + CE0_USEC => CE_USEC, + CE0_MSEC => CE_MSEC, + CLK1 => CLKS, + CE1_USEC => open, + CE1_MSEC => CES_MSEC, + LOCKED => open + ); + + HIO : sn_humanio + generic map ( + SWIDTH => 16, + BWIDTH => 5, + LWIDTH => 16, + DEBOUNCE => sys_conf_hio_debounce) + port map ( + CLK => CLK, + RESET => '0', + CE_MSEC => CE_MSEC, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + RESET <= BTN(0); -- BTN(0) will reset tester !! + + HIOMAP : tst_serloop_hiomap + port map ( + CLK => CLK, + RESET => RESET, + HIO_CNTL => HIO_CNTL, + HIO_STAT => HIO_STAT, + SER_MONI => SER_MONI, + SWI => SWI(7 downto 0), + BTN => BTN(3 downto 0), + LED => LED(7 downto 0), + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP + ); + + IOB_RS232 : bp_rs232_2line_iob + port map ( + CLK => CLKS, + RXD => RXD, + TXD => TXD, + I_RXD => I_RXD, + O_TXD => O_TXD + ); + + SERPORT : serport_2clock2 + generic map ( + CDWIDTH => 12, + CDINIT => sys_conf_uart_cdinit, + RXFAWIDTH => 5, + TXFAWIDTH => 5) + port map ( + CLKU => CLK, + RESET => RESET, + CLKS => CLKS, + CES_MSEC => CES_MSEC, + ENAXON => HIO_CNTL.enaxon, + ENAESC => HIO_CNTL.enaesc, + RXDATA => RXDATA, + RXVAL => RXVAL, + RXHOLD => RXHOLD, + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY, + MONI => SER_MONI, + RXSD => RXD, + TXSD => TXD, + RXRTS_N => open, + TXCTS_N => '0' + ); + + TESTER : tst_serloop + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + HIO_CNTL => HIO_CNTL, + HIO_STAT => HIO_STAT, + SER_MONI => SER_MONI, + RXDATA => RXDATA, + RXVAL => RXVAL, + RXHOLD => RXHOLD, + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY + ); + +end syn; diff --git a/rtl/sys_gen/tst_serloop/basys3/sys_tst_serloop2_b3.vmfset b/rtl/sys_gen/tst_serloop/basys3/sys_tst_serloop2_b3.vmfset new file mode 100644 index 00000000..90fffcc8 --- /dev/null +++ b/rtl/sys_gen/tst_serloop/basys3/sys_tst_serloop2_b3.vmfset @@ -0,0 +1,67 @@ +# $Id: sys_tst_serloop2_b3.vmfset 1369 2023-02-08 18:59:50Z mueller $ +# +# Validated code/tool version combinations +# Date rev viv +# 2023-02-08 1369 2022.1 +# +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[syn] +# general issues ----------------------------------------------- +{2018.2:} +# stupid new warning, Xilinx suggests to safely ingnore +I [Constraints 18-5210] # generic +{2022.1:} +# new warning on 'Parallel synthesis criteria is not met', safe tp ignore +I [Synth 8-7080] +{:} + +# false_path -hold ignored by synth ---------------------------- +I [Designutils 20-1567] # generic + +# port driven by constant -------------------------------------- +# --> upper 8 LEDs unused # OK 2023-02-08 +i [Synth 8-3917] O_LED[(8|9)] +i [Synth 8-3917] O_LED[1\d] + +# tying undriven pin to constant ------------------------------- +# upper 8 LEDs unused # OK 2023-02-08 +i [Synth 8-3295] HIO:LED[\d*] + +# unconnected ports -------------------------------------------- +{:2019.2} +# --> unused SWI and BTN # OK 2023-02-08 +i [Synth 8-3331] tst_serloop_hiomap.*SWI[\d] +i [Synth 8-3331] tst_serloop_hiomap.*BTN[\d] +# --> clkdiv isn't displayed # OK 2023-02-08 +i [Synth 8-3331] SER_MONI[abclkdiv.*][\d*] +# --> other unused fields which aren't visualized # OK 2023-02-08 +i [Synth 8-3331] SER_MONI[(rxact|txact|abdone|rxerr|rxovr)] +i [Synth 8-3331] HIO_CNTL[enaftdi] +{2022.1:} +# --> unused SWI and BTN # OK 2023-02-08 +i [Synth 8-7129] SWI[\d] .* tst_serloop_hiomap +i [Synth 8-7129] BTN[\d] .* tst_serloop_hiomap +# --> clkdiv isn't displayed # OK 2023-02-08 +i [Synth 8-7129] SER_MONI[abclkdiv.*][\d*] +# --> other unused fields which aren't visualized # OK 2023-02-08 +i [Synth 8-7129] SER_MONI[(rxact|txact|abdone|rxerr|rxovr)] +i [Synth 8-7129] HIO_CNTL[enaftdi] +{:} + +# sequential element removed (2017.1 nonsense) ----------------- +I [Synth 8-6014] _reg # generic + +# unused sequential element ------------------------------------ +{2017.2:2018.2} +I [Synth 8-3332] R_REGS_reg[(btn|swi)(eff)?][\d*] # generic +# --> currently CDUWIDTH=8, but clock below 127 MHz # OK 2023-02-08 +i [Synth 8-3332] GEN_CLKALL/DIV_CLK0/R_REGS_reg[ucnt][7] +# --> many HIO pins not used # OK 2023-02-08 +i [Synth 8-3332] HIO/IOB_(SWI|BTN)/R_DI_reg[\d*] +i [Synth 8-3332] HIO/DEB.DEB_(SWI|BTN)/R_REGS_reg[(dref|dout|dchange)][\d*] +{:} + +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[imp] +I [Vivado 12-2489] # multiple of 1 ps +I [Physopt 32-742] # BRAM Flop Optimization diff --git a/rtl/sys_gen/tst_serloop/basys3/tb/.gitignore b/rtl/sys_gen/tst_serloop/basys3/tb/.gitignore new file mode 100644 index 00000000..e3af4925 --- /dev/null +++ b/rtl/sys_gen/tst_serloop/basys3/tb/.gitignore @@ -0,0 +1,3 @@ +tb_tst_serloop1_b3 +tb_tst_serloop2_b3 +tb_tst_serloop_stim diff --git a/rtl/sys_gen/tst_serloop/basys3/tb/Makefile b/rtl/sys_gen/tst_serloop/basys3/tb/Makefile new file mode 100644 index 00000000..095a499c --- /dev/null +++ b/rtl/sys_gen/tst_serloop/basys3/tb/Makefile @@ -0,0 +1,42 @@ +# $Id: Makefile 1369 2023-02-08 18:59:50Z mueller $ +# SPDX-License-Identifier: GPL-3.0-or-later +# Copyright 2023- by Walter F.J. Mueller +# +# Revision History: +# Date Rev Version Comment +# 2023-02-07 1369 1.0 Initial version +# +EXE_all = tb_tst_serloop1_b3 +EXE_all += tb_tst_serloop2_b3 +# +include ${RETROBASE}/rtl/make_viv/viv_default_basys3.mk +# +.PHONY : all all_ssim all_osim clean +.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_osim : $(EXE_all:=_osim) +# +all_XSim : $(EXE_all:=_XSim) +all_XSim_ssim : $(EXE_all:=_XSim_ssim) +all_XSim_osim : $(EXE_all:=_XSim_osim) +all_XSim_tsim : $(EXE_all:=_XSim_tsim) +# +clean : viv_clean ghdl_clean xsim_clean +# +#----- +# +include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk +include ${RETROBASE}/rtl/make_viv/generic_xsim.mk +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(VBOM_all:.vbom=.dep_vsim) +include $(wildcard *.o.dep_ghdl) +endif +# diff --git a/rtl/sys_gen/tst_serloop/basys3/tb/sys_conf1_sim.vhd b/rtl/sys_gen/tst_serloop/basys3/tb/sys_conf1_sim.vhd new file mode 100644 index 00000000..3bd19060 --- /dev/null +++ b/rtl/sys_gen/tst_serloop/basys3/tb/sys_conf1_sim.vhd @@ -0,0 +1,49 @@ +-- $Id: sys_conf1_sim.vhd 1369 2023-02-08 18:59:50Z mueller $ +-- SPDX-License-Identifier: GPL-3.0-or-later +-- Copyright 2023- by Walter F.J. Mueller +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_serloop1_b3 (for test bench) +-- +-- Dependencies: - +-- Tool versions: viv 2022.1-; ghdl 2.0.0 +-- Revision History: +-- Date Rev Version Comment +-- 2023-02-07 1369 1.0 Initial version (cloned from sys_tst_serloop1_n4) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + -- in simulation a usec stays to 120 cycles (1.0 usec) and a msec to + -- 240 cycles (2 usec). This affects mainly the autobauder. A break will be + -- detected after 128 msec periods, this in simulation after 256 usec or + -- 30720 cycles. This is compatible with bitrates of 115200 baud or higher + -- (115200 <-> 8.68 usec <-> 1040 cycles) + + -- configure clocks -------------------------------------------------------- + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 12; -- vco 1200 MHz + constant sys_conf_clksys_outdivide : positive := 10; -- sys 120 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + + constant sys_conf_clkdiv_msecdiv : integer := 2; -- shortened !! + + -- configure hio interfaces ----------------------------------------------- + constant sys_conf_hio_debounce : boolean := false; -- no debouncers + + -- configure serport ------------------------------------------------------ + constant sys_conf_uart_cdinit : integer := 1-1; -- 1 cycle/bit in sim + + -- derived constants ======================================================= + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + +end package sys_conf; diff --git a/rtl/sys_gen/tst_serloop/basys3/tb/sys_conf2_sim.vhd b/rtl/sys_gen/tst_serloop/basys3/tb/sys_conf2_sim.vhd new file mode 100644 index 00000000..3247e958 --- /dev/null +++ b/rtl/sys_gen/tst_serloop/basys3/tb/sys_conf2_sim.vhd @@ -0,0 +1,61 @@ +-- $Id: sys_conf2_sim.vhd 1369 2023-02-08 18:59:50Z mueller $ +-- SPDX-License-Identifier: GPL-3.0-or-later +-- Copyright 2023- by Walter F.J. Mueller +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_serloop1_b3 (for test bench) +-- +-- Dependencies: - +-- Tool versions: viv 2022.1-; ghdl 2.0.0 +-- Revision History: +-- Date Rev Version Comment +-- 2023-02-07 1369 1.0 Initial version (cloned from sys_tst_serloop1_n4) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + -- in simulation a usec stays to 120 cycles (1.0 usec) and a msec to + -- 240 cycles (2 usec). This affects mainly the autobauder. A break will be + -- detected after 128 msec periods, this in simulation after 256 usec or + -- 30720 cycles. This is compatible with bitrates of 115200 baud or higher + -- (115200 <-> 8.68 usec <-> 1040 cycles) + + -- configure clocks -------------------------------------------------------- + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 12; -- vco 1200 MHz + constant sys_conf_clksys_outdivide : positive := 10; -- sys 120 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + + constant sys_conf_clksys_msecdiv : integer := 2; -- shortened !! + + constant sys_conf_clkser_vcodivide : positive := 1; + constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz + constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz + constant sys_conf_clkser_gentype : string := "PLL"; + + constant sys_conf_clkser_msecdiv : integer := 2; -- shortened !! + + -- configure hio interfaces ----------------------------------------------- + constant sys_conf_hio_debounce : boolean := false; -- no debouncers + + -- configure serport ------------------------------------------------------ + constant sys_conf_uart_cdinit : integer := 1-1; -- 1 cycle/bit in sim + + -- derived constants ======================================================= + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_clkser : integer := + ((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) / + sys_conf_clkser_outdivide; + constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000; + +end package sys_conf; diff --git a/rtl/sys_gen/tst_serloop/basys3/tb/tb_tst_serloop1_b3.vbom b/rtl/sys_gen/tst_serloop/basys3/tb/tb_tst_serloop1_b3.vbom new file mode 100644 index 00000000..95be82bb --- /dev/null +++ b/rtl/sys_gen/tst_serloop/basys3/tb/tb_tst_serloop1_b3.vbom @@ -0,0 +1,12 @@ +# libs +../../../../vlib/slvtypes.vhd +../../../../vlib/xlib/xlib.vhd +../../../../vlib/simlib/simlib.vhd +${sys_conf := sys_conf1_sim.vhd} +# components +../../../../vlib/simlib/simclk.vbom +../../../../vlib/xlib/sfs_gsim_core.vbom +../sys_tst_serloop1_b3.vbom -UUT +../../tb/tb_tst_serloop.vbom +# design +tb_tst_serloop1_b3.vhd diff --git a/rtl/sys_gen/tst_serloop/basys3/tb/tb_tst_serloop1_b3.vhd b/rtl/sys_gen/tst_serloop/basys3/tb/tb_tst_serloop1_b3.vhd new file mode 100644 index 00000000..74d18e32 --- /dev/null +++ b/rtl/sys_gen/tst_serloop/basys3/tb/tb_tst_serloop1_b3.vhd @@ -0,0 +1,112 @@ +-- $Id: tb_tst_serloop1_b3.vhd 1369 2023-02-08 18:59:50Z mueller $ +-- SPDX-License-Identifier: GPL-3.0-or-later +-- Copyright 2023- by Walter F.J. Mueller +-- +------------------------------------------------------------------------------ +-- Module Name: tb_tst_serloop1_b3 - sim +-- Description: Test bench for sys_tst_serloop1_b3 +-- +-- Dependencies: simlib/simclk +-- xlib/sfs_gsim_core +-- sys_tst_serloop1_b3 [UUT] +-- tb/tb_tst_serloop +-- +-- To test: sys_tst_serloop1_b3 +-- +-- Target Devices: generic +-- +-- Revision History: +-- Date Rev Version Comment +-- 2023-02-07 1369 1.0 Initial version (cloned from tb_tst_serloop1_n4) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.simlib.all; +use work.sys_conf.all; + +entity tb_tst_serloop1_b3 is +end tb_tst_serloop1_b3; + +architecture sim of tb_tst_serloop1_b3 is + + signal CLK100 : slbit := '0'; + + signal CLK : slbit := '0'; + + signal I_RXD : slbit := '1'; + signal O_TXD : slbit := '1'; + signal I_SWI : slv16 := (others=>'0'); + signal I_BTN : slv5 := (others=>'0'); + + signal RXD : slbit := '1'; + signal TXD : slbit := '1'; + signal SWI : slv16 := (others=>'0'); + signal BTN : slv5 := (others=>'0'); + + constant clock_period : Delay_length := 10 ns; + constant clock_offset : Delay_length := 200 ns; + constant delay_time : Delay_length := 2 ns; + +begin + + SYSCLK : simclk + generic map ( + PERIOD => clock_period, + OFFSET => clock_offset) + port map ( + CLK => CLK100 + ); + + GEN_CLKSYS : sfs_gsim_core + generic map ( + VCO_DIVIDE => sys_conf_clksys_vcodivide, + VCO_MULTIPLY => sys_conf_clksys_vcomultiply, + OUT_DIVIDE => sys_conf_clksys_outdivide) + port map ( + CLKIN => CLK100, + CLKFX => CLK, + LOCKED => open + ); + + UUT : entity work.sys_tst_serloop1_b3 + port map ( + I_CLK100 => CLK100, + I_RXD => I_RXD, + O_TXD => O_TXD, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => open, + O_ANO_N => open, + O_SEG_N => open + ); + + GENTB : entity work.tb_tst_serloop + port map ( + CLKS => CLK, + CLKH => CLK, + P0_RXD => RXD, + P0_TXD => TXD, + P0_RTS_N => '0', + P0_CTS_N => open, + P1_RXD => open, -- port 1 unused for b3 ! + P1_TXD => '0', + P1_RTS_N => '0', + P1_CTS_N => open, + SWI => SWI(7 downto 0), + BTN => BTN(3 downto 0) + ); + + I_RXD <= RXD after delay_time; + TXD <= O_TXD after delay_time; + + I_SWI <= SWI after delay_time; + I_BTN <= BTN after delay_time; + +end sim; diff --git a/rtl/sys_gen/tst_serloop/basys3/tb/tb_tst_serloop2_b3.vbom b/rtl/sys_gen/tst_serloop/basys3/tb/tb_tst_serloop2_b3.vbom new file mode 100644 index 00000000..fdbbe475 --- /dev/null +++ b/rtl/sys_gen/tst_serloop/basys3/tb/tb_tst_serloop2_b3.vbom @@ -0,0 +1,12 @@ +# libs +../../../../vlib/slvtypes.vhd +../../../../vlib/xlib/xlib.vhd +../../../../vlib/simlib/simlib.vhd +${sys_conf := sys_conf2_sim.vhd} +# components +../../../../vlib/simlib/simclk.vbom +../../../../vlib/xlib/sfs_gsim_core.vbom +../sys_tst_serloop2_b3.vbom -UUT +../../tb/tb_tst_serloop.vbom +# design +tb_tst_serloop2_b3.vhd diff --git a/rtl/sys_gen/tst_serloop/basys3/tb/tb_tst_serloop2_b3.vhd b/rtl/sys_gen/tst_serloop/basys3/tb/tb_tst_serloop2_b3.vhd new file mode 100644 index 00000000..1a947143 --- /dev/null +++ b/rtl/sys_gen/tst_serloop/basys3/tb/tb_tst_serloop2_b3.vhd @@ -0,0 +1,124 @@ +-- $Id: tb_tst_serloop2_b3.vhd 1369 2023-02-08 18:59:50Z mueller $ +-- SPDX-License-Identifier: GPL-3.0-or-later +-- Copyright 2023- by Walter F.J. Mueller +-- +------------------------------------------------------------------------------ +-- Module Name: tb_tst_serloop2_b3 - sim +-- Description: Test bench for sys_tst_serloop2_b3 +-- +-- Dependencies: simlib/simclk +-- xlib/sfs_gsim_core +-- sys_tst_serloop2_b3 [UUT] +-- tb/tb_tst_serloop +-- +-- To test: sys_tst_serloop2_b3 +-- +-- Target Devices: generic +-- +-- Revision History: +-- Date Rev Version Comment +-- 2023-02-07 1369 1.0 Initial version (cloned from tb_tst_serloop2_n4) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.simlib.all; +use work.sys_conf.all; + +entity tb_tst_serloop2_b3 is +end tb_tst_serloop2_b3; + +architecture sim of tb_tst_serloop2_b3 is + + signal CLK100 : slbit := '0'; + + signal CLKS : slbit := '0'; + signal CLKH : slbit := '0'; + + signal I_RXD : slbit := '1'; + signal O_TXD : slbit := '1'; + signal I_SWI : slv16 := (others=>'0'); + signal I_BTN : slv5 := (others=>'0'); + + signal RXD : slbit := '1'; + signal TXD : slbit := '1'; + signal SWI : slv16 := (others=>'0'); + signal BTN : slv5 := (others=>'0'); + + constant clock_period : Delay_length := 10 ns; + constant clock_offset : Delay_length := 200 ns; + constant delay_time : Delay_length := 2 ns; + +begin + + SYSCLK : simclk + generic map ( + PERIOD => clock_period, + OFFSET => clock_offset) + port map ( + CLK => CLK100 + ); + + GEN_CLKSYS : sfs_gsim_core + generic map ( + VCO_DIVIDE => sys_conf_clksys_vcodivide, + VCO_MULTIPLY => sys_conf_clksys_vcomultiply, + OUT_DIVIDE => sys_conf_clksys_outdivide) + port map ( + CLKIN => CLK100, + CLKFX => CLKH, + LOCKED => open + ); + + GEN_CLKSER : sfs_gsim_core + generic map ( + VCO_DIVIDE => sys_conf_clkser_vcodivide, + VCO_MULTIPLY => sys_conf_clkser_vcomultiply, + OUT_DIVIDE => sys_conf_clkser_outdivide) + port map ( + CLKIN => CLK100, + CLKFX => CLKS, + LOCKED => open + ); + + UUT : entity work.sys_tst_serloop2_b3 + port map ( + I_CLK100 => CLK100, + I_RXD => I_RXD, + O_TXD => O_TXD, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => open, + O_ANO_N => open, + O_SEG_N => open + ); + + GENTB : entity work.tb_tst_serloop + port map ( + CLKS => CLKS, + CLKH => CLKH, + P0_RXD => RXD, + P0_TXD => TXD, + P0_RTS_N => '0', + P0_CTS_N => open, + P1_RXD => open, -- port 1 unused for b3 ! + P1_TXD => '0', + P1_RTS_N => '0', + P1_CTS_N => open, + SWI => SWI(7 downto 0), + BTN => BTN(3 downto 0) + ); + + I_RXD <= RXD after delay_time; + TXD <= O_TXD after delay_time; + + I_SWI <= SWI after delay_time; + I_BTN <= BTN after delay_time; + +end sim; diff --git a/rtl/sys_gen/tst_serloop/basys3/tb/tbrun.yml b/rtl/sys_gen/tst_serloop/basys3/tb/tbrun.yml new file mode 100644 index 00000000..0d06e229 --- /dev/null +++ b/rtl/sys_gen/tst_serloop/basys3/tb/tbrun.yml @@ -0,0 +1,16 @@ +# $Id: tbrun.yml 1369 2023-02-08 18:59:50Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2023-02-07 1369 1.0 Initial version +# +- default: + mode: ${viv_modes} +# +- tag: [default, viv, sys_tst_serloop1, b3] + test: | + tbrun_tbw tb_tst_serloop1_b3${ms} + +- tag: [default, viv, sys_tst_serloop2, b3] + test: | + tbrun_tbw tb_tst_serloop2_b3${ms} diff --git a/rtl/sys_gen/tst_serloop/basys3/tb/tbw.dat b/rtl/sys_gen/tst_serloop/basys3/tb/tbw.dat new file mode 100644 index 00000000..1d6b89b2 --- /dev/null +++ b/rtl/sys_gen/tst_serloop/basys3/tb/tbw.dat @@ -0,0 +1,6 @@ +# $Id: tbw.dat 1369 2023-02-08 18:59:50Z mueller $ +# +[tb_tst_serloop1_b3] +tb_tst_serloop_stim = ../../tb/tb_tst_serloop_p0_xon_stim.dat +[tb_tst_serloop2_b3] +tb_tst_serloop_stim = ../../tb/tb_tst_serloop_p0_xon_stim.dat diff --git a/rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop1_n2.vhd b/rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop1_n2.vhd index 9dab5443..83f560d5 100644 --- a/rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop1_n2.vhd +++ b/rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop1_n2.vhd @@ -1,10 +1,10 @@ --- $Id: sys_tst_serloop1_n2.vhd 1181 2019-07-08 17:00:50Z mueller $ +-- $Id: sys_tst_serloop1_n2.vhd 1369 2023-02-08 18:59:50Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later -- Copyright 2011- by Walter F.J. Mueller -- ------------------------------------------------------------------------------ -- Module Name: sys_tst_serloop1_n2 - syn --- Description: Tester serial link for nexys2 +-- Description: Serial link tester design for nexys2 (serport_1clock case) -- -- Dependencies: genlib/clkdivce -- bpgen/bp_rs232_2l4l_iob diff --git a/rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop2_n2.vhd b/rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop2_n2.vhd index ff64ea64..0d3eb37b 100644 --- a/rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop2_n2.vhd +++ b/rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop2_n2.vhd @@ -1,10 +1,10 @@ --- $Id: sys_tst_serloop2_n2.vhd 1181 2019-07-08 17:00:50Z mueller $ +-- $Id: sys_tst_serloop2_n2.vhd 1369 2023-02-08 18:59:50Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later -- Copyright 2011- by Walter F.J. Mueller -- ------------------------------------------------------------------------------ -- Module Name: sys_tst_serloop2_n2 - syn --- Description: Tester serial link for nexys2 +-- Description: Serial link tester design for nexys2 (serport_2clock case) -- -- Dependencies: vlib/xlib/dcm_sfs -- genlib/clkdivce diff --git a/rtl/sys_gen/tst_serloop/nexys3/sys_tst_serloop1_n3.vhd b/rtl/sys_gen/tst_serloop/nexys3/sys_tst_serloop1_n3.vhd index b6695fb5..ebd8eb68 100644 --- a/rtl/sys_gen/tst_serloop/nexys3/sys_tst_serloop1_n3.vhd +++ b/rtl/sys_gen/tst_serloop/nexys3/sys_tst_serloop1_n3.vhd @@ -1,10 +1,10 @@ --- $Id: sys_tst_serloop1_n3.vhd 1181 2019-07-08 17:00:50Z mueller $ +-- $Id: sys_tst_serloop1_n3.vhd 1369 2023-02-08 18:59:50Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later -- Copyright 2011- by Walter F.J. Mueller -- ------------------------------------------------------------------------------ -- Module Name: sys_tst_serloop1_n3 - syn --- Description: Tester serial link for nexys3 (serport_1clock case) +-- Description: Serial link tester design for nexys3 (serport_1clock case) -- -- Dependencies: genlib/clkdivce -- bpgen/bp_rs232_2l4l_iob diff --git a/rtl/sys_gen/tst_serloop/nexys3/sys_tst_serloop2_n3.vhd b/rtl/sys_gen/tst_serloop/nexys3/sys_tst_serloop2_n3.vhd index 8ecb26ba..9ea28035 100644 --- a/rtl/sys_gen/tst_serloop/nexys3/sys_tst_serloop2_n3.vhd +++ b/rtl/sys_gen/tst_serloop/nexys3/sys_tst_serloop2_n3.vhd @@ -1,10 +1,10 @@ --- $Id: sys_tst_serloop2_n3.vhd 1181 2019-07-08 17:00:50Z mueller $ +-- $Id: sys_tst_serloop2_n3.vhd 1369 2023-02-08 18:59:50Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later -- Copyright 2011- by Walter F.J. Mueller -- ------------------------------------------------------------------------------ -- Module Name: sys_tst_serloop2_n3 - syn --- Description: Tester serial link for nexys3 +-- Description: Serial link tester design for nexys3 (serport_2clock case) -- -- Dependencies: vlib/xlib/dcm_sfs -- genlib/clkdivce diff --git a/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop1_n4.vhd b/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop1_n4.vhd index 7d128f1f..71667b97 100644 --- a/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop1_n4.vhd +++ b/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop1_n4.vhd @@ -1,10 +1,10 @@ --- $Id: sys_tst_serloop1_n4.vhd 1181 2019-07-08 17:00:50Z mueller $ +-- $Id: sys_tst_serloop1_n4.vhd 1369 2023-02-08 18:59:50Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later -- Copyright 2015-2019 by Walter F.J. Mueller -- ------------------------------------------------------------------------------ -- Module Name: sys_tst_serloop1_n4 - syn --- Description: Tester serial link for nexys4 (serport_1clock case) +-- Description: Serial link tester design for nexys4 (serport_1clock case) -- -- Dependencies: vlib/xlib/s7_cmt_sfs -- vlib/genlib/clkdivce diff --git a/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop2_n4.vhd b/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop2_n4.vhd index 26c5135e..28be3054 100644 --- a/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop2_n4.vhd +++ b/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop2_n4.vhd @@ -1,10 +1,10 @@ --- $Id: sys_tst_serloop2_n4.vhd 1181 2019-07-08 17:00:50Z mueller $ +-- $Id: sys_tst_serloop2_n4.vhd 1369 2023-02-08 18:59:50Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later -- Copyright 2016-2019 by Walter F.J. Mueller -- ------------------------------------------------------------------------------ -- Module Name: sys_tst_serloop2_n4 - syn --- Description: Tester serial link for nexys4 (serport_2clock case) +-- Description: Serial link tester design for nexys4 (serport_2clock case) -- -- Dependencies: bplib/bpgen/s7_cmt_1ce1ce -- bpgen/bp_rs232_4line_iob diff --git a/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop1_n4d.vhd b/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop1_n4d.vhd index a1e6cd85..ba06b2b7 100644 --- a/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop1_n4d.vhd +++ b/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop1_n4d.vhd @@ -1,10 +1,10 @@ --- $Id: sys_tst_serloop1_n4d.vhd 1247 2022-07-06 07:04:33Z mueller $ +-- $Id: sys_tst_serloop1_n4d.vhd 1369 2023-02-08 18:59:50Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later -- Copyright 2017-2022 by Walter F.J. Mueller -- ------------------------------------------------------------------------------ -- Module Name: sys_tst_serloop1_n4d - syn --- Description: Tester serial link for nexys4d (serport_1clock case) +-- Description: Serial link tester design for nexys4d (serport_1clock case) -- -- Dependencies: vlib/xlib/s7_cmt_sfs -- vlib/genlib/clkdivce diff --git a/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop2_n4d.vhd b/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop2_n4d.vhd index 4372726f..c27d386c 100644 --- a/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop2_n4d.vhd +++ b/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop2_n4d.vhd @@ -1,10 +1,10 @@ --- $Id: sys_tst_serloop2_n4d.vhd 1247 2022-07-06 07:04:33Z mueller $ +-- $Id: sys_tst_serloop2_n4d.vhd 1369 2023-02-08 18:59:50Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later -- Copyright 2017-2022 by Walter F.J. Mueller -- ------------------------------------------------------------------------------ -- Module Name: sys_tst_serloop2_n4d - syn --- Description: Tester serial link for nexys4d (serport_2clock case) +-- Description: Serial link tester design for nexys4d (serport_2clock case) -- -- Dependencies: bplib/bpgen/s7_cmt_1ce1ce -- bpgen/bp_rs232_4line_iob diff --git a/rtl/sys_gen/tst_serloop/s3board/sys_tst_serloop_s3.vhd b/rtl/sys_gen/tst_serloop/s3board/sys_tst_serloop_s3.vhd index 3ba588ea..e2a22a4d 100644 --- a/rtl/sys_gen/tst_serloop/s3board/sys_tst_serloop_s3.vhd +++ b/rtl/sys_gen/tst_serloop/s3board/sys_tst_serloop_s3.vhd @@ -1,10 +1,10 @@ --- $Id: sys_tst_serloop_s3.vhd 1181 2019-07-08 17:00:50Z mueller $ +-- $Id: sys_tst_serloop_s3.vhd 1369 2023-02-08 18:59:50Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later -- Copyright 2011- by Walter F.J. Mueller -- ------------------------------------------------------------------------------ -- Module Name: sys_tst_serloop_s3 - syn --- Description: Tester serial link for s3board +-- Description: Serial link tester design for s3board -- -- Dependencies: vlib/xlib/dcm_sfs -- genlib/clkdivce diff --git a/rtl/sys_gen/tst_serloop/tb/tb_tst_serloop_p0_xon_stim.dat b/rtl/sys_gen/tst_serloop/tb/tb_tst_serloop_p0_xon_stim.dat new file mode 100644 index 00000000..1dc004a8 --- /dev/null +++ b/rtl/sys_gen/tst_serloop/tb/tb_tst_serloop_p0_xon_stim.dat @@ -0,0 +1,75 @@ +# $Id: tb_tst_serloop_p0_xon_stim.dat 1369 2023-02-08 18:59:50Z mueller $ +# SPDX-License-Identifier: GPL-3.0-or-later +# Copyright 2023- by Walter F.J. Mueller +# +# Revision History: +# Date Rev Version Comment +# 2023-02-07 1369 1.0 Initial version (for port 0 xon) +# +C ------------------------------------------------ +C try SWI settings +# only the 4 LBS (disp and enable control) +# don't touch the 2 mode settings here !! +# +wait 10 +# +swi 10000000 2 +swi 01000000 2 +swi 00100000 2 +swi 00010000 2 +swi 00000000 2 +wait 2 +# +C ------------------------------------------------ +C loop-back message with 16 bytes on port 0 +# +port 0 +swi 00000000 2 +btn 0 10 +# +# mode=11(loop); +swi 00000110 2 +btn 1 10 +# +expect 16 0 0 +send 16 0 0 +wait 100 +expect 0 0 0 +# +C ------------------------------------------------ +C loop-back message with 32 bytes escaped on port 0 +# +port 0 +swi 00000000 2 +btn 0 10 +# +# enaesc=1; mode=11(loop) +swi 00100110 2 +btn 1 10 +# +expect 32 1 0 +send 32 1 0 +wait 100 +expect 0 0 0 +# +C ------------------------------------------------ +C loop-back message with 256 bytes escaped on port 0; xon throttle +# +port 0 +swi 00000000 2 +btn 0 10 +# +# enaesc=1;enaxon=1; mode=11(loop); port=0 +swi 00110110 2 +btn 1 10 +# +xon 200 100 +expect 256 1 1 +send 256 1 1 +wait 1500 +expect 0 0 0 +xon 0 0 +# +C ------------------------------------------------ +C cool down +wait 200 diff --git a/rtl/sys_gen/tst_serloop/tbrun.yml b/rtl/sys_gen/tst_serloop/tbrun.yml index 22c2ea6c..59609e0c 100644 --- a/rtl/sys_gen/tst_serloop/tbrun.yml +++ b/rtl/sys_gen/tst_serloop/tbrun.yml @@ -1,7 +1,8 @@ -# $Id: tbrun.yml 1231 2022-04-28 08:40:50Z mueller $ +# $Id: tbrun.yml 1369 2023-02-08 18:59:50Z mueller $ # # Revision History: # Date Rev Version Comment +# 2023-02-08 1369 1.1.1 add basys3 # 2022-04-25 1231 1.1 drop nexys4,atlys; add nexys4d # 2016-08-22 800 1.0 Initial version # @@ -9,3 +10,4 @@ - include: nexys2/tb/tbrun.yml - include: nexys3/tb/tbrun.yml - include: nexys4d/tb/tbrun.yml +- include: basys3/tb/tbrun.yml diff --git a/rtl/sys_gen/tst_serloop/tst_serloop.c b/rtl/sys_gen/tst_serloop/tst_serloop.c new file mode 100644 index 00000000..71a70d63 --- /dev/null +++ b/rtl/sys_gen/tst_serloop/tst_serloop.c @@ -0,0 +1,865 @@ +/* $Id: tst_serloop.c 1369 2023-02-08 18:59:50Z mueller $ */ +/* SPDX-License-Identifier: GPL-3.0-or-later + * Copyright 2011-2023 by Walter F.J. Mueller + * + * Revision History: + * Date Rev Version Comment + * 2023-02-08 1369 1.1.2 use %9.1f cps, it can be > 1000000.0 + * 2016-03-25 751 1.1.1 clear ASYNC_SPD_CUST if not needed + * 2015-02-01 641 1.1 add non-standart baud rates (via custom divisor) + * 2011-12-22 442 1.0.2 more text in usage() + * 2011-12-18 440 1.0.1 add -lowlat command (optionally, linux specific) + * 2011-12-09 438 1.0 Initial version (from sys_s3board/tst_serport/...) +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +typedef unsigned int u_int; +typedef unsigned char u_char; + +static char c_xon = 0x11; /* XON char -> ^Q = hex 11 */ +static char c_xoff = 0x13; /* XOFF char -> ^S = hex 13 */ +static char c_xesc = 0x1b; /* XESC char -> ^[ = ESC = hex 1B */ + +static int nsigint = 0; +static int trace = 0; +static int xesc = 0; +static unsigned int iseed = 1234567; + +void usage(FILE* of); +int get_pint(char* p); +double get_double(char* p); +#ifdef HAS_LOWLAT +void do_lowlat(int fd); +#endif +void do_ptios(struct termios* tios, struct serial_struct* sioctl); +void do_break(int fd); +void do_write(int fd, char* buf, int nc); +void do_read(int fd); +void do_txblast(int fd, int nsec); +void do_rxblast(int fd, int nsec, int nbyt); +void do_loop(int fd, int nsec, int nbyt); +void do_sleep(int nms, int pe); +void do_sleep1(double dms); +void prt_time(void); +double get_time(void); +void mysleep(double dt); +double myrandom(void); + +void sigint_handler(int signum) +{ + printf("\n"); + nsigint += 1; + if (nsigint > 3) { + fprintf(stderr, "tst_serloop-I: 3rd ^C, aborting\n"); + exit(EXIT_FAILURE); + } + return; +} + +int main(int argc,char *argv[]) +{ + int argi = 0; + int fd = -1; + int baud = -1; + int flow = -1; + tcflag_t baudbits = 0; + struct termios oldtios; + struct termios newtios; + struct termios chktios; + struct serial_struct sioctl; + int cdivisor = 0; + + struct sigaction new_action; + + char devnam[256]; + + new_action.sa_handler = sigint_handler; + sigemptyset (&new_action.sa_mask); + new_action.sa_flags = 0; + sigaction (SIGINT, &new_action, NULL); + + if (argc < 4) { + fprintf(stderr, "tst_serloop-E: missing port, speed, or flow\n"); + usage(stderr); + return EXIT_FAILURE; + } + + if (argv[1][0] == '/') { + strncpy(devnam, argv[1], 256); + devnam[255] = 0; + } else { + strcpy(devnam, "/dev/tty"); + strncpy(devnam+strlen(devnam), argv[1], 256-strlen(devnam)); + devnam[255] = 0; + } + + fd = open(devnam, /* open tty device */ + O_RDWR|O_NOCTTY); /* read/write, not controlling TTY*/ + + if (fd == -1) { + fprintf(stderr, "tst_serloop-E: failed to open \"%s\"\n", devnam); + perror("open:"); + return EXIT_FAILURE; + } + + if (!isatty(fd)) { + fprintf(stderr, "tst_serloop-E: \"%s\" is not a tty port\n", devnam); + return EXIT_FAILURE; + } + + if(tcgetattr(fd, &oldtios) == -1) { /* save old tios */ + perror("failed to tcgetattr:"); + return EXIT_FAILURE; + } + + if (ioctl(fd, TIOCGSERIAL, &sioctl) < 0) { + perror("failed to ioctl(TIOCGSERIAL):"); + return EXIT_FAILURE; + } + + baud = get_pint(argv[2]); + if (baud < 0) return EXIT_FAILURE; + + /* Note: allow all baud rates above 2400 baud which are defined by linux + * in /usr/include/bits/termios.h . Only a subset of them might be + * supported in a given device. + */ + switch (baud) { + case 2400: baudbits = B2400; break; + case 4800: baudbits = B4800; break; + case 9600: baudbits = B9600; break; + case 19200: baudbits = B19200; break; + case 38400: baudbits = B38400; break; + case 57600: baudbits = B57600; break; + case 115200: baudbits = B115200; break; + case 230400: baudbits = B230400; break; + case 460800: baudbits = B460800; break; + case 500000: baudbits = B500000; break; + case 576000: baudbits = B576000; break; + case 921600: baudbits = B921600; break; + case 1000000: baudbits = B1000000; break; + case 1152000: baudbits = B1152000; break; + case 1500000: baudbits = B1500000; break; + case 2000000: baudbits = B2000000; break; + case 2500000: baudbits = B2500000; break; + case 3000000: baudbits = B3000000; break; + case 3500000: baudbits = B3500000; break; + case 4000000: baudbits = B4000000; break; + } + + if (baudbits == 0) { + double fcdivisor = (double)sioctl.baud_base / (double)baud; + cdivisor = fcdivisor + 0.5; + baudbits = B38400; + // printf("+++ fcdivisor = %6.2f\n", fcdivisor); + } + + flow = get_pint(argv[3]); + if (flow < 0) return EXIT_FAILURE; + if (flow > 2) { + fprintf(stderr, "tst_serloop-E: flow must be 0,1,2; seen: %d\n", flow); + return EXIT_FAILURE; + } + if (flow == 2) xesc = 1; + + memset(&newtios,0,sizeof(newtios)); /* clear new tios */ + newtios.c_iflag = IGNPAR; /* ignore parity errors */ + newtios.c_oflag = 0; + newtios.c_cflag = CS8| /* 8 bit chars */ + CSTOPB| /* 2 stop bits */ + CREAD| /* enable receiver */ + CLOCAL| /* ignore modem control */ + baudbits; /* baud rate flags */ + newtios.c_lflag = 0; + newtios.c_cc[VTIME] = 1; /* timeout after 100 ms */ + newtios.c_cc[VMIN] = 0; /* don't wait for char's */ + + if (flow == 1) { + newtios.c_cflag |= CRTSCTS; /* enable rts/cts flow control */ + } else if (flow == 2) { + newtios.c_iflag |= IXON| /* XON/XOFF flow control output */ + IXOFF; /* XON/XOFF flow control input */ + newtios.c_cc[VSTART] = c_xon; /* setup XON -> ^Q */ + newtios.c_cc[VSTOP] = c_xoff; /* setup XOFF -> ^S */ + } + + if (tcsetattr(fd, TCSANOW, &newtios) == -1) { /* set tios */ + perror("failed to tcsetattr:"); + return EXIT_FAILURE; + } + + if (sioctl.flags & ASYNC_SPD_CUST) { /* old CUST set ? */ + sioctl.flags &= ~(ASYNC_SPD_CUST); + sioctl.custom_divisor = 0; + if (ioctl(fd, TIOCSSERIAL, &sioctl) < 0) { + perror("failed to ioctl(TIOCSSERIAL):"); + tcsetattr(fd, TCSANOW, &oldtios); + return EXIT_FAILURE; + } + } + + if (cdivisor != 0) { /* new CUST needed ? */ + sioctl.flags |= ASYNC_SPD_CUST; + sioctl.custom_divisor = cdivisor; + if (ioctl(fd, TIOCSSERIAL, &sioctl) < 0) { + perror("failed to ioctl(TIOCSSERIAL):"); + tcsetattr(fd, TCSANOW, &oldtios); + return EXIT_FAILURE; + } + } + + + if (tcgetattr(fd, &chktios) == -1) { /* verify tios */ + perror("failed to tcgetattr:"); + tcsetattr(fd, TCSANOW, &oldtios); + return EXIT_FAILURE; + } + + for (argi = 4; argi < argc; ) { + if (strcmp(argv[argi],"-help") == 0) { + argi += 1; + usage(stdout); + return EXIT_SUCCESS; + +#ifdef HAS_LOWLAT + } else if (strcmp(argv[argi],"-lowlat") == 0) { + argi += 1; + do_lowlat(fd); +#endif + + } else if (strcmp(argv[argi],"-ptios") == 0) { + argi += 1; + do_ptios(&newtios, &sioctl); + + } else if (strcmp(argv[argi],"-break") == 0) { + argi += 1; + do_break(fd); + + } else if (strcmp(argv[argi],"-trace") == 0) { + argi += 1; + trace = 1; + + } else if (strcmp(argv[argi],"-write") == 0) { + char buf[4096]; + int nc = 0; + argi += 1; + while(argi < argc && nc < 4096) { + char *argp = argv[argi]; + int doneg = 0; + int val = 0; + if (argp[0] == '-') break; + if (strcmp(argp,"XON") == 0) { + val = c_xon; + } else if (strcmp(argp,"XOFF") == 0) { + val = c_xoff; + } else if (strcmp(argp,"XESC") == 0) { + val = c_xesc; + } else { + if (argp[0] == '~') { + argp += 1; + doneg = 1; + } + val = get_pint(argp); + if (val < 0) { + nc = 0; + break; + } + if (doneg) val = ~val; + } + + argi += 1; + buf[nc++] = val; + } + if (nc == 0) { + fprintf(stderr, "tst_serloop-E: bad char list\n"); + break; + } + + do_write(fd, buf, nc); + + } else if (strcmp(argv[argi],"-read") == 0) { + argi += 1; + do_read(fd); + + } else if (strcmp(argv[argi],"-txblast") == 0) { + int nsec = -1; + argi += 1; + if (argi < argc) nsec = get_pint(argv[argi++]); + if (nsec >= 0) do_txblast(fd, nsec); + else { + fprintf(stderr, "tst_serloop-E: bad args for -txblast\n"); + break; + } + + } else if (strcmp(argv[argi],"-rxblast") == 0) { + int nsec = -1; + int nbyt = -1; + argi += 1; + if (argi < argc) nsec = get_pint(argv[argi++]); + if (argi < argc) nbyt = get_pint(argv[argi++]); + if (nsec >= 0 && nbyt > 0 && nbyt <= 4096) do_rxblast(fd, nsec, nbyt); + else { + fprintf(stderr, "tst_serloop-E: bad args for -rxblast\n"); + break; + } + + } else if (strcmp(argv[argi],"-loop") == 0) { + int nsec = -1; + int nbyt = -1; + argi += 1; + if (argi < argc) nsec = get_pint(argv[argi++]); + if (argi < argc) nbyt = get_pint(argv[argi++]); + if (nsec >= 0 && nbyt > 0 && nbyt <= 4096) do_loop(fd, nsec, nbyt); + else { + fprintf(stderr, "tst_serloop-E: bad args for -loop\n"); + break; + } + + } else if (strcmp(argv[argi],"-sleep") == 0) { + int nms = -1; + argi += 1; + if (argi < argc) nms = get_pint(argv[argi++]); + if (nms > 0) do_sleep(nms, 1); + else { + fprintf(stderr, "tst_serloop-E: bad args for -sleep\n"); + break; + } + + } else if (strcmp(argv[argi],"-sleep1") == 0) { + double dms = -1.; + argi += 1; + if (argi < argc) dms = get_double(argv[argi++]); + if (dms > 0) do_sleep1(dms); + else { + fprintf(stderr, "tst_serloop-E: bad args for -sleep1\n"); + break; + } + + } else { + fprintf(stderr, "tst_serloop-E: unknown option %s\n", argv[argi]); + usage(stderr); + return EXIT_FAILURE; + } + } + + /* a delay is needed between tcdrain() and tcsetattr() because the baud + * rate reset can take effect in FT232Rs before the internal tx buffer is + * transmitted, so some late chars will be send with oldtios baud rate. + */ + + tcdrain(fd); + do_sleep(50, 0); + tcsetattr(fd, TCSANOW, &oldtios); + return EXIT_SUCCESS; +} + +/*--------------------------------------------------------------------------*/ + +void usage(FILE* of) +{ + fprintf(of, "Usage: tst_serloop port speed flow [option...]\n"); + fprintf(of, " port name of /dev file, e.g. /dev/ttyUSB0\n"); + fprintf(of, " speed baud rate: 2400,4800,9600,19200,38400,57600\n"); + fprintf(of, " 115200,230400,460800,500000,921600,1000000\n"); + fprintf(of, " 1152000,1500000,2000000,2500000,3000000\n"); + fprintf(of, " 3500000,4000000, others via custom divisor\n"); + fprintf(of, " flow 0 no flow control\n"); + fprintf(of, " 1 hardware flow control (RTS/CTS)\n"); + fprintf(of, " 2 software flow control (XON/XOFF)\n"); + fprintf(of, "-help this text\n"); + fprintf(of, "-ptios print tios structures\n"); +#ifdef HAS_LOWLAT + fprintf(of, "-lowlat set low latency mode\n"); +#endif + fprintf(of, "-break send break\n"); + fprintf(of, "-trace trace i/o in blast and loop\n"); + fprintf(of, "-write c.. write sequence of chars\n"); + fprintf(of, "-read read chars till timeout\n"); + fprintf(of, "-txblast ns read txblast output for ns sec (ns=0->forever)\n"); + fprintf(of, "-rxblast ns nb write rxblast input for ns sec, nb byte bufs \n"); + fprintf(of, "-loop ns nb write/read loop-back data for ns sec, nb bufs\n"); + fprintf(of, "-sleep n wait n msec (n int, 1msec resolutions)\n"); + fprintf(of, "-sleep1 dt wait dt msec (dt float, busy wait)\n"); +} + +/*--------------------------------------------------------------------------*/ + +int get_pint(char* p) +{ + char *endptr; + long num = 0; + + num = strtol(p, &endptr, 0); + if ((endptr && *endptr) || num < 0 || num > INT_MAX) { + fprintf(stderr, "tst_serloop-E: \"%s\" not a non-negative integer\n", p); + return -1; + } + return num; +} + +/*--------------------------------------------------------------------------*/ + +double get_double(char* p) +{ + char *endptr; + double num = 0.; + + num = strtod(p, &endptr); + if ((endptr && *endptr) || num < 0.) { + fprintf(stderr, "tst_serloop-E: \"%s\" not a valid positive float\n", p); + return -1.; + } + return num; +} + +/*--------------------------------------------------------------------------*/ + +#ifdef HAS_LOWLAT +void do_lowlat(int fd) +{ + struct serial_struct serial_ioctl; + + if (ioctl(fd, TIOCGSERIAL, &serial_ioctl) != 0) + perror("do_lowlat->ioctl(TIOCGSERIAL):"); + printf("old: serial_ioctl.flags = %8.8x\n", serial_ioctl.flags); + + serial_ioctl.flags |= ASYNC_LOW_LATENCY; + + if (ioctl(fd, TIOCSSERIAL, &serial_ioctl) != 0) + perror("do_lowlat->ioctl(TIOCSSERIAL):"); + if (ioctl(fd, TIOCGSERIAL, &serial_ioctl) != 0) + perror("do_lowlat->ioctl(TIOCGSERIAL)(2):"); + printf("new: serial_ioctl.flags = %8.8x\n", serial_ioctl.flags); + return; +} +#endif + +/*--------------------------------------------------------------------------*/ +void do_ptios(struct termios* tios, struct serial_struct* sioctl) +{ + printf(" sioctl->flags: 0x%8.8x\n", sioctl->flags); + printf(" sioctl->custom_divisor: %8d\n", sioctl->custom_divisor); + printf(" sioctl->baud_base: %8d\n", sioctl->baud_base); + return; +} + +/*--------------------------------------------------------------------------*/ +void do_break(int fd) +{ + char buf[1]; + buf[0] = 0x80; + + if (tcflush(fd, TCIOFLUSH) < 0) perror("do_break->tcflush:"); + if (tcsendbreak(fd, 0) < 0) perror("do_break->tcsendbreak:"); + if (write(fd, buf, 1) != 1) perror("do_break->write:"); + if (tcdrain(fd) < 0) perror("do_break->tcdrain:"); + return; +} + +/*--------------------------------------------------------------------------*/ + +void do_write(int fd, char* buf, int nc) +{ + int rc; + int i; + rc = write(fd, buf, nc); + prt_time(); + printf("write %3d char:", nc); + for (i = 0; i < nc; i++) printf(" %2.2x", (u_char)buf[i]); + printf("\n"); + if (rc < 0) perror("do_write->write:"); + return; +} + + +/*--------------------------------------------------------------------------*/ + +void do_read(int fd) +{ + int rc; + int i; + char buf[4096]; + while (1) { + rc = read(fd, buf, 4096); + if (rc == 0) break; + prt_time(); + printf("read %3d char:", rc); + for (i = 0; i < rc; i++) printf(" %2.2x", (u_char)buf[i]); + printf("\n"); + if (rc < 0) perror("do_read->read:"); + } + return; +} + +/*--------------------------------------------------------------------------*/ + +void do_txblast(int fd, int nsec) +{ + char buf[4096]; + double t_start; + double t_first; + double t_lastto; + double t_delta; + double ntot = 0.; + char cval = 0; + int xesc_pend = 0; + int i; + + prt_time(); + printf("read txblast output for %d seconds\n", nsec); + + t_start = get_time(); + t_first = t_start; + t_lastto = t_start; + + while (nsec == 0 || (get_time()-t_start) < nsec) { + if (nsigint > 0) break; + + int nc; + while (1) { + nc = read(fd, buf, 4096); + if (nc >= 0 || errno != EINTR) break; + } + if (nc < 0) { + perror("do_txblast->read:"); + break; + } + if (trace) { + prt_time(); + printf("got %4d char: ", nc); + if (nc <= 5) { + int i; + for (i = 0; i < nc; i++) printf(" %2.2x", (u_char)buf[i]); + } else { + printf(" %2.2x %2.2x", (u_char)buf[0], (u_char)buf[1]); + printf(" .. %2.2x %2.2x", (u_char)buf[nc-2], (u_char)buf[nc-1]); + } + printf("\n"); + } + if (nc == 0) { + double t_now = get_time(); + if (t_now-t_lastto > 1.) { + prt_time(); + printf("time out, no data seen\n"); + t_lastto = t_now; + } + } + + for (i = 0; i < nc; i++) { + char dat = buf[i]; + if (xesc) { + if (dat == c_xesc) { + xesc_pend = 1; + continue; + } + if (xesc_pend) { + dat = ~dat; + xesc_pend = 0; + } + } + if (ntot == 0.) { + cval = dat; + prt_time(); + printf("sequence starts with %2.2x\n", (u_char)dat); + t_first = get_time(); + } else { + cval += 1; + if (cval != dat) { + prt_time(); + printf("error: seen %2.2x expect %2.2x after %10.0f char\n", + (u_char)dat, (u_char)cval, ntot); + cval = dat; + } + } + ntot += 1.; + } + } + + t_delta = get_time() - t_first; + if (t_delta > 0. && ntot > 0.) { + prt_time(); + printf("%10.0f char in %7.2f sec -> %8.1f char/sec\n", + ntot, t_delta, ntot/t_delta); + } + + return; +} + +/*--------------------------------------------------------------------------*/ + +void do_rxblast(int fd, int nsec, int nbyt) +{ + char buf[8192]; + double t_start; + double t_delta; + double ntot = 0.; + char cval = 0; + int i; + + prt_time(); + printf("write rxblast input for %d seconds\n", nsec); + + t_start = get_time(); + + while (nsec == 0 || (get_time()-t_start) < nsec) { + if (nsigint > 0) break; + + int nc = 0; + for (i = 0; i < nbyt; i++) { + if (xesc && (cval==c_xon || cval==c_xoff || cval==c_xesc)) { + buf[nc++] = c_xesc; + buf[nc++] = ~cval; + } else { + buf[nc++] = cval; + } + cval += 1; + } + + int ndone = 0; + while (ndone < nc) { + int rc = write(fd, buf+ndone, nc-ndone); + if (rc > 0) { + ndone += rc; + } else { + if (errno != EINTR) { + perror("do_rxblast->write:"); + nsigint += 1; + break; + } + } + } + /*tcdrain(fd);*/ + ntot += nbyt; + } + + t_delta = get_time() - t_start; + if (t_delta > 0. && ntot > 0.) { + prt_time(); + printf("%10.0f char in %7.2f sec -> %8.1f char/sec\n", + ntot, t_delta, ntot/t_delta); + } + + return; +} + +/*--------------------------------------------------------------------------*/ + +void do_loop(int fd, int nsec, int nbyt) +{ + char buftx[8192]; + char bufrx[8192]; + double t_start; + double t_delta; + double ntot = 0.; + double nloop = 0.; + char cval = 0; + int i; + + prt_time(); + printf("write/read loop-back data for %d seconds\n", nsec); + + t_start = get_time(); + + while (nsec == 0 || (get_time()-t_start) < nsec) { + if (nsigint > 0) break; + + int nc = 0; + for (i = 0; i < nbyt; i++) { + if (xesc && (cval==c_xon || cval==c_xoff || cval==c_xesc)) { + buftx[nc++] = c_xesc; + buftx[nc++] = ~cval; + } else { + buftx[nc++] = cval; + } + cval += 1; + } + + int ndone = 0; + while (ndone < nc) { + int rc = write(fd, buftx+ndone, nc-ndone); + if (rc > 0) { + ndone += rc; + } else { + if (errno != EINTR) { + perror("do_loop->write:"); + nsigint += 1; + break; + } + } + } + + if (trace) { + prt_time(); + printf("tx %4d char: ", nc); + for (i = 0; i < nc; i++) { + printf(" %2.2x", (u_char)buftx[i]); + if ((i+1)%16==0 && i+1!=nc) printf("\n "); + } + printf("\n"); + } + + /*tcdrain(fd);*/ + + ndone = 0; + while (ndone < nc) { + int rc = read(fd, bufrx+ndone, nc-ndone); + if (rc > 0) { + ndone += rc; + } else if (rc == 0) { + prt_time(); + printf("loop read time out, expected %4d seen %4d\n", nc, ndone); + nsigint += 1; + break; + } else { + if (errno != EINTR) { + perror("do_loop->read:"); + nsigint += 1; + break; + } + } + } + + if (trace) { + prt_time(); + printf("rx %4d char: ", ndone); + for (i = 0; i < ndone; i++) { + printf(" %2.2x", (u_char)bufrx[i]); + if ((i+1)%16==0 && i+1!=ndone) + printf("\n "); + } + printf("\n"); + } + + for (i = 0; i < nc; i++) { + if (bufrx[i] != buftx[i]) { + prt_time(); + printf("rx-tx mismatch: ind: %4d rx: %2.2x tx: %2.2x\n", + i, (u_char)bufrx[i], (u_char)buftx[i]); + } + } + + ntot += nbyt; + nloop += 1.; + } + + t_delta = get_time() - t_start; + if (t_delta > 0. && nloop > 0. && ntot > 0.) { + prt_time(); + printf("%7.2fs %5.0f l %9.0f c: %5.1f lps %9.1f cps\n", + t_delta, nloop, ntot, nloop/t_delta, ntot/t_delta); + } + + return; +} + +/*--------------------------------------------------------------------------*/ + +void do_sleep(int nms, int pe) +{ + struct timespec req; + struct timespec rem; + int irc; + double t_start; + double t_delta; + + req.tv_sec = nms/1000; + req.tv_nsec = 1000000*(nms%1000); + + t_start = get_time(); + irc = nanosleep(&req, &rem); + if (irc < 0) perror("do_sleep->nanosleep:"); + t_delta = get_time() - t_start; + if (pe) { + prt_time(); + printf("slept for %8.6f seconds\n", t_delta); + } +} + +/*--------------------------------------------------------------------------*/ + +void do_sleep1(double dms) +{ + double t_start; + double t_delta; + + prt_time(); + t_start = get_time(); + mysleep(dms/1000.); + t_delta = get_time() - t_start; + printf("slept for %8.6f seconds\n", t_delta); +} + +/*--------------------------------------------------------------------------*/ + +void prt_time(void) +{ + struct timeval tv; + struct timezone tz; + struct tm tmval; + + gettimeofday(&tv, &tz); + localtime_r(&tv.tv_sec, &tmval); + printf("%04d-%02d-%02d:%02d:%02d:%02d.%06d: ", + tmval.tm_year+1900, tmval.tm_mon+1, tmval.tm_mday, + tmval.tm_hour, tmval.tm_min, tmval.tm_sec, + (int) tv.tv_usec); +} + +/*--------------------------------------------------------------------------*/ + +double get_time(void) +{ + struct timeval tv; + struct timezone tz; + gettimeofday(&tv, &tz); + return (double)tv.tv_sec + 1.e-6 * (double)tv.tv_usec; +} + +/*--------------------------------------------------------------------------*/ + +void mysleep(double dt) +{ + double t_start; + double t_end; + int nloop=0; + + t_start = get_time(); + t_end = t_start + dt; + + while (dt>0. && get_time()>8 & 0x00ffffff) / (256.*256.*256.); + + //printf("rndm() %9.6f\n", rndm); + return rndm; +} + diff --git a/tools/bin/gwstart b/tools/bin/gwstart index 87017d6f..75feaec2 100755 --- a/tools/bin/gwstart +++ b/tools/bin/gwstart @@ -1,7 +1,7 @@ #!/bin/bash -# $Id: gwstart 1336 2022-12-23 19:31:01Z mueller $ +# $Id: gwstart 1369 2023-02-08 18:59:50Z mueller $ # SPDX-License-Identifier: GPL-3.0-or-later -# Copyright 2016-2022 by Walter F.J. Mueller +# Copyright 2016-2023 by Walter F.J. Mueller # # Revision History: # Date Rev Version Comment @@ -24,7 +24,7 @@ done if (( $# == 0 )) ; then echo "Usage: gwstart [opts] ghw-file tcl-commands ..." echo " Options:" - echo " -w enable Tcl command line on stdio" + echo " -nw disable Tcl command line input on stdio" exit 1 fi diff --git a/tools/man/man1/gwstart.1 b/tools/man/man1/gwstart.1 index b27fac02..acc3f4bf 100644 --- a/tools/man/man1/gwstart.1 +++ b/tools/man/man1/gwstart.1 @@ -1,11 +1,11 @@ .\" -*- nroff -*- -.\" $Id: gwstart.1 1336 2022-12-23 19:31:01Z mueller $ +.\" $Id: gwstart.1 1369 2023-02-08 18:59:50Z mueller $ .\" SPDX-License-Identifier: GPL-3.0-or-later -.\" Copyright 2022- by Walter F.J. Mueller +.\" Copyright 2022-2023 by Walter F.J. Mueller .\" .\" ------------------------------------------------------------------ . -.TH GWSTART 1 2022-12-23 "Retro Project" "Retro Project Manual" +.TH GWSTART 1 2023-02-07 "Retro Project" "Retro Project Manual" .\" ------------------------------------------------------------------ .SH NAME gwstart \- gtkwave starter @@ -122,7 +122,7 @@ If not defined, the default '.' is used. . .\" ------------------------------------------------------------------ .SH EXAMPLES - COMMAND -.IP "\fBgwstart -w tb_w11a_c7.ghw\fP" 4 +.IP "\fBgwstart tb_w11a_c7.ghw\fP" 4 Starts \fBgtkwave\fP(1) with Tcl command line input enabled on \fIstdio\fP and reads the file \fItb_w11a_c7.ghw\fP. .