From 93307c746d1c7a8ccf38ced3115374f68d3ab649 Mon Sep 17 00:00:00 2001 From: wfjm Date: Fri, 2 Dec 2022 10:29:03 +0100 Subject: [PATCH] minor edits; add cpu_mmu test - tools/bin/tmuconv: change VFETCH text for MMU(250) and FPP(244) - tools/tcode/cpu_mmu.mac: add test C2.4: mmu abort vs nxm abort - doc/w11a_diff_70_mmu_nxm_prio.md: additional known w11 difference --- doc/w11a_diff_70_mmu_nxm_prio.md | 28 +++++++++++++++++++ doc/w11a_known_differences.md | 1 + tools/bin/tmuconv | 7 ++--- tools/tcode/cpu_mmu.mac | 46 +++++++++++++++++++++++++++++--- 4 files changed, 76 insertions(+), 6 deletions(-) create mode 100644 doc/w11a_diff_70_mmu_nxm_prio.md diff --git a/doc/w11a_diff_70_mmu_nxm_prio.md b/doc/w11a_diff_70_mmu_nxm_prio.md new file mode 100644 index 00000000..c0914690 --- /dev/null +++ b/doc/w11a_diff_70_mmu_nxm_prio.md @@ -0,0 +1,28 @@ +## Known differences between w11a and KB11-C (11/70) + +### MMU aborts have priority over NXM aborts + +Let's assume a case where two address errors are present: +- the MMU rejects the access +- the MMU translated physical address is located in non-existent memory + +Both checks run in parallel in hardware. The MMU logic uses the access control +field and the page length field to check whether access is allowed. +And the physical address is formed from the selected PAR and the resulting +virtual address and compared with the memory size register. + +In the KB11-C processor, the NXM condition is handled before the MMU condition. +This leads to the surprising situation that the access is aborted with a +vector 4 flow rather than a vector 250 flow. + +The w11 logic inspects the MMU condition first and then the NXM condition. +So a case like the one described above is terminated with a vector 250 flow. + +The `ekbee1` diagnostic tests this behavior in test 122. In fact, the code +distinguishes between the KB11-B/C processor and the KB11-E processor +that never made it to market. +In the case of KB11-C, NXM takes precedence over MMU, and and in the case of +KB11-E, MMU takes precedence over NXM. + +In case of an MMU plus NXM double error, the w11 therefore behaves like +a KB11-E and not like a KB11-C. diff --git a/doc/w11a_known_differences.md b/doc/w11a_known_differences.md index 616fad91..b87d4275 100644 --- a/doc/w11a_known_differences.md +++ b/doc/w11a_known_differences.md @@ -13,6 +13,7 @@ The issues of the w11 CPU and systems are listed in a separate document - [`jsr sp` pushes original `sp` value](w11a_diff_70_jsr_sp.md) - [18-bit UNIBUS address space not mapped](w11a_diff_70_unibus_mapping.md) - [MMU traps not suppressed when MMU register accessed](w11a_diff_70_mmu_trap_suppression.md) +- [MMU aborts have priority over NXM aborts](w11a_diff_70_mmu_nxm_prio.md) All points relate to very 11/70 specific behavior, no operating system depends on them, therefore they are considered acceptable implementation diff --git a/tools/bin/tmuconv b/tools/bin/tmuconv index 4b740107..88dc6129 100755 --- a/tools/bin/tmuconv +++ b/tools/bin/tmuconv @@ -1,10 +1,11 @@ #!/usr/bin/perl -w -# $Id: tmuconv 1316 2022-11-18 15:26:40Z mueller $ +# $Id: tmuconv 1324 2022-12-01 11:24:20Z mueller $ # SPDX-License-Identifier: GPL-3.0-or-later # Copyright 2008-2022 by Walter F.J. Mueller # # Revision History: # Date Rev Version Comment +# 2022-12-01 1324 1.1.11 change VFETCH text for MMU(250) and FPP(244) # 2022-11-18 1316 1.1.10 add -t_ru06 and -t_flow # 2022-10-25 1309 1.1.9 rename _gpr -> _gr # 2022-08-22 1283 1.1.8 print ru after em,ib, best for reg from mem cases @@ -773,8 +774,8 @@ sub do_file { $emtyp_str .= " 220 RK11" if ($emlast_addr == 0220); $emtyp_str .= " 224 TM11" if ($emlast_addr == 0224); $emtyp_str .= " 240 PIRQ" if ($emlast_addr == 0240); - $emtyp_str .= " 244 FPP exp" if ($emlast_addr == 0244); - $emtyp_str .= " 250 MMU trap" if ($emlast_addr == 0250); + $emtyp_str .= " 244 FPE" if ($emlast_addr == 0244); + $emtyp_str .= " 250 MMU" if ($emlast_addr == 0250); $emtyp_str .= " 254 RHRP" if ($emlast_addr == 0254); $emtyp_str .= " 260 IIST" if ($emlast_addr == 0260); $emtyp_str .= " 300 DL11-2-TTI" if ($emlast_addr == 0300); diff --git a/tools/tcode/cpu_mmu.mac b/tools/tcode/cpu_mmu.mac index dee0eb3b..468995a4 100644 --- a/tools/tcode/cpu_mmu.mac +++ b/tools/tcode/cpu_mmu.mac @@ -1,10 +1,10 @@ -; $Id: cpu_mmu.mac 1323 2022-12-01 08:00:41Z mueller $ +; $Id: cpu_mmu.mac 1324 2022-12-01 11:24:20Z mueller $ ; SPDX-License-Identifier: GPL-3.0-or-later ; Copyright 2022- by Walter F.J. Mueller ; ; Revision History: ; Date Rev Version Comment -; 2022-11-29 1323 1.0 Initial version +; 2022-12-01 1324 1.0 Initial version ; 2022-07-24 1262 0.1 First draft ; ; Test CPU MMU: all aspects of the MMU @@ -1268,6 +1268,46 @@ tc0203: mov #vhmmua,v..mmu clr v..mmu+2 9999$: iot ; end of test C2.3 ; +; Test C2.4 -- mmu abort vs nxm abort ++++++++++++++++++++++++++++++++ +; On a KB11-C a NXM abort has priority over an MMU abort. An access via +; an acf=7 (reserved) page mapped to non-existing memory is aborted as an +; NXM error (vector 4) and not as an MMU error (vector 250). On a KB11-E +; an MMU error is taken. This behavior is checked in test 122 of ekbee1. +; The w11, and also SimH and e11, follow the KB11-E behavior which is the +; natural and expected behavior. +; + +tc0204: mov cp.los,kipar6 ; map begin of non-existent memory + mov #<127.*md.plf>!md.arw,kipdr6 ; allow access + mov #m3.e22,mmr3 ; enable 22-bit mode + mov #m0.ena,mmr0 ; enable mmu with traps ;! MMU 22 +; +; part1: MMU allows access to NXM memory --> NXM abort --------------- +; + clr cp.err ; clear CPUERR + mov #1000$,v..iit ; set vector 4 handler for NXM abort + clr @#p6p1p2 ; access + halt +1000$: mov #stack,sp ; vector 4 taken + hcmpeq cp.err,#cp.nxm ; NXM error seen + mov #v..iit+2,v..iit ; restore iit handler to catcher +; +; part2: MMU denies access to NXM memory --> MMU abort --------------- +; + mov #<127.*md.plf>!md.an7,kipdr6 ; deny access via acf=7 + clr cp.err ; clear CPUERR + mov #2000$,v..mmu ; set vector 250 handler for MMU abort + clr @#p6p1p2 ; access + halt +2000$: mov #stack,sp ; vector 250 taken + htsteq cp.err ; check CPUERR (no NXM expected) + mov #v..mmu+2,v..mmu ; restore mmu handler to catcher +; + reset ; mmu off ;! MMU off + mov #001400,kipar6 ; reset kipar6 + mov #<127.*md.plf>!md.arw,kipdr6 ; reset kipdr6 +; +9999$: iot ; end of test C2.4 ; ; Section D: mmr2+mmr1+mmr0 register, abort recovery ========================= ; @@ -1922,7 +1962,7 @@ tf0102: mov #154345,@#p6base ; inititialize target ;; END OF ALL TESTS - loop closure ============================================ ; mov tstno,r0 ; hack, for easy monitoring ... - hcmpeq tstno,#22. ; all tests done ? + hcmpeq tstno,#23. ; all tests done ? ; jmp loop ;