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- add sources for C++/Tcl based backend, add directories

Browse Source 
- tools/src/...
  - tools/tcl/...
  - tools/dox
  - tools/make
- add rlink test system
  - rtl/sys_gen/tst_rlink/nexys2/...
This commit is contained in:
Walter F.J. Mueller
2011-04-02 11:08:56 +00:00
parent c3d40ba4b9
commit a20f49fcd5
183 changed files with 17944 additions and 34 deletions
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3
rtl/sys_gen/tst_rlink/nexys2/.cvsignore Normal file
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_impactbatch.log
sys_tst_rlink_n2.ucf
*.dep_ucf_cpp

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rtl/sys_gen/tst_rlink/nexys2/Makefile Normal file
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# $Id: Makefile 351 2010-12-30 21:50:54Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2010-12-29 351 1.0 Initial version
#
VBOM_all = $(wildcard *.vbom)
BIT_all = $(VBOM_all:.vbom=.bit)
#
ISE_BOARD = nexys2
ISE_PATH = xc3s1200e-fg320-4
#
.phony : all clean
#
all : $(BIT_all)
#
clean : ise_clean
rm -f sys_tst_rlink_n2.ucf
#
sys_tst_rlink_n2.mcs : sys_tst_rlink_n2.bit
promgen -w -x xcf04s -p mcs -u 0 sys_tst_rlink_n2
mv sys_tst_rlink_n2.prm sys_tst_rlink_n2_prm.log
mv sys_tst_rlink_n2.cfi sys_tst_rlink_n2_cfi.log
#
#----
#
include $(RETROBASE)/rtl/vlib/Makefile.xflow
include $(RETROBASE)/rtl/vlib/Makefile.ghdl
#
include $(VBOM_all:.vbom=.dep_xst)
include $(VBOM_all:.vbom=.dep_ghdl)
#

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rtl/sys_gen/tst_rlink/nexys2/sys_conf.vhd Normal file
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-- $Id: sys_conf.vhd 351 2010-12-30 21:50:54Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_n2 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 12.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-29 351 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 1; --
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-- derived constants
constant sys_conf_clksys : integer :=
(50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;

19
rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.ucf_cpp Normal file
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## $Id: mueller $
##
## Revision History:
## Date Rev Version Comment
## 2010-12-29 351 1.0 Initial version
##
NET "I_CLK50" TNM_NET = "I_CLK50";
TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20.0 ns HIGH 50 %;
OFFSET = IN 10 ns BEFORE "I_CLK50";
OFFSET = OUT 20 ns AFTER "I_CLK50";
## std board
##
#include "bplib/nexys2/nexys2_pins.ucf"
##
## Pmod B0 - RS232
##
#include "bplib/nexys2/nexys2_pins_pmb0_rs232.ucf"

17
rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vbom Normal file
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# libs
../../../vlib/slvtypes.vhd
../../../vlib/xlib/xlib.vhd
../../../vlib/genlib/genlib.vhd
../../../bplib/s3board/s3boardlib.vbom
../../../bplib/nexys2/nexys2lib.vhd
sys_conf : sys_conf.vhd
# components
[xst,isim]../../../vlib/xlib/dcm_sp_sfs_unisim.vbom
[ghdl]../../../vlib/xlib/dcm_sp_sfs_gsim.vbom
../../../vlib/genlib/clkdivce.vbom
../../../bplib/s3board/s3_rs232_iob_int_ext.vbom
../tst_rlink.vbom
../../../bplib/nexys2/n2_cram_dummy.vbom
# design
sys_tst_rlink_n2.vhd
@ucf_cpp: sys_tst_rlink_n2.ucf

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rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd Normal file
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-- $Id: sys_tst_rlink_n2.vhd 375 2011-04-02 07:56:47Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_rlink_n2 - syn
-- Description: rlink tester design for nexys2
--
-- Dependencies: vlib/xlib/dcm_sp_sfs
-- vlib/genlib/clkdivce
-- bplib/s3board/s3_rs232_iob_int_ext
-- vlib/nexys2/n2_cram_dummy
--
-- Test bench: tb/tb_tst_rlink_n2
--
-- Target Devices: generic
-- Tool versions: xst 12.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-04-02 375 12.1 M53d xc3s1200e-4 688 1572 68 994 t 13.8
-- 2010-12-29 351 12.1 M53d xc3s1200e-4 604 1298 68 851 t 14.7
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-29 351 1.0 Initial version
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.s3boardlib.all;
use work.nexys2lib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_rlink_n2 is -- top level
-- implements nexys2_fusp_aif
port (
I_CLK50 : in slbit; -- 50 MHz clock
O_CLKSYS : out slbit; -- DCM derived system clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- s3 switches
I_BTN : in slv4; -- s3 buttons
O_LED : out slv8; -- s3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end sys_tst_rlink_n2;
architecture syn of sys_tst_rlink_n2 is
signal CLK : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RTS_N : slbit := '0';
signal CTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
DCM : dcm_sp_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => I_CLK50,
CLKFX => CLK,
LOCKED => open
);
O_CLKSYS <= CLK;
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
IOB_RS232 : s3_rs232_iob_int_ext
port map (
CLK => CLK,
SEL => SWI(0),
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
RLTEST : entity work.tst_rlink
generic map (
DEBOUNCE => sys_conf_hio_debounce,
CDINIT => sys_conf_ser2rri_cdinit)
port map (
CLK => CLK,
RESET => RESET,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
SWI => SWI,
BTN => BTN,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
SRAM_PROT : n2_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_FLA_CE_N => O_FLA_CE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
end syn;

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rtl/sys_gen/tst_rlink/nexys2/tb/.cvsignore Normal file
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tb_tst_rlink_n2
tb_tst_rlink_n2_[sft]sim
rlink_cext_fifo_rx
rlink_cext_fifo_tx
rlink_cext_conf
sys_tst_rlink_n2.ucf
*.dep_ucf_cpp

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rtl/sys_gen/tst_rlink/nexys2/tb/Makefile Normal file
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# $Id: Makefile 351 2010-12-30 21:50:54Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2010-12-29 351 1.0 Initial version
#
EXE_all = tb_tst_rlink_n2
#
ISE_PATH = xc3s1200e-fg320-4
#
.phony : all all_ssim all_tsim clean
#
all : $(EXE_all)
all_ssim : $(EXE_all:=_ssim)
all_tsim : $(EXE_all:=_tsim)
#
clean : ise_clean ghdl_clean
rm -f sys_tst_rlink_n2.ucf
#
#-----
#
include $(RETROBASE)/rtl/vlib/Makefile.ghdl
include $(RETROBASE)/rtl/vlib/Makefile.xflow
#
VBOM_all = $(wildcard *.vbom)
#
include $(VBOM_all:.vbom=.dep_xst)
include $(VBOM_all:.vbom=.dep_ghdl)
include $(wildcard *.o.dep_ghdl)
#

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rtl/sys_gen/tst_rlink/nexys2/tb/sys_conf_sim.vhd Normal file
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-- $Id: sys_conf_sim.vhd 351 2010-12-30 21:50:54Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_n2 (for simulation)
--
-- Dependencies: -
-- Tool versions: xst 12.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-29 351 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 1;
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
-- derived constants
constant sys_conf_clksys : integer :=
(50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
end package sys_conf;

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rtl/sys_gen/tst_rlink/nexys2/tb/sys_tst_rlink_n2.ucf_cpp Symbolic link
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../sys_tst_rlink_n2.ucf_cpp

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rtl/sys_gen/tst_rlink/nexys2/tb/tb_tst_rlink_n2.vbom Normal file
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# configure tb_nexsy2_fusp with sys_tst_rlink_n2 target;
# use vhdl configure file (tb_tst_rlink_n2.vhd) to allow
# that all configurations will co-exist in work library
nexys2_aif : ../sys_tst_rlink_n2.vbom
sys_conf = sys_conf_sim.vhd
../../../../bplib/nexys2/tb/tb_nexys2_fusp.vbom
tb_tst_rlink_n2.vhd

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rtl/sys_gen/tst_rlink/nexys2/tb/tb_tst_rlink_n2.vhd Normal file
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-- $Id: tb_tst_rlink_n2.vhd 351 2010-12-30 21:50:54Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_rlink
-- Description: Configuration for tb_tst_rlink_s2 for tb_nexys2_fusp
--
-- Dependencies: sys_tst_rlink_n2
--
-- To test: sys_tst_rlink_n2
--
-- Verified:
-- Date Rev Code ghdl ise Target Comment
-- 2010-12-xx xxx - 0.29 12.1 M53d xc3s1200e u:???
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-29 351 1.0 Initial version
------------------------------------------------------------------------------
configuration tb_tst_rlink_n2 of tb_nexys2_fusp is
for sim
for all : nexys2_fusp_aif
use entity work.sys_tst_rlink_n2;
end for;
end for;
end tb_tst_rlink_n2;

6
rtl/sys_gen/tst_rlink/nexys2/tb/tb_tst_rlink_n2_ssim.vbom Normal file
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# configure for _*sim case
# Note: this tb uses sys_tst_rlink_n2.vbom in local directory
# (not in .. as usual) to allow a tb specific configure !!!
nexys2_aif = sys_tst_rlink_n2_ssim.vhd
tb_tst_rlink_n2.vbom
@top:tb_tst_rlink_n2

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rtl/sys_gen/tst_rlink/nexys2/tb/tbw.dat Normal file
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# $Id: tbw.dat 351 2010-12-30 21:50:54Z mueller $
#
[tb_tst_rlink_n2]
rlink_cext_fifo_rx = <fifo>
rlink_cext_fifo_tx = <fifo>
rlink_cext_conf = <null>

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rtl/sys_gen/tst_rlink/tst_rlink.vbom Normal file
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# libs
../../vlib/slvtypes.vhd
../../vlib/rbus/rblib.vhd
../../vlib/rbus/rbdlib.vhd
../../vlib/rlink/rlinklib.vbom
../../bplib/s3board/s3boardlib.vhd
# components
../../vlib/rlink/rlink_base_serport.vbom
../../vlib/rbus/rbd_tester.vbom
../../vlib/rbus/rbd_bram.vbom
../../vlib/rbus/rbd_rbmon.vbom
../../vlib/rbus/rbd_eyemon.vbom
../../vlib/rbus/rbd_timer.vbom
../../bplib/s3board/s3_humanio_rbus.vbom
../../vlib/rbus/rb_sres_or_4.vbom
# design
tst_rlink.vhd

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rtl/sys_gen/tst_rlink/tst_rlink.vhd Normal file
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-- $Id: tst_rlink.vhd 375 2011-04-02 07:56:47Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tst_rlink - syn
-- Description: tester for rlink
--
-- Dependencies: rlink/rlink_base_serport
-- rbus/rbd_tester
-- rbus/rbd_bram
-- rbus/rbd_rbmon
-- rbus/rbd_eyemon
-- rbus/rbd_timer
-- s3board/s3_humanio_rbus
-- rbus/rb_sres_or_4
--
-- Test bench: nexys2/tb/tb_tst_rlink_n2
--
-- Target Devices: generic
-- Tool versions: xst 12.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-04-02 375 1.0.1 add rbd_eyemon and two timer
-- 2010-12-29 351 1.0 Initial version (inspired by sys_tst_rri)
------------------------------------------------------------------------------
-- Usage of Nexys 2 Switches, Buttons, LEDs:
--
-- SWI(0): 0 -> main board RS232 port - implemented in sys_tst_rlink_*
-- 1 -> Pmod B/top RS232 port /
-- (1:7): no function (only connected to s3_humanio_rbus)
--
-- LED(0): timer 0 busy
-- LED(1): timer 1 busy
-- LED(2:7): no function (only connected to s3_humanio_rbus)
--
-- DSP: RL_SER_MONI.clkdiv (from auto bauder)
-- DP(0): RXSD (inverted to signal activity)
-- DP(1): RTS_N (shows rx back preasure)
-- DP(2): TXSD (inverted to signal activity)
-- DP(3): CTS_N (shows tx back preasure)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.slvtypes.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.s3boardlib.all;
-- ----------------------------------------------------------------------------
entity tst_rlink is -- tester for rlink
generic (
DEBOUNCE : boolean := true;
CDINIT : natural := 15);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CE_USEC : in slbit; -- usec pulse
CE_MSEC : in slbit; -- msec pulse
RXD : in slbit; -- receive data (board view)
TXD : out slbit; -- transmit data (board view)
CTS_N : in slbit; -- rs232 cts_n
RTS_N : out slbit; -- rs232 rts_n
SWI : out slv8; -- switches (for top cntl)
BTN : out slv4; -- buttons (for top cntl)
I_SWI : in slv8; -- s3 switches
I_BTN : in slv4; -- s3 buttons
O_LED : out slv8; -- s3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8 -- 7 segment disp: segments (act.low)
);
end tst_rlink;
architecture syn of tst_rlink is
signal RTS_N_L : slbit := '0';
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal SWI_L : slv8 := (others=>'0');
signal BTN_L : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_TEST : rb_sres_type := rb_sres_init;
signal RB_SRES_BRAM : rb_sres_type := rb_sres_init;
signal RB_SRES_MON : rb_sres_type := rb_sres_init;
signal RB_SRES_EMON : rb_sres_type := rb_sres_init;
signal RB_SRES_TIM0 : rb_sres_type := rb_sres_init;
signal RB_SRES_TIM1 : rb_sres_type := rb_sres_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal RB_SRES_SUM1 : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv3 := (others=>'0');
signal RB_LAM_TEST : slv16 := (others=>'0');
signal TIM0_DONE : slbit := '0';
signal TIM0_BUSY : slbit := '0';
signal TIM1_DONE : slbit := '0';
signal TIM1_BUSY : slbit := '0';
signal RL_MONI : rl_moni_type := rl_moni_init;
signal RL_SER_MONI : rl_ser_moni_type := rl_ser_moni_init;
constant rbaddr_mon : slv8 := "11111100"; -- 111111xx
constant rbaddr_emon : slv8 := "11111000"; -- 111110xx
constant rbaddr_bram : slv8 := "11110100"; -- 111101xx
constant rbaddr_test : slv8 := "11110000"; -- 111100xx
constant rbaddr_tim1 : slv8 := "11100001"; -- 11100001
constant rbaddr_tim0 : slv8 := "11100000"; -- 11100000
constant rbaddr_hio : slv8 := "11000000"; -- 110000xx
begin
RLINK : rlink_base_serport
generic map (
ATOWIDTH => 6, -- 64 cycles access timeout
ITOWIDTH => 6, -- 64 periods max idle timeout
CPREF => c_rlink_cpref,
IFAWIDTH => 5,
OFAWIDTH => 0,
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
RB_ADDR => conv_std_logic_vector(2#11111110#,8),
CDWIDTH => 13,
CDINIT => CDINIT)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N_L,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => RL_MONI,
RL_SER_MONI => RL_SER_MONI
);
RB_LAM(15 downto 2) <= RB_LAM_TEST(15 downto 2);
RB_LAM(1) <= TIM1_DONE;
RB_LAM(0) <= TIM0_DONE;
TEST : rbd_tester
generic map (
RB_ADDR => rbaddr_test)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TEST,
RB_LAM => RB_LAM_TEST,
RB_STAT => RB_STAT
);
BRAM : rbd_bram
generic map (
RB_ADDR => rbaddr_bram)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_BRAM
);
MON : rbd_rbmon
generic map (
RB_ADDR => rbaddr_mon,
AWIDTH => 9)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_MON,
RB_SRES_SUM => RB_SRES
);
EMON : rbd_eyemon
generic map (
RB_ADDR => rbaddr_emon,
RDIV => conv_std_logic_vector(0,8))
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_EMON,
RXSD => RXD,
RXACT => RL_SER_MONI.rxact
);
TIM0 : rbd_timer
generic map (
RB_ADDR => rbaddr_tim0)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TIM0,
DONE => TIM0_DONE,
BUSY => TIM0_BUSY
);
TIM1 : rbd_timer
generic map (
RB_ADDR => rbaddr_tim1)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TIM1,
DONE => TIM1_DONE,
BUSY => TIM1_BUSY
);
HIO : s3_humanio_rbus
generic map (
DEBOUNCE => DEBOUNCE,
RB_ADDR => rbaddr_hio)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI_L,
BTN => BTN_L,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RB_SRES_OR1 : rb_sres_or_4
port map (
RB_SRES_1 => RB_SRES_TEST,
RB_SRES_2 => RB_SRES_BRAM,
RB_SRES_3 => RB_SRES_MON,
RB_SRES_4 => RB_SRES_HIO,
RB_SRES_OR => RB_SRES_SUM1
);
RB_SRES_OR : rb_sres_or_4
port map (
RB_SRES_1 => RB_SRES_SUM1,
RB_SRES_2 => RB_SRES_EMON,
RB_SRES_3 => RB_SRES_TIM0,
RB_SRES_4 => RB_SRES_TIM1,
RB_SRES_OR => RB_SRES
);
DSP_DAT <= RL_SER_MONI.clkdiv;
DSP_DP(0) <= RL_SER_MONI.rxact;
DSP_DP(1) <= RTS_N_L;
DSP_DP(2) <= RL_SER_MONI.txact;
DSP_DP(3) <= CTS_N;
LED(0) <= TIM0_BUSY;
LED(1) <= TIM1_BUSY;
LED(7) <= RL_SER_MONI.abact;
RTS_N <= RTS_N_L;
SWI <= SWI_L;
BTN <= BTN_L;
end syn;

6
rtl/sys_gen/w11a/tb/.cvsignore
View File

@@ -1,6 +1,6 @@
tb_rriext_fifo_rx
tb_rriext_fifo_tx
tb_rriext_conf
rlink_cext_fifo_rx
rlink_cext_fifo_tx
rlink_cext_conf
to_ptp
to_lda
tmu_ofile