From a2264ab4639fc715d3c22db4365d55f6ed308b77 Mon Sep 17 00:00:00 2001 From: "Walter F.J. Mueller" Date: Sun, 29 Jan 2017 14:08:04 +0100 Subject: [PATCH] 23 line interrupt mapper for full system configuration --- doc/CHANGELOG.md | 1 + rtl/ibus/ib_intmap.vhd | 12 +- rtl/ibus/ib_intmap24.vbom | 5 + rtl/ibus/ib_intmap24.vhd | 164 ++++++++++++++++++++++++ rtl/ibus/ibdr_maxisys.vbom | 2 +- rtl/ibus/ibdr_maxisys.vhd | 49 ++++--- rtl/ibus/iblib.vhd | 24 +++- rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd | 3 +- rtl/vlib/slvtypes.vhd | 8 +- 9 files changed, 240 insertions(+), 28 deletions(-) create mode 100644 rtl/ibus/ib_intmap24.vbom create mode 100644 rtl/ibus/ib_intmap24.vhd diff --git a/doc/CHANGELOG.md b/doc/CHANGELOG.md index ed969080..25d4ab92 100644 --- a/doc/CHANGELOG.md +++ b/doc/CHANGELOG.md @@ -17,6 +17,7 @@ software or firmware builds or that the documentation is consistent. The full set of tests is only run for tagged releases._ ### Summary +- 23 line interrupt mapper now for full system configuration - man pages now [available online](http://www.retro11.de/manp/w11/man/cat1/). - add `sysmon_rbus` in `sys_tst_sram_n4` - Auto-dection of Digilent boards with `FT2232HQ` interface for diff --git a/rtl/ibus/ib_intmap.vhd b/rtl/ibus/ib_intmap.vhd index 2cce71ff..e18a9c1d 100644 --- a/rtl/ibus/ib_intmap.vhd +++ b/rtl/ibus/ib_intmap.vhd @@ -1,4 +1,4 @@ --- $Id: ib_intmap.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: ib_intmap.vhd 846 2017-01-29 13:01:59Z mueller $ -- -- Copyright 2006-2011 by Walter F.J. Mueller -- @@ -13,12 +13,18 @@ -- ------------------------------------------------------------------------------ -- Module Name: ib_intmap - syn --- Description: pdp11: external interrupt mapper +-- Description: pdp11: external interrupt mapper (15 line) -- -- Dependencies: - -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 +-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.4; ghdl 0.18-0.33 +-- +-- Synthesized: +-- Date Rev viv Target flop lutl lutm bram slic MHz +-- 2016-05-26 641 2016.4 xc7a100t-1 0 30 0 0 - - +-- 2015-02-22 641 i 14.7 xc6slx16-2 0 20 0 0 9 - +-- -- Revision History: -- Date Rev Version Comment -- 2011-11-18 427 1.2.2 now numeric_std clean diff --git a/rtl/ibus/ib_intmap24.vbom b/rtl/ibus/ib_intmap24.vbom new file mode 100644 index 00000000..e93d0ecf --- /dev/null +++ b/rtl/ibus/ib_intmap24.vbom @@ -0,0 +1,5 @@ +# libs +../vlib/slvtypes.vhd +iblib.vhd +# design +ib_intmap24.vhd diff --git a/rtl/ibus/ib_intmap24.vhd b/rtl/ibus/ib_intmap24.vhd new file mode 100644 index 00000000..4ed41399 --- /dev/null +++ b/rtl/ibus/ib_intmap24.vhd @@ -0,0 +1,164 @@ +-- $Id: ib_intmap24.vhd 846 2017-01-29 13:01:59Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: ib_intmap24 - syn +-- Description: pdp11: external interrupt mapper (23 line) +-- +-- Dependencies: - +-- Test bench: tb/tb_pdp11_core (implicit) +-- Target Devices: generic +-- Tool versions: ise 14.7; viv 2016.4; ghdl 0.33 +-- +-- Synthesized: +-- Date Rev viv Target flop lutl lutm bram slic MHz +-- 2016-05-26 641 2016.4 xc7a100t-1 0 48 0 0 - - +-- 2015-02-22 641 i 14.7 xc6slx16-2 0 38 0 0 20 - +-- +-- Revision History: +-- Date Rev Version Comment +-- 2017-01-28 846 1.0 Initial version (cloned from ib_intmap.vhd) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.iblib.all; + +-- ---------------------------------------------------------------------------- + +entity ib_intmap24 is -- external interrupt mapper (23 line) + generic ( + INTMAP : intmap24_array_type := intmap24_array_init); + port ( + EI_REQ : in slv24_1; -- interrupt request lines + EI_ACKM : in slbit; -- interrupt acknowledge (from master) + EI_ACK : out slv24_1; -- interrupt acknowledge (to requestor) + EI_PRI : out slv3; -- interrupt priority + EI_VECT : out slv9_2 -- interrupt vector + ); +end ib_intmap24; + +architecture syn of ib_intmap24 is + + signal EI_LINE : slv5 := (others=>'0'); -- external interrupt line + + type intp_type is array (23 downto 0) of slv3; + type intv_type is array (23 downto 0) of slv9; + + constant conf_intp : intp_type := + (slv(to_unsigned(INTMAP(23).pri,3)), -- line 23 + slv(to_unsigned(INTMAP(22).pri,3)), -- line 22 + slv(to_unsigned(INTMAP(21).pri,3)), -- line 21 + slv(to_unsigned(INTMAP(20).pri,3)), -- line 20 + slv(to_unsigned(INTMAP(19).pri,3)), -- line 19 + slv(to_unsigned(INTMAP(18).pri,3)), -- line 18 + slv(to_unsigned(INTMAP(17).pri,3)), -- line 17 + slv(to_unsigned(INTMAP(16).pri,3)), -- line 16 + slv(to_unsigned(INTMAP(15).pri,3)), -- line 15 + slv(to_unsigned(INTMAP(14).pri,3)), -- line 14 + slv(to_unsigned(INTMAP(13).pri,3)), -- line 13 + slv(to_unsigned(INTMAP(12).pri,3)), -- line 12 + slv(to_unsigned(INTMAP(11).pri,3)), -- line 11 + slv(to_unsigned(INTMAP(10).pri,3)), -- line 10 + slv(to_unsigned(INTMAP( 9).pri,3)), -- line 9 + slv(to_unsigned(INTMAP( 8).pri,3)), -- line 8 + slv(to_unsigned(INTMAP( 7).pri,3)), -- line 7 + slv(to_unsigned(INTMAP( 6).pri,3)), -- line 6 + slv(to_unsigned(INTMAP( 5).pri,3)), -- line 5 + slv(to_unsigned(INTMAP( 4).pri,3)), -- line 4 + slv(to_unsigned(INTMAP( 3).pri,3)), -- line 3 + slv(to_unsigned(INTMAP( 2).pri,3)), -- line 2 + slv(to_unsigned(INTMAP( 1).pri,3)), -- line 1 + slv(to_unsigned( 0,3)) -- line 0 (always 0 !!) + ); + + constant conf_intv : intv_type := + ( + slv(to_unsigned(INTMAP(23).vec,9)), -- line 23 + slv(to_unsigned(INTMAP(22).vec,9)), -- line 22 + slv(to_unsigned(INTMAP(21).vec,9)), -- line 21 + slv(to_unsigned(INTMAP(20).vec,9)), -- line 20 + slv(to_unsigned(INTMAP(19).vec,9)), -- line 19 + slv(to_unsigned(INTMAP(18).vec,9)), -- line 18 + slv(to_unsigned(INTMAP(17).vec,9)), -- line 17 + slv(to_unsigned(INTMAP(16).vec,9)), -- line 16 + slv(to_unsigned(INTMAP(15).vec,9)), -- line 15 + slv(to_unsigned(INTMAP(14).vec,9)), -- line 14 + slv(to_unsigned(INTMAP(13).vec,9)), -- line 13 + slv(to_unsigned(INTMAP(12).vec,9)), -- line 12 + slv(to_unsigned(INTMAP(11).vec,9)), -- line 11 + slv(to_unsigned(INTMAP(10).vec,9)), -- line 10 + slv(to_unsigned(INTMAP( 9).vec,9)), -- line 9 + slv(to_unsigned(INTMAP( 8).vec,9)), -- line 8 + slv(to_unsigned(INTMAP( 7).vec,9)), -- line 7 + slv(to_unsigned(INTMAP( 6).vec,9)), -- line 6 + slv(to_unsigned(INTMAP( 5).vec,9)), -- line 5 + slv(to_unsigned(INTMAP( 4).vec,9)), -- line 4 + slv(to_unsigned(INTMAP( 3).vec,9)), -- line 3 + slv(to_unsigned(INTMAP( 2).vec,9)), -- line 2 + slv(to_unsigned(INTMAP( 1).vec,9)), -- line 1 + slv(to_unsigned( 0,9)) -- line 0 (always 0 !!) + ); + +-- attribute PRIORITY_EXTRACT : string; +-- attribute PRIORITY_EXTRACT of EI_LINE : signal is "force"; + +begin + + EI_LINE <= "10111" when EI_REQ(23)='1' else + "10110" when EI_REQ(22)='1' else + "10101" when EI_REQ(21)='1' else + "10100" when EI_REQ(20)='1' else + "10011" when EI_REQ(19)='1' else + "10010" when EI_REQ(18)='1' else + "10001" when EI_REQ(17)='1' else + "10000" when EI_REQ(16)='1' else + "01111" when EI_REQ(15)='1' else + "01110" when EI_REQ(14)='1' else + "01101" when EI_REQ(13)='1' else + "01100" when EI_REQ(12)='1' else + "01011" when EI_REQ(11)='1' else + "01010" when EI_REQ(10)='1' else + "01001" when EI_REQ( 9)='1' else + "01000" when EI_REQ( 8)='1' else + "00111" when EI_REQ( 7)='1' else + "00110" when EI_REQ( 6)='1' else + "00101" when EI_REQ( 5)='1' else + "00100" when EI_REQ( 4)='1' else + "00011" when EI_REQ( 3)='1' else + "00010" when EI_REQ( 2)='1' else + "00001" when EI_REQ( 1)='1' else + "00000"; + + proc_intmap : process (EI_LINE, EI_ACKM) + variable iline : integer := 0; + variable iei_ack : slv24 := (others=>'0'); + begin + + iline := to_integer(unsigned(EI_LINE)); + + iei_ack := (others=>'0'); + if EI_ACKM = '1' then + iei_ack(iline) := '1'; + end if; + + EI_ACK <= iei_ack(EI_ACK'range); + EI_PRI <= conf_intp(iline); + EI_VECT <= conf_intv(iline)(8 downto 2); + + end process proc_intmap; + +end syn; diff --git a/rtl/ibus/ibdr_maxisys.vbom b/rtl/ibus/ibdr_maxisys.vbom index 4cf4ffe2..1e1eba9c 100644 --- a/rtl/ibus/ibdr_maxisys.vbom +++ b/rtl/ibus/ibdr_maxisys.vbom @@ -16,6 +16,6 @@ ibdr_lp11.vbom ibdr_sdreg.vbom ib_sres_or_4.vbom ib_sres_or_3.vbom -ib_intmap.vbom +ib_intmap24.vbom # design ibdr_maxisys.vhd diff --git a/rtl/ibus/ibdr_maxisys.vhd b/rtl/ibus/ibdr_maxisys.vhd index 954d6252..50ae755e 100644 --- a/rtl/ibus/ibdr_maxisys.vhd +++ b/rtl/ibus/ibdr_maxisys.vhd @@ -1,6 +1,6 @@ --- $Id: ibdr_maxisys.vhd 683 2015-05-17 21:54:35Z mueller $ +-- $Id: ibdr_maxisys.vhd 846 2017-01-29 13:01:59Z mueller $ -- --- Copyright 2009-2015 by Walter F.J. Mueller +-- Copyright 2009-2017 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -27,13 +27,16 @@ -- ibdr_sdreg -- ib_sres_or_4 -- ib_sres_or_3 --- ib_intmap +-- ib_intmap24 -- Test bench: - -- Target Devices: generic --- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 +-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.4; ghdl 0.18-0.33 -- --- Synthesized (xst): +-- Synthesized: -- Date Rev ise Target flop lutl lutm slic t peri +-- 2017-01-28 846 14.7 131013 xc6slx16-2 668 1562 30 577 s 8.5 intmap24 +-- 2017-01-28 683 viv 2016.4 xc7a100t-1 683 1684 48 - - +-- 2017-01-28 683 14.7 131013 xc6slx16-2 668 1557 30 576 s 8.5 +TM11 -- 2015-04-06 664 14.7 131013 xc6slx16-2 559 1068 29 410 s 9.1 +RHRP -- 2015-01-04 630 14.7 131013 xc6slx16-2 388 761 20 265 s 8.0 +RL11 -- 2014-06-08 560 14.7 131013 xc6slx16-2 311 615 8 216 s 7.1 @@ -42,6 +45,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2017-01-28 846 1.4 use ib_intmap24 -- 2015-05-15 683 1.3.1 add TM11 -- 2015-05-10 678 1.3 start/stop/suspend overhaul -- 2015-04-06 664 1.2.3 rename RPRM to RHRP @@ -116,9 +120,17 @@ end ibdr_maxisys; architecture syn of ibdr_maxisys is - constant conf_intmap : intmap_array_type := - ((8#260#,6), -- line 15 IIST - (8#100#,6), -- line 14 KW11-L + constant conf_intmap24 : intmap24_array_type := + (intmap_init, -- line 23 (unused) + intmap_init, -- line 22 (unused) + intmap_init, -- line 21 (unused) + intmap_init, -- line 20 (unused) + intmap_init, -- line 19 (unused) + intmap_init, -- line 18 (unused) + (8#104#,7), -- line 17 KW11-P + (8#260#,6), -- line 16 IIST + (8#100#,6), -- line 15 KW11-L + (8#120#,5), -- line 14 DENUA (8#254#,5), -- line 13 RHRP (8#160#,5), -- line 12 RL11 (8#220#,5), -- line 11 RK11 @@ -166,8 +178,8 @@ architecture syn of ibdr_maxisys is signal IB_SRES_3 : ib_sres_type := ib_sres_init; signal IB_SRES_4 : ib_sres_type := ib_sres_init; - signal EI_REQ : slv16_1 := (others=>'0'); - signal EI_ACK : slv16_1 := (others=>'0'); + signal EI_REQ : slv24_1 := (others=>'0'); + signal EI_ACK : slv24_1 := (others=>'0'); signal EI_REQ_IIST : slbit := '0'; signal EI_REQ_KW11P : slbit := '0'; @@ -429,9 +441,9 @@ begin IB_SRES_OR => IB_SRES ); - INTMAP : ib_intmap + INTMAP : ib_intmap24 generic map ( - INTMAP => conf_intmap) + INTMAP => conf_intmap24) port map ( EI_REQ => EI_REQ, EI_ACKM => EI_ACKM, @@ -440,8 +452,11 @@ begin EI_VECT => EI_VECT ); - EI_REQ(15) <= EI_REQ_IIST; - EI_REQ(14) <= EI_REQ_KW11L; + EI_REQ(23 downto 18) <= (others=>'0'); + EI_REQ(17) <= EI_REQ_KW11P; + EI_REQ(16) <= EI_REQ_IIST; + EI_REQ(15) <= EI_REQ_KW11L; + EI_REQ(14) <= EI_REQ_DEUNA; EI_REQ(13) <= EI_REQ_RHRP; EI_REQ(12) <= EI_REQ_RL11; EI_REQ(11) <= EI_REQ_RK11; @@ -456,8 +471,10 @@ begin EI_REQ( 2) <= EI_REQ_PC11PTP; EI_REQ( 1) <= EI_REQ_LP11; - EI_ACK_IIST <= EI_ACK(15); - EI_ACK_KW11L <= EI_ACK(14); + EI_ACK_KW11P <= EI_ACK(17); + EI_ACK_IIST <= EI_ACK(16); + EI_ACK_KW11L <= EI_ACK(15); + EI_ACK_DEUNA <= EI_ACK(14); EI_ACK_RHRP <= EI_ACK(13); EI_ACK_RL11 <= EI_ACK(12); EI_ACK_RK11 <= EI_ACK(11); diff --git a/rtl/ibus/iblib.vhd b/rtl/ibus/iblib.vhd index 3544be8c..0096705a 100644 --- a/rtl/ibus/iblib.vhd +++ b/rtl/ibus/iblib.vhd @@ -1,6 +1,6 @@ --- $Id: iblib.vhd 770 2016-05-28 14:15:00Z mueller $ +-- $Id: iblib.vhd 846 2017-01-29 13:01:59Z mueller $ -- --- Copyright 2008-2016 by Walter F.J. Mueller +-- Copyright 2008-2017 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,9 +16,10 @@ -- Description: Definitions for ibus interface and bus entities -- -- Dependencies: - --- Tool versions: ise 8.1-14.7; viv 2014.4-2016.1; ghdl 0.18-0.33 +-- Tool versions: ise 8.1-14.7; viv 2014.4-2016.4; ghdl 0.18-0.33 -- Revision History: -- Date Rev Version Comment +-- 2017-01-28 846 2.2 add ib_intmap24 -- 2016-05-28 770 2.1.1 use type natural for vec,pri fields of intmap_type -- 2015-04-24 668 2.1 add ibd_ibmon -- 2010-10-23 335 2.0.1 add ib_sel; add ib_sres_or_mon @@ -124,7 +125,7 @@ constant intmap_init : intmap_type := (0,0); type intmap_array_type is array (15 downto 0) of intmap_type; constant intmap_array_init : intmap_array_type := (others=>intmap_init); -component ib_intmap is -- external interrupt mapper +component ib_intmap is -- external interrupt mapper (15 line) generic ( INTMAP : intmap_array_type := intmap_array_init); port ( @@ -136,6 +137,21 @@ component ib_intmap is -- external interrupt mapper ); end component; +type intmap24_array_type is array (23 downto 0) of intmap_type; +constant intmap24_array_init : intmap24_array_type := (others=>intmap_init); + +component ib_intmap24 is -- external interrupt mapper (23 line) + generic ( + INTMAP : intmap24_array_type := intmap24_array_init); + port ( + EI_REQ : in slv24_1; -- interrupt request lines + EI_ACKM : in slbit; -- interrupt acknowledge (from master) + EI_ACK : out slv24_1; -- interrupt acknowledge (to requestor) + EI_PRI : out slv3; -- interrupt priority + EI_VECT : out slv9_2 -- interrupt vector + ); +end component; + component ibd_ibmon is -- ibus dev: ibus monitor generic ( IB_ADDR : slv16 := slv(to_unsigned(8#160000#,16)); diff --git a/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd b/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd index 2f8c8601..e8799371 100644 --- a/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd +++ b/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd @@ -1,4 +1,4 @@ --- $Id: sys_w11a_n3.vhd 791 2016-07-21 22:01:10Z mueller $ +-- $Id: sys_w11a_n3.vhd 846 2017-01-29 13:01:59Z mueller $ -- -- Copyright 2011-2016 by Walter F.J. Mueller -- @@ -34,6 +34,7 @@ -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri +-- 2017-01-28 846 14.7 131013 xc6slx16-2 2680 5208 177 1843 ok: 80% -- 2015-07-05 698 14.7 131013 xc6slx16-2 2500 4852 161 1782 ok: +dmhbpt 78% -- 2015-07-05 697 14.7 131013 xc6slx16-2 2428 4786 161 1756 ok: +dmcmon 77% -- 2015-06-27 695 14.7 131013 xc6slx16-2 2281 4638 161 1714 ok: +dmscnt 75% diff --git a/rtl/vlib/slvtypes.vhd b/rtl/vlib/slvtypes.vhd index 5021954f..641e76e5 100644 --- a/rtl/vlib/slvtypes.vhd +++ b/rtl/vlib/slvtypes.vhd @@ -1,6 +1,6 @@ --- $Id: slvtypes.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: slvtypes.vhd 846 2017-01-29 13:01:59Z mueller $ -- --- Copyright 2007-2008 by Walter F.J. Mueller +-- Copyright 2007-2017 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -20,9 +20,10 @@ -- commonly used (n downto 0) vectors -- -- Dependencies: - --- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31 +-- Tool versions: ise 8.1-14.7; viv 2014.4-2016.4; ghdl 0.18-0.33 -- Revision History: -- Date Rev Version Comment +-- 2017-01-28 846 1.0.5 add slv24_1 -- 2008-08-24 162 1.0.4 add slv60 and 64 -- 2008-08-22 161 1.0.3 add slvnn_m subtypes from pdp11 package -- 2008-03-24 129 1.0.2 add slv31 @@ -75,5 +76,6 @@ package slvtypes is subtype slv16_1 is std_logic_vector(15 downto 1); -- 16 bit word, 1 lsb drop subtype slv18_1 is std_logic_vector(17 downto 1); -- 18 bit word, 1 lsb drop subtype slv22_1 is std_logic_vector(21 downto 1); -- 22 bit word, 1 lsb drop + subtype slv24_1 is std_logic_vector(23 downto 1); -- 24 bit word, 1 lsb drop end package slvtypes;