github.com/wfjm.w11
1
0
Fork 0
mirror of https://github.com/wfjm/w11.git synced 2026-01-28 05:07:39 +00:00
Code Issues Releases Wiki Activity

add tools/xxdp; tcode comments [skip ci]

Browse Source
This commit is contained in:
wfjm
2022-12-10 08:40:42 +01:00
parent e257162109
commit a442a225e5
30 changed files with 1052 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

59
tools/tcode/cpu_basics.mac
View File

@@ -19,6 +19,19 @@
.include |lib/defs_kwl.mac|
;
; Section A: ccops + flow control bxx, sob, jmp, jsr, rts, mark ==============
; A1 ccop + bbx
; A1.1 ccop + psw
; A1.2 ccop + bxx
; A2 sob
; A3 jmp
; A3.1 jmp + dsta
; A3.2 jmp + cc
; A4 jsr + rts
; A4.1 jsr + dsta
; A4.2 jsr + cc
; A4.3 jsr r0-r5
; A4.4 jsr sp and rts sp
; A5 mark
;
; Test A1: ccop + bxx +++++++++++++++++++++++++++++++++++++++++++++++++++++++
; This sub-section verifies
@@ -1028,6 +1041,20 @@ ta0501: mov #123456,r5 ; token
9999$: iot ; end of test A5.1
;
; Section B: unary instructions (word) =======================================
; B1 inc
; B2 dec
; B3 com
; B4 neg
; B5 adc
; B6 sbc
; B7 tst
; B8 ror
; B9 rol
; B10 asr
; B11 asl
; B12 clr
; B13 sxt
; B14 swab
;
jmp tb0101
;
@@ -1634,6 +1661,13 @@ tb1401: clr cp.psw
9999$: iot ; end of test B14.1
;
; Section C: binary instructions (word) ======================================
; C1 add
; C2 sub
; C3 bic
; C4 bis
; C5 cmp
; C6 bit
; C7 mov
;
jmp tc0101
;
@@ -2114,6 +2148,18 @@ tc0701: clr cp.psw
9999$: iot ; end of test C7.1
;
; Section D: unary instructions (byte) =======================================
; D1 incb
; D2 decb
; D3 comb
; D4 negb
; D5 adcb
; D6 sbcb
; D7 tstb
; D8 rorb
; D9 rolb
; D10 asrb
; D11 aslb
; D12 clrb
;
jmp td0101
;
@@ -2651,6 +2697,11 @@ td1201: clr cp.psw
;
;
; Section E: binary instructions (byte) ======================================
; E1 bicb
; E2 bisb
; E3 cmpb
; E4 bitb
; E5 movb
;
jmp te0101
;
@@ -2914,6 +2965,14 @@ te0501: clr cp.psw
9999$: iot ; end of test E5.1
;
; Section F: miscellaneous (spl, reset) ======================================
; F1 spl
; F1.1 spl in kernel mode
; F1.2 spl in supervisor and user mode
; F2 reset
; F2.1 reset in kernel mode
; F2.2 reset in supervisor and user mode
; F2.3 reset settling time
; F3 trap instructions: bpt,iot,emt,trap
;
; Test F1: spl ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; This sub-section verifies

57
tools/tcode/cpu_details.mac
View File

@@ -44,6 +44,52 @@
p6base = <6*20000> ; page 6
;
; Section A: CPU registers ===================================================
; A1 PIRQ
; A1.1 PIRQ + spl
; A1.2 PIRQ and immediate interrupt
; A2 CPUERR
; A2.1 CPUERR cp.hlt
; A2.2 CPUERR cp.odd
; A2.3 CPUERR cp.nxm
; A2.4 CPUERR cp.iot
; A2.5 CPUERR cp.ysv
; A2.6 CPUERR cp.rsv
; A2.7 CPUERR cp.odd + stack error
; A2.8 CPUERR cp.nxm + stack error
; A2.9 CPUERR cp.ito + stack error
; A2.10 CPUERR mmu abort + stack error
; A3 STKLIM + stack traps and aborts
; A3.1 STKLIM write/read test
; A3.2 yellow trap + red abort boundary
; part 1: sequence of yellow traps and a final red stack abort
; part 2: check that red zone does not have yellow islands
; part 3: check red zone PSW protection
; A3.3 stack trap conditions
; part 1: test instructions that should trap
; part 2: test instructions that should not trap
; part 3: test that interrupt (from PIRQ) vector push traps
; A3.4 red stack abort conditions
; A4 PSW + tbit traps
; A4.1 PSW direct write/read test
; part 1: all bits except register set (cp.ars)
; part 2: PSW(11) - register set
; part 3: PSW(cm) and stack registers
; A4.2 PSW write/read via RTI/RTT
; part 1: from cm=0,rset=0: set cm=11 and rset=1 (fine!)
; part 2: from cm=s,rset=1 mode: set cm=0 and rset=0 (fail!)
; part 3: from cm=s,rset=0 mode: set cm=u and rset=1 (fine!)
; part 4: from cm=u,rset=1 mode: set cm=0 and rset=0 (fail!)
; A4.3 RTI/RTT tbit basics
; part 1: tbit after RTI
; part 2: tbit after RTT
; A4.4 Test A4.4 -- tbit trace tests
; part 1: simple instruction sequence
; part 2: tracing of trap instructions (EMT tested)
; part 3: tbit vs interrupt precedence (via PIRQ)
; part 4: traced WAIT and tbit
; part 5: WAIT and SPL in user mode
; part 6: tbit trap after continuation over s_idle
; part 7: no tbit trap after an abort
;
; Test A1: PIRQ +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; This sub-section verifies operation of PIRQ register
@@ -1246,6 +1292,13 @@ ta0404: mov #vhtbpt,v..bpt ; BPT handler
9999$: iot ; end of test A4.4
;
; Section B: Stress tests ====================================================
; B1 address mode torture tests
; B1.1 src-dst update hazards with (r0)+,(r0)
; B1.2 (pc)+ as destination
; B1.3 pc as destination in clr, mov, and add
; B2 pipeline torture tests
; B2.1 self-modifying code, use (pc), -(pc)
; B2.2 self-modifying code, use (pc) case 2
;
; Test B1: address mode torture tests +++++++++++++++++++++++++++++++++++++++
; This sub-section tests peculiar address node usage
@@ -1402,6 +1455,10 @@ tb0202: mov #2,r5
9999$: iot ; end of test B2.2
;
; Section C: 11/70 specifics =================================================
; C1 Implementation differences
; C1.1 Register used as source and changed in dst flow
; C1.2 PC used as source
; C1.3 Registers accessible via 177700-1777717
;
; Test C1: Implementation differences +++++++++++++++++++++++++++++++++++++++
; This sub-section verifies that w11 shows 11/70 behavior in cases

13
tools/tcode/cpu_eis.mac
View File

@@ -15,6 +15,10 @@
; This section verifies
; x xxx xxx xxx xxx xxx NZVC Instruction / Remark
; 0 111 001 rrr sss sss NZVC DIV
;
; A1.1 div test basics
; A1.2 div test systematic
; A1.3 div odd register
;
jmp ta0101
@@ -328,6 +332,9 @@ ta0103: mov #1000$,r4 ; setup data pointer
; x xxx xxx xxx xxx xxx NZVC Instruction / Remark
; 0 111 000 rrr sss sss NZ0C MUL
;
; B1.1 mul even and odd
; B1.2 mul+div (and adc,adc,sxt)
;
; Test B1.1 -- mul even and odd ++++++++++++++++++++++++++++++++++++++
; check that mul works with even and odd destination register
;
@@ -510,6 +517,9 @@ tc0101: mov #1000$,r4 ; setup data pointer
; x xxx xxx xxx xxx xxx NZVC Instruction / Remark
; 0 111 011 rrr sss sss NZVC ASHC
;
; D1.1 ashc even register
; D1.2 ashc odd register
;
; Test D1.1 -- ashc even register +++++++++++++++++++++++++++++++++++
;
td0101: mov #1000$,r4 ; setup data pointer
@@ -658,6 +668,9 @@ td0102: mov #1000$,r4 ; setup data pointer
; x xxx xxx xxx xxx xxx NZVC Instruction / Remark
; 0 111 100 rrr ddd ddd NZ0- XOR
;
; E1.1 xor znvc=0
; E1.2 xor znvc=1
;
; Test E1.1 -- xor znvc=0 ++++++++++++++++++++++++++++++++++++++++++++
; check xor with all ccs cleared; memory destination
;

41
tools/tcode/cpu_mmu.mac
View File

@@ -68,6 +68,8 @@
p7base = <7*20000> ; page 7
;
; Section A: pdr,par registers ===============================================
; A1.1 test that pdr/par are 16 bit write/readable
; A1.2 set up MMU default configuration
;
; Test A1: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
@@ -198,6 +200,19 @@ ta0102:
; Section B: mmr0,mmr3 registers, mapping, instructions ======================
; Test whether address mapping works (traps and aborts avoided)
;
; B1 mmr0, mmr3 write/read and clear by RESET
; B1.1 test mmr0 write/read
; B1.2 test mmr3 write/read
; B2 kernel mode mapping
; B2.1 test 1-to-1 kernel mode mapping
; B2.2 test variable kernel mode mapping
; B3 user and supervisor mode
; B3.1 run code in user/supervisor mode
; B3.2 run code in user mode with D space enabled
; B4 invalid cpu mode 10
; B4.1 check that cmode=10 causes abort
; B4.2 check MFPI/MTPI SP response for pmode=10
;
; Test B1: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Test mmr0, mmr3 write/read and clear by RESET
;
@@ -683,6 +698,21 @@ tb0402: tstb systyp ; skip if not on w11
9999$: iot
;
; Section C: mmr1+mmr0 register, aborts ======================================
; C1 MMU response in mmr1 after a write to that fakes an abort
; C2 MMU abort response in mmr0 and mmr1
; C2.1 test unary/binary instructions
; part 1: unary instructions; test acf to mmr0(15:13) mapping
; part 2: unary instructions; fail in second access
; part 3: binary instructions; fail in src field
; part 4: binary instructions; fail in dst field
; part 5: multiple abort flags
; C2.2 test MFPI,MFPD,MTPI,MFPD dst aborts
; part 1: MFPI, MFPD
; part 2: MTPD, MTPI
; C2.3 test aborts in implied push/pop
; part 1: JSR, MFPI, MFPD (push)
; part 2: RTS, MTPI, MTPD (pop)
; C2.4 mmu abort vs nxm abort
;
; Test C1: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Verify MMU response in mmr1 after a write to that fakes an abort
@@ -1164,7 +1194,7 @@ tc0202: mov #vhmmua,v..mmu
clr v..mmu+2
9999$: iot ; end of test C2.2
;
; Test C2.3 -- test aborts in implied push/pop; ++++++++++++++++++++++
; Test C2.3 -- test aborts in implied push/pop +++++++++++++++++++++++
; jsr,mfp* have an implied push; rts,mft* have an implied pop
; This must be tested in supervisor mode to separate 'stack under test'
; from the kernel stack used in MMU 250 vector handling
@@ -1439,6 +1469,13 @@ td0101:
9999$: iot ; end of test D1.1
;
; Section E: traps and pdr aia and aiw bits ==================================
; E1 basic MMU trap and PDR aia/aiw logic
; E1.1 test m0.trp, pdr aia/aiw transitions
; E1.2 systematic abort/trap testing for all valid afc
; E1.3 test trap request logic (trap on non-last access)
; E1.4 test trap request after prefetched instructions
; E2 MMU trap priority behavior
; E2.1 mmu trap + interrupt priority
;
; Test E1: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Check basic MMU trap and PDR aia/aiw logic
@@ -1850,6 +1887,8 @@ te0201: mov #m0.ent!m0.ena,mmr0 ; enable mmu with traps ;! MMU 18
clr v..pir+2
;
; Section F: miscellaneous ===================================================
; F1.1 test D-to-I mapping for (PC) address modes I
; F1.2 test D-to-I mapping for (PC) address modes II
;
; Test F1: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;

2
tools/tcode/cpu_selftest.mac
View File

@@ -12,6 +12,8 @@
.include |lib/tcode_std_base.mac|
;
; Section A: Self-Test codes
; A1 11/34 self test
; A2 11/70 self test
;
; Test A1 -- 11/34 self test ++++++++++++++++++++++++++++++++++++++++++
; adopted from tb_pdp11core_stim.dat code 34