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Code Issues Releases Wiki Activity

- interim release w11a_V0.57 (untagged)

Browse Source 
- new C++ and Tcl based backend server supports now RK11 handling
- w11a systems operate with rlink over USB on nexsy2 and nexsy3 boards.
  See w11a_os_guide.txt for details
This commit is contained in:
Walter F.J. Mueller
2013-04-27 14:21:46 +00:00
parent 99de9893cb
commit b06cbef00a
105 changed files with 5202 additions and 593 deletions
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25
rtl/bplib/fx2rlink/Makefile Normal file
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# $Id: $
#
# Revision History:
# Date Rev Version Comment
# 2013-04-20 509 1.0 Initial version (cloned..)
#
VBOM_all = $(wildcard *.vbom)
NGC_all = $(VBOM_all:.vbom=.ngc)
#
include $(RETROBASE)/rtl/make/xflow_default_nexys2.mk
#
.PHONY : all clean
#
all : $(NGC_all)
#
clean : ise_clean
#
#----
#
include $(RETROBASE)/rtl/make/generic_xflow.mk
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_xst)
endif
#

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rtl/bplib/fx2rlink/fx2rlinklib.vbom Normal file
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# libs
../../vlib/slvtypes.vhd
../../vlib/rbus/rblib.vhd
../../vlib/rlink/rlinklib.vhd
../../vlib/serport/serportlib.vbom
../fx2lib/fx2lib.vhd
fx2rlinklib.vhd

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rtl/bplib/fx2rlink/fx2rlinklib.vhd Normal file
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-- $Id: $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: fx2rlinklib
-- Description: Definitions for rlink + fx2 interface combos
--
-- Dependencies: -
-- Tool versions: xst 13.3; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-04-20 509 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
use work.rlinklib.all;
use work.serportlib.all;
use work.fx2lib.all;
package fx2rlinklib is
--
-- core + fx2 interface combo
--
component rlink_sp1c_fx2 is -- rlink_core8+serport_1clk+fx2_ic combo
generic (
ATOWIDTH : positive := 5; -- access timeout counter width
ITOWIDTH : positive := 6; -- idle timeout counter width
CPREF : slv4 := c_rlink_cpref; -- comma prefix
IFAWIDTH : natural := 5; -- ser input fifo addr width (0=none)
OFAWIDTH : natural := 5; -- ser output fifo addr width (0=none)
PETOWIDTH : positive := 10; -- fx2 packet end time-out counter width
CCWIDTH : positive := 5; -- fx2 chunk counter width
ENAPIN_RLMON : integer := sbcntl_sbf_rlmon; -- SB_CNTL for rlmon (-1=none)
ENAPIN_RBMON : integer := sbcntl_sbf_rbmon; -- SB_CNTL for rbmon (-1=none)
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15); -- clk divider initial/reset setting
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable
CE_MSEC : in slbit; -- 1 msec clock enable
CE_INT : in slbit := '0'; -- rri ito time unit clock enable
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
ENAFX2 : in slbit; -- enable fx2 usage
RXSD : in slbit; -- receive serial data (board view)
TXSD : out slbit; -- transmit serial data (board view)
CTS_N : in slbit := '0'; -- clear to send (act.low, board view)
RTS_N : out slbit; -- request to send (act.low, board view)
RB_MREQ : out rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv3; -- rbus: status flags
RL_MONI : out rl_moni_type; -- rlink_core: monitor port
RLB_MONI : out rlb_moni_type; -- rlink 8b: monitor port
SER_MONI : out serport_moni_type; -- ser: monitor port
FX2_MONI : out fx2ctl_moni_type; -- fx2: monitor port
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end component;
component ioleds_sp1c_fx2 -- io activity leds for rlink_sp1c_fx2
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable
RESET : in slbit; -- reset
ENAFX2 : in slbit; -- enable fx2 usage
RB_SRES : in rb_sres_type; -- rbus: response
RLB_MONI : in rlb_moni_type; -- rlink 8b: monitor port
SER_MONI : in serport_moni_type; -- ser: monitor port
IOLEDS : out slv4 -- 4 bit IO monitor (e.g. for DSP_DP)
);
end component;
end package fx2rlinklib;

10
rtl/bplib/fx2rlink/ioleds_sp1c_fx2.vbom Normal file
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# libs
../../vlib/slvtypes.vhd
../../vlib/genlib/genlib.vhd
../../vlib/rbus/rblib.vhd
../../vlib/rlink/rlinklib.vbom
../../vlib/serport/serportlib.vbom
# components
../../vlib/genlib/led_pulse_stretch.vbom
# design
ioleds_sp1c_fx2.vhd

115
rtl/bplib/fx2rlink/ioleds_sp1c_fx2.vhd Normal file
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-- $Id: ioleds_sp1c_fx2.vhd 509 2013-04-21 20:46:20Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ioleds_sp1c_fx2 - syn
-- Description: io activity leds for rlink+serport_1clk+fx2_ic combo
--
-- Dependencies:
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-04-21 509 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.genlib.all;
use work.rblib.all;
use work.rlinklib.all;
use work.serportlib.all;
entity ioleds_sp1c_fx2 is -- io activity leds for rlink_sp1c_fx2
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable
RESET : in slbit; -- reset
ENAFX2 : in slbit; -- enable fx2 usage
RB_SRES : in rb_sres_type; -- rbus: response
RLB_MONI : in rlb_moni_type; -- rlink 8b: monitor port
SER_MONI : in serport_moni_type; -- ser: monitor port
IOLEDS : out slv4 -- 4 bit IO monitor (e.g. for DSP_DP)
);
end entity ioleds_sp1c_fx2;
architecture syn of ioleds_sp1c_fx2 is
signal R_LEDDIV : slv6 := (others=>'0'); -- clock divider for LED pulses
signal R_LEDCE : slbit := '0'; -- ce every 64 usec
signal TXENA_LED : slbit := '0';
signal RXVAL_LED : slbit := '0';
begin
RXVAL_PSTR : led_pulse_stretch
port map (
CLK => CLK,
CE_INT => R_LEDCE,
RESET => '0',
DIN => RLB_MONI.rxval,
POUT => RXVAL_LED
);
TXENA_PSTR : led_pulse_stretch
port map (
CLK => CLK,
CE_INT => R_LEDCE,
RESET => '0',
DIN => RLB_MONI.txena,
POUT => TXENA_LED
);
proc_leddiv: process (CLK)
begin
if rising_edge(CLK) then
R_LEDCE <= '0';
if CE_USEC = '1' then
R_LEDDIV <= slv(unsigned(R_LEDDIV) - 1);
if unsigned(R_LEDDIV) = 0 then
R_LEDCE <= '1';
end if;
end if;
end if;
end process proc_leddiv;
proc_ledmux : process (ENAFX2, SER_MONI, RLB_MONI, RB_SRES,
TXENA_LED, RXVAL_LED)
begin
if ENAFX2 = '0' then
IOLEDS(3) <= not SER_MONI.txok;
IOLEDS(2) <= SER_MONI.txact;
IOLEDS(1) <= not SER_MONI.rxok;
IOLEDS(0) <= SER_MONI.rxact;
else
IOLEDS(3) <= RB_SRES.busy;
IOLEDS(2) <= RLB_MONI.txbusy;
IOLEDS(1) <= TXENA_LED;
IOLEDS(0) <= RXVAL_LED;
end if;
end process proc_ledmux;
end syn;

13
rtl/bplib/fx2rlink/rlink_sp1c_fx2.vbom Normal file
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@@ -0,0 +1,13 @@
# libs
../../vlib/slvtypes.vhd
../../vlib/rbus/rblib.vhd
../../vlib/rlink/rlinklib.vbom
../../vlib/serport/serportlib.vbom
../fx2lib/fx2lib.vhd
# components
../../vlib/rlink/rlink_core8.vbom
../../vlib/serport/serport_1clock.vbom
../../vlib/rlink/rlink_rlbmux.vbom
../fx2lib/fx2_2fifoctl_ic.vbom
# design
rlink_sp1c_fx2.vhd

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rtl/bplib/fx2rlink/rlink_sp1c_fx2.vhd Normal file
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@@ -0,0 +1,227 @@
-- $Id: $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rlink_sp1c_fx2 - syn
-- Description: rlink_core8 + serport_1clock + fx2 combo
--
-- Dependencies: rlinklib/rlink_core8
-- serport/serport_1clock
-- rlinklib/rlink_rlbmux
-- fx2lib/fx2_2fifoctl_ic
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri ifa ofa
-- 2013-04-20 509 13.3 O76d xc3s1200e-4 441 903 128 637 s 8.7 - -
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-04-20 509 1.0 Initial version (derived from rlink_sp1c)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
use work.rlinklib.all;
use work.serportlib.all;
use work.fx2lib.all;
entity rlink_sp1c_fx2 is -- rlink_core8+serport_1clk+fx2_ic combo
generic (
ATOWIDTH : positive := 5; -- access timeout counter width
ITOWIDTH : positive := 6; -- idle timeout counter width
CPREF : slv4 := c_rlink_cpref; -- comma prefix
IFAWIDTH : natural := 5; -- ser input fifo addr width (0=none)
OFAWIDTH : natural := 5; -- ser output fifo addr width (0=none)
PETOWIDTH : positive := 10; -- fx2 packet end time-out counter width
CCWIDTH : positive := 5; -- fx2 chunk counter width
ENAPIN_RLMON : integer := sbcntl_sbf_rlmon; -- SB_CNTL for rlmon (-1=none)
ENAPIN_RBMON : integer := sbcntl_sbf_rbmon; -- SB_CNTL for rbmon (-1=none)
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15); -- clk divider initial/reset setting
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable
CE_MSEC : in slbit; -- 1 msec clock enable
CE_INT : in slbit := '0'; -- rri ito time unit clock enable
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
ENAFX2 : in slbit; -- enable fx2 usage
RXSD : in slbit; -- receive serial data (board view)
TXSD : out slbit; -- transmit serial data (board view)
CTS_N : in slbit := '0'; -- clear to send (act.low, board view)
RTS_N : out slbit; -- request to send (act.low, board view)
RB_MREQ : out rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv3; -- rbus: status flags
RL_MONI : out rl_moni_type; -- rlink_core: monitor port
RLB_MONI : out rlb_moni_type; -- rlink 8b: monitor port
SER_MONI : out serport_moni_type; -- ser: monitor port
FX2_MONI : out fx2ctl_moni_type; -- fx2: monitor port
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end entity rlink_sp1c_fx2;
architecture syn of rlink_sp1c_fx2 is
signal RLB_DI : slv8 := (others=>'0');
signal RLB_ENA : slbit := '0';
signal RLB_BUSY : slbit := '0';
signal RLB_DO : slv8 := (others=>'0');
signal RLB_VAL : slbit := '0';
signal RLB_HOLD : slbit := '0';
signal SER_RXDATA : slv8 := (others=>'0');
signal SER_RXVAL : slbit := '0';
signal SER_RXHOLD : slbit := '0';
signal SER_TXDATA : slv8 := (others=>'0');
signal SER_TXENA : slbit := '0';
signal SER_TXBUSY : slbit := '0';
signal FX2_RXDATA : slv8 := (others=>'0');
signal FX2_RXVAL : slbit := '0';
signal FX2_RXHOLD : slbit := '0';
signal FX2_RXAEMPTY : slbit := '0';
signal FX2_TXDATA : slv8 := (others=>'0');
signal FX2_TXENA : slbit := '0';
signal FX2_TXBUSY : slbit := '0';
signal FX2_TXAFULL : slbit := '0';
begin
CORE : rlink_core8
generic map (
ATOWIDTH => ATOWIDTH,
ITOWIDTH => ITOWIDTH,
CPREF => CPREF,
ENAPIN_RLMON => ENAPIN_RLMON,
ENAPIN_RBMON => ENAPIN_RBMON)
port map (
CLK => CLK,
CE_INT => CE_INT,
RESET => RESET,
RLB_DI => RLB_DI,
RLB_ENA => RLB_ENA,
RLB_BUSY => RLB_BUSY,
RLB_DO => RLB_DO,
RLB_VAL => RLB_VAL,
RLB_HOLD => RLB_HOLD,
RL_MONI => RL_MONI,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
SERPORT : serport_1clock
generic map (
CDWIDTH => CDWIDTH,
CDINIT => CDINIT,
RXFAWIDTH => IFAWIDTH,
TXFAWIDTH => OFAWIDTH)
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
RESET => RESET,
ENAXON => ENAXON,
ENAESC => ENAESC,
RXDATA => SER_RXDATA,
RXVAL => SER_RXVAL,
RXHOLD => SER_RXHOLD,
TXDATA => SER_TXDATA,
TXENA => SER_TXENA,
TXBUSY => SER_TXBUSY,
MONI => SER_MONI,
RXSD => RXSD,
TXSD => TXSD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
RLBMUX : rlink_rlbmux
port map (
SEL => ENAFX2,
RLB_DI => RLB_DI,
RLB_ENA => RLB_ENA,
RLB_BUSY => RLB_BUSY,
RLB_DO => RLB_DO,
RLB_VAL => RLB_VAL,
RLB_HOLD => RLB_HOLD,
P0_RXDATA => SER_RXDATA,
P0_RXVAL => SER_RXVAL,
P0_RXHOLD => SER_RXHOLD,
P0_TXDATA => SER_TXDATA,
P0_TXENA => SER_TXENA,
P0_TXBUSY => SER_TXBUSY,
P1_RXDATA => FX2_RXDATA,
P1_RXVAL => FX2_RXVAL,
P1_RXHOLD => FX2_RXHOLD,
P1_TXDATA => FX2_TXDATA,
P1_TXENA => FX2_TXENA,
P1_TXBUSY => FX2_TXBUSY
);
FX2CNTL : fx2_2fifoctl_ic
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
PETOWIDTH => PETOWIDTH,
CCWIDTH => CCWIDTH,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1)
port map (
CLK => CLK,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
RLB_MONI.rxval <= RLB_VAL;
RLB_MONI.rxhold <= RLB_HOLD;
RLB_MONI.txena <= RLB_ENA;
RLB_MONI.txbusy <= RLB_BUSY;
end syn;

4
rtl/bplib/nexys2/nexys2lib.vhd
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@@ -1,6 +1,6 @@
-- $Id: nexys2lib.vhd 467 2013-01-02 19:49:05Z mueller $
-- $Id: nexys2lib.vhd 509 2013-04-21 20:46:20Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2010-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free

4
rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vhd
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@@ -1,4 +1,4 @@
-- $Id: tb_nexys2_fusp_cuff.vhd 476 2013-01-26 22:23:53Z mueller $
-- $Id: tb_nexys2_fusp_cuff.vhd 509 2013-04-21 20:46:20Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -22,7 +22,7 @@
-- tb_nexys2_core
-- serport/serport_uart_rxtx
-- fx2lib/tb/fx2_2fifo_core
-- nexys2_fusp_aif [UUT]
-- nexys2_fusp_cuff_aif [UUT]
--
-- To test: generic, any nexys2_fusp_cuff_aif target
--

77
rtl/bplib/nexys3/nexys3lib.vhd
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@@ -1,6 +1,6 @@
-- $Id: nexys3lib.vhd 432 2011-11-25 20:16:28Z mueller $
-- $Id: nexys3lib.vhd 509 2013-04-21 20:46:20Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -20,6 +20,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-04-21 509 1.1 add nexys3_cuff_aif, nexys3_fusp_cuff_aif
-- 2011-11-25 432 1.0 Initial version
------------------------------------------------------------------------------
@@ -55,7 +56,7 @@ component nexys3_aif is -- NEXYS 3, abstract iface, base
);
end component;
component nexys3_fusp_aif is -- NEXYS 2, abstract iface, base+fusp
component nexys3_fusp_aif is -- NEXYS 3, abstract iface, base+fusp
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
@@ -84,4 +85,74 @@ component nexys3_fusp_aif is -- NEXYS 2, abstract iface, base+fusp
);
end component;
component nexys3_cuff_aif is -- NEXYS 3, abstract iface, base+cuff
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit; -- ppcm: ...
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end component;
component nexys3_fusp_cuff_aif is -- NEXYS 3, abstract iface, +fusp+cuff
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit; -- ppcm: ...
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit; -- fusp: rs232 tx
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end component;
end package nexys3lib;

7
rtl/bplib/nexys3/tb/.cvsignore
View File

@@ -1,7 +1,2 @@
tb_nexys3_dummy
tb_nexys3_fusp_dummy
tb_n3_cram_memctl_as
tb_n3_cram_memctl_as_[sft]sim
tb_n3_cram_memctl_as_ISim
tb_n3_cram_memctl_as_ISim_[sft]sim
tb_n3_cram_memctl_stim
tb_nexys3_fusp_cuff_dummy

5
rtl/bplib/nexys3/tb/Makefile
View File

@@ -1,10 +1,11 @@
# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $
# $Id: Makefile 509 2013-04-21 20:46:20Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-11-26 432 1.0 Initial version
#
EXE_all = tb_nexys3_fusp_dummy
EXE_all = tb_nexys3_fusp_dummy
EXE_all += tb_nexys3_fusp_cuff_dummy
#
include $(RETROBASE)/rtl/make/xflow_default_nexys3.mk
#

26
rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vbom Normal file
View File

@@ -0,0 +1,26 @@
# Not meant for direct top level usage. Used with
# tb_nexys3_fusp_cuff_(....)[_ssim].vbom and config
# lines to generate the different cases.
#
# libs
../../../vlib/slvtypes.vhd
../../../vlib/rlink/rlinklib.vbom
../../../vlib/rlink/tb/rlinktblib.vhd
../../../vlib/serport/serportlib.vbom
../../../vlib/xlib/xlib.vhd
../nexys3lib.vhd
../../../vlib/simlib/simlib.vhd
../../../vlib/simlib/simbus.vhd
${sys_conf := sys_conf_sim.vhd}
# components
../../../vlib/simlib/simclk.vbom
../../../vlib/simlib/simclkcnt.vbom
../../../vlib/rlink/tb/tbcore_rlink.vbom
../../../vlib/xlib/dcm_sfs_gsim.vbom
tb_nexys3_core.vbom
../../../vlib/serport/serport_uart_rxtx.vbom
../../../bplib/fx2lib/tb/fx2_2fifo_core.vbom
${nexys3_fusp_cuff_aif := nexys3_fusp_cuff_dummy.vbom}
# design
tb_nexys3_fusp_cuff.vhd
@top:tb_nexys3_fusp_cuff

331
rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vhd Normal file
View File

@@ -0,0 +1,331 @@
-- $Id: tb_nexys3_fusp_cuff.vhd 509 2013-04-21 20:46:20Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys3_fusp_cuff - sim
-- Description: Test bench for nexys3 (base+fusp+cuff)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- xlib/dcm_sfs
-- rlink/tb/tbcore_rlink
-- tb_nexys3_core
-- serport/serport_uart_rxtx
-- fx2lib/tb/fx2_2fifo_core
-- nexys3_fusp_cuff_aif [UUT]
--
-- To test: generic, any nexys3_fusp_cuff_aif target
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-04-21 509 1.0 Initial version (derived from tb_nexys3_fusp and
-- tb_nexys2_fusp_cuff)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.rlinktblib.all;
use work.serportlib.all;
use work.xlib.all;
use work.nexys3lib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_nexys3_fusp_cuff is
end tb_nexys3_fusp_cuff;
architecture sim of tb_nexys3_fusp_cuff is
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
signal CLK_STOP : slbit := '0';
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal TBC_RXDATA : slv8 := (others=>'0');
signal TBC_RXVAL : slbit := '0';
signal TBC_RXHOLD : slbit := '0';
signal TBC_TXDATA : slv8 := (others=>'0');
signal TBC_TXENA : slbit := '0';
signal UART_RXDATA : slv8 := (others=>'0');
signal UART_RXVAL : slbit := '0';
signal UART_RXERR : slbit := '0';
signal UART_RXACT : slbit := '0';
signal UART_TXDATA : slv8 := (others=>'0');
signal UART_TXENA : slbit := '0';
signal UART_TXBUSY : slbit := '0';
signal FX2_RXDATA : slv8 := (others=>'0');
signal FX2_RXENA : slbit := '0';
signal FX2_RXBUSY : slbit := '0';
signal FX2_TXDATA : slv8 := (others=>'0');
signal FX2_TXVAL : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv5 := (others=>'0');
signal O_LED : slv8 := (others=>'0');
signal O_ANO_N : slv4 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal O_MEM_CE_N : slbit := '1';
signal O_MEM_BE_N : slv2 := (others=>'1');
signal O_MEM_WE_N : slbit := '1';
signal O_MEM_OE_N : slbit := '1';
signal O_MEM_ADV_N : slbit := '1';
signal O_MEM_CLK : slbit := '0';
signal O_MEM_CRE : slbit := '0';
signal I_MEM_WAIT : slbit := '0';
signal O_MEM_ADDR : slv23 := (others=>'Z');
signal IO_MEM_DATA : slv16 := (others=>'0');
signal O_PPCM_CE_N : slbit := '0';
signal O_PPCM_RST_N : slbit := '0';
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
signal I_FX2_IFCLK : slbit := '0';
signal O_FX2_FIFO : slv2 := (others=>'0');
signal I_FX2_FLAG : slv4 := (others=>'0');
signal O_FX2_SLRD_N : slbit := '1';
signal O_FX2_SLWR_N : slbit := '1';
signal O_FX2_SLOE_N : slbit := '1';
signal O_FX2_PKTEND_N : slbit := '1';
signal IO_FX2_DATA : slv8 := (others=>'Z');
signal UART_RESET : slbit := '0';
signal UART_RXD : slbit := '1';
signal UART_TXD : slbit := '1';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal R_PORTSEL_SER : slbit := '0'; -- if 1 use alternate serport
signal R_PORTSEL_FX2 : slbit := '0'; -- if 1 use fx2
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : time := 10 ns;
constant clock_offset : time := 200 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC,
CLK_STOP => CLK_STOP
);
SB_CLKSTOP <= CLK_STOP;
DCM_COM : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 10.0)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : tbcore_rlink
port map (
CLK => CLKCOM,
CLK_STOP => CLK_STOP,
RX_DATA => TBC_RXDATA,
RX_VAL => TBC_RXVAL,
RX_HOLD => TBC_RXHOLD,
TX_DATA => TBC_TXDATA,
TX_ENA => TBC_TXENA
);
N3CORE : entity work.tb_nexys3_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
UUT : nexys3_fusp_cuff_aif
port map (
I_CLK100 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA,
O_PPCM_CE_N => O_PPCM_CE_N,
O_PPCM_RST_N => O_PPCM_RST_N,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
UART : serport_uart_rxtx
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => UART_RESET,
CLKDIV => CLKDIV,
RXSD => UART_RXD,
RXDATA => UART_RXDATA,
RXVAL => UART_RXVAL,
RXERR => UART_RXERR,
RXACT => UART_RXACT,
TXSD => UART_TXD,
TXDATA => UART_TXDATA,
TXENA => UART_TXENA,
TXBUSY => UART_TXBUSY
);
FX2 : entity work.fx2_2fifo_core
port map (
CLK => CLKCOM,
RESET => '0',
RXDATA => FX2_RXDATA,
RXENA => FX2_RXENA,
RXBUSY => FX2_RXBUSY,
TXDATA => FX2_TXDATA,
TXVAL => FX2_TXVAL,
IFCLK => I_FX2_IFCLK,
FIFO => O_FX2_FIFO,
FLAG => I_FX2_FLAG,
SLRD_N => O_FX2_SLRD_N,
SLWR_N => O_FX2_SLWR_N,
SLOE_N => O_FX2_SLOE_N,
PKTEND_N => O_FX2_PKTEND_N,
DATA => IO_FX2_DATA
);
proc_fx2_mux: process (R_PORTSEL_FX2, TBC_RXDATA, TBC_RXVAL,
UART_TXBUSY, RTS_N, UART_RXDATA, UART_RXVAL,
FX2_RXBUSY, FX2_TXDATA, FX2_TXVAL
)
begin
if R_PORTSEL_FX2 = '0' then -- use serport
UART_TXDATA <= TBC_RXDATA;
UART_TXENA <= TBC_RXVAL;
TBC_RXHOLD <= UART_TXBUSY or RTS_N;
TBC_TXDATA <= UART_RXDATA;
TBC_TXENA <= UART_RXVAL;
else -- otherwise use fx2
FX2_RXDATA <= TBC_RXDATA;
FX2_RXENA <= TBC_RXVAL;
TBC_RXHOLD <= FX2_RXBUSY;
TBC_TXDATA <= FX2_TXDATA;
TBC_TXENA <= FX2_TXVAL;
end if;
end process proc_fx2_mux;
proc_ser_mux: process (R_PORTSEL_SER, UART_TXD, CTS_N,
O_TXD, O_FUSP_TXD, O_FUSP_RTS_N)
begin
if R_PORTSEL_SER = '0' then -- use main board rs232, no flow cntl
I_RXD <= UART_TXD; -- write port 0 inputs
UART_RXD <= O_TXD; -- get port 0 outputs
RTS_N <= '0';
I_FUSP_RXD <= '1'; -- port 1 inputs to idle state
I_FUSP_CTS_N <= '0';
else -- otherwise use pmod1 rs232
I_FUSP_RXD <= UART_TXD; -- write port 1 inputs
I_FUSP_CTS_N <= CTS_N;
UART_RXD <= O_FUSP_TXD; -- get port 1 outputs
RTS_N <= O_FUSP_RTS_N;
I_RXD <= '1'; -- port 0 inputs to idle state
end if;
end process proc_ser_mux;
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
if UART_RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen UART_RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_SER <= to_x01(SB_DATA(0));
R_PORTSEL_FX2 <= to_x01(SB_DATA(1));
end if;
end if;
end process proc_simbus;
end sim;

8
rtl/sys_gen/tst_fx2loop/tst_fx2loop.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: tst_fx2loop.vhd 453 2012-01-15 17:51:18Z mueller $
-- $Id: tst_fx2loop.vhd 510 2013-04-26 16:14:57Z mueller $
--
-- Copyright 2011-2012 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -24,6 +24,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-04-24 510 1.0.1 fix sensitivity list of proc_next
-- 2012-01-15 453 1.0 Initial version
-- 2011-12-26 445 0.5 First draft
------------------------------------------------------------------------------
@@ -162,7 +163,8 @@ begin
end process proc_regs;
proc_next: process (R_REGS, CE_MSEC, HIO_CNTL, FX2_MONI,
RXWDATA, RXWVAL, TXWBUSY, TX2WBUSY)
RXWDATA, RXWVAL, TXWBUSY, TX2WBUSY,
RXHOLD_L, TXBUSY, TX2BUSY)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;

1
rtl/sys_gen/w11a/nexys2/.cvsignore
View File

@@ -2,3 +2,4 @@ sys_w11a_n2.ucf
*.dep_ucf_cpp
log_*
_impact*
*.svf

4
rtl/sys_gen/w11a/nexys2/Makefile
View File

@@ -1,7 +1,8 @@
# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $
# $Id: Makefile 509 2013-04-21 20:46:20Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2013-04-20 509 1.2 add fx2 support
# 2011-08-13 405 1.1 use includes from rtl/make
# 2010-05-28 295 1.0 Initial version (derived from _s3 version)
#
@@ -9,6 +10,7 @@ VBOM_all = $(wildcard *.vbom)
BIT_all = $(VBOM_all:.vbom=.bit)
#
include $(RETROBASE)/rtl/make/xflow_default_nexys2.mk
FX2_FILE = nexys2_jtag_2fifo_ic.ihx
#
.PHONY : all clean
#

9
rtl/sys_gen/w11a/nexys2/sys_conf.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: sys_conf.vhd 428 2011-11-20 12:19:31Z mueller $
-- $Id: sys_conf.vhd 509 2013-04-21 20:46:20Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2010-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -19,6 +19,7 @@
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2013-04-21 509 1.2 add fx2 settings
-- 2011-11-19 428 1.1.1 use clksys=56 (58 no closure after numeric_std...)
-- 2010-11-27 341 1.1 add dcm and memctl related constants (clksys=58)
-- 2010-05-05 295 1.0 Initial version (derived from _s3 version)
@@ -46,6 +47,10 @@ package sys_conf is
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
-- fx2 settings: petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec
constant sys_conf_fx2_petowidth : positive := 10;
constant sys_conf_fx2_ccwidth : positive := 5;
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
constant sys_conf_bram : integer := 0; -- no bram, use cache

8
rtl/sys_gen/w11a/nexys2/sys_w11a_n2.ucf_cpp
View File

@@ -1,7 +1,8 @@
## $Id: sys_w11a_n2.ucf_cpp 336 2010-11-06 18:28:27Z mueller $
## $Id: sys_w11a_n2.ucf_cpp 509 2013-04-21 20:46:20Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2013-04-20 509 1.1 add fx2 support
## 2010-11-06 336 1.0.1 rename input pin CLK -> I_CLK50
## 2010-05-26 295 1.0 Initial version
##
@@ -18,3 +19,8 @@ OFFSET = OUT 20 ns AFTER "I_CLK50";
## Pmod B0 - RS232
##
#include "bplib/nexys2/nexys2_pins_pmb0_rs232.ucf"
##
## Cypress FX2
##
#include "bplib/nexys2/nexys2_pins_fx2.ucf"
#include "bplib/nexys2/nexys2_time_fx2_ic.ucf"

5
rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vbom
View File

@@ -5,6 +5,8 @@
../../../vlib/serport/serportlib.vbom
../../../vlib/rbus/rblib.vhd
../../../vlib/rlink/rlinklib.vbom
../../../bplib/fx2lib/fx2lib.vhd
../../../bplib/fx2rlink/fx2rlinklib.vbom
../../../bplib/bpgen/bpgenlib.vbom
../../../bplib/bpgen/bpgenrbuslib.vbom
../../../bplib/nxcramlib/nxcramlib.vhd
@@ -18,7 +20,8 @@ sys_conf = sys_conf.vhd
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom
../../../bplib/bpgen/sn_humanio_rbus.vbom
../../../vlib/rlink/rlink_sp1c.vbom
../../../bplib/fx2rlink/rlink_sp1c_fx2.vbom
../../../bplib/fx2rlink/ioleds_sp1c_fx2.vbom
../../../vlib/rbus/rb_sres_or_3.vbom
../../../w11a/pdp11_core_rbus.vbom
../../../w11a/pdp11_core.vbom

86
rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: sys_w11a_n2.vhd 476 2013-01-26 22:23:53Z mueller $
-- $Id: sys_w11a_n2.vhd 509 2013-04-21 20:46:20Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2010-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -19,7 +19,8 @@
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/bpgen/sn_humanio_rbus
-- vlib/rlink/rlink_sp1c
-- bplib/fx2rlink/rlink_sp1c_fx2
-- bplib/fx2rlink/ioleds_sp1c_fx2
-- vlib/rri/rb_sres_or_3
-- w11a/pdp11_core_rbus
-- w11a/pdp11_core
@@ -40,6 +41,7 @@
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2013-04-20 509 13.3 O76d xc3s1200e-4 1541 4598 334 2889 ok: now + FX2 !
-- 2011-12-18 440 13.1 O40d xc3s1200e-4 1450 4439 270 2740 ok: LP+PC+DL+II
-- 2011-11-18 427 13.1 O40d xc3s1200e-4 1433 4374 242 2680 ok: LP+PC+DL+II
-- 2010-12-30 351 12.1 M53d xc3s1200e-4 1389 4368 242 2674 ok: LP+PC+DL+II
@@ -64,6 +66,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-04-20 509 1.4 added fx2 (cuff) support; ATOWIDTH=7
-- 2011-12-23 444 1.3 remove clksys output hack
-- 2011-12-18 440 1.2.7 use rlink_sp1c
-- 2011-11-26 433 1.2.6 use nx_cram_(dummy|memctl_as) now
@@ -92,13 +95,15 @@
------------------------------------------------------------------------------
--
-- w11a test design for nexys2
-- w11a + rlink + serport
-- w11a + rlink + serport + cuff
--
-- Usage of Nexys 2 Switches, Buttons, LEDs:
--
-- SWI(7:2): no function (only connected to sn_humanio_rbus)
-- SWI(1): 1 enable XON
-- SWI(0): 0 -> main board RS232 port
-- SWI(7:3): no function (only connected to sn_humanio_rbus)
-- (2) 0 -> int/ext RS242 port for rlink
-- 1 -> use USB interface for rlink
-- (1): 1 enable XON
-- (0): 0 -> main board RS232 port
-- 1 -> Pmod B/top RS232 port
--
-- LED(7) MEM_ACT_W
@@ -114,10 +119,17 @@
-- (3:0) cpurust code
-- (4) '1'
--
-- DP(3): not SER_MONI.txok (shows tx back preasure)
-- DP(2): SER_MONI.txact (shows tx activity)
-- DP(1): not SER_MONI.rxok (shows rx back preasure)
-- DP(0): SER_MONI.rxact (shows rx activity)
-- DP(3:0) shows IO activity
-- if SWI(2)=0 (serport)
-- (3): not SER_MONI.txok (shows tx back preasure)
-- (2): SER_MONI.txact (shows tx activity)
-- (1): not SER_MONI.rxok (shows rx back preasure)
-- (0): SER_MONI.rxact (shows rx activity)
-- if SWI(2)=1 (fx2-usb)
-- (3): RB_SRES.busy (shows rbus back preasure)
-- (2): RLB_TXBUSY (shows tx back preasure)
-- (1): RLB_TXENA (shows tx activity)
-- (0): RLB_RXVAL (shows rx activity)
--
library ieee;
@@ -130,6 +142,8 @@ use work.genlib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rlinklib.all;
use work.fx2lib.all;
use work.fx2rlinklib.all;
use work.bpgenlib.all;
use work.bpgenrbuslib.all;
use work.nxcramlib.all;
@@ -141,7 +155,7 @@ use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_w11a_n2 is -- top level
-- implements nexys2_fusp_aif
-- implements nexys2_fusp_cuff_aif
port (
I_CLK50 : in slbit; -- 50 MHz clock
I_RXD : in slbit; -- receive data (board view)
@@ -165,7 +179,15 @@ entity sys_w11a_n2 is -- top level
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
O_FUSP_TXD : out slbit; -- fusp: rs232 tx
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end sys_w11a_n2;
@@ -187,7 +209,9 @@ architecture syn of sys_w11a_n2 is
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv3 := (others=>'0');
signal RLB_MONI : rlb_moni_type := rlb_moni_init;
signal SER_MONI : serport_moni_type := serport_moni_init;
signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init;
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
@@ -316,13 +340,15 @@ begin
O_SEG_N => O_SEG_N
);
RLINK : rlink_sp1c
RLINK : rlink_sp1c_fx2
generic map (
ATOWIDTH => 6, -- 64 cycles access timeout
ATOWIDTH => 7, -- 128 cycles access timeout
ITOWIDTH => 6, -- 64 periods max idle timeout
CPREF => c_rlink_cpref,
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
PETOWIDTH => sys_conf_fx2_petowidth,
CCWIDTH => sys_conf_fx2_ccwidth,
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 13,
@@ -335,6 +361,7 @@ begin
RESET => RESET,
ENAXON => SWI(1),
ENAESC => SWI(1),
ENAFX2 => SWI(2),
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
@@ -344,7 +371,17 @@ begin
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
RLB_MONI => RLB_MONI,
SER_MONI => SER_MONI,
FX2_MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
RB_SRES_OR : rb_sres_or_3
@@ -557,12 +594,19 @@ begin
);
end generate IBD_MAXI;
DSP_DAT(15 downto 0) <= DISPREG;
IOLEDS : ioleds_sp1c_fx2
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => CPU_RESET,
ENAFX2 => SWI(2),
RB_SRES => RB_SRES,
RLB_MONI => RLB_MONI,
SER_MONI => SER_MONI,
IOLEDS => DSP_DP
);
DSP_DP(3) <= not SER_MONI.txok;
DSP_DP(2) <= SER_MONI.txact;
DSP_DP(1) <= not SER_MONI.rxok;
DSP_DP(0) <= SER_MONI.rxact;
DSP_DAT(15 downto 0) <= DISPREG;
proc_led: process (MEM_ACT_W, MEM_ACT_R, CP_STAT, DM_STAT_DP.psw)
variable iled : slv8 := (others=>'0');

9
rtl/sys_gen/w11a/nexys2/tb/sys_conf_sim.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: sys_conf_sim.vhd 433 2011-11-27 22:04:39Z mueller $
-- $Id: sys_conf_sim.vhd 509 2013-04-21 20:46:20Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2010-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -19,6 +19,7 @@
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2013-04-21 509 1.2 add fx2 settings
-- 2011-11-27 433 1.1.1 use /1*1 to skip dcm in sim, _ssim fails with dcm
-- 2010-11-27 341 1.1 add dcm and memctl related constants (clksys=58)
-- 2010-05-28 295 1.0 Initial version (cloned from _s3)
@@ -41,6 +42,10 @@ package sys_conf is
constant sys_conf_memctl_writedelay : positive := 4;
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
-- fx2 settings: petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec
constant sys_conf_fx2_petowidth : positive := 10;
constant sys_conf_fx2_ccwidth : positive := 5;
constant sys_conf_hio_debounce : boolean := false; -- no debouncers

6
rtl/sys_gen/w11a/nexys2/tb/tb_w11a_n2.vbom
View File

@@ -1,7 +1,7 @@
# configure tb_nexys2_fusp with sys_w11a_n2 target;
# configure tb_nexys2_fusp_cuff with sys_w11a_n2 target;
# use vhdl configure file (tb_w11a_n2.vhd) to allow
# that all configurations will co-exist in work library
nexys2_fusp_aif = ../sys_w11a_n2.vbom
nexys2_fusp_cuff_aif = ../sys_w11a_n2.vbom
sys_conf = sys_conf_sim.vhd
../../../../bplib/nexys2/tb/tb_nexys2_fusp.vbom
../../../../bplib/nexys2/tb/tb_nexys2_fusp_cuff.vbom
tb_w11a_n2.vhd

11
rtl/sys_gen/w11a/nexys2/tb/tb_w11a_n2.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: tb_w11a_n2.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: tb_w11a_n2.vhd 509 2013-04-21 20:46:20Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2010-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -13,7 +13,7 @@
--
------------------------------------------------------------------------------
-- Module Name: tb_w11a_n2
-- Description: Configuration for tb_w11a_n2 for tb_nexys2_fusp
-- Description: Configuration for tb_w11a_n2 for tb_nexys2_fusp_cuff
--
-- Dependencies: sys_w11a_n2
--
@@ -26,13 +26,14 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-04-21 509 1.1 now based on tb_nexys2_fusp_cuff
-- 2010-05-26 295 1.0 Initial version (cloned from _s3)
------------------------------------------------------------------------------
configuration tb_w11a_n2 of tb_nexys2_fusp is
configuration tb_w11a_n2 of tb_nexys2_fusp_cuff is
for sim
for all : nexys2_fusp_aif
for all : nexys2_fusp_cuff_aif
use entity work.sys_w11a_n2;
end for;
end for;

1
rtl/sys_gen/w11a/nexys3/.cvsignore
View File

@@ -2,3 +2,4 @@ sys_w11a_n3.ucf
*.dep_ucf_cpp
log_*
_impact*
*.svf

4
rtl/sys_gen/w11a/nexys3/Makefile
View File

@@ -1,13 +1,15 @@
# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $
# $Id: Makefile 509 2013-04-21 20:46:20Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2013-04-20 509 1.2 add fx2 support
# 2011-11-20 430 1.0 Initial version (derived from _n2 version)
#
VBOM_all = $(wildcard *.vbom)
BIT_all = $(VBOM_all:.vbom=.bit)
#
include $(RETROBASE)/rtl/make/xflow_default_nexys3.mk
FX2_FILE = nexys3_jtag_2fifo_ic.ihx
#
.PHONY : all clean
#

9
rtl/sys_gen/w11a/nexys3/sys_conf.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: sys_conf.vhd 433 2011-11-27 22:04:39Z mueller $
-- $Id: sys_conf.vhd 509 2013-04-21 20:46:20Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -19,6 +19,7 @@
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2013-04-21 509 1.1 add fx2 settings
-- 2011-11-26 433 1.0.1 use 80 MHz clksys (no closure for 85 after rev 432)
-- 2011-11-20 430 1.0 Initial version (derived from _n2 version)
------------------------------------------------------------------------------
@@ -48,6 +49,10 @@ package sys_conf is
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
-- fx2 settings: petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec
constant sys_conf_fx2_petowidth : positive := 10;
constant sys_conf_fx2_ccwidth : positive := 5;
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
constant sys_conf_bram : integer := 0; -- no bram, use cache

8
rtl/sys_gen/w11a/nexys3/sys_w11a_n3.ucf_cpp
View File

@@ -1,7 +1,8 @@
## $Id: sys_w11a_n3.ucf_cpp 430 2011-11-20 20:48:39Z mueller $
## $Id: sys_w11a_n3.ucf_cpp 509 2013-04-21 20:46:20Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2013-04-21 509 1.1 add fx2 support
## 2011-11-20 430 1.0 Initial version
##
@@ -17,3 +18,8 @@ OFFSET = OUT 20 ns AFTER "I_CLK100";
## Pmod B0 - RS232
##
#include "bplib/nexys3/nexys3_pins_pmb0_rs232.ucf"
##
## Cypress FX2
##
#include "bplib/nexys3/nexys3_pins_fx2.ucf"
#include "bplib/nexys3/nexys3_time_fx2_ic.ucf"

5
rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vbom
View File

@@ -5,6 +5,8 @@
../../../vlib/serport/serportlib.vbom
../../../vlib/rbus/rblib.vhd
../../../vlib/rlink/rlinklib.vbom
../../../bplib/fx2lib/fx2lib.vhd
../../../bplib/fx2rlink/fx2rlinklib.vbom
../../../bplib/bpgen/bpgenlib.vbom
../../../bplib/bpgen/bpgenrbuslib.vbom
../../../bplib/nxcramlib/nxcramlib.vhd
@@ -18,7 +20,8 @@ sys_conf = sys_conf.vhd
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom
../../../bplib/bpgen/sn_humanio_rbus.vbom
../../../vlib/rlink/rlink_sp1c.vbom
../../../bplib/fx2rlink/rlink_sp1c_fx2.vbom
../../../bplib/fx2rlink/ioleds_sp1c_fx2.vbom
../../../vlib/rbus/rb_sres_or_3.vbom
../../../w11a/pdp11_core_rbus.vbom
../../../w11a/pdp11_core.vbom

78
rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: sys_w11a_n3.vhd 476 2013-01-26 22:23:53Z mueller $
-- $Id: sys_w11a_n3.vhd 509 2013-04-21 20:46:20Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -19,7 +19,8 @@
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/bpgen/sn_humanio_rbus
-- vlib/rlink/rlink_sp1c
-- bplib/fx2rlink/rlink_sp1c_fx2
-- bplib/fx2rlink/ioleds_sp1c_fx2
-- vlib/rri/rb_sres_or_3
-- w11a/pdp11_core_rbus
-- w11a/pdp11_core
@@ -40,11 +41,13 @@
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2013-04-21 509 13.3 O76d xc6slx16-2 1516 3274 140 1184 ok: now + FX2 !
-- 2011-12-18 440 13.1 O40d xc6slx16-2 1441 3161 96 1084 ok: LP+PC+DL+II
-- 2011-11-20 430 13.1 O40d xc6slx16-2 1412 3206 84 1063 ok: LP+PC+DL+II
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-04-21 509 1.4 added fx2 (cuff) support
-- 2011-12-18 440 1.0.4 use rlink_sp1c
-- 2011-12-04 435 1.0.3 increase ATOWIDTH 6->7 (saw i/o timeouts on wblks)
-- 2011-11-26 433 1.0.2 use nx_cram_(dummy|memctl_as) now
@@ -57,7 +60,9 @@
--
-- Usage of Nexys 3 Switches, Buttons, LEDs:
--
-- SWI(7:2): no function (only connected to sn_humanio_rbus)
-- SWI(7:3): no function (only connected to sn_humanio_rbus)
-- (2) 0 -> int/ext RS242 port for rlink
-- 1 -> use USB interface for rlink
-- SWI(1): 1 enable XON
-- SWI(0): 0 -> main board RS232 port
-- 1 -> Pmod B/top RS232 port
@@ -75,10 +80,17 @@
-- (3:0) cpurust code
-- (4) '1'
--
-- DP(3): not SER_MONI.txok (shows tx back preasure)
-- DP(2): SER_MONI.txact (shows tx activity)
-- DP(1): not SER_MONI.rxok (shows rx back preasure)
-- DP(0): SER_MONI.rxact (shows rx activity)
-- DP(3:0) shows IO activity
-- if SWI(2)=0 (serport)
-- (3): not SER_MONI.txok (shows tx back preasure)
-- (2): SER_MONI.txact (shows tx activity)
-- (1): not SER_MONI.rxok (shows rx back preasure)
-- (0): SER_MONI.rxact (shows rx activity)
-- if SWI(2)=1 (fx2-usb)
-- (3): RB_SRES.busy (shows rbus back preasure)
-- (2): RLB_TXBUSY (shows tx back preasure)
-- (1): RLB_TXENA (shows tx activity)
-- (0): RLB_RXVAL (shows rx activity)
--
library ieee;
@@ -91,6 +103,8 @@ use work.genlib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rlinklib.all;
use work.fx2lib.all;
use work.fx2rlinklib.all;
use work.bpgenlib.all;
use work.bpgenrbuslib.all;
use work.nxcramlib.all;
@@ -102,7 +116,7 @@ use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_w11a_n3 is -- top level
-- implements nexys3_fusp_aif
-- implements nexys3_fusp_cuff_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
@@ -127,7 +141,15 @@ entity sys_w11a_n3 is -- top level
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
O_FUSP_TXD : out slbit; -- fusp: rs232 tx
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end sys_w11a_n3;
@@ -149,7 +171,9 @@ architecture syn of sys_w11a_n3 is
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv3 := (others=>'0');
signal RLB_MONI : rlb_moni_type := rlb_moni_init;
signal SER_MONI : serport_moni_type := serport_moni_init;
signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init;
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
@@ -279,13 +303,15 @@ begin
O_SEG_N => O_SEG_N
);
RLINK : rlink_sp1c
RLINK : rlink_sp1c_fx2
generic map (
ATOWIDTH => 7, -- 128 cycles access timeout
ITOWIDTH => 6, -- 64 periods max idle timeout
CPREF => c_rlink_cpref,
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
PETOWIDTH => sys_conf_fx2_petowidth,
CCWIDTH => sys_conf_fx2_ccwidth,
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 13,
@@ -298,6 +324,7 @@ begin
RESET => RESET,
ENAXON => SWI(1),
ENAESC => SWI(1),
ENAFX2 => SWI(2),
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
@@ -307,7 +334,17 @@ begin
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
RLB_MONI => RLB_MONI,
SER_MONI => SER_MONI,
FX2_MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
RB_SRES_OR : rb_sres_or_3
@@ -522,12 +559,19 @@ begin
);
end generate IBD_MAXI;
DSP_DAT(15 downto 0) <= DISPREG;
IOLEDS : ioleds_sp1c_fx2
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => CPU_RESET,
ENAFX2 => SWI(2),
RB_SRES => RB_SRES,
RLB_MONI => RLB_MONI,
SER_MONI => SER_MONI,
IOLEDS => DSP_DP
);
DSP_DP(3) <= not SER_MONI.txok;
DSP_DP(2) <= SER_MONI.txact;
DSP_DP(1) <= not SER_MONI.rxok;
DSP_DP(0) <= SER_MONI.rxact;
DSP_DAT(15 downto 0) <= DISPREG;
proc_led: process (MEM_ACT_W, MEM_ACT_R, CP_STAT, DM_STAT_DP.psw)
variable iled : slv8 := (others=>'0');

9
rtl/sys_gen/w11a/nexys3/tb/sys_conf_sim.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: sys_conf_sim.vhd 433 2011-11-27 22:04:39Z mueller $
-- $Id: sys_conf_sim.vhd 509 2013-04-21 20:46:20Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -19,6 +19,7 @@
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2013-04-21 509 1.2 add fx2 settings
-- 2011-11-25 432 1.0 Initial version (cloned from _n3)
------------------------------------------------------------------------------
@@ -40,6 +41,10 @@ package sys_conf is
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
-- fx2 settings: petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec
constant sys_conf_fx2_petowidth : positive := 10;
constant sys_conf_fx2_ccwidth : positive := 5;
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
constant sys_conf_bram : integer := 0; -- no bram, use cache

4
rtl/sys_gen/w11a/nexys3/tb/tb_w11a_n3.vbom
View File

@@ -1,7 +1,7 @@
# configure tb_nexys3_fusp with sys_w11a_n3 target;
# use vhdl configure file (tb_w11a_n3.vhd) to allow
# that all configurations will co-exist in work library
nexys3_fusp_aif = ../sys_w11a_n3.vbom
nexys3_fusp_cuff_aif = ../sys_w11a_n3.vbom
sys_conf = sys_conf_sim.vhd
../../../../bplib/nexys3/tb/tb_nexys3_fusp.vbom
../../../../bplib/nexys3/tb/tb_nexys3_fusp_cuff.vbom
tb_w11a_n3.vhd

11
rtl/sys_gen/w11a/nexys3/tb/tb_w11a_n3.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: tb_w11a_n3.vhd 432 2011-11-25 20:16:28Z mueller $
-- $Id: tb_w11a_n3.vhd 509 2013-04-21 20:46:20Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -13,7 +13,7 @@
--
------------------------------------------------------------------------------
-- Module Name: tb_w11a_n3
-- Description: Configuration for tb_w11a_n3 for tb_nexys3_fusp
-- Description: Configuration for tb_w11a_n3 for tb_nexys3_fusp_cuff
--
-- Dependencies: sys_w11a_n3
--
@@ -26,13 +26,14 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-04-21 509 1.1 now based on tb_nexys3_fusp_cuff
-- 2011-11-25 432 1.0 Initial version (cloned from _n2)
------------------------------------------------------------------------------
configuration tb_w11a_n3 of tb_nexys3_fusp is
configuration tb_w11a_n3 of tb_nexys3_fusp_cuff is
for sim
for all : nexys3_fusp_aif
for all : nexys3_fusp_cuff_aif
use entity work.sys_w11a_n3;
end for;
end for;

1
rtl/sys_gen/w11a/s3board/.cvsignore
View File

@@ -2,3 +2,4 @@ sys_w11a_s3.ucf
*.dep_ucf_cpp
log_*
_impact*
*.svf

38
rtl/sys_gen/w11a/tb/211bsd_rk_boot.tcl Normal file
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@@ -0,0 +1,38 @@
# $Id: 211bsd_rk_boot.tcl 511 2013-04-27 13:51:46Z mueller $
#
# Setup file for 211bsd RK based system (w11a, in sys/tb area...)
#
# Usage:
#
# telnet_starter -d DL0 &
# telnet_starter -d DL1 &
# torri -xxx @211bsd_rk_boot.tcl ( -xxx depends on sim or fpga connect)
#
# setup w11 cpu
puts [rlw]
# 2.11 bsd uses parity, so strip it
cpu0tta0 set to7bit 1
cpu0ttb0 set to7bit 1
# setup tcp links for terminals
cpu0tta0 att "tcp:?port=8000"
cpu0ttb0 att "tcp:?port=8001"
# setup log files
cpu0tta0 set log "tt_dl0.log?crlf"
cpu0ttb0 set log "tt_dl1.log?crlf"
# mount disks
cpu0rka0 att 211bsd_rk_root.dsk
cpu0rka1 att 211bsd_rk_swap.dsk
cpu0rka2 att 211bsd_rk_tmp.dsk
cpu0rka3 att 211bsd_rk_bin.dsk
cpu0rka4 att 211bsd_rk_usr.dsk
# and boot
#cpu0rka set trace 1
rw11::cpumon
rw11::cpucons
cpu0 boot rka0

4
rtl/sys_gen/w11a/tb/dorri
View File

@@ -1,5 +1,5 @@
#!/usr/bin/perl -w
# $Id: dorri 503 2013-04-06 19:44:13Z mueller $
# $Id: dorri 510 2013-04-26 16:14:57Z mueller $
#
# Revision History:
# Date Rev Version Comment
@@ -139,7 +139,7 @@ if ($opt_io eq "f") {
} elsif ($opt_io eq "t") {
push @arglist, "--term=$val_term";
} else {
print STDERR "dorri-E: neither -s3/-n2/-n3 nor -t specified\n";
print STDERR "dorri-E: neither -s3/-n2/-n3 nor -t or -u specified\n";
print_usage();
exit 1;
}

229
rtl/sys_gen/w11a/tb/torri Executable file
View File

@@ -0,0 +1,229 @@
#!/usr/bin/perl -w
# $Id: torri 511 2013-04-27 13:51:46Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2013-04-26 510 1.0 Initial version (derived from dorri)
#
use 5.005; # require Perl 5.005 or higher
use strict; # require strict checking
use FileHandle;
sub print_usage;
autoflush STDOUT 1; # autoflush, so noting lost on exec later
my $opt_b;
my $opt_io = '';
my $opt_f = '';
my $opt_tmu;
my $tirri;
my $val_term;
my $val_tb_s3='tbw ../s3board/tb/tb_w11a_s3';
my $val_tb_n2='tbw ../nexys2/tb/tb_w11a_n2';
my $val_tb_n3='tbw ../nexys3/tb/tb_w11a_n3';
my $val_tb;
my $val_e;
my @arglist;
#
# process torri options
#
while (scalar(@ARGV)) {
my $curarg = $ARGV[0];
if ($curarg =~ m{^-b$} ) { # -b
$opt_b = 1;
shift @ARGV;
} elsif ($curarg =~ m{^-tmu$} ) { # -tmu
$opt_tmu = 1;
shift @ARGV;
} elsif ($curarg =~ m{^-s3$} ) { # -s3
$opt_io = 'f';
$val_tb = $val_tb_s3;
shift @ARGV;
} elsif ($curarg =~ m{^-n2$} ) { # -n2
$opt_io = 'f';
$val_tb = $val_tb_n2;
shift @ARGV;
} elsif ($curarg =~ m{^-n3$} ) { # -n3
$opt_io = 'f';
$val_tb = $val_tb_n3;
shift @ARGV;
} elsif ($curarg =~ m{^-f(s\d?|u)$} ) { # -f[su]
$opt_f = $1;
shift @ARGV;
} elsif ($curarg =~ m{^-t([su])(\d?),?} ) { # -t[su]...
my $devnam = ($1 eq 's') ? '/dev/ttyS' : '/dev/ttyUSB';
my $devnum = $2;
my ($dev,$baud,$opt1,$opt2) = split /,/,$curarg;
$baud = '115k' unless defined $baud;
if ($baud !~ m{^\d*k?$}) {
print STDERR "torri-E: invalid format of -ts or -tu option\n";
exit 1;
}
$opt_io = 't';
$val_term = sprintf '%s%d,%s', $devnam, $devnum, $baud;
$val_term .= ",$opt1" if defined $opt1;
$val_term .= ",$opt2" if defined $opt2;
shift @ARGV;
} elsif ($curarg =~ m{^-u$} ) { # -u
$opt_io = 'u';
shift @ARGV;
} elsif ($curarg =~ m{^-e$} ) { # -e <file>
print STDERR "torri-W: multiple -e options, only last taken\n"
if defined $val_e;
shift @ARGV;
if (scalar(@ARGV) == 0 || $ARGV[0] =~ m{^-}) {
print STDERR "torri-E: no file name after -e option\n";
exit 1;
} else {
$val_e = shift @ARGV;
if (not -r $val_e) {
print STDERR "torri-E: file '$val_e' not found\n";
exit 1;
}
}
} else {
last;
}
}
#
# check that either -s3/n2/n3 or -t or -u given
# setup pi_rri options for either case
#
if ($opt_io eq 'f') {
push @arglist, '--fifo';
push @arglist, "--run=$val_tb";
} elsif ($opt_io eq 't') {
push @arglist, "--term=$val_term";
} elsif ($opt_io eq 'u') {
push @arglist, '--cuff';
} else {
print STDERR "torri-E: neither -s3/-n2/-n3 nor -t or -u specified\n";
print_usage();
exit 1;
}
#
# setup all other ti_rri options
#
push @arglist, '--logl=2';
push @arglist, '--int' unless $opt_b;
push @arglist, '--pack=rw11';
push @arglist, '--';
#
# actions prior to first exec
# setup tmu ect
# setup access path --> handle -f options
#
if ($opt_io eq 'f') {
if ($opt_tmu) {
push @arglist, 'rlc oob -sbcntl 13 1';
}
if ($opt_f eq 'u') {
push @arglist, 'rlc oob -sbdata 8 0x2';
push @arglist, 'rlc oob -sbdata 16 0x4';
}
}
#
# initialize w11 cpu system
#
push @arglist, 'rw11::setup_sys';
#
# handle -e option
#
if (defined $val_e) {
if ($val_e =~ m/\.mac$/) {
push @arglist, "cpu0 ldasm -file $val_e -sym ldasm_sym -lst ldasm_lst";
} else {
push @arglist, "cpu0 ldabs $val_e";
}
push @arglist, 'rw11::cpumon';
push @arglist, 'rw11::cpucons';
push @arglist, 'cpu0 cp -stapc 0200';
}
#
# all remaining commands
#
while (scalar(@ARGV)) {
my $curarg = shift @ARGV;
if ($curarg =~ m{^@(.*)$} && ! -r $1) {
print STDERR "torri-E: file '$1' not found\n";
exit 1;
}
push @arglist,$curarg;
}
#
# find ti_rri executable
#
$tirri=`which ti_rri`;
chomp $tirri;
if ($tirri eq '' || ! -e $tirri) {
print STDERR "torri-E: failed to locate ti_rri\n";
exit 1;
}
#
# print command file
#
if (1) {
print 'ti_rri ', join (' ', map {(m{\s}) ? "\"$_\"" : $_} @arglist) , "\n";
}
#
# and do it
#
exec $tirri, @arglist
or die "failed to exec: $!";
exit 1;
# ----------------------------------------------------------------------------
sub print_usage {
print "usage: torri <setup options> <ti_rri opts and cmds>...\n";
print " setup options for ghdl simulation runs:\n";
print " -s3 start tb_w11a_s3 simulation\n";
print " -n2 start tb_w11a_n2 simulation\n";
print " -n3 start tb_w11a_n3 simulation\n";
print " -f.. simulation communication options\n";
print " -fu use cuff data path\n";
print " -tmu activate trace and monitoring unit\n";
print " setup options for FPGA connects:\n";
print " -u use --cuff connect\n";
print " -t.. use --term connect\n";
print " -ts*[,opts] use /dev/ttyS* (* is device number)\n";
print " -tu*[,opts] use /dev/ttyUSB* (* is device number)\n";
print " opts can be ',break', ',xon'\n";
print " common options:\n";
print " -e <file> load and execute file\n";
print " file type '.mac': on the fly compile with asm-11\n";
print " any other file type: assume lda format\n";
print "\n";
print " either one of -s3,-n2, or -n3 must be given -> sim run\n";
print " or one of -t or -u must be given -> fpga run\n";
}

29
rtl/sys_gen/w11a/tb/uv5_boot.tcl Normal file
View File

@@ -0,0 +1,29 @@
# $Id: uv5_boot.tcl 511 2013-04-27 13:51:46Z mueller $
#
# Setup file for Unix V5 System
#
# Usage:
#
# telnet_starter -d DL0 &
# torri -xxx @uv5_boot.tcl ( -xxx depends on sim or fpga connect)
# setup w11 cpu
puts [rlw]
# 2.11 bsd uses parity, so strip it
cpu0tta0 set to7bit 1
# setup tcp links for terminals
cpu0tta0 att "tcp:?port=8000"
# setup log files
cpu0tta0 set log "tt_dl0.log?crlf"
# mount disks
cpu0rka0 att unix_v5_rk.dsk
# and boot
#cpu0rka set trace 1
rw11::cpumon
rw11::cpucons
cpu0 boot rka0

15
rtl/vlib/rlink/rlinklib.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: rlinklib.vhd 495 2013-03-06 17:13:48Z mueller $
-- $Id: rlinklib.vhd 509 2013-04-21 20:46:20Z mueller $
--
-- Copyright 2007-2012 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -20,6 +20,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-04-21 509 3.3.2 add rlb_moni record definition
-- 2012-12-29 466 3.3.1 add rlink_rlbmux
-- 2011-12-23 444 3.3 CLK_CYCLE now integer
-- 2011-12-21 442 3.2.1 retire old, deprecated interfaces
@@ -100,6 +101,16 @@ end record rl_moni_type;
constant rl_moni_init : rl_moni_type :=
('0','0','0'); -- eop,attn,lamp
type rlb_moni_type is record -- rlink 8b monitor port
rxval : slbit; -- data in valid
rxhold : slbit; -- data in hold
txena : slbit; -- data out enable
txbusy : slbit; -- data out busy
end record rlb_moni_type;
constant rlb_moni_init : rlb_moni_type :=
('0','0','0','0'); -- rxval,rxhold,txena,txbusy
-- ise 13.1 xst can bug check if generic defaults in a package are defined via
-- 'slv(to_unsigned())'. The conv_ construct prior to numeric_std was ok.
-- As workaround the ibus default addresses are defined here as constant.