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Code Issues Releases Wiki Activity

- interim release w11a_V0.57 (untagged)

Browse Source 
- new C++ and Tcl based backend server supports now RK11 handling
- w11a systems operate with rlink over USB on nexsy2 and nexsy3 boards.
  See w11a_os_guide.txt for details
This commit is contained in:
Walter F.J. Mueller
2013-04-27 14:21:46 +00:00
parent 99de9893cb
commit b06cbef00a
105 changed files with 5202 additions and 593 deletions
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25
rtl/bplib/fx2rlink/Makefile Normal file
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# $Id: $
#
# Revision History:
# Date Rev Version Comment
# 2013-04-20 509 1.0 Initial version (cloned..)
#
VBOM_all = $(wildcard *.vbom)
NGC_all = $(VBOM_all:.vbom=.ngc)
#
include $(RETROBASE)/rtl/make/xflow_default_nexys2.mk
#
.PHONY : all clean
#
all : $(NGC_all)
#
clean : ise_clean
#
#----
#
include $(RETROBASE)/rtl/make/generic_xflow.mk
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_xst)
endif
#

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rtl/bplib/fx2rlink/fx2rlinklib.vbom Normal file
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# libs
../../vlib/slvtypes.vhd
../../vlib/rbus/rblib.vhd
../../vlib/rlink/rlinklib.vhd
../../vlib/serport/serportlib.vbom
../fx2lib/fx2lib.vhd
fx2rlinklib.vhd

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rtl/bplib/fx2rlink/fx2rlinklib.vhd Normal file
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-- $Id: $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: fx2rlinklib
-- Description: Definitions for rlink + fx2 interface combos
--
-- Dependencies: -
-- Tool versions: xst 13.3; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-04-20 509 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
use work.rlinklib.all;
use work.serportlib.all;
use work.fx2lib.all;
package fx2rlinklib is
--
-- core + fx2 interface combo
--
component rlink_sp1c_fx2 is -- rlink_core8+serport_1clk+fx2_ic combo
generic (
ATOWIDTH : positive := 5; -- access timeout counter width
ITOWIDTH : positive := 6; -- idle timeout counter width
CPREF : slv4 := c_rlink_cpref; -- comma prefix
IFAWIDTH : natural := 5; -- ser input fifo addr width (0=none)
OFAWIDTH : natural := 5; -- ser output fifo addr width (0=none)
PETOWIDTH : positive := 10; -- fx2 packet end time-out counter width
CCWIDTH : positive := 5; -- fx2 chunk counter width
ENAPIN_RLMON : integer := sbcntl_sbf_rlmon; -- SB_CNTL for rlmon (-1=none)
ENAPIN_RBMON : integer := sbcntl_sbf_rbmon; -- SB_CNTL for rbmon (-1=none)
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15); -- clk divider initial/reset setting
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable
CE_MSEC : in slbit; -- 1 msec clock enable
CE_INT : in slbit := '0'; -- rri ito time unit clock enable
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
ENAFX2 : in slbit; -- enable fx2 usage
RXSD : in slbit; -- receive serial data (board view)
TXSD : out slbit; -- transmit serial data (board view)
CTS_N : in slbit := '0'; -- clear to send (act.low, board view)
RTS_N : out slbit; -- request to send (act.low, board view)
RB_MREQ : out rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv3; -- rbus: status flags
RL_MONI : out rl_moni_type; -- rlink_core: monitor port
RLB_MONI : out rlb_moni_type; -- rlink 8b: monitor port
SER_MONI : out serport_moni_type; -- ser: monitor port
FX2_MONI : out fx2ctl_moni_type; -- fx2: monitor port
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end component;
component ioleds_sp1c_fx2 -- io activity leds for rlink_sp1c_fx2
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable
RESET : in slbit; -- reset
ENAFX2 : in slbit; -- enable fx2 usage
RB_SRES : in rb_sres_type; -- rbus: response
RLB_MONI : in rlb_moni_type; -- rlink 8b: monitor port
SER_MONI : in serport_moni_type; -- ser: monitor port
IOLEDS : out slv4 -- 4 bit IO monitor (e.g. for DSP_DP)
);
end component;
end package fx2rlinklib;

10
rtl/bplib/fx2rlink/ioleds_sp1c_fx2.vbom Normal file
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# libs
../../vlib/slvtypes.vhd
../../vlib/genlib/genlib.vhd
../../vlib/rbus/rblib.vhd
../../vlib/rlink/rlinklib.vbom
../../vlib/serport/serportlib.vbom
# components
../../vlib/genlib/led_pulse_stretch.vbom
# design
ioleds_sp1c_fx2.vhd

115
rtl/bplib/fx2rlink/ioleds_sp1c_fx2.vhd Normal file
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-- $Id: ioleds_sp1c_fx2.vhd 509 2013-04-21 20:46:20Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ioleds_sp1c_fx2 - syn
-- Description: io activity leds for rlink+serport_1clk+fx2_ic combo
--
-- Dependencies:
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-04-21 509 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.genlib.all;
use work.rblib.all;
use work.rlinklib.all;
use work.serportlib.all;
entity ioleds_sp1c_fx2 is -- io activity leds for rlink_sp1c_fx2
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable
RESET : in slbit; -- reset
ENAFX2 : in slbit; -- enable fx2 usage
RB_SRES : in rb_sres_type; -- rbus: response
RLB_MONI : in rlb_moni_type; -- rlink 8b: monitor port
SER_MONI : in serport_moni_type; -- ser: monitor port
IOLEDS : out slv4 -- 4 bit IO monitor (e.g. for DSP_DP)
);
end entity ioleds_sp1c_fx2;
architecture syn of ioleds_sp1c_fx2 is
signal R_LEDDIV : slv6 := (others=>'0'); -- clock divider for LED pulses
signal R_LEDCE : slbit := '0'; -- ce every 64 usec
signal TXENA_LED : slbit := '0';
signal RXVAL_LED : slbit := '0';
begin
RXVAL_PSTR : led_pulse_stretch
port map (
CLK => CLK,
CE_INT => R_LEDCE,
RESET => '0',
DIN => RLB_MONI.rxval,
POUT => RXVAL_LED
);
TXENA_PSTR : led_pulse_stretch
port map (
CLK => CLK,
CE_INT => R_LEDCE,
RESET => '0',
DIN => RLB_MONI.txena,
POUT => TXENA_LED
);
proc_leddiv: process (CLK)
begin
if rising_edge(CLK) then
R_LEDCE <= '0';
if CE_USEC = '1' then
R_LEDDIV <= slv(unsigned(R_LEDDIV) - 1);
if unsigned(R_LEDDIV) = 0 then
R_LEDCE <= '1';
end if;
end if;
end if;
end process proc_leddiv;
proc_ledmux : process (ENAFX2, SER_MONI, RLB_MONI, RB_SRES,
TXENA_LED, RXVAL_LED)
begin
if ENAFX2 = '0' then
IOLEDS(3) <= not SER_MONI.txok;
IOLEDS(2) <= SER_MONI.txact;
IOLEDS(1) <= not SER_MONI.rxok;
IOLEDS(0) <= SER_MONI.rxact;
else
IOLEDS(3) <= RB_SRES.busy;
IOLEDS(2) <= RLB_MONI.txbusy;
IOLEDS(1) <= TXENA_LED;
IOLEDS(0) <= RXVAL_LED;
end if;
end process proc_ledmux;
end syn;

13
rtl/bplib/fx2rlink/rlink_sp1c_fx2.vbom Normal file
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@@ -0,0 +1,13 @@
# libs
../../vlib/slvtypes.vhd
../../vlib/rbus/rblib.vhd
../../vlib/rlink/rlinklib.vbom
../../vlib/serport/serportlib.vbom
../fx2lib/fx2lib.vhd
# components
../../vlib/rlink/rlink_core8.vbom
../../vlib/serport/serport_1clock.vbom
../../vlib/rlink/rlink_rlbmux.vbom
../fx2lib/fx2_2fifoctl_ic.vbom
# design
rlink_sp1c_fx2.vhd

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rtl/bplib/fx2rlink/rlink_sp1c_fx2.vhd Normal file
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@@ -0,0 +1,227 @@
-- $Id: $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rlink_sp1c_fx2 - syn
-- Description: rlink_core8 + serport_1clock + fx2 combo
--
-- Dependencies: rlinklib/rlink_core8
-- serport/serport_1clock
-- rlinklib/rlink_rlbmux
-- fx2lib/fx2_2fifoctl_ic
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri ifa ofa
-- 2013-04-20 509 13.3 O76d xc3s1200e-4 441 903 128 637 s 8.7 - -
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-04-20 509 1.0 Initial version (derived from rlink_sp1c)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
use work.rlinklib.all;
use work.serportlib.all;
use work.fx2lib.all;
entity rlink_sp1c_fx2 is -- rlink_core8+serport_1clk+fx2_ic combo
generic (
ATOWIDTH : positive := 5; -- access timeout counter width
ITOWIDTH : positive := 6; -- idle timeout counter width
CPREF : slv4 := c_rlink_cpref; -- comma prefix
IFAWIDTH : natural := 5; -- ser input fifo addr width (0=none)
OFAWIDTH : natural := 5; -- ser output fifo addr width (0=none)
PETOWIDTH : positive := 10; -- fx2 packet end time-out counter width
CCWIDTH : positive := 5; -- fx2 chunk counter width
ENAPIN_RLMON : integer := sbcntl_sbf_rlmon; -- SB_CNTL for rlmon (-1=none)
ENAPIN_RBMON : integer := sbcntl_sbf_rbmon; -- SB_CNTL for rbmon (-1=none)
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15); -- clk divider initial/reset setting
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable
CE_MSEC : in slbit; -- 1 msec clock enable
CE_INT : in slbit := '0'; -- rri ito time unit clock enable
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
ENAFX2 : in slbit; -- enable fx2 usage
RXSD : in slbit; -- receive serial data (board view)
TXSD : out slbit; -- transmit serial data (board view)
CTS_N : in slbit := '0'; -- clear to send (act.low, board view)
RTS_N : out slbit; -- request to send (act.low, board view)
RB_MREQ : out rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv3; -- rbus: status flags
RL_MONI : out rl_moni_type; -- rlink_core: monitor port
RLB_MONI : out rlb_moni_type; -- rlink 8b: monitor port
SER_MONI : out serport_moni_type; -- ser: monitor port
FX2_MONI : out fx2ctl_moni_type; -- fx2: monitor port
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end entity rlink_sp1c_fx2;
architecture syn of rlink_sp1c_fx2 is
signal RLB_DI : slv8 := (others=>'0');
signal RLB_ENA : slbit := '0';
signal RLB_BUSY : slbit := '0';
signal RLB_DO : slv8 := (others=>'0');
signal RLB_VAL : slbit := '0';
signal RLB_HOLD : slbit := '0';
signal SER_RXDATA : slv8 := (others=>'0');
signal SER_RXVAL : slbit := '0';
signal SER_RXHOLD : slbit := '0';
signal SER_TXDATA : slv8 := (others=>'0');
signal SER_TXENA : slbit := '0';
signal SER_TXBUSY : slbit := '0';
signal FX2_RXDATA : slv8 := (others=>'0');
signal FX2_RXVAL : slbit := '0';
signal FX2_RXHOLD : slbit := '0';
signal FX2_RXAEMPTY : slbit := '0';
signal FX2_TXDATA : slv8 := (others=>'0');
signal FX2_TXENA : slbit := '0';
signal FX2_TXBUSY : slbit := '0';
signal FX2_TXAFULL : slbit := '0';
begin
CORE : rlink_core8
generic map (
ATOWIDTH => ATOWIDTH,
ITOWIDTH => ITOWIDTH,
CPREF => CPREF,
ENAPIN_RLMON => ENAPIN_RLMON,
ENAPIN_RBMON => ENAPIN_RBMON)
port map (
CLK => CLK,
CE_INT => CE_INT,
RESET => RESET,
RLB_DI => RLB_DI,
RLB_ENA => RLB_ENA,
RLB_BUSY => RLB_BUSY,
RLB_DO => RLB_DO,
RLB_VAL => RLB_VAL,
RLB_HOLD => RLB_HOLD,
RL_MONI => RL_MONI,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
SERPORT : serport_1clock
generic map (
CDWIDTH => CDWIDTH,
CDINIT => CDINIT,
RXFAWIDTH => IFAWIDTH,
TXFAWIDTH => OFAWIDTH)
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
RESET => RESET,
ENAXON => ENAXON,
ENAESC => ENAESC,
RXDATA => SER_RXDATA,
RXVAL => SER_RXVAL,
RXHOLD => SER_RXHOLD,
TXDATA => SER_TXDATA,
TXENA => SER_TXENA,
TXBUSY => SER_TXBUSY,
MONI => SER_MONI,
RXSD => RXSD,
TXSD => TXSD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
RLBMUX : rlink_rlbmux
port map (
SEL => ENAFX2,
RLB_DI => RLB_DI,
RLB_ENA => RLB_ENA,
RLB_BUSY => RLB_BUSY,
RLB_DO => RLB_DO,
RLB_VAL => RLB_VAL,
RLB_HOLD => RLB_HOLD,
P0_RXDATA => SER_RXDATA,
P0_RXVAL => SER_RXVAL,
P0_RXHOLD => SER_RXHOLD,
P0_TXDATA => SER_TXDATA,
P0_TXENA => SER_TXENA,
P0_TXBUSY => SER_TXBUSY,
P1_RXDATA => FX2_RXDATA,
P1_RXVAL => FX2_RXVAL,
P1_RXHOLD => FX2_RXHOLD,
P1_TXDATA => FX2_TXDATA,
P1_TXENA => FX2_TXENA,
P1_TXBUSY => FX2_TXBUSY
);
FX2CNTL : fx2_2fifoctl_ic
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
PETOWIDTH => PETOWIDTH,
CCWIDTH => CCWIDTH,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1)
port map (
CLK => CLK,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
RLB_MONI.rxval <= RLB_VAL;
RLB_MONI.rxhold <= RLB_HOLD;
RLB_MONI.txena <= RLB_ENA;
RLB_MONI.txbusy <= RLB_BUSY;
end syn;

4
rtl/bplib/nexys2/nexys2lib.vhd
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@@ -1,6 +1,6 @@
-- $Id: nexys2lib.vhd 467 2013-01-02 19:49:05Z mueller $
-- $Id: nexys2lib.vhd 509 2013-04-21 20:46:20Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2010-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free

4
rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vhd
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@@ -1,4 +1,4 @@
-- $Id: tb_nexys2_fusp_cuff.vhd 476 2013-01-26 22:23:53Z mueller $
-- $Id: tb_nexys2_fusp_cuff.vhd 509 2013-04-21 20:46:20Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -22,7 +22,7 @@
-- tb_nexys2_core
-- serport/serport_uart_rxtx
-- fx2lib/tb/fx2_2fifo_core
-- nexys2_fusp_aif [UUT]
-- nexys2_fusp_cuff_aif [UUT]
--
-- To test: generic, any nexys2_fusp_cuff_aif target
--

77
rtl/bplib/nexys3/nexys3lib.vhd
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@@ -1,6 +1,6 @@
-- $Id: nexys3lib.vhd 432 2011-11-25 20:16:28Z mueller $
-- $Id: nexys3lib.vhd 509 2013-04-21 20:46:20Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -20,6 +20,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-04-21 509 1.1 add nexys3_cuff_aif, nexys3_fusp_cuff_aif
-- 2011-11-25 432 1.0 Initial version
------------------------------------------------------------------------------
@@ -55,7 +56,7 @@ component nexys3_aif is -- NEXYS 3, abstract iface, base
);
end component;
component nexys3_fusp_aif is -- NEXYS 2, abstract iface, base+fusp
component nexys3_fusp_aif is -- NEXYS 3, abstract iface, base+fusp
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
@@ -84,4 +85,74 @@ component nexys3_fusp_aif is -- NEXYS 2, abstract iface, base+fusp
);
end component;
component nexys3_cuff_aif is -- NEXYS 3, abstract iface, base+cuff
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit; -- ppcm: ...
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end component;
component nexys3_fusp_cuff_aif is -- NEXYS 3, abstract iface, +fusp+cuff
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit; -- ppcm: ...
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit; -- fusp: rs232 tx
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end component;
end package nexys3lib;

7
rtl/bplib/nexys3/tb/.cvsignore
View File

@@ -1,7 +1,2 @@
tb_nexys3_dummy
tb_nexys3_fusp_dummy
tb_n3_cram_memctl_as
tb_n3_cram_memctl_as_[sft]sim
tb_n3_cram_memctl_as_ISim
tb_n3_cram_memctl_as_ISim_[sft]sim
tb_n3_cram_memctl_stim
tb_nexys3_fusp_cuff_dummy

5
rtl/bplib/nexys3/tb/Makefile
View File

@@ -1,10 +1,11 @@
# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $
# $Id: Makefile 509 2013-04-21 20:46:20Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-11-26 432 1.0 Initial version
#
EXE_all = tb_nexys3_fusp_dummy
EXE_all = tb_nexys3_fusp_dummy
EXE_all += tb_nexys3_fusp_cuff_dummy
#
include $(RETROBASE)/rtl/make/xflow_default_nexys3.mk
#

26
rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vbom Normal file
View File

@@ -0,0 +1,26 @@
# Not meant for direct top level usage. Used with
# tb_nexys3_fusp_cuff_(....)[_ssim].vbom and config
# lines to generate the different cases.
#
# libs
../../../vlib/slvtypes.vhd
../../../vlib/rlink/rlinklib.vbom
../../../vlib/rlink/tb/rlinktblib.vhd
../../../vlib/serport/serportlib.vbom
../../../vlib/xlib/xlib.vhd
../nexys3lib.vhd
../../../vlib/simlib/simlib.vhd
../../../vlib/simlib/simbus.vhd
${sys_conf := sys_conf_sim.vhd}
# components
../../../vlib/simlib/simclk.vbom
../../../vlib/simlib/simclkcnt.vbom
../../../vlib/rlink/tb/tbcore_rlink.vbom
../../../vlib/xlib/dcm_sfs_gsim.vbom
tb_nexys3_core.vbom
../../../vlib/serport/serport_uart_rxtx.vbom
../../../bplib/fx2lib/tb/fx2_2fifo_core.vbom
${nexys3_fusp_cuff_aif := nexys3_fusp_cuff_dummy.vbom}
# design
tb_nexys3_fusp_cuff.vhd
@top:tb_nexys3_fusp_cuff

331
rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vhd Normal file
View File

@@ -0,0 +1,331 @@
-- $Id: tb_nexys3_fusp_cuff.vhd 509 2013-04-21 20:46:20Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys3_fusp_cuff - sim
-- Description: Test bench for nexys3 (base+fusp+cuff)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- xlib/dcm_sfs
-- rlink/tb/tbcore_rlink
-- tb_nexys3_core
-- serport/serport_uart_rxtx
-- fx2lib/tb/fx2_2fifo_core
-- nexys3_fusp_cuff_aif [UUT]
--
-- To test: generic, any nexys3_fusp_cuff_aif target
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-04-21 509 1.0 Initial version (derived from tb_nexys3_fusp and
-- tb_nexys2_fusp_cuff)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.rlinktblib.all;
use work.serportlib.all;
use work.xlib.all;
use work.nexys3lib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_nexys3_fusp_cuff is
end tb_nexys3_fusp_cuff;
architecture sim of tb_nexys3_fusp_cuff is
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
signal CLK_STOP : slbit := '0';
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal TBC_RXDATA : slv8 := (others=>'0');
signal TBC_RXVAL : slbit := '0';
signal TBC_RXHOLD : slbit := '0';
signal TBC_TXDATA : slv8 := (others=>'0');
signal TBC_TXENA : slbit := '0';
signal UART_RXDATA : slv8 := (others=>'0');
signal UART_RXVAL : slbit := '0';
signal UART_RXERR : slbit := '0';
signal UART_RXACT : slbit := '0';
signal UART_TXDATA : slv8 := (others=>'0');
signal UART_TXENA : slbit := '0';
signal UART_TXBUSY : slbit := '0';
signal FX2_RXDATA : slv8 := (others=>'0');
signal FX2_RXENA : slbit := '0';
signal FX2_RXBUSY : slbit := '0';
signal FX2_TXDATA : slv8 := (others=>'0');
signal FX2_TXVAL : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv5 := (others=>'0');
signal O_LED : slv8 := (others=>'0');
signal O_ANO_N : slv4 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal O_MEM_CE_N : slbit := '1';
signal O_MEM_BE_N : slv2 := (others=>'1');
signal O_MEM_WE_N : slbit := '1';
signal O_MEM_OE_N : slbit := '1';
signal O_MEM_ADV_N : slbit := '1';
signal O_MEM_CLK : slbit := '0';
signal O_MEM_CRE : slbit := '0';
signal I_MEM_WAIT : slbit := '0';
signal O_MEM_ADDR : slv23 := (others=>'Z');
signal IO_MEM_DATA : slv16 := (others=>'0');
signal O_PPCM_CE_N : slbit := '0';
signal O_PPCM_RST_N : slbit := '0';
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
signal I_FX2_IFCLK : slbit := '0';
signal O_FX2_FIFO : slv2 := (others=>'0');
signal I_FX2_FLAG : slv4 := (others=>'0');
signal O_FX2_SLRD_N : slbit := '1';
signal O_FX2_SLWR_N : slbit := '1';
signal O_FX2_SLOE_N : slbit := '1';
signal O_FX2_PKTEND_N : slbit := '1';
signal IO_FX2_DATA : slv8 := (others=>'Z');
signal UART_RESET : slbit := '0';
signal UART_RXD : slbit := '1';
signal UART_TXD : slbit := '1';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal R_PORTSEL_SER : slbit := '0'; -- if 1 use alternate serport
signal R_PORTSEL_FX2 : slbit := '0'; -- if 1 use fx2
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : time := 10 ns;
constant clock_offset : time := 200 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC,
CLK_STOP => CLK_STOP
);
SB_CLKSTOP <= CLK_STOP;
DCM_COM : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 10.0)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : tbcore_rlink
port map (
CLK => CLKCOM,
CLK_STOP => CLK_STOP,
RX_DATA => TBC_RXDATA,
RX_VAL => TBC_RXVAL,
RX_HOLD => TBC_RXHOLD,
TX_DATA => TBC_TXDATA,
TX_ENA => TBC_TXENA
);
N3CORE : entity work.tb_nexys3_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
UUT : nexys3_fusp_cuff_aif
port map (
I_CLK100 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA,
O_PPCM_CE_N => O_PPCM_CE_N,
O_PPCM_RST_N => O_PPCM_RST_N,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
UART : serport_uart_rxtx
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => UART_RESET,
CLKDIV => CLKDIV,
RXSD => UART_RXD,
RXDATA => UART_RXDATA,
RXVAL => UART_RXVAL,
RXERR => UART_RXERR,
RXACT => UART_RXACT,
TXSD => UART_TXD,
TXDATA => UART_TXDATA,
TXENA => UART_TXENA,
TXBUSY => UART_TXBUSY
);
FX2 : entity work.fx2_2fifo_core
port map (
CLK => CLKCOM,
RESET => '0',
RXDATA => FX2_RXDATA,
RXENA => FX2_RXENA,
RXBUSY => FX2_RXBUSY,
TXDATA => FX2_TXDATA,
TXVAL => FX2_TXVAL,
IFCLK => I_FX2_IFCLK,
FIFO => O_FX2_FIFO,
FLAG => I_FX2_FLAG,
SLRD_N => O_FX2_SLRD_N,
SLWR_N => O_FX2_SLWR_N,
SLOE_N => O_FX2_SLOE_N,
PKTEND_N => O_FX2_PKTEND_N,
DATA => IO_FX2_DATA
);
proc_fx2_mux: process (R_PORTSEL_FX2, TBC_RXDATA, TBC_RXVAL,
UART_TXBUSY, RTS_N, UART_RXDATA, UART_RXVAL,
FX2_RXBUSY, FX2_TXDATA, FX2_TXVAL
)
begin
if R_PORTSEL_FX2 = '0' then -- use serport
UART_TXDATA <= TBC_RXDATA;
UART_TXENA <= TBC_RXVAL;
TBC_RXHOLD <= UART_TXBUSY or RTS_N;
TBC_TXDATA <= UART_RXDATA;
TBC_TXENA <= UART_RXVAL;
else -- otherwise use fx2
FX2_RXDATA <= TBC_RXDATA;
FX2_RXENA <= TBC_RXVAL;
TBC_RXHOLD <= FX2_RXBUSY;
TBC_TXDATA <= FX2_TXDATA;
TBC_TXENA <= FX2_TXVAL;
end if;
end process proc_fx2_mux;
proc_ser_mux: process (R_PORTSEL_SER, UART_TXD, CTS_N,
O_TXD, O_FUSP_TXD, O_FUSP_RTS_N)
begin
if R_PORTSEL_SER = '0' then -- use main board rs232, no flow cntl
I_RXD <= UART_TXD; -- write port 0 inputs
UART_RXD <= O_TXD; -- get port 0 outputs
RTS_N <= '0';
I_FUSP_RXD <= '1'; -- port 1 inputs to idle state
I_FUSP_CTS_N <= '0';
else -- otherwise use pmod1 rs232
I_FUSP_RXD <= UART_TXD; -- write port 1 inputs
I_FUSP_CTS_N <= CTS_N;
UART_RXD <= O_FUSP_TXD; -- get port 1 outputs
RTS_N <= O_FUSP_RTS_N;
I_RXD <= '1'; -- port 0 inputs to idle state
end if;
end process proc_ser_mux;
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
if UART_RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen UART_RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_SER <= to_x01(SB_DATA(0));
R_PORTSEL_FX2 <= to_x01(SB_DATA(1));
end if;
end if;
end process proc_simbus;
end sim;