diff --git a/doc/CHANGELOG.md b/doc/CHANGELOG.md index c4ddcb45..baa5505d 100644 --- a/doc/CHANGELOG.md +++ b/doc/CHANGELOG.md @@ -34,6 +34,7 @@ The full set of tests is only run for tagged releases. - sys_w11a_arty: w11a with full 3840 MB memory - for Digilent Nexys4 DDR - sys_tst_mig_n4d: low level MIG interface test + - sys_tst_sram_n4d: memory test - new components - s7_cmt_sfs_2: dual-channel frequency synthesis MMCM/PLL wrapper - s7_cmt_1ce1ce2c: clocking block for 7-Series: 2 clk+CEs + 2 clk diff --git a/rtl/sys_gen/tst_sram/nexys4d/Makefile b/rtl/sys_gen/tst_sram/nexys4d/Makefile new file mode 100644 index 00000000..568a8a17 --- /dev/null +++ b/rtl/sys_gen/tst_sram/nexys4d/Makefile @@ -0,0 +1,25 @@ +# $Id: Makefile 1099 2018-12-31 09:07:36Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2018-12-30 1099 1.0 Initial version +# +VBOM_all = sys_tst_sram_n4d.vbom +BIT_all = $(VBOM_all:.vbom=.bit) +# +include ${RETROBASE}/rtl/make_viv/viv_default_nexys4d.mk +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : viv_clean +# +#---- +# +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +endif +# diff --git a/rtl/sys_gen/tst_sram/nexys4d/sys_conf.vhd b/rtl/sys_gen/tst_sram/nexys4d/sys_conf.vhd new file mode 100644 index 00000000..9df37a6c --- /dev/null +++ b/rtl/sys_gen/tst_sram/nexys4d/sys_conf.vhd @@ -0,0 +1,59 @@ +-- $Id: sys_conf.vhd 1099 2018-12-31 09:07:36Z mueller $ +-- +-- Copyright 2018- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 3, or (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_sram_n4d (for synthesis) +-- +-- Dependencies: - +-- Tool versions: viv 2017.2; ghdl 0.34 +-- Revision History: +-- Date Rev Version Comment +-- 2018-12-30 1099 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 1; -- vco --- MHz + constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + -- dual clock design, clkser = 120 MHz + constant sys_conf_clkser_vcodivide : positive := 1; + constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz + constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz + constant sys_conf_clkser_gentype : string := "PLL"; + + constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud + + -- derived constants + + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_clkser : integer := + ((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) / + sys_conf_clkser_outdivide; + constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000; + + constant sys_conf_ser2rri_cdinit : integer := + (sys_conf_clkser/sys_conf_ser2rri_defbaud)-1; + +end package sys_conf; diff --git a/rtl/sys_gen/tst_sram/nexys4d/sys_tst_sram_n4d.vbom b/rtl/sys_gen/tst_sram/nexys4d/sys_tst_sram_n4d.vbom new file mode 100644 index 00000000..6b8ba198 --- /dev/null +++ b/rtl/sys_gen/tst_sram/nexys4d/sys_tst_sram_n4d.vbom @@ -0,0 +1,28 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/cdclib/cdclib.vhd +../../../vlib/serport/serportlib.vbom +../../../vlib/rbus/rblib.vhd +../../../vlib/rbus/rbdlib.vhd +../../../vlib/rlink/rlinklib.vbom +../../../bplib/bpgen/bpgenlib.vbom +../../../bplib/sysmon/sysmonrbuslib.vbom +../../../bplib/s3board/s3boardlib.vbom +../../../bplib/mig/miglib.vbom +../../../bplib/nexys4d/miglib_nexys4d.vbom +${sys_conf := sys_conf.vhd} +# components +../../../bplib/bpgen/s7_cmt_1ce1ce2c.vbom +../../../vlib/cdclib/cdc_signal_s1_as.vbom +../../../bplib/bpgen/bp_rs232_4line_iob.vbom +../../../bplib/bpgen/sn_humanio.vbom +../../../vlib/rlink/rlink_sp2c.vbom +../tst_sram.vbom +../../../bplib/nexys4d/sramif_mig_nexys4d.vbom +../../../bplib/sysmon/sysmonx_rbus_base.vbom +../../../vlib/rbus/rbd_usracc.vbom +../../../vlib/rbus/rb_sres_or_3.vbom +# design +sys_tst_sram_n4d.vhd +@xdc:../../../bplib/nexys4d/nexys4d_pclk.xdc +@xdc:../../../bplib/nexys4d/nexys4d_pins.xdc diff --git a/rtl/sys_gen/tst_sram/nexys4d/sys_tst_sram_n4d.vhd b/rtl/sys_gen/tst_sram/nexys4d/sys_tst_sram_n4d.vhd new file mode 100644 index 00000000..f1becd24 --- /dev/null +++ b/rtl/sys_gen/tst_sram/nexys4d/sys_tst_sram_n4d.vhd @@ -0,0 +1,400 @@ +-- $Id: sys_tst_sram_n4d.vhd 1101 2019-01-02 21:22:37Z mueller $ +-- +-- Copyright 2018-2019 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 3, or (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_tst_sram_n4d - syn +-- Description: test of nexys4d ddr and its mig controller +-- +-- Dependencies: bplib/bpgen/s7_cmt_1ce1ce2c +-- cdclib/cdc_signal_s1_as +-- bplib/bpgen/bp_rs232_4line_iob +-- bplib/bpgen/sn_humanio +-- vlib/rlink/rlink_sp2c +-- tst_sram +-- bplib/nexyx4d/sramif_mig_nexys4d +-- bplib/sysmon/sysmonx_rbus_base +-- vlib/rbus/rbd_usracc +-- vlib/rbus/rb_sres_or_3 +-- +-- Test bench: tb/tb_tst_sram_n4d +-- +-- Target Devices: generic +-- Tool versions: viv 2017.2; ghdl 0.34 +-- +-- Synthesized: +-- Date Rev viv Target flop lutl lutm bram slic +-- 2019-01-02 1101 2017.2 xc7a100t-1 4403 4900 640 5 1983 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2019-01-02 1101 1.0 Initial version +-- 2018-12-30 1099 0.1 First draft (derived from sys_tst_sram_n4/arty) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.cdclib.all; +use work.serportlib.all; +use work.rblib.all; +use work.rbdlib.all; +use work.rlinklib.all; +use work.bpgenlib.all; +use work.sysmonrbuslib.all; +use work.s3boardlib.all; +use work.miglib.all; +use work.miglib_nexys4d.all; +use work.sys_conf.all; + +library unisim; +use unisim.vcomponents.ALL; + +-- ---------------------------------------------------------------------------- + +entity sys_tst_sram_n4d is -- top level + -- implements nexys4d_mig_aif + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + O_RTS_N : out slbit; -- rx rts (board view; act.low) + I_CTS_N : in slbit; -- tx cts (board view; act.low) + I_SWI : in slv16; -- n4 switches + I_BTN : in slv5; -- n4 buttons + I_BTNRST_N : in slbit; -- n4 reset button + O_LED : out slv16; -- n4 leds + O_RGBLED0 : out slv3; -- n4 rgb-led 0 + O_RGBLED1 : out slv3; -- n4 rgb-led 1 + O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + DDR2_DQ : inout slv16; -- dram: data in/out + DDR2_DQS_P : inout slv2; -- dram: data strobe (diff-p) + DDR2_DQS_N : inout slv2; -- dram: data strobe (diff-n) + DDR2_ADDR : out slv13; -- dram: address + DDR2_BA : out slv3; -- dram: bank address + DDR2_RAS_N : out slbit; -- dram: row addr strobe (act.low) + DDR2_CAS_N : out slbit; -- dram: column addr strobe (act.low) + DDR2_WE_N : out slbit; -- dram: write enable (act.low) + DDR2_CK_P : out slv1; -- dram: clock (diff-p) + DDR2_CK_N : out slv1; -- dram: clock (diff-n) + DDR2_CKE : out slv1; -- dram: clock enable + DDR2_CS_N : out slv1; -- dram: chip select (act.low) + DDR2_DM : out slv2; -- dram: data input mask + DDR2_ODT : out slv1 -- dram: on-die termination + ); +end sys_tst_sram_n4d; + +architecture syn of sys_tst_sram_n4d is + + signal CLK100_BUF : slbit := '0'; + + signal CLK : slbit := '0'; + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal CLKS : slbit := '0'; + signal CES_MSEC : slbit := '0'; + + signal CLKMIG : slbit := '0'; + signal CLKREF : slbit := '0'; + + signal LOCKED : slbit := '0'; -- raw LOCKED + signal LOCKED_CLK : slbit := '0'; -- sync'ed to CLKMIG + + signal GBL_RESET : slbit := '0'; + signal MEM_RESET : slbit := '0'; + signal MEM_RESET_RRI : slbit := '0'; + + signal RXD : slbit := '1'; + signal TXD : slbit := '0'; + signal CTS_N : slbit := '0'; + signal RTS_N : slbit := '0'; + + signal SWI : slv16 := (others=>'0'); + signal BTN : slv5 := (others=>'0'); + signal LED : slv16 := (others=>'0'); + signal DSP_DAT : slv32 := (others=>'0'); + signal DSP_DP : slv8 := (others=>'0'); + + signal RB_MREQ : rb_mreq_type := rb_mreq_init; + signal RB_SRES : rb_sres_type := rb_sres_init; + signal RB_LAM : slv16 := (others=>'0'); + signal RB_STAT : slv4 := (others=>'0'); + + signal SER_MONI : serport_moni_type := serport_moni_init; + + signal RB_SRES_TST : rb_sres_type := rb_sres_init; + signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init; + signal RB_SRES_USRACC : rb_sres_type := rb_sres_init; + + signal RB_LAM_TST : slbit := '0'; + + signal MEM_REQ : slbit := '0'; + signal MEM_WE : slbit := '0'; + signal MEM_BUSY : slbit := '0'; + signal MEM_ACK_R : slbit := '0'; + signal MEM_ACK_W : slbit := '0'; + signal MEM_ACT_R : slbit := '0'; + signal MEM_ACT_W : slbit := '0'; + signal MEM_ADDR : slv20 := (others=>'0'); + signal MEM_BE : slv4 := (others=>'0'); + signal MEM_DI : slv32 := (others=>'0'); + signal MEM_DO : slv32 := (others=>'0'); + + signal MIG_MONI : sramif2migui_moni_type := sramif2migui_moni_init; + signal XADC_TEMP : slv12 := (others=>'0'); -- xadc die temp; on CLK + + constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx + + constant sysid_proj : slv16 := x"0104"; -- tst_sram + constant sysid_board : slv8 := x"08"; -- nexys4d + constant sysid_vers : slv8 := x"00"; + +begin + + CLK100_BUFG: bufg + port map ( + I => I_CLK100, + O => CLK100_BUF + ); + + GEN_CLKALL : s7_cmt_1ce1ce2c -- clock generator system ------------ + generic map ( + CLKIN_PERIOD => 10.0, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + CLK0_VCODIV => sys_conf_clksys_vcodivide, + CLK0_VCOMUL => sys_conf_clksys_vcomultiply, + CLK0_OUTDIV => sys_conf_clksys_outdivide, + CLK0_GENTYPE => sys_conf_clksys_gentype, + CLK0_CDUWIDTH => 7, + CLK0_USECDIV => sys_conf_clksys_mhz, + CLK0_MSECDIV => 1000, + CLK1_VCODIV => sys_conf_clkser_vcodivide, + CLK1_VCOMUL => sys_conf_clkser_vcomultiply, + CLK1_OUTDIV => sys_conf_clkser_outdivide, + CLK1_GENTYPE => sys_conf_clkser_gentype, + CLK1_CDUWIDTH => 7, + CLK1_USECDIV => sys_conf_clkser_mhz, + CLK1_MSECDIV => 1000, + CLK23_VCODIV => 1, + CLK23_VCOMUL => 12, -- vco 1200 MHz + CLK2_OUTDIV => 8, -- mig sys 150.0 MHz + CLK3_OUTDIV => 6, -- mig ref 200.0 MHz + CLK23_GENTYPE => "PLL") + port map ( + CLKIN => CLK100_BUF, + CLK0 => CLK, + CE0_USEC => CE_USEC, + CE0_MSEC => CE_MSEC, + CLK1 => CLKS, + CE1_USEC => open, + CE1_MSEC => CES_MSEC, + CLK2 => CLKMIG, + CLK3 => CLKREF, + LOCKED => LOCKED + ); + + CDC_CLK_LOCKED : cdc_signal_s1_as + port map ( + CLKO => CLKMIG, + DI => LOCKED, + DO => LOCKED_CLK + ); + + IOB_RS232 : bp_rs232_4line_iob + port map ( + CLK => CLKS, + RXD => RXD, + TXD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + I_RXD => I_RXD, + O_TXD => O_TXD, + I_CTS_N => I_CTS_N, + O_RTS_N => O_RTS_N + ); + + HIO : sn_humanio + generic map ( + SWIDTH => 16, + BWIDTH => 5, + LWIDTH => 16, + DCWIDTH => 3) + port map ( + CLK => CLK, + RESET => '0', + CE_MSEC => CE_MSEC, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + RLINK : rlink_sp2c + generic map ( + BTOWIDTH => 6, -- 64 cycles access timeout + RTAWIDTH => 12, + SYSID => sysid_proj & sysid_board & sysid_vers, + IFAWIDTH => 5, -- 32 word input fifo + OFAWIDTH => 5, -- 32 word output fifo + ENAPIN_RLMON => sbcntl_sbf_rlmon, + ENAPIN_RBMON => sbcntl_sbf_rbmon, + CDWIDTH => 12, + CDINIT => sys_conf_ser2rri_cdinit, + RBMON_AWIDTH => 0, + RBMON_RBADDR => x"ffe8") + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + CE_INT => CE_MSEC, + RESET => GBL_RESET, + CLKS => CLKS, + CES_MSEC => CES_MSEC, + ENAXON => SWI(1), + ESCFILL => '0', + RXSD => RXD, + TXSD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT, + RL_MONI => open, + SER_MONI => SER_MONI + ); + + TST : entity work.tst_sram + generic map ( + RB_ADDR => slv(to_unsigned(2#0000000000000000#,16)), + AWIDTH => 18) + port map ( + CLK => CLK, + RESET => GBL_RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_TST, + RB_STAT => RB_STAT, + RB_LAM => RB_LAM_TST, + SWI => SWI(7 downto 0), + BTN => BTN(3 downto 0), + LED => LED(7 downto 0), + DSP_DAT => DSP_DAT(15 downto 0), + MEM_RESET => MEM_RESET_RRI, + MEM_REQ => MEM_REQ, + MEM_WE => MEM_WE, + MEM_BUSY => MEM_BUSY, + MEM_ACK_R => MEM_ACK_R, + MEM_ACK_W => MEM_ACK_W, + MEM_ACT_R => MEM_ACT_R, + MEM_ACT_W => MEM_ACT_W, + MEM_ADDR => MEM_ADDR(17 downto 0), -- ?? FIXME ?? allow AWIDTH=20 + MEM_BE => MEM_BE, + MEM_DI => MEM_DI, + MEM_DO => MEM_DO + ); + + MEM_ADDR(19 downto 18) <= (others=>'0'); --?? FIXME ?? allow AWIDTH=20 + + MEM_RESET <= not LOCKED_CLK or MEM_RESET_RRI; + + MEMCTL: sramif_mig_nexys4d -- SRAM to MIG iface ----------------- + port map ( + CLK => CLK, + RESET => MEM_RESET, + REQ => MEM_REQ, + WE => MEM_WE, + BUSY => MEM_BUSY, + ACK_R => MEM_ACK_R, + ACK_W => MEM_ACK_W, + ACT_R => MEM_ACT_R, + ACT_W => MEM_ACT_W, + ADDR => MEM_ADDR, + BE => MEM_BE, + DI => MEM_DI, + DO => MEM_DO, + CLKMIG => CLKMIG, + CLKREF => CLKREF, + TEMP => XADC_TEMP, + MONI => MIG_MONI, + DDR2_DQ => DDR2_DQ, + DDR2_DQS_P => DDR2_DQS_P, + DDR2_DQS_N => DDR2_DQS_N, + DDR2_ADDR => DDR2_ADDR, + DDR2_BA => DDR2_BA, + DDR2_RAS_N => DDR2_RAS_N, + DDR2_CAS_N => DDR2_CAS_N, + DDR2_WE_N => DDR2_WE_N, + DDR2_CK_P => DDR2_CK_P, + DDR2_CK_N => DDR2_CK_N, + DDR2_CKE => DDR2_CKE, + DDR2_CS_N => DDR2_CS_N, + DDR2_DM => DDR2_DM, + DDR2_ODT => DDR2_ODT + ); + + SMRB : sysmonx_rbus_base + generic map ( -- use default INIT_ (Vccint=1.00) + CLK_MHZ => sys_conf_clksys_mhz, + RB_ADDR => rbaddr_sysmon) + port map ( + CLK => CLK, + RESET => GBL_RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_SYSMON, + ALM => open, + OT => open, + TEMP => XADC_TEMP + ); + + UARB : rbd_usracc + port map ( + CLK => CLK, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_USRACC + ); + + RB_SRES_OR : rb_sres_or_3 -- rbus or --------------------------- + port map ( + RB_SRES_1 => RB_SRES_TST, + RB_SRES_2 => RB_SRES_SYSMON, + RB_SRES_3 => RB_SRES_USRACC, + RB_SRES_OR => RB_SRES + ); + + RB_LAM(0) <= RB_LAM_TST; + + DSP_DP(3) <= not SER_MONI.txok; + DSP_DP(2) <= SER_MONI.txact; + DSP_DP(1) <= not SER_MONI.rxok; + DSP_DP(0) <= SER_MONI.rxact; + + DSP_DP(7 downto 4) <= "0010"; + DSP_DAT(31 downto 16) <= SER_MONI.abclkdiv(11 downto 0) & + '0' & SER_MONI.abclkdiv_f; + + -- setup unused outputs in nexys4 + O_RGBLED0 <= (others=>'0'); + O_RGBLED1 <= (others=>not I_BTNRST_N); + +end syn; + diff --git a/rtl/sys_gen/tst_sram/nexys4d/sys_tst_sram_n4d.vmfset b/rtl/sys_gen/tst_sram/nexys4d/sys_tst_sram_n4d.vmfset new file mode 100644 index 00000000..d48fba86 --- /dev/null +++ b/rtl/sys_gen/tst_sram/nexys4d/sys_tst_sram_n4d.vmfset @@ -0,0 +1,70 @@ +# $Id: sys_tst_sram_n4d.vmfset 1101 2019-01-02 21:22:37Z mueller $ +# +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[syn] +# general issues ----------------------------------------------- +{2018.2:} +# stupid new warning, Xilinx suggests to safely ingnore +i [Constraints 18-5210] # generic +{:} + +# false_path -hold ignored by synth ---------------------------- +I [Designutils 20-1567] # generic + +# port driven by constant -------------------------------------- +i [Synth 8-3917] O_RGBLED0[\d] # OK 2019-01-02 + +# tying undriven pin to constant ------------------------------- +# upper 8 LEDs unused # OK 2019-01-02 +i [Synth 8-3295] HIO:LED[\d*] +# only few LAMs used # OK 2019-01-02 +i [Synth 8-3295] RLINK:RB_LAM[\d*] + +# unconnected ports -------------------------------------------- +I [Synth 8-3331] RB_MREQ # generic +# --> MEM_ACK_W not used by current tst_sram # OK 2019-01-02 +i [Synth 8-3331] tst_sram.*MEM_ACK_W +# --> rlink_sp2c doesn't use CE_USEC and CE_MSEC # OK 2019-01-02 +i [Synth 8-3331] rlink_sp2c.*CE_(USEC|MSEC) +# --> data end marker not used # OK 2019-01-02 +i [Synth 8-3331] sramif2migui_core .*APP_RD_DATA_END + +# sequential element removed (2017.1 nonsense) ----------------- +I [Synth 8-6014] _reg # generic + +# unused sequential element ------------------------------------ +I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic +# --> only 18 bit address # OK 2019-01-02 +i [Synth 8-3332] R_REGS_reg[wrtag][1(6|7)].* sramif2migui_core +i [Synth 8-3332] R_REGS_reg[rdtag][1(6|7)].* sramif2migui_core +i [Synth 8-3332] R_REGS_reg[req_addr][1(8|9)].* sramif2migui_core +# --> rdnew only used in MONI, that not used in tst_sram # OK 2019-01-02 +i [Synth 8-3332] R_REGS_reg[rdnew].* sramif2migui_core +# --> many HIO pins not used # OK 2019-01-02 +i [Synth 8-3332] HIO/IOB_LED/R_DO_reg[\d*] +i [Synth 8-3332] HIO/IOB_(SWI|BTN)/R_DI_reg[\d*] +i [Synth 8-3332] HIO/DEB.DEB_(SWI|BTN)/R_REGS_reg[(dref|dout|dchange)][\d*] + +# --> monitor outputs moneop,monattn currently not used # OK 2019-01-02 +i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[moneop] +i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[monattn] +# --> only RB_STAT 0,1 used by tst_sram # OK 2019-01-02 +i [Synth 8-3332] RLINK/CORE/RL/R_BREGS_reg[stat][(2|3)] +# --> CE_USEC isn't used (also not in rlink_sp2c) # OK 2019-01-02 +i [Synth 8-3332] CLKALL/DIV_CLK0/R_REGS_reg[usec] +# --> CES_USEC isn't used # OK 2019-01-02 +i [Synth 8-3332] GEN_CLKALL/DIV_CLK1/R_REGS_reg[usec] + +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[imp] +I [Vivado 12-2489] # multiple of 1 ps +I [Physopt 32-742] # BRAM Flop Optimization +{:2017.2} +# --> spurious Invalid VCCINTIO messages # OK 2019-01-02 +i [Designutils 20-266] Invalid Voltage Source VCCINTIO +{:} + +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[bit] +# see https://www.xilinx.com/support/answers/64180.html # OK 2019-01-02 +i [DRC REQP-1709] PLLE2_ADV diff --git a/rtl/sys_gen/tst_sram/nexys4d/tb/.gitignore b/rtl/sys_gen/tst_sram/nexys4d/tb/.gitignore new file mode 100644 index 00000000..e443445e --- /dev/null +++ b/rtl/sys_gen/tst_sram/nexys4d/tb/.gitignore @@ -0,0 +1,2 @@ +tb_tst_sram_n4d +sysmon_stim diff --git a/rtl/sys_gen/tst_sram/nexys4d/tb/Makefile b/rtl/sys_gen/tst_sram/nexys4d/tb/Makefile new file mode 100644 index 00000000..7151d4e3 --- /dev/null +++ b/rtl/sys_gen/tst_sram/nexys4d/tb/Makefile @@ -0,0 +1,39 @@ +# $Id: Makefile 1099 2018-12-31 09:07:36Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2018-12-30 1099 1.0 Initial version +# +EXE_all = tb_tst_sram_n4d +# +include ${RETROBASE}/rtl/make_viv/viv_default_nexys4d.mk +# +.PHONY : all all_ssim all_osim clean +.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_osim : $(EXE_all:=_osim) +# +all_XSim : $(EXE_all:=_XSim) +all_XSim_ssim : $(EXE_all:=_XSim_ssim) +all_XSim_osim : $(EXE_all:=_XSim_osim) +all_XSim_tsim : $(EXE_all:=_XSim_tsim) +# +clean : viv_clean ghdl_clean xsim_clean +# +#----- +# +include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk +include ${RETROBASE}/rtl/make_viv/generic_xsim.mk +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(VBOM_all:.vbom=.dep_vsim) +include $(wildcard *.o.dep_ghdl) +endif +# diff --git a/rtl/sys_gen/tst_sram/nexys4d/tb/sys_conf_sim.vhd b/rtl/sys_gen/tst_sram/nexys4d/tb/sys_conf_sim.vhd new file mode 100644 index 00000000..109dee05 --- /dev/null +++ b/rtl/sys_gen/tst_sram/nexys4d/tb/sys_conf_sim.vhd @@ -0,0 +1,56 @@ +-- $Id: sys_conf_sim.vhd 1099 2018-12-31 09:07:36Z mueller $ +-- +-- Copyright 2018- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 3, or (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_sram_n4d (for simulation) +-- +-- Dependencies: - +-- Tool versions: viv 2017.2; ghdl 0.34 +-- Revision History: +-- Date Rev Version Comment +-- 2018-12-30 1099 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 1; -- vco --- MHz + constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + -- dual clock design, clkser = 120 MHz + constant sys_conf_clkser_vcodivide : positive := 1; + constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz + constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz + constant sys_conf_clkser_gentype : string := "PLL"; + + constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim + + -- derived constants + + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_clkser : integer := + ((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) / + sys_conf_clkser_outdivide; + constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000; + +end package sys_conf; diff --git a/rtl/sys_gen/tst_sram/nexys4d/tb/tb_tst_sram_n4d.vbom b/rtl/sys_gen/tst_sram/nexys4d/tb/tb_tst_sram_n4d.vbom new file mode 100644 index 00000000..21293359 --- /dev/null +++ b/rtl/sys_gen/tst_sram/nexys4d/tb/tb_tst_sram_n4d.vbom @@ -0,0 +1,9 @@ +# configure tb_nexsy4d_dram with sys_tst_sram_n4d target; +# use vhdl configure file (tb_tst_sram_n4d.vhd) to allow +# that all configurations will co-exist in work library +# configure +nexys4d_dram_aif = ../sys_tst_sram_n4d.vbom +sys_conf = sys_conf_sim.vhd +# design +../../../../bplib/nexys4d/tb/tb_nexys4d_dram.vbom +tb_tst_sram_n4d.vhd diff --git a/rtl/sys_gen/tst_sram/nexys4d/tb/tb_tst_sram_n4d.vhd b/rtl/sys_gen/tst_sram/nexys4d/tb/tb_tst_sram_n4d.vhd new file mode 100644 index 00000000..235a4d52 --- /dev/null +++ b/rtl/sys_gen/tst_sram/nexys4d/tb/tb_tst_sram_n4d.vhd @@ -0,0 +1,39 @@ +-- $Id: tb_tst_sram_n4d.vhd 1099 2018-12-31 09:07:36Z mueller $ +-- +-- Copyright 2018- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 3, or (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_tst_sram_n4d +-- Description: Configuration for tb_tst_sram_n4d for tb_nexys4d_dram +-- +-- Dependencies: sys_tst_sram_n4d +-- +-- To test: sys_tst_sram_n4d +-- +-- Verified: +-- Date Rev Code ghdl ise Target Comment +-- 2013-??-?? 534 - 0.29 13.1 O40d xc6slx16 ??? +-- +-- Revision History: +-- Date Rev Version Comment +-- 2018-12-30 1099 1.0 Initial version +------------------------------------------------------------------------------ + +configuration tb_tst_sram_n4d of tb_nexys4d_dram is + + for sim + for all : nexys4d_dram_aif + use entity work.sys_tst_sram_n4d; + end for; + end for; + +end tb_tst_sram_n4d; diff --git a/rtl/sys_gen/tst_sram/nexys4d/tb/tbrun.yml b/rtl/sys_gen/tst_sram/nexys4d/tb/tbrun.yml new file mode 100644 index 00000000..ba67e590 --- /dev/null +++ b/rtl/sys_gen/tst_sram/nexys4d/tb/tbrun.yml @@ -0,0 +1,18 @@ +# $Id: tbrun.yml 1099 2018-12-31 09:07:36Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2018-12-30 1099 1.0 Initial version +# +- default: + mode: ${viv_modes} +# +- tag: [viv, sys_tst_sram, n4d, base] + test: | + tbrun_tbwrri --lsuf base --pack tst_sram tb_tst_sram_n4d${ms} \ + tst_sram::setup tst_sram::test_all + +- tag: [viv, sys_tst_sram, n4d, stress] + test: | + tbrun_tbwrri --lsuf stress --pack tst_sram tb_tst_sram_n4d${ms} \ + tst_sram::setup tst_sram::test_sim diff --git a/rtl/sys_gen/tst_sram/nexys4d/tb/tbw.dat b/rtl/sys_gen/tst_sram/nexys4d/tb/tbw.dat new file mode 100644 index 00000000..9bf78585 --- /dev/null +++ b/rtl/sys_gen/tst_sram/nexys4d/tb/tbw.dat @@ -0,0 +1,7 @@ +# $Id: tbw.dat 1099 2018-12-31 09:07:36Z mueller $ +# +[tb_tst_sram_n4d] +rlink_cext_fifo_rx = +rlink_cext_fifo_tx = +rlink_cext_conf = +sysmon_stim = ../../../../bplib/sysmon/tb/sysmon_stim_n4.dat diff --git a/rtl/sys_gen/tst_sram/tbrun.yml b/rtl/sys_gen/tst_sram/tbrun.yml index b82f8365..4542590c 100644 --- a/rtl/sys_gen/tst_sram/tbrun.yml +++ b/rtl/sys_gen/tst_sram/tbrun.yml @@ -1,8 +1,8 @@ -# $Id: tbrun.yml 1101 2019-01-02 21:22:37Z mueller $ +# $Id: tbrun.yml 1103 2019-01-04 13:18:54Z mueller $ # # Revision History: # Date Rev Version Comment -# 2019-01-02 1101 1.2 add arty +# 2019-01-04 1103 1.2 add arty,nexys4d # 2017-06-25 917 1.1 add cmoda7 # 2016-08-13 798 1.0 Initial version # @@ -11,4 +11,5 @@ - include: nexys2/tb/tbrun.yml - include: nexys3/tb/tbrun.yml - include: nexys4/tb/tbrun.yml +- include: nexys4d/tb/tbrun.yml - include: cmoda7/tb/tbrun.yml