From b24fd9a3cb307c39fb735e7b629f79cafe79c15b Mon Sep 17 00:00:00 2001 From: wfjm Date: Sat, 25 Aug 2018 07:58:05 +0200 Subject: [PATCH] add Digilent Arty S7 board support --- rtl/bplib/artys7/artys7_pclk.xdc | 14 ++ rtl/bplib/artys7/artys7_pins.xdc | 85 ++++++++++ rtl/bplib/artys7/artys7_setup.tcl | 4 + rtl/bplib/artys7/artys7lib.vhd | 46 ++++++ rtl/bplib/artys7/tb/Makefile | 39 +++++ rtl/bplib/artys7/tb/artys7_dummy.vbom | 5 + rtl/bplib/artys7/tb/artys7_dummy.vhd | 58 +++++++ rtl/bplib/artys7/tb/sys_conf_sim.vhd | 54 +++++++ rtl/bplib/artys7/tb/tb_artys7.vbom | 24 +++ rtl/bplib/artys7/tb/tb_artys7.vhd | 197 ++++++++++++++++++++++++ rtl/bplib/artys7/tb/tb_artys7_core.vbom | 6 + rtl/bplib/artys7/tb/tb_artys7_core.vhd | 70 +++++++++ rtl/bplib/bpgen/bpgenlib.vhd | 20 ++- rtl/bplib/bpgen/rgbdrv_3x2mux.vbom | 7 + rtl/bplib/bpgen/rgbdrv_3x2mux.vhd | 101 ++++++++++++ rtl/make_viv/viv_default_artys7.mk | 16 ++ 16 files changed, 743 insertions(+), 3 deletions(-) create mode 100644 rtl/bplib/artys7/artys7_pclk.xdc create mode 100644 rtl/bplib/artys7/artys7_pins.xdc create mode 100644 rtl/bplib/artys7/artys7_setup.tcl create mode 100644 rtl/bplib/artys7/artys7lib.vhd create mode 100644 rtl/bplib/artys7/tb/Makefile create mode 100644 rtl/bplib/artys7/tb/artys7_dummy.vbom create mode 100644 rtl/bplib/artys7/tb/artys7_dummy.vhd create mode 100644 rtl/bplib/artys7/tb/sys_conf_sim.vhd create mode 100644 rtl/bplib/artys7/tb/tb_artys7.vbom create mode 100644 rtl/bplib/artys7/tb/tb_artys7.vhd create mode 100644 rtl/bplib/artys7/tb/tb_artys7_core.vbom create mode 100644 rtl/bplib/artys7/tb/tb_artys7_core.vhd create mode 100644 rtl/bplib/bpgen/rgbdrv_3x2mux.vbom create mode 100644 rtl/bplib/bpgen/rgbdrv_3x2mux.vhd create mode 100644 rtl/make_viv/viv_default_artys7.mk diff --git a/rtl/bplib/artys7/artys7_pclk.xdc b/rtl/bplib/artys7/artys7_pclk.xdc new file mode 100644 index 00000000..18593511 --- /dev/null +++ b/rtl/bplib/artys7/artys7_pclk.xdc @@ -0,0 +1,14 @@ +# -*- tcl -*- +# $Id: artys7_pclk.xdc 1038 2018-08-11 12:39:52Z mueller $ +# +# Copyright 2018- by Walter F.J. Mueller +# License disclaimer see License.txt in $RETROBASE directory +# +# Primary clocks for Digilent Arty +# +# Revision History: +# Date Rev Version Comment +# 2018-08-05 1038 1.0 Initial version +# + +create_clock -name I_CLK100 -period 10 -waveform {0 5} [get_ports I_CLK100] diff --git a/rtl/bplib/artys7/artys7_pins.xdc b/rtl/bplib/artys7/artys7_pins.xdc new file mode 100644 index 00000000..4c1b2716 --- /dev/null +++ b/rtl/bplib/artys7/artys7_pins.xdc @@ -0,0 +1,85 @@ +# -*- tcl -*- +# $Id: artys7_pins.xdc 1038 2018-08-11 12:39:52Z mueller $ +# +# Copyright 2018- by Walter F.J. Mueller +# License disclaimer see License.txt in $RETROBASE directory +# +# Digilent Arty core functionality +# - Configuration setup +# - config voltage +# - enable bitstream timestamp +# - Pin Locks for +# - USB UART +# - human I/O (switches, buttons, leds) +# +# Revision History: +# Date Rev Version Comment +# 2018-08-05 1038 1.0 Initial version +# + +# config setup -------------------------------------------------------------- +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design] +# other setups -------------------------------------------------------------- +# force internal ref for bank 34, allows to use M5 for SWI[3] +set_property INTERNAL_VREF 0.675 [get_iobanks 34] + +# clocks -- in bank 34 ------------------------------------------------------ +set_property PACKAGE_PIN r2 [get_ports {I_CLK100}] +set_property IOSTANDARD SSTL135 [get_ports {I_CLK100}] + +# +# USB UART Interface -- in bank 14 ------------------------------------------ +set_property PACKAGE_PIN v12 [get_ports {I_RXD}] +set_property PACKAGE_PIN r12 [get_ports {O_TXD}] + +set_property IOSTANDARD LVCMOS33 [get_ports {I_RXD O_TXD}] +set_property DRIVE 12 [get_ports {O_TXD}] +set_property SLEW SLOW [get_ports {O_TXD}] + +# +# switches -- in bank 15+34 ------------------------------------------------- +set_property PACKAGE_PIN h14 [get_ports {I_SWI[0]}] +set_property PACKAGE_PIN h18 [get_ports {I_SWI[1]}] +set_property PACKAGE_PIN g18 [get_ports {I_SWI[2]}] +set_property PACKAGE_PIN m5 [get_ports {I_SWI[3]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {I_SWI[0] I_SWI[1] I_SWI[2] }] +set_property IOSTANDARD SSTL135 [get_ports {I_SWI[3]}] + +# +# buttons -- in bank 15 ----------------------------------------------------- +set_property PACKAGE_PIN g15 [get_ports {I_BTN[0]}] +set_property PACKAGE_PIN k16 [get_ports {I_BTN[1]}] +set_property PACKAGE_PIN j16 [get_ports {I_BTN[2]}] +set_property PACKAGE_PIN h13 [get_ports {I_BTN[3]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {I_BTN[*]}] + +# +# LEDs -- in bank 15 -------------------------------------------------------- +set_property PACKAGE_PIN e18 [get_ports {O_LED[0]}] +set_property PACKAGE_PIN f13 [get_ports {O_LED[1]}] +set_property PACKAGE_PIN e13 [get_ports {O_LED[2]}] +set_property PACKAGE_PIN h15 [get_ports {O_LED[3]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {O_LED[*]}] +set_property DRIVE 12 [get_ports {O_LED[*]}] +set_property SLEW SLOW [get_ports {O_LED[*]}] + +# +# RGB-LEDs -- in bank 35 ---------------------------------------------------- +# Note: [0] red [1] green [2] blue +set_property PACKAGE_PIN j15 [get_ports {O_RGBLED0[0]}] +set_property PACKAGE_PIN g17 [get_ports {O_RGBLED0[1]}] +set_property PACKAGE_PIN f15 [get_ports {O_RGBLED0[2]}] + +set_property PACKAGE_PIN e15 [get_ports {O_RGBLED1[0]}] +set_property PACKAGE_PIN f18 [get_ports {O_RGBLED1[1]}] +set_property PACKAGE_PIN e14 [get_ports {O_RGBLED1[2]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {O_RGBLED0[*] O_RGBLED1[*]}] +set_property DRIVE 12 [get_ports {O_RGBLED0[*] O_RGBLED1[*]}] +set_property SLEW SLOW [get_ports {O_RGBLED0[*] O_RGBLED1[*]}] + diff --git a/rtl/bplib/artys7/artys7_setup.tcl b/rtl/bplib/artys7/artys7_setup.tcl new file mode 100644 index 00000000..50f6fdab --- /dev/null +++ b/rtl/bplib/artys7/artys7_setup.tcl @@ -0,0 +1,4 @@ +# $Id: artys7_setup.tcl 1038 2018-08-11 12:39:52Z mueller $ +# +set rvtb_part "xc7s50csga324-1" +set rvtb_board "artys7" diff --git a/rtl/bplib/artys7/artys7lib.vhd b/rtl/bplib/artys7/artys7lib.vhd new file mode 100644 index 00000000..a6702de5 --- /dev/null +++ b/rtl/bplib/artys7/artys7lib.vhd @@ -0,0 +1,46 @@ +-- $Id: artys7lib.vhd 1038 2018-08-11 12:39:52Z mueller $ +-- +-- Copyright 2018- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 3, or (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: artylib +-- Description: Digilent Arty S7 components +-- +-- Dependencies: - +-- Tool versions: viv 2017.2-2018.2; ghdl 0.34 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2018-08-05 1028 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package artys7lib is + +component artys7_aif is -- ARTY S7, abstract iface, base + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv4; -- artys7 switches + I_BTN : in slv4; -- artys7 buttons + O_LED : out slv4; -- artys7 leds + O_RGBLED0 : out slv3; -- artys7 rgb-led 0 + O_RGBLED1 : out slv3 -- artys7 rgb-led 1 + ); +end component; + +end package artys7lib; diff --git a/rtl/bplib/artys7/tb/Makefile b/rtl/bplib/artys7/tb/Makefile new file mode 100644 index 00000000..5a62cc97 --- /dev/null +++ b/rtl/bplib/artys7/tb/Makefile @@ -0,0 +1,39 @@ +# $Id: Makefile 1038 2018-08-11 12:39:52Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2018-08-05 1038 1.0 Initial version +# +EXE_all = tb_artys7_dummy +# +include ${RETROBASE}/rtl/make_viv/viv_default_artys7.mk +# +.PHONY : all all_ssim all_osim clean +.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_osim : $(EXE_all:=_osim) +# +all_XSim : $(EXE_all:=_XSim) +all_XSim_ssim : $(EXE_all:=_XSim_ssim) +all_XSim_osim : $(EXE_all:=_XSim_osim) +all_XSim_tsim : $(EXE_all:=_XSim_tsim) +# +clean : viv_clean ghdl_clean xsim_clean +# +#----- +# +include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk +include ${RETROBASE}/rtl/make_viv/generic_xsim.mk +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(VBOM_all:.vbom=.dep_vsim) +include $(wildcard *.o.dep_ghdl) +endif +# diff --git a/rtl/bplib/artys7/tb/artys7_dummy.vbom b/rtl/bplib/artys7/tb/artys7_dummy.vbom new file mode 100644 index 00000000..902f6f37 --- /dev/null +++ b/rtl/bplib/artys7/tb/artys7_dummy.vbom @@ -0,0 +1,5 @@ +# libs +../../../vlib/slvtypes.vhd +# components +# design +artys7_dummy.vhd diff --git a/rtl/bplib/artys7/tb/artys7_dummy.vhd b/rtl/bplib/artys7/tb/artys7_dummy.vhd new file mode 100644 index 00000000..47963a0e --- /dev/null +++ b/rtl/bplib/artys7/tb/artys7_dummy.vhd @@ -0,0 +1,58 @@ +-- $Id: artys7_dummy.vhd 1038 2018-08-11 12:39:52Z mueller $ +-- +-- Copyright 2018- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 3, or (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: artys7_dummy - syn +-- Description: artys7 minimal target (base; serport loopback) +-- +-- Dependencies: - +-- To test: tb_artys7 +-- Target Devices: generic +-- Tool versions: viv 2017.2-2018.2; ghdl 0.34 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2018-08-05 1038 1.0 Initial version (cloned from artya7) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +entity artys7_dummy is -- ARTY S7 dummy (base; loopback) + -- implements artys7_aif + port ( + I_CLK100 : in slbit; -- 100 MHz board clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv4; -- artys7 switches + I_BTN : in slv4; -- artys7 buttons + O_LED : out slv4; -- artys7 leds + O_RGBLED0 : out slv3; -- artys7 rgb-led 0 + O_RGBLED1 : out slv3 -- artys7 rgb-led 1 + ); +end artys7_dummy; + +architecture syn of artys7_dummy is + +begin + + O_TXD <= I_RXD; -- loop back serport + + O_LED <= I_SWI; -- mirror SWI on LED + + O_RGBLED0 <= I_BTN(2 downto 0); -- mirror BTN on RGBLED0 + O_RGBLED1 <= (others=>'0'); + +end syn; diff --git a/rtl/bplib/artys7/tb/sys_conf_sim.vhd b/rtl/bplib/artys7/tb/sys_conf_sim.vhd new file mode 100644 index 00000000..87dff8fe --- /dev/null +++ b/rtl/bplib/artys7/tb/sys_conf_sim.vhd @@ -0,0 +1,54 @@ +-- $Id: sys_conf_sim.vhd 1038 2018-08-11 12:39:52Z mueller $ +-- +-- Copyright 2018- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 3, or (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for tb_artys7_dummy (for simulation) +-- +-- Dependencies: - +-- Tool versions: viv 2017.2-2018.2; ghdl 0.34 +-- Revision History: +-- Date Rev Version Comment +-- 2018-08-05 1028 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz + constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + constant sys_conf_clkser_vcodivide : positive := 1; + constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz + constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz + constant sys_conf_clkser_gentype : string := "MMCM"; + + -- derived constants + + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_clkser : integer := + ((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) / + sys_conf_clkser_outdivide; + constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000; + +end package sys_conf; + diff --git a/rtl/bplib/artys7/tb/tb_artys7.vbom b/rtl/bplib/artys7/tb/tb_artys7.vbom new file mode 100644 index 00000000..23850a2e --- /dev/null +++ b/rtl/bplib/artys7/tb/tb_artys7.vbom @@ -0,0 +1,24 @@ +# Not meant for direct top level usage. Used with +# tb_artys7_(....)[_ssim].vbom and config +# lines to generate the different cases. +# +# libs +../../../vlib/slvtypes.vhd +../../../vlib/rlink/rlinklib.vbom +../../../vlib/xlib/xlib.vhd +../artys7lib.vhd +../../../vlib/simlib/simlib.vhd +../../../vlib/simlib/simbus.vhd +${sys_conf := sys_conf_sim.vhd} +# components +${gsr_pulse := ../../../vlib/xlib/gsr_pulse_dummy.vbom} +../../../vlib/simlib/simclk.vbom +../../../vlib/simlib/simclkcnt.vbom +../../../vlib/rlink/tbcore/tbcore_rlink.vbom +../../../vlib/xlib/tb/s7_cmt_sfs_tb.vbom +tb_artys7_core.vbom +../../../vlib/serport/tb/serport_master_tb.vbom +${artys7_aif := artys7_dummy.vbom} -UUT +# design +tb_artys7.vhd +@top:tb_artys7 diff --git a/rtl/bplib/artys7/tb/tb_artys7.vhd b/rtl/bplib/artys7/tb/tb_artys7.vhd new file mode 100644 index 00000000..82693a8d --- /dev/null +++ b/rtl/bplib/artys7/tb/tb_artys7.vhd @@ -0,0 +1,197 @@ +-- $Id: tb_artys7.vhd 1038 2018-08-11 12:39:52Z mueller $ +-- +-- Copyright 2018- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 3, or (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_artys7 - sim +-- Description: Test bench for artys7 (base) +-- +-- Dependencies: simlib/simclk +-- simlib/simclkcnt +-- rlink/tbcore/tbcore_rlink +-- xlib/tb/s7_cmt_sfs_tb +-- tb_basys3_core +-- serport/tb/serport_master_tb +-- artys7_aif [UUT] +-- +-- To test: generic, any artys7_aif target +-- +-- Target Devices: generic +-- Tool versions: viv 2017.2-2018.2; ghdl 0.34 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2018-08-05 1038 1.0 Initial version (derived from tb_artya7) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.rlinklib.all; +use work.xlib.all; +use work.artys7lib.all; +use work.simlib.all; +use work.simbus.all; +use work.sys_conf.all; + +entity tb_artys7 is +end tb_artys7; + +architecture sim of tb_artys7 is + + signal CLKOSC : slbit := '0'; -- board clock (100 Mhz) + signal CLKCOM : slbit := '0'; -- communication clock + + signal CLKCOM_CYCLE : integer := 0; + + signal RESET : slbit := '0'; + signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !! + signal RXDATA : slv8 := (others=>'0'); + signal RXVAL : slbit := '0'; + signal RXERR : slbit := '0'; + signal RXACT : slbit := '0'; + signal TXDATA : slv8 := (others=>'0'); + signal TXENA : slbit := '0'; + signal TXBUSY : slbit := '0'; + + signal I_RXD : slbit := '1'; + signal O_TXD : slbit := '1'; + signal I_SWI : slv4 := (others=>'0'); + signal I_BTN : slv4 := (others=>'0'); + signal O_LED : slv4 := (others=>'0'); + signal O_RGBLED0 : slv3 := (others=>'0'); + signal O_RGBLED1 : slv3 := (others=>'0'); + signal O_RGBLED2 : slv3 := (others=>'0'); + signal O_RGBLED3 : slv3 := (others=>'0'); + + signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff + + constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8)); + + constant clock_period : Delay_length := 10 ns; + constant clock_offset : Delay_length := 200 ns; + +begin + + GINIT : entity work.gsr_pulse; + + CLKGEN : simclk + generic map ( + PERIOD => clock_period, + OFFSET => clock_offset) + port map ( + CLK => CLKOSC + ); + + CLKGEN_COM : entity work.s7_cmt_sfs_tb + generic map ( + VCO_DIVIDE => sys_conf_clkser_vcodivide, + VCO_MULTIPLY => sys_conf_clkser_vcomultiply, + OUT_DIVIDE => sys_conf_clkser_outdivide, + CLKIN_PERIOD => 10.0, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clkser_gentype) + port map ( + CLKIN => CLKOSC, + CLKFX => CLKCOM, + LOCKED => open + ); + + CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE); + + TBCORE : entity work.tbcore_rlink + port map ( + CLK => CLKCOM, + RX_DATA => TXDATA, + RX_VAL => TXENA, + RX_HOLD => TXBUSY, + TX_DATA => RXDATA, + TX_ENA => RXVAL + ); + + ARTYS7CORE : entity work.tb_artys7_core + port map ( + I_SWI => I_SWI, + I_BTN => I_BTN + ); + + UUT : artys7_aif + port map ( + I_CLK100 => CLKOSC, + I_RXD => I_RXD, + O_TXD => O_TXD, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_RGBLED0 => O_RGBLED0, + O_RGBLED1 => O_RGBLED1 + ); + + SERMSTR : entity work.serport_master_tb + generic map ( + CDWIDTH => CLKDIV'length) + port map ( + CLK => CLKCOM, + RESET => RESET, + CLKDIV => CLKDIV, + ENAXON => R_PORTSEL_XON, + ENAESC => '0', + RXDATA => RXDATA, + RXVAL => RXVAL, + RXERR => RXERR, + RXOK => '1', + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY, + RXSD => O_TXD, + TXSD => I_RXD, + RXRTS_N => open, + TXCTS_N => '0' + ); + + proc_moni: process + variable oline : line; + begin + + loop + wait until rising_edge(CLKCOM); + + if RXERR = '1' then + writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1"); + writeline(output, oline); + end if; + + end loop; + + end process proc_moni; + + -- + -- Notes on portsel and XON control: + -- - most artys7 designs will use hardwired XON=1 + -- - but some (especially basis tests) might not use flow control + -- - that's why XON flow control must be optional and configurable ! + -- + proc_simbus: process (SB_VAL) + begin + if SB_VAL'event and to_x01(SB_VAL)='1' then + if SB_ADDR = sbaddr_portsel then + R_PORTSEL_XON <= to_x01(SB_DATA(1)); + end if; + end if; + end process proc_simbus; + +end sim; diff --git a/rtl/bplib/artys7/tb/tb_artys7_core.vbom b/rtl/bplib/artys7/tb/tb_artys7_core.vbom new file mode 100644 index 00000000..0511490f --- /dev/null +++ b/rtl/bplib/artys7/tb/tb_artys7_core.vbom @@ -0,0 +1,6 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/simlib/simbus.vhd +# components +# design +tb_artys7_core.vhd diff --git a/rtl/bplib/artys7/tb/tb_artys7_core.vhd b/rtl/bplib/artys7/tb/tb_artys7_core.vhd new file mode 100644 index 00000000..f77c8c5b --- /dev/null +++ b/rtl/bplib/artys7/tb/tb_artys7_core.vhd @@ -0,0 +1,70 @@ +-- $Id: tb_artys7_core.vhd 1038 2018-08-11 12:39:52Z mueller $ +-- +-- Copyright 2018- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 3, or (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_artys7_core - sim +-- Description: Test bench for artys7 - core device handling +-- +-- Dependencies: - +-- +-- To test: generic, any artys7 target +-- +-- Target Devices: generic +-- Tool versions: viv 2017.2-2018.2; ghdl 0.34 +-- Revision History: +-- Date Rev Version Comment +-- 2018-08-05 1038 1.0 Initial version (derived from tb_artya7_core) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.simbus.all; + +entity tb_artys7_core is + port ( + I_SWI : out slv4; -- artys7 switches + I_BTN : out slv4 -- artys7 buttons + ); +end tb_artys7_core; + +architecture sim of tb_artys7_core is + + signal R_SWI : slv4 := (others=>'0'); + signal R_BTN : slv4 := (others=>'0'); + + constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8)); + constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8)); + +begin + + proc_simbus: process (SB_VAL) + begin + if SB_VAL'event and to_x01(SB_VAL)='1' then + if SB_ADDR = sbaddr_swi then + R_SWI <= to_x01(SB_DATA(R_SWI'range)); + end if; + if SB_ADDR = sbaddr_btn then + R_BTN <= to_x01(SB_DATA(R_BTN'range)); + end if; + end if; + end process proc_simbus; + + I_SWI <= R_SWI; + I_BTN <= R_BTN; + +end sim; diff --git a/rtl/bplib/bpgen/bpgenlib.vhd b/rtl/bplib/bpgen/bpgenlib.vhd index 1a4c3934..d60dd34e 100644 --- a/rtl/bplib/bpgen/bpgenlib.vhd +++ b/rtl/bplib/bpgen/bpgenlib.vhd @@ -1,6 +1,6 @@ --- $Id: bpgenlib.vhd 984 2018-01-02 20:56:27Z mueller $ +-- $Id: bpgenlib.vhd 1038 2018-08-11 12:39:52Z mueller $ -- --- Copyright 2011-2017 by Walter F.J. Mueller +-- Copyright 2011-2018 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,9 +16,10 @@ -- Description: Generic Board/Part components -- -- Dependencies: - --- Tool versions: ise 12.1-14.7; viv 2014.4-2016.4; ghdl 0.26-0.34 +-- Tool versions: ise 12.1-14.7; viv 2014.4-2018.2; ghdl 0.26-0.34 -- Revision History: -- Date Rev Version Comment +-- 2018-08-11 1038 1.2.2 add rgbdrv_3x2mux -- 2017-06-05 907 1.2.1 rgbdrv_analog: add ACTLOW generic -- 2016-02-27 737 1.2 add rgbdrv entity -- 2015-01-24 637 1.1.2 add generics to sn_humanio and sn_7segctl @@ -239,4 +240,17 @@ component rgbdrv_3x4mux is -- rgbled driver: mux three 4bit inputs ); end component; +component rgbdrv_3x2mux is -- rgbled driver: mux three 2bit inputs + port ( + CLK : in slbit; -- clock + RESET : in slbit := '0'; -- reset + CE_USEC : in slbit; -- 1 us clock enable + DATR : in slv2; -- red data + DATG : in slv2; -- green data + DATB : in slv2; -- blue data + O_RGBLED0 : out slv3; -- pad-o: rgb led 0 + O_RGBLED1 : out slv3 -- pad-o: rgb led 1 + ); +end component; + end package bpgenlib; diff --git a/rtl/bplib/bpgen/rgbdrv_3x2mux.vbom b/rtl/bplib/bpgen/rgbdrv_3x2mux.vbom new file mode 100644 index 00000000..4e9b4dd0 --- /dev/null +++ b/rtl/bplib/bpgen/rgbdrv_3x2mux.vbom @@ -0,0 +1,7 @@ +# libs +../../vlib/slvtypes.vhd +../../vlib/xlib/xlib.vhd +# components +../../vlib/xlib/iob_reg_o_gen.vbom +# design +rgbdrv_3x2mux.vhd diff --git a/rtl/bplib/bpgen/rgbdrv_3x2mux.vhd b/rtl/bplib/bpgen/rgbdrv_3x2mux.vhd new file mode 100644 index 00000000..7422d7d2 --- /dev/null +++ b/rtl/bplib/bpgen/rgbdrv_3x2mux.vhd @@ -0,0 +1,101 @@ +-- $Id: rgbdrv_3x2mux.vhd 1038 2018-08-11 12:39:52Z mueller $ +-- +-- Copyright 2018- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 3, or (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: rgbdrv_3x2mux - syn +-- Description: rgbled driver: mux three 2bit inputs +-- +-- Dependencies: xlib/iob_reg_o_gen +-- Test bench: - +-- Target Devices: generic +-- Tool versions: viv 2017.2-2018.2; ghdl 0.34 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2018-08-11 1038 1.0 Initial version (derived from rgbdrv_3x4mux) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.xlib.all; + +entity rgbdrv_3x2mux is -- rgbled driver: mux three 2bit inputs + port ( + CLK : in slbit; -- clock + RESET : in slbit := '0'; -- reset + CE_USEC : in slbit; -- 1 us clock enable + DATR : in slv2; -- red data + DATG : in slv2; -- green data + DATB : in slv2; -- blue data + O_RGBLED0 : out slv3; -- pad-o: rgb led 0 + O_RGBLED1 : out slv3 -- pad-o: rgb led 1 + ); +end rgbdrv_3x2mux; + + +architecture syn of rgbdrv_3x2mux is + + signal R_LED : slv4 := "0001"; -- keep 4 states to keep brightness ! + signal R_COL : slv3 := "001"; + signal R_DIM : slbit := '1'; + + signal RGB0 : slv3 := (others=>'0'); + signal RGB1 : slv3 := (others=>'0'); + +begin + + IOB_RGB0: iob_reg_o_gen + generic map (DWIDTH => 3) + port map (CLK => CLK, CE => '1', DO => RGB0, PAD => O_RGBLED0); + IOB_RGB1: iob_reg_o_gen + generic map (DWIDTH => 3) + port map (CLK => CLK, CE => '1', DO => RGB1, PAD => O_RGBLED1); + + proc_regs: process (CLK) + begin + + if rising_edge(CLK) then + if RESET = '1' then + R_LED <= "0001"; + R_COL <= "001"; + R_DIM <= '1'; + else + if CE_USEC = '1' then + R_DIM <= not R_DIM; + if R_DIM = '1' then + R_COL <= R_COL(1) & R_COL(0) & R_COL(2); + if R_COL(2) = '1' then + R_LED <= R_LED(2) & R_LED(1) & R_LED(0) & R_LED(3); + end if; + end if; + end if; + end if; + end if; + + end process proc_regs; + + proc_mux: process (R_DIM, R_COL, R_LED, DATR, DATG, DATB) + begin + RGB0(0) <= (not R_DIM) and R_COL(0) and R_LED(0) and DATR(0); + RGB0(1) <= (not R_DIM) and R_COL(1) and R_LED(0) and DATG(0); + RGB0(2) <= (not R_DIM) and R_COL(2) and R_LED(0) and DATB(0); + + RGB1(0) <= (not R_DIM) and R_COL(0) and R_LED(1) and DATR(1); + RGB1(1) <= (not R_DIM) and R_COL(1) and R_LED(1) and DATG(1); + RGB1(2) <= (not R_DIM) and R_COL(2) and R_LED(1) and DATB(1); + end process proc_mux; + +end syn; diff --git a/rtl/make_viv/viv_default_artys7.mk b/rtl/make_viv/viv_default_artys7.mk new file mode 100644 index 00000000..859a4455 --- /dev/null +++ b/rtl/make_viv/viv_default_artys7.mk @@ -0,0 +1,16 @@ +# $Id: viv_default_artys7.mk 1038 2018-08-11 12:39:52Z mueller $ +# +# Copyright 2018- by Walter F.J. Mueller +# License disclaimer see License.txt in $RETROBASE directory +# +# Revision History: +# Date Rev Version Comment +# 2018-08-05 1038 1.0 Initial version +#--- +# +# Setup for Digilent Arty S7 +# +# setup default board and part +# +VIV_BOARD_SETUP = ${RETROBASE}/rtl/bplib/artys7/artys7_setup.tcl +#