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remove Atlys support (only test designs, w11 design never done)
This commit is contained in:
wfjm
parent
c560147d6d
commit
c1f2c0bfae
@ -32,6 +32,7 @@ The full set of tests is only run for tagged releases.
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- all actively used commands have now a man page
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- Doxygen support now for V1.9.4; remove discontinued Tcl support
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- build flow Vivado 2022.1 ready; handle synth 8-3331 -> 8-7129 transition
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- remove Atlys support (only test designs, a w11 design was never done)
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### New features
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- new verification codes
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- tools/tcode: fast cpu verification codes
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@ -51,6 +52,9 @@ The full set of tests is only run for tagged releases.
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- w11_tcl.Doxyfile: removed, Tcl support removed in Doxygen V1.8.18
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- firmware changes
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- vlib/xlib/bufg_unisim: added, encapulate unisim BUFG
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- removed designs (drop Atlys)
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- rtl/sys_gen/tst_rlink_cuff/atlys/sys_tst_rlink_cuff_atlys
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- rtl/sys_gen/tst_snhumanio/atlys/sys_tst_snhumanio_atlys
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### Bug Fixes
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- tools/mcode
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- m9312/bootw11.mac: proper init of unit number in getnam
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@ -38,8 +38,8 @@ For internal lab use one can use
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### <a id="usb-access">Setup USB access</a>
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For using the Cypress FX2 USB interface on Digilent Nexys2, Nexys3 and
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Atlys boards `udev` rules must be setup to allow user level access to
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For using the Cypress FX2 USB interface on Digilent Nexys2 and Nexys3
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boards `udev` rules must be setup to allow user level access to
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these devices. A set of rules is provided under
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$RETROBASE/tools/fx2/sys
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@ -54,7 +54,7 @@ Notes:
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### <a id="fx2-firmware">Rebuild Cypress FX2 firmware</a>
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The download includes pre-build firmware images for the Cypress FX2
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USB interface used on the Digilent Nexys2, Nexys3 and Atlys Boards.
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USB interface used on the Digilent Nexys2 and Nexys3 boards.
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These firmware images are under
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$RETROBASE/tools/fx2/bin
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@ -213,8 +213,8 @@ simply use
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make <sys>.iconfig
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For using the Cypress FX2 USB controller on Digilent Nexys2, Nexys3 and
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Atlys boards just connect the USB cable and
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For using the Cypress FX2 USB controller on Digilent Nexys2 and Nexys3
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boards just connect the USB cable and
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make <sys>.jconfig
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@ -5,7 +5,6 @@ and is organized in
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| --------- | ------- |
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| [arty](arty) | support for Digilent Arty A7-35 board |
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| [artys7](artys7) | support for Digilent Arty S7-50 board |
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| [atlys](atlys) | support for Digilent Atlys board |
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| [basys3](basys3) | support for Digilent Basys3 board |
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| [bpgen](bpgen) | interfaces for IO devices common on Digilent boards |
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| [cmoda7](cmoda7) | support for Digilent Cmod A7-35 board |
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@ -1,61 +0,0 @@
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## $Id: atlys_pins.ucf 414 2011-10-11 19:38:12Z mueller $
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##
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## Pin locks for Atlys core functionality
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## - USB UART
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## - human I/O (switches, buttons, leds)
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##
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## Revision History:
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## Date Rev Version Comment
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## 2011-10-10 413 1.0.2 new BTN sequence: clockwise(U-R-D-L) - mid - reset
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## 2011-08-05 403 1.0.1 Fix IOSTANDARD typos; rename _GPIO_ to _HIO_
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## 2011-08-04 402 1.0 Initial version
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##
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## Notes:
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## - Bank 0+1 are 3V3; Bank 2 switchable 3V3 or 2V5; Bank 3 is 1V8 (DDR mem)
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## - default is DRIVE=12 | SLEW=SLOW
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## - pin names from Digilent master AtlysGeneralUCF.zip are given as comments
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##
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## clocks --------------------------------------------------------------------
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## AtlysGeneralUCF: clk
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##
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NET "I_CLK100" LOC = "l15" | IOSTANDARD=LVCMOS25;
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##
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## USB UART interface --------------------------------------------------------
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## AtlysGeneralUCF: UartRx, UartTx (crossed!)
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##
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NET "I_USB_RXD" LOC = "a16" | IOSTANDARD=LVCMOS33;
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NET "O_USB_TXD" LOC = "b16" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=SLOW;
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##
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## SWIs ----------------------------------------------------------------------
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## AtlysGeneralUCF: sw<0:7>
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##
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NET "I_HIO_SWI<0>" LOC = "a10" | IOSTANDARD=LVCMOS33;
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NET "I_HIO_SWI<1>" LOC = "d14" | IOSTANDARD=LVCMOS33;
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NET "I_HIO_SWI<2>" LOC = "c14" | IOSTANDARD=LVCMOS33;
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NET "I_HIO_SWI<3>" LOC = "p15" | IOSTANDARD=LVCMOS33;
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NET "I_HIO_SWI<4>" LOC = "p12" | IOSTANDARD=LVCMOS33;
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NET "I_HIO_SWI<5>" LOC = "r5" | IOSTANDARD=LVCMOS33;
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NET "I_HIO_SWI<6>" LOC = "t5" | IOSTANDARD=LVCMOS33;
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NET "I_HIO_SWI<7>" LOC = "e4" | IOSTANDARD=LVCMOS33;
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##
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## BTNs ----------------------------------------------------------------------
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## AtlysGeneralUCF: btn<0:5>; clockwise(U-R-D-L) - middle - reset
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##
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NET "I_HIO_BTN<0>" LOC = "n4" | IOSTANDARD=LVCMOS18; # BTNU
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NET "I_HIO_BTN<1>" LOC = "f6" | IOSTANDARD=LVCMOS18; # BTNR
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NET "I_HIO_BTN<2>" LOC = "p3" | IOSTANDARD=LVCMOS18; # BTND
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NET "I_HIO_BTN<3>" LOC = "p4" | IOSTANDARD=LVCMOS18; # BTNL
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NET "I_HIO_BTN<4>" LOC = "f5" | IOSTANDARD=LVCMOS18; # BTNC
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NET "I_HIO_BTN<5>" LOC = "t15" | IOSTANDARD=LVCMOS18; # RESET (act.low!!)
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##
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## LEDs ----------------------------------------------------------------------
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## AtlysGeneralUCF: Led<0:7>
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##
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NET "O_HIO_LED<0>" LOC = "u18" | IOSTANDARD=LVCMOS33;
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NET "O_HIO_LED<1>" LOC = "m14" | IOSTANDARD=LVCMOS33;
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NET "O_HIO_LED<2>" LOC = "n14" | IOSTANDARD=LVCMOS33;
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NET "O_HIO_LED<3>" LOC = "l14" | IOSTANDARD=LVCMOS33;
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NET "O_HIO_LED<4>" LOC = "m13" | IOSTANDARD=LVCMOS33;
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NET "O_HIO_LED<5>" LOC = "d4" | IOSTANDARD=LVCMOS33;
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NET "O_HIO_LED<6>" LOC = "p16" | IOSTANDARD=LVCMOS33;
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NET "O_HIO_LED<7>" LOC = "n12" | IOSTANDARD=LVCMOS33;
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@ -1,36 +0,0 @@
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## $Id: atlys_pins_fx2.ucf 471 2013-01-05 19:46:38Z mueller $
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##
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## Revision History:
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## Date Rev Version Comment
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## 2013-01-05 471 1.0 Initial version
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##
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## Cypress EZ-USB FX2 Interface -- in Bank 0 ---------------------------------
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##
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##
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NET "I_FX2_IFCLK" LOC = "c10" | IOSTANDARD=LVCMOS33;
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##
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NET "IO_FX2_DATA<0>" LOC = "a2" | IOSTANDARD=LVCMOS33;
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NET "IO_FX2_DATA<1>" LOC = "d6" | IOSTANDARD=LVCMOS33;
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NET "IO_FX2_DATA<2>" LOC = "c6" | IOSTANDARD=LVCMOS33;
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NET "IO_FX2_DATA<3>" LOC = "b3" | IOSTANDARD=LVCMOS33;
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NET "IO_FX2_DATA<4>" LOC = "a3" | IOSTANDARD=LVCMOS33;
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NET "IO_FX2_DATA<5>" LOC = "b4" | IOSTANDARD=LVCMOS33;
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NET "IO_FX2_DATA<6>" LOC = "a4" | IOSTANDARD=LVCMOS33;
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NET "IO_FX2_DATA<7>" LOC = "c5" | IOSTANDARD=LVCMOS33;
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NET "IO_FX2_DATA<*>" DRIVE=12 | SLEW=FAST | KEEPER;
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##
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NET "O_FX2_SLWR_N" LOC = "e13" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
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NET "O_FX2_SLRD_N" LOC = "f13" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
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NET "O_FX2_SLOE_N" LOC = "a15" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
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##
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NET "O_FX2_PKTEND_N" LOC = "c4" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
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##
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NET "O_FX2_FIFO<0>" LOC = "a14" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
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NET "O_FX2_FIFO<1>" LOC = "b14" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
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##
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## assume that PA.7 is used as FLAGD (and not as SLCS#)
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NET "I_FX2_FLAG<0>" LOC = "b9" | IOSTANDARD=LVCMOS33; ## flag a (program)
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NET "I_FX2_FLAG<1>" LOC = "a9" | IOSTANDARD=LVCMOS33; ## flag b (full)
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NET "I_FX2_FLAG<2>" LOC = "c15" | IOSTANDARD=LVCMOS33; ## flag c (empty)
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NET "I_FX2_FLAG<3>" LOC = "b2" | IOSTANDARD=LVCMOS33; ## flag d (slcs)
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##
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@ -1,23 +0,0 @@
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## $Id: atlys_pins_pma0_rs232.ucf 403 2011-08-06 17:36:22Z mueller $
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##
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## Revision History:
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## Date Rev Version Comment
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## 2011-08-06 403 1.0 Initial version
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##
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## Pmod connector A top / usage RS232 for FTDI USB serport -------------------
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##
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## front view (towards PCB edge):
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##
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## P-6 P-1
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## | |
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## +-------------------------+
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## | VCC GND TXD RXD CTS RTS |
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## | VCC GND ... ... ... ... |
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## =============================
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## < HDMI connector>
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##
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##
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NET "O_FUSP_RTS_N" LOC = "t3" | IOSTANDARD=LVCMOS33 | DRIVE=4 | SLEW=SLOW;
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NET "I_FUSP_CTS_N" LOC = "r3" | IOSTANDARD=LVCMOS33 | PULLDOWN;
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NET "I_FUSP_RXD" LOC = "p6" | IOSTANDARD=LVCMOS33 | PULLUP;
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NET "O_FUSP_TXD" LOC = "n5" | IOSTANDARD=LVCMOS33 | DRIVE=4 | SLEW=SLOW;
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@ -1,25 +0,0 @@
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## $Id: atlys_pins_pmod.ucf 403 2011-08-06 17:36:22Z mueller $
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##
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## Revision History:
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## Date Rev Version Comment
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## 2011-08-06 403 1.0 Initial version
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##
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## Pmod connectors -----------------------------------------------------------
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##
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## front view (towards PCB edge):
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##
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## +-------------------------+
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## | VCC GND P-4 P-3 P-2 P-1 |
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## | VCC GND P10 P-9 P-8 P-7 |
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## =============================
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## < HDMI connector>
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##
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## Pmod A (top: 0-3; bot: 4-7; all 8 shared with HDMI Type D connector...)
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NET "IO_PMODA<0>" LOC = "t3" | IOSTANDARD=LVCMOS33;
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NET "IO_PMODA<1>" LOC = "r3" | IOSTANDARD=LVCMOS33;
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NET "IO_PMODA<2>" LOC = "p6" | IOSTANDARD=LVCMOS33;
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NET "IO_PMODA<3>" LOC = "n5" | IOSTANDARD=LVCMOS33;
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NET "IO_PMODA<4>" LOC = "v9" | IOSTANDARD=LVCMOS33;
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NET "IO_PMODA<5>" LOC = "t9" | IOSTANDARD=LVCMOS33;
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NET "IO_PMODA<6>" LOC = "v4" | IOSTANDARD=LVCMOS33;
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NET "IO_PMODA<7>" LOC = "t4" | IOSTANDARD=LVCMOS33;
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@ -1,18 +0,0 @@
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## $Id: atlys_time_fx2_ic.ucf 537 2013-10-06 09:06:23Z mueller $
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##
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## Revision History:
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## Date Rev Version Comment
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## 2013-10-05 537 1.1 add VALID for hold time check
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## 2013-01-05 471 1.0 Initial version (copied from nexys3)
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##
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## timing rules for a 30 MHz internal clock design:
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## Period: 30 MHz
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## clk->out: longest setup time in FX2 is t_SRD (clk->SLRD) of 18.7 ns
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## clk->out < 33.3-18.7 = 14.6 ns
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## --> use 10 ns
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##
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NET "I_FX2_IFCLK" TNM_NET = "I_FX2_IFCLK";
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TIMESPEC "TS_I_FX2_IFCLK" = PERIOD "I_FX2_IFCLK" 33.34 ns HIGH 50 %;
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OFFSET = IN 2 ns VALID 33 ns BEFORE "I_FX2_IFCLK";
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OFFSET = OUT 10 ns VALID 33 ns AFTER "I_FX2_IFCLK";
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@ -1,7 +0,0 @@
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# libs
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../../vlib/slvtypes.vhd
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bpgenlib.vbom
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# components
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bp_swibtnled.vbom
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# design
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sn_humanio_demu.vhd
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@ -1,186 +0,0 @@
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-- $Id: sn_humanio_demu.vhd 1181 2019-07-08 17:00:50Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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------------------------------------------------------------------------------
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-- Module Name: sn_humanio_demu - syn
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-- Description: All BTN, SWI, LED handling for atlys
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--
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-- Dependencies: bpgen/bp_swibtnled
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--
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-- Test bench: -
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--
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-- Target Devices: generic
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-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31
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--
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2011-10-10 413 13.1 O40d xc3s1000-4 67 66 0 55 s 6.1 ns
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2011-10-11 414 1.0.1 take care of RESET BTN being active low
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-- 2011-10-10 413 1.0 Initial version
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------------------------------------------------------------------------------
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.bpgenlib.all;
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-- ----------------------------------------------------------------------------
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entity sn_humanio_demu is -- human i/o handling: swi,btn,led only
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generic (
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DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN
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port (
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CLK : in slbit; -- clock
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RESET : in slbit := '0'; -- reset
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CE_MSEC : in slbit; -- 1 ms clock enable
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SWI : out slv8; -- switch settings, debounced
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BTN : out slv4; -- button settings, debounced
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LED : in slv8; -- led data
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DSP_DAT : in slv16; -- display data
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DSP_DP : in slv4; -- display decimal points
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I_SWI : in slv8; -- pad-i: switches
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I_BTN : in slv6; -- pad-i: buttons
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O_LED : out slv8 -- pad-o: leds
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);
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end sn_humanio_demu;
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architecture syn of sn_humanio_demu is
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constant c_mode_led : slv2 := "00";
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constant c_mode_dp : slv2 := "01";
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constant c_mode_datl : slv2 := "10";
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constant c_mode_dath : slv2 := "11";
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type regs_type is record
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mode : slv2; -- current mode
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cnt : slv9; -- msec counter
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up_1 : slbit; -- btn up last cycle
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dn_1 : slbit; -- btn dn last cycle
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led : slv8; -- led state
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end record regs_type;
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constant regs_init : regs_type := (
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c_mode_led, -- mode
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(others=>'0'), -- cnt
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'0','0', -- up_1, dn_1
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(others=>'0') -- led
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);
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signal R_REGS : regs_type := regs_init; -- state registers
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signal N_REGS : regs_type := regs_init; -- next value state regs
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signal BTN_HW : slv6 := (others=>'0');
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signal LED_HW : slv8 := (others=>'0');
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begin
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HIO : bp_swibtnled
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generic map (
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SWIDTH => 8,
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BWIDTH => 6,
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LWIDTH => 8,
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DEBOUNCE => DEBOUNCE)
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port map (
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CLK => CLK,
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RESET => RESET,
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CE_MSEC => CE_MSEC,
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SWI => SWI,
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BTN => BTN_HW,
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LED => LED_HW,
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I_SWI => I_SWI,
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I_BTN => I_BTN,
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O_LED => O_LED
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);
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proc_regs: process (CLK)
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begin
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if rising_edge(CLK) then
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if RESET = '1' then
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R_REGS <= regs_init;
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else
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R_REGS <= N_REGS;
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end if;
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end if;
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end process proc_regs;
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proc_next: process (R_REGS, CE_MSEC, LED, DSP_DAT, DSP_DP, BTN_HW)
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variable r : regs_type := regs_init;
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variable n : regs_type := regs_init;
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variable ibtn : slv4 := (others=>'0');
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variable iup : slbit := '0';
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variable idn : slbit := '0';
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variable ipuls : slbit := '0';
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begin
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r := R_REGS;
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n := R_REGS;
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ibtn(0) := not BTN_HW(5); -- RESET button is act. low !
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ibtn(1) := BTN_HW(1);
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ibtn(2) := BTN_HW(4);
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ibtn(3) := BTN_HW(3);
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iup := BTN_HW(0);
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idn := BTN_HW(2);
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ipuls := '0';
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n.up_1 := iup;
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n.dn_1 := idn;
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if iup='0' and idn='0' then
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n.cnt := (others=>'0');
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else
|
||||
if CE_MSEC = '1' then
|
||||
n.cnt := slv(unsigned(r.cnt) + 1);
|
||||
if r.cnt = "111111111" then
|
||||
ipuls := '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if iup='1' or idn='1' then
|
||||
n.led := (others=>'0');
|
||||
case r.mode is
|
||||
when c_mode_led => n.led(0) := '1';
|
||||
when c_mode_dp => n.led(1) := '1';
|
||||
when c_mode_datl => n.led(2) := '1';
|
||||
when c_mode_dath => n.led(3) := '1';
|
||||
when others => null;
|
||||
end case;
|
||||
|
||||
if iup='1' and (r.up_1='0' or ipuls='1') then
|
||||
n.mode := slv(unsigned(r.mode) + 1);
|
||||
elsif idn='1' and (r.dn_1='0' or ipuls='1') then
|
||||
n.mode := slv(unsigned(r.mode) - 1);
|
||||
end if;
|
||||
|
||||
else
|
||||
case r.mode is
|
||||
when c_mode_led => n.led := LED;
|
||||
when c_mode_dp => n.led := "0000" & DSP_DP;
|
||||
when c_mode_datl => n.led := DSP_DAT( 7 downto 0);
|
||||
when c_mode_dath => n.led := DSP_DAT(15 downto 8);
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
|
||||
N_REGS <= n;
|
||||
|
||||
BTN <= ibtn;
|
||||
LED_HW <= r.led;
|
||||
|
||||
end process proc_next;
|
||||
|
||||
end syn;
|
||||
@ -1,8 +0,0 @@
|
||||
# libs
|
||||
../../vlib/slvtypes.vhd
|
||||
../../vlib/rbus/rblib.vhd
|
||||
bpgenlib.vbom
|
||||
# components
|
||||
sn_humanio_demu.vbom
|
||||
# design
|
||||
sn_humanio_demu_rbus.vhd
|
||||
@ -1,292 +0,0 @@
|
||||
-- $Id: sn_humanio_demu_rbus.vhd 1181 2019-07-08 17:00:50Z mueller $
|
||||
-- SPDX-License-Identifier: GPL-3.0-or-later
|
||||
-- Copyright 2013-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
||||
--
|
||||
------------------------------------------------------------------------------
|
||||
-- Module Name: sn_humanio_demu_rbus - syn
|
||||
-- Description: sn_humanio_demu with rbus interceptor
|
||||
--
|
||||
-- Dependencies: bpgen/sn_humanio_demu
|
||||
--
|
||||
-- Test bench: -
|
||||
--
|
||||
-- Target Devices: generic
|
||||
-- Tool versions: xst 13.3-14.7; ghdl 0.0.29-0.35
|
||||
--
|
||||
-- Synthesized (xst):
|
||||
-- Date Rev ise Target flop lutl lutm slic t peri
|
||||
-- 2013-01-06 472 13.3 O76xd xc3s1000-4 160 136 0 124 s 6.1 ns
|
||||
--
|
||||
-- Revision History:
|
||||
-- Date Rev Version Comment
|
||||
-- 2014-08-15 583 1.1 rb_mreq addr now 16 bit
|
||||
-- 2013-01-06 472 1.0 Initial version (cloned from sn_humanio_rbus
|
||||
------------------------------------------------------------------------------
|
||||
--
|
||||
-- rbus registers:
|
||||
--
|
||||
-- Address Bits Name r/w/f Function
|
||||
-- bbbbbb00 cntl r/w/- Control register and BTN access
|
||||
-- x:08 btn r/w/- r: return hio BTN status
|
||||
-- w: ored with hio BTN to drive BTN
|
||||
-- 3 dsp_en r/w/- if 1 display data will be driven by rbus
|
||||
-- 2 dp_en r/w/- if 1 display dp's will be driven by rbus
|
||||
-- 1 led_en r/w/- if 1 LED will be driven by rri
|
||||
-- 0 swi_en r/w/- if 1 SWI will be driven by rri
|
||||
--
|
||||
-- bbbbbb01 7:00 swi r/w/- r: return hio SWI status
|
||||
-- w: will drive SWI when swi_en=1
|
||||
--
|
||||
-- bbbbbb10 led r/w/- Interface to LED and DSP_DP
|
||||
-- 15:12 dp r/w/- r: returns DSP_DP status
|
||||
-- w: will drive display dp's when dp_en=1
|
||||
-- 7:00 led r/w/- r: returns LED status
|
||||
-- w: will drive led's when led_en=1
|
||||
--
|
||||
-- bbbbbb11 15:00 dsp r/w/- r: return hio DSP_DAT status
|
||||
-- w: will drive DSP_DAT when dsp_en=1
|
||||
--
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
use work.slvtypes.all;
|
||||
use work.rblib.all;
|
||||
use work.bpgenlib.all;
|
||||
|
||||
-- ----------------------------------------------------------------------------
|
||||
|
||||
entity sn_humanio_demu_rbus is -- human i/o swi,btn,led only /w rbus
|
||||
generic (
|
||||
DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN
|
||||
RB_ADDR : slv16 := x"fef0");
|
||||
port (
|
||||
CLK : in slbit; -- clock
|
||||
RESET : in slbit := '0'; -- reset
|
||||
CE_MSEC : in slbit; -- 1 ms clock enable
|
||||
RB_MREQ : in rb_mreq_type; -- rbus: request
|
||||
RB_SRES : out rb_sres_type; -- rbus: response
|
||||
SWI : out slv8; -- switch settings, debounced
|
||||
BTN : out slv4; -- button settings, debounced
|
||||
LED : in slv8; -- led data
|
||||
DSP_DAT : in slv16; -- display data
|
||||
DSP_DP : in slv4; -- display decimal points
|
||||
I_SWI : in slv8; -- pad-i: switches
|
||||
I_BTN : in slv6; -- pad-i: buttons
|
||||
O_LED : out slv8 -- pad-o: leds
|
||||
);
|
||||
end sn_humanio_demu_rbus;
|
||||
|
||||
architecture syn of sn_humanio_demu_rbus is
|
||||
|
||||
type regs_type is record
|
||||
rbsel : slbit; -- rbus select
|
||||
swi : slv8; -- rbus swi
|
||||
btn : slv4; -- rbus btn
|
||||
led : slv8; -- rbus led
|
||||
dsp_dat : slv16; -- rbus dsp_dat
|
||||
dsp_dp : slv4; -- rbus dsp_dp
|
||||
ledin : slv8; -- led from design
|
||||
swieff : slv8; -- effective swi
|
||||
btneff : slv4; -- effective btn
|
||||
ledeff : slv8; -- effective led
|
||||
dpeff : slv4; -- effective dsp_dp
|
||||
dateff : slv16; -- effective dsp_dat
|
||||
swi_en : slbit; -- enable: swi from rbus
|
||||
led_en : slbit; -- enable: led from rbus
|
||||
dsp_en : slbit; -- enable: dsp_dat from rbus
|
||||
dp_en : slbit; -- enable: dsp_dp from rbus
|
||||
end record regs_type;
|
||||
|
||||
constant regs_init : regs_type := (
|
||||
'0', -- rbsel
|
||||
(others=>'0'), -- swi
|
||||
(others=>'0'), -- btn
|
||||
(others=>'0'), -- led
|
||||
(others=>'0'), -- dsp_dat
|
||||
(others=>'0'), -- dsp_dp
|
||||
(others=>'0'), -- ledin
|
||||
(others=>'0'), -- swieff
|
||||
(others=>'0'), -- btneff
|
||||
(others=>'0'), -- ledeff
|
||||
(others=>'0'), -- dpeff
|
||||
(others=>'0'), -- dateff
|
||||
'0','0','0','0' -- (swi|led|dsp|dp)_en
|
||||
);
|
||||
|
||||
signal R_REGS : regs_type := regs_init; -- state registers
|
||||
signal N_REGS : regs_type := regs_init; -- next value state regs
|
||||
|
||||
subtype cntl_rbf_btn is integer range 11 downto 8;
|
||||
constant cntl_rbf_dsp_en: integer := 3;
|
||||
constant cntl_rbf_dp_en: integer := 2;
|
||||
constant cntl_rbf_led_en: integer := 1;
|
||||
constant cntl_rbf_swi_en: integer := 0;
|
||||
subtype led_rbf_dp is integer range 15 downto 12;
|
||||
subtype led_rbf_led is integer range 7 downto 0;
|
||||
|
||||
constant rbaddr_cntl: slv2 := "00"; -- 0 r/w/-
|
||||
constant rbaddr_swi: slv2 := "01"; -- 1 r/w/-
|
||||
constant rbaddr_led: slv2 := "10"; -- 2 r/w/-
|
||||
constant rbaddr_dsp: slv2 := "11"; -- 3 r/w/-
|
||||
|
||||
signal HIO_SWI : slv8 := (others=>'0');
|
||||
signal HIO_BTN : slv4 := (others=>'0');
|
||||
signal HIO_LED : slv8 := (others=>'0');
|
||||
signal HIO_DSP_DAT : slv16 := (others=>'0');
|
||||
signal HIO_DSP_DP : slv4 := (others=>'0');
|
||||
|
||||
begin
|
||||
|
||||
HIO : sn_humanio_demu
|
||||
generic map (
|
||||
DEBOUNCE => DEBOUNCE)
|
||||
port map (
|
||||
CLK => CLK,
|
||||
RESET => RESET,
|
||||
CE_MSEC => CE_MSEC,
|
||||
SWI => HIO_SWI,
|
||||
BTN => HIO_BTN,
|
||||
LED => HIO_LED,
|
||||
DSP_DAT => HIO_DSP_DAT,
|
||||
DSP_DP => HIO_DSP_DP,
|
||||
I_SWI => I_SWI,
|
||||
I_BTN => I_BTN,
|
||||
O_LED => O_LED
|
||||
);
|
||||
|
||||
proc_regs: process (CLK)
|
||||
begin
|
||||
|
||||
if rising_edge(CLK) then
|
||||
if RESET = '1' then
|
||||
R_REGS <= regs_init;
|
||||
else
|
||||
R_REGS <= N_REGS;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end process proc_regs;
|
||||
|
||||
proc_next: process (R_REGS, RB_MREQ, LED, DSP_DAT, DSP_DP,
|
||||
HIO_SWI, HIO_BTN, HIO_DSP_DAT, HIO_DSP_DP)
|
||||
|
||||
variable r : regs_type := regs_init;
|
||||
variable n : regs_type := regs_init;
|
||||
|
||||
variable irb_ack : slbit := '0';
|
||||
variable irb_busy : slbit := '0';
|
||||
variable irb_err : slbit := '0';
|
||||
variable irb_dout : slv16 := (others=>'0');
|
||||
variable irbena : slbit := '0';
|
||||
|
||||
begin
|
||||
|
||||
r := R_REGS;
|
||||
n := R_REGS;
|
||||
|
||||
irb_ack := '0';
|
||||
irb_busy := '0';
|
||||
irb_err := '0';
|
||||
irb_dout := (others=>'0');
|
||||
|
||||
irbena := RB_MREQ.re or RB_MREQ.we;
|
||||
|
||||
-- input register for LED signal
|
||||
n.ledin := LED;
|
||||
|
||||
-- rbus address decoder
|
||||
n.rbsel := '0';
|
||||
if RB_MREQ.aval='1' and RB_MREQ.addr(15 downto 2)=RB_ADDR(15 downto 2) then
|
||||
n.rbsel := '1';
|
||||
end if;
|
||||
|
||||
-- rbus transactions
|
||||
if r.rbsel = '1' then
|
||||
irb_ack := irbena; -- ack all accesses
|
||||
|
||||
case RB_MREQ.addr(1 downto 0) is
|
||||
|
||||
when rbaddr_cntl =>
|
||||
irb_dout(cntl_rbf_btn) := HIO_BTN;
|
||||
irb_dout(cntl_rbf_dsp_en) := r.dsp_en;
|
||||
irb_dout(cntl_rbf_dp_en) := r.dp_en;
|
||||
irb_dout(cntl_rbf_led_en) := r.led_en;
|
||||
irb_dout(cntl_rbf_swi_en) := r.swi_en;
|
||||
if RB_MREQ.we = '1' then
|
||||
n.btn := RB_MREQ.din(cntl_rbf_btn);
|
||||
n.dsp_en := RB_MREQ.din(cntl_rbf_dsp_en);
|
||||
n.dp_en := RB_MREQ.din(cntl_rbf_dp_en);
|
||||
n.led_en := RB_MREQ.din(cntl_rbf_led_en);
|
||||
n.swi_en := RB_MREQ.din(cntl_rbf_swi_en);
|
||||
end if;
|
||||
|
||||
when rbaddr_swi =>
|
||||
irb_dout(HIO_SWI'range) := HIO_SWI;
|
||||
if RB_MREQ.we = '1' then
|
||||
n.swi := RB_MREQ.din(n.swi'range);
|
||||
end if;
|
||||
|
||||
when rbaddr_led =>
|
||||
irb_dout(led_rbf_dp) := HIO_DSP_DP;
|
||||
irb_dout(led_rbf_led) := r.ledin;
|
||||
if RB_MREQ.we = '1' then
|
||||
n.dsp_dp := RB_MREQ.din(led_rbf_dp);
|
||||
n.led := RB_MREQ.din(led_rbf_led);
|
||||
end if;
|
||||
|
||||
when rbaddr_dsp =>
|
||||
irb_dout := HIO_DSP_DAT;
|
||||
if RB_MREQ.we = '1' then
|
||||
n.dsp_dat := RB_MREQ.din;
|
||||
end if;
|
||||
|
||||
when others => null;
|
||||
end case;
|
||||
|
||||
end if;
|
||||
|
||||
n.btneff := HIO_BTN or r.btn;
|
||||
|
||||
if r.swi_en = '0' then
|
||||
n.swieff := HIO_SWI;
|
||||
else
|
||||
n.swieff := r.swi;
|
||||
end if;
|
||||
|
||||
if r.led_en = '0' then
|
||||
n.ledeff := r.ledin;
|
||||
else
|
||||
n.ledeff := r.led;
|
||||
end if;
|
||||
|
||||
if r.dp_en = '0' then
|
||||
n.dpeff := DSP_DP;
|
||||
else
|
||||
n.dpeff := r.dsp_dp;
|
||||
end if;
|
||||
|
||||
if r.dsp_en = '0' then
|
||||
n.dateff := DSP_DAT;
|
||||
else
|
||||
n.dateff := r.dsp_dat;
|
||||
end if;
|
||||
|
||||
N_REGS <= n;
|
||||
|
||||
BTN <= R_REGS.btneff;
|
||||
SWI <= R_REGS.swieff;
|
||||
HIO_LED <= R_REGS.ledeff;
|
||||
HIO_DSP_DP <= R_REGS.dpeff;
|
||||
HIO_DSP_DAT <= R_REGS.dateff;
|
||||
|
||||
RB_SRES <= rb_sres_init;
|
||||
RB_SRES.ack <= irb_ack;
|
||||
RB_SRES.busy <= irb_busy;
|
||||
RB_SRES.err <= irb_err;
|
||||
RB_SRES.dout <= irb_dout;
|
||||
|
||||
end process proc_next;
|
||||
|
||||
end syn;
|
||||
@ -1,26 +0,0 @@
|
||||
# $Id: xflow_default_atlys.mk 1176 2019-06-30 07:16:06Z mueller $
|
||||
# SPDX-License-Identifier: GPL-3.0-or-later
|
||||
# Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
||||
#
|
||||
# Revision History:
|
||||
# Date Rev Version Comment
|
||||
# 2013-01-27 477 1.0 Initial version
|
||||
#---
|
||||
#
|
||||
# Setup for Digilent Atlys
|
||||
#
|
||||
# setup default board (for impact), device and userid (for bitgen)
|
||||
#
|
||||
ISE_BOARD = atlys
|
||||
ISE_PATH = xc6slx45-csg324-2
|
||||
#
|
||||
# setup defaults for xflow option files for synthesis and implementation
|
||||
#
|
||||
ifndef XFLOWOPT_SYN
|
||||
XFLOWOPT_SYN = syn_s6_speed.opt
|
||||
endif
|
||||
#
|
||||
ifndef XFLOWOPT_IMP
|
||||
XFLOWOPT_IMP = imp_s6_speed.opt
|
||||
endif
|
||||
#
|
||||
@ -3,6 +3,5 @@ and is organized in
|
||||
|
||||
| Directory | Content |
|
||||
| --------- | ------- |
|
||||
| [atlys](atlys) | design for Digilent Atlys |
|
||||
| [nexys2](nexys2) | design for Digilent Nexys2 |
|
||||
| [nexys3](nexys3) | design for Digilent Nexys3 |
|
||||
|
||||
@ -1 +0,0 @@
|
||||
sys_tst_rlink_cuff_ic_atlys.ucf
|
||||
@ -1,32 +0,0 @@
|
||||
# $Id: Makefile 1176 2019-06-30 07:16:06Z mueller $
|
||||
# SPDX-License-Identifier: GPL-3.0-or-later
|
||||
# Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
||||
#
|
||||
# Revision History:
|
||||
# Date Rev Version Comment
|
||||
# 2013-01-06 472 1.0 Initial version
|
||||
#
|
||||
#
|
||||
VBOM_all = $(wildcard *.vbom)
|
||||
BIT_all = $(VBOM_all:.vbom=.bit)
|
||||
#
|
||||
include ${RETROBASE}/rtl/make_ise/xflow_default_atlys.mk
|
||||
FX2_FILE = nexys3_jtag_2fifo_ic.ihx
|
||||
#
|
||||
.PHONY : all clean
|
||||
#
|
||||
all : $(BIT_all)
|
||||
#
|
||||
clean : ise_clean
|
||||
rm -f $(VBOM_all:.vbom=.ucf)
|
||||
#
|
||||
#----
|
||||
#
|
||||
include ${RETROBASE}/rtl/make_ise/generic_xflow.mk
|
||||
include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk
|
||||
#
|
||||
ifndef DONTINCDEP
|
||||
include $(VBOM_all:.vbom=.dep_xst)
|
||||
include $(VBOM_all:.vbom=.dep_ghdl)
|
||||
endif
|
||||
#
|
||||
@ -1,53 +0,0 @@
|
||||
-- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
|
||||
-- SPDX-License-Identifier: GPL-3.0-or-later
|
||||
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
||||
--
|
||||
------------------------------------------------------------------------------
|
||||
-- Package Name: sys_conf
|
||||
-- Description: Definitions for sys_tst_rlink_cuff_ic_atlys (for synthesis)
|
||||
--
|
||||
-- Dependencies: -
|
||||
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
|
||||
-- Revision History:
|
||||
-- Date Rev Version Comment
|
||||
-- 2013-01-06 472 1.0 Initial version
|
||||
------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
use work.slvtypes.all;
|
||||
|
||||
package sys_conf is
|
||||
|
||||
constant sys_conf_clkfx_divide : positive := 1;
|
||||
constant sys_conf_clkfx_multiply : positive := 1;
|
||||
|
||||
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
|
||||
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
|
||||
|
||||
constant sys_conf_fx2_type : string := "ic2";
|
||||
|
||||
-- dummy values defs for generic parameters of as controller
|
||||
constant sys_conf_fx2_rdpwldelay : positive := 1;
|
||||
constant sys_conf_fx2_rdpwhdelay : positive := 1;
|
||||
constant sys_conf_fx2_wrpwldelay : positive := 1;
|
||||
constant sys_conf_fx2_wrpwhdelay : positive := 1;
|
||||
constant sys_conf_fx2_flagdelay : positive := 1;
|
||||
|
||||
-- pktend timer setting
|
||||
-- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation)
|
||||
constant sys_conf_fx2_petowidth : positive := 10;
|
||||
|
||||
constant sys_conf_fx2_ccwidth : positive := 5;
|
||||
|
||||
-- derived constants
|
||||
|
||||
constant sys_conf_clksys : integer :=
|
||||
(100000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
|
||||
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
|
||||
|
||||
constant sys_conf_ser2rri_cdinit : integer :=
|
||||
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
|
||||
|
||||
end package sys_conf;
|
||||
@ -1,97 +0,0 @@
|
||||
# $Id: sys_tst_rlink_cuff_ic_atlys.imfset 769 2016-05-28 11:36:22Z mueller $
|
||||
#
|
||||
# ----------------------------------------------------------------------------
|
||||
[xst]
|
||||
Case statement is complete. others clause is never selected
|
||||
Using initial value '0' for reset since it is never assigned
|
||||
Using initial value '0' for fx2_tx2ena_l since it is never assigned
|
||||
|
||||
Net <FX2_TX2BUSY> does not have a driver.
|
||||
|
||||
Output port <LOCKED> of the instance <DCM> is unconnected
|
||||
Output port <RXAEMPTY> of the instance <FX2_CNTL_IC.CNTL> is unconnected
|
||||
Output port <TXAFULL> of the instance <FX2_CNTL_IC.CNTL> is unconnected
|
||||
Output port <FX2_TX2DATA> of the instance <TST> is unconnected
|
||||
Output port <FX2_TX2ENA> of the instance <TST> is unconnected
|
||||
Output port <SIZER> of the instance <TXFIFO> is unconnected
|
||||
Output port <DOA> of the instance <RAM> is unconnected
|
||||
Output port <RL_MONI_eop> of the instance <RLCORE> is unconnected
|
||||
Output port <RL_MONI_attn> of the instance <RLCORE> is unconnected
|
||||
Output port <RL_MONI_lamp> of the instance <RLCORE> is unconnected
|
||||
Output port <MONI_rxerr> of the instance <SERPORT> is unconnected
|
||||
Output port <MONI_rxovr> of the instance <SERPORT> is unconnected
|
||||
Output port <MONI_abdone> of the instance <SERPORT> is unconnected
|
||||
Output port <SIZE> of the instance <TXFIFO> is unconnected or connected
|
||||
Output port <SIZE> of the instance <FIFO> is unconnected or connected
|
||||
Output port <DOB> of the instance <BRAM> is unconnected
|
||||
|
||||
Signal <FX2_TX2DATA> is used but never assigned
|
||||
|
||||
Signal 'FX2_TX2BUSY', unconnected in block 'sys_tst_rlink_cuff_atlys'
|
||||
|
||||
Node <FX2_CNTL_IC.CNTL/R_MONI_[CS]_.*> of sequential type is unconnected
|
||||
Node <FX2_CNTL_IC.CNTL/R_REGS_moni_ep6_sel> of sequential type is unconnected
|
||||
Node <FX2_CNTL_IC.CNTL/R_REGS_moni_ep6_pf> of sequential type is unconnected
|
||||
Node <FX2_CNTL_IC.CNTL/R_REGS_moni_ep4_pf> of sequential type is unconnected
|
||||
ode <FX2_CNTL_IC.CNTL/R_REGS_moni_ep4_sel> of sequential type is unconnected
|
||||
Node <IOB_FX2_FLAG/R_DI_3> of sequential type is unconnected
|
||||
Node <HIO/R_REGS_swieff_[3-7]> of sequential type is unconnected
|
||||
Node <HIO/R_REGS_btn_[0-4]> of sequential type is unconnected
|
||||
Node <HIO/R_REGS_swi_[3-7]> of sequential type is unconnected
|
||||
Node <HIO/R_REGS_btneff_[0-4]> of sequential type is unconnected
|
||||
Node <FX2_CNTL_IC.CNTL/[RT]XFIFO/R_REG[RW]_size[rw]_\d> of sequential type is unconnected
|
||||
Node <TST/RLCORE/RL/R_REGS_monattn> of sequential type is unconnected
|
||||
Node <TST/RLCORE/RL/R_REGS_monlamp> of sequential type is unconnected
|
||||
Node <TST/RLCORE/RL/R_REGS_moneop> of sequential type is unconnected
|
||||
Node <TST/SERPORT/XONRX/R_REGS_rxovr> of sequential type is unconnected
|
||||
|
||||
Input <RB_MREQ_init> is never used
|
||||
Input <RB_MREQ_din<15:10>> is never used
|
||||
Input <SWI<7:3>> is never used
|
||||
Input <SWI<0:0>> is never used
|
||||
Input <BTN<3:0>> is never used
|
||||
Input <FX2_MONI_fifo_ep4> is never used
|
||||
Input <FX2_MONI_fifo_ep6> is never used
|
||||
Input <FX2_MONI_fifo_ep8> is never used
|
||||
Input <FX2_MONI_flag_ep4_empty> is never used
|
||||
Input <FX2_MONI_flag_ep4_almost> is never used
|
||||
Input <FX2_MONI_flag_ep6_full> is never used
|
||||
Input <FX2_MONI_flag_ep6_almost> is never used
|
||||
Input <FX2_MONI_flag_ep8_full> is never used
|
||||
Input <FX2_MONI_flag_ep8_almost> is never used
|
||||
Input <FX2_MONI_slrd> is never used
|
||||
Input <FX2_MONI_slwr> is never used
|
||||
Input <FX2_MONI_pktend> is never used
|
||||
|
||||
FF/Latch <R_MONI_[CS]_.*> has a constant value of 0
|
||||
FF/Latch <TX2ENA_PSTR/R_REGS_busy_1> has a constant value
|
||||
FF/Latch <TX2ENA_PSTR/R_REGS_busy_0> has a constant value
|
||||
|
||||
of type RAMB16_S18 has been replaced by RAMB16BWER
|
||||
of type RAMB16_S36 has been replaced by RAMB16BWER
|
||||
of type RAMB16_S36_S36 has been replaced by RAMB16BWER
|
||||
|
||||
FF/Latch <HIO/R_REGS_ledin_[2-6]> has a constant value of 0
|
||||
FF/Latch <FX2_CNTL_IC.CNTL/[RT]XFIFO/R_REG[RW]_rst.*> has a constant value
|
||||
|
||||
The FF/Latch <R_REGS_rbre> .* is equivalent
|
||||
The FF/Latch <HIO/HIO/HIO/DEB.DEB_SWI/R_REGS_cecnt_[01]> .* is equivalent
|
||||
|
||||
#
|
||||
# ----------------------------------------------------------------------------
|
||||
[tra]
|
||||
|
||||
#
|
||||
# ----------------------------------------------------------------------------
|
||||
[map]
|
||||
INFO:.*
|
||||
|
||||
#
|
||||
# ----------------------------------------------------------------------------
|
||||
[par]
|
||||
The signal I_FX2_FLAG<3>_IBUF has no load
|
||||
There are 1 loadless signals in this design
|
||||
|
||||
#
|
||||
# ----------------------------------------------------------------------------
|
||||
[bgn]
|
||||
@ -1,24 +0,0 @@
|
||||
## $Id: sys_tst_rlink_cuff_ic_atlys.ucf_cpp 472 2013-01-06 14:39:10Z mueller $
|
||||
##
|
||||
## Revision History:
|
||||
## Date Rev Version Comment
|
||||
## 2013-01-06 472 1.0 Initial version
|
||||
##
|
||||
|
||||
NET "I_CLK100" TNM_NET = "I_CLK100";
|
||||
TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %;
|
||||
OFFSET = IN 10 ns BEFORE "I_CLK100";
|
||||
OFFSET = OUT 20 ns AFTER "I_CLK100";
|
||||
|
||||
## std board
|
||||
##
|
||||
#include "bplib/atlys/atlys_pins.ucf"
|
||||
##
|
||||
## Pmod A0 - RS232
|
||||
##
|
||||
#include "bplib/atlys/atlys_pins_pma0_rs232.ucf"
|
||||
##
|
||||
## FX2 interface
|
||||
##
|
||||
#include "bplib/atlys/atlys_pins_fx2.ucf"
|
||||
#include "bplib/atlys/atlys_time_fx2_ic.ucf"
|
||||
@ -1,8 +0,0 @@
|
||||
# configure
|
||||
sys_conf = sys_conf.vhd
|
||||
# libs
|
||||
# components
|
||||
# design
|
||||
../sys_tst_rlink_cuff_atlys.vbom
|
||||
@ucf_cpp: sys_tst_rlink_cuff_ic_atlys.ucf
|
||||
@top: sys_tst_rlink_cuff_atlys
|
||||
@ -1,26 +0,0 @@
|
||||
# this is the vbom for the 'generic' top level entity
|
||||
# to be referenced in the vbom's of the specific systems
|
||||
# ./ic/sys_tst_rlink_cuff_ic_atlys
|
||||
# ./ic3/sys_tst_rlink_cuff_ic3_atlys
|
||||
#
|
||||
# libs
|
||||
../../../vlib/slvtypes.vhd
|
||||
../../../vlib/xlib/xlib.vhd
|
||||
../../../vlib/genlib/genlib.vhd
|
||||
../../../bplib/bpgen/bpgenlib.vbom
|
||||
../../../bplib/bpgen/bpgenrbuslib.vbom
|
||||
../../../vlib/rbus/rblib.vhd
|
||||
../../../bplib/fx2lib/fx2lib.vhd
|
||||
${sys_conf}
|
||||
# components
|
||||
[xst,vsyn]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom
|
||||
[ghdl,isim,vsim]../../../vlib/xlib/dcm_sfs_gsim.vbom
|
||||
../../../vlib/genlib/clkdivce.vbom
|
||||
../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom
|
||||
../../../bplib/bpgen/sn_humanio_demu_rbus.vbom
|
||||
../../../bplib/fx2lib/fx2_2fifoctl_ic.vbom
|
||||
../../../bplib/fx2lib/fx2_3fifoctl_ic.vbom
|
||||
../tst_rlink_cuff.vbom
|
||||
# design
|
||||
sys_tst_rlink_cuff_atlys.vhd
|
||||
## no @ucf_cpp
|
||||
@ -1,302 +0,0 @@
|
||||
-- $Id: sys_tst_rlink_cuff_atlys.vhd 1181 2019-07-08 17:00:50Z mueller $
|
||||
-- SPDX-License-Identifier: GPL-3.0-or-later
|
||||
-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
||||
--
|
||||
------------------------------------------------------------------------------
|
||||
-- Module Name: sys_tst_rlink_cuff_atlys - syn
|
||||
-- Description: rlink tester design for atlys with fx2 interface
|
||||
--
|
||||
-- Dependencies: vlib/xlib/dcm_sfs
|
||||
-- vlib/genlib/clkdivce
|
||||
-- bplib/bpgen/bp_rs232_2l4l_iob
|
||||
-- bplib/bpgen/sn_humanio_demu_rbus
|
||||
-- bplib/fx2lib/fx2_2fifoctl_ic [sys_conf_fx2_type="ic2"]
|
||||
-- bplib/fx2lib/fx2_3fifoctl_ic [sys_conf_fx2_type="ic3"]
|
||||
-- tst_rlink_cuff
|
||||
--
|
||||
-- Test bench: -
|
||||
--
|
||||
-- Target Devices: generic
|
||||
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
|
||||
--
|
||||
-- Synthesized (xst):
|
||||
-- Date Rev ise Target flop lutl lutm slic t peri ctl/MHz
|
||||
-- 2013-01-06 472 13.3 O76d xc6slx45 ??? ???? ??? ???? p ??.? ic2/100
|
||||
--
|
||||
-- Revision History:
|
||||
-- Date Rev Version Comment
|
||||
-- 2015-01-25 638 1.1.2 retire fx2_2fifoctl_as
|
||||
-- 2014-12-24 620 1.1.1 relocate hio rbus address
|
||||
-- 2014-08-15 583 1.1 rb_mreq addr now 16 bit
|
||||
-- 2013-01-06 472 1.0 Initial version; derived from sys_tst_rlink_cuff_n3
|
||||
-- and sys_tst_fx2loop_atlys
|
||||
------------------------------------------------------------------------------
|
||||
-- Usage of Atlys Switches, Buttons, LEDs:
|
||||
--
|
||||
-- SWI(7:3) no function (only connected to sn_humanio_demu_rbus)
|
||||
-- (2) 0 -> int/ext RS242 port for rlink
|
||||
-- 1 -> use USB interface for rlink
|
||||
-- (1) 1 enable XON
|
||||
-- (0) 0 -> main board RS232 port - implemented in bp_rs232_2l4l_iob
|
||||
-- 1 -> Pmod B/top RS232 port /
|
||||
--
|
||||
-- LED(7) SER_MONI.abact
|
||||
-- (6:2) no function (only connected to sn_humanio_demu_rbus)
|
||||
-- (1) timer 1 busy
|
||||
-- (0) timer 0 busy
|
||||
--
|
||||
-- DSP: SER_MONI.clkdiv (from auto bauder)
|
||||
-- for SWI(2)='0' (serport)
|
||||
-- DP(3) not SER_MONI.txok (shows tx back pressure)
|
||||
-- (2) SER_MONI.txact (shows tx activity)
|
||||
-- (1) not SER_MONI.rxok (shows rx back pressure)
|
||||
-- (0) SER_MONI.rxact (shows rx activity)
|
||||
-- for SWI(2)='1' (fx2)
|
||||
-- DP(3) FX2_TX2BUSY (shows tx2 back pressure)
|
||||
-- (2) FX2_TX2ENA(stretched) (shows tx2 activity)
|
||||
-- (1) FX2_TXENA(streched) (shows tx activity)
|
||||
-- (0) FX2_RXVAL(stretched) (shows rx activity)
|
||||
--
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
use work.slvtypes.all;
|
||||
use work.xlib.all;
|
||||
use work.genlib.all;
|
||||
use work.bpgenlib.all;
|
||||
use work.bpgenrbuslib.all;
|
||||
use work.rblib.all;
|
||||
use work.fx2lib.all;
|
||||
use work.sys_conf.all;
|
||||
|
||||
-- ----------------------------------------------------------------------------
|
||||
|
||||
entity sys_tst_rlink_cuff_atlys is -- top level
|
||||
-- implements atlys_fusp_cuff_aif
|
||||
port (
|
||||
I_CLK100 : in slbit; -- 100 MHz clock
|
||||
I_USB_RXD : in slbit; -- USB UART receive data (board view)
|
||||
O_USB_TXD : out slbit; -- USB UART transmit data (board view)
|
||||
I_HIO_SWI : in slv8; -- atlys hio switches
|
||||
I_HIO_BTN : in slv6; -- atlys hio buttons
|
||||
O_HIO_LED: out slv8; -- atlys hio leds
|
||||
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
|
||||
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
|
||||
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
|
||||
O_FUSP_TXD : out slbit; -- fusp: rs232 tx
|
||||
I_FX2_IFCLK : in slbit; -- fx2: interface clock
|
||||
O_FX2_FIFO : out slv2; -- fx2: fifo address
|
||||
I_FX2_FLAG : in slv4; -- fx2: fifo flags
|
||||
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
|
||||
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
|
||||
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
|
||||
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
|
||||
IO_FX2_DATA : inout slv8 -- fx2: data lines
|
||||
);
|
||||
end sys_tst_rlink_cuff_atlys;
|
||||
|
||||
architecture syn of sys_tst_rlink_cuff_atlys is
|
||||
|
||||
signal CLK : slbit := '0';
|
||||
signal RESET : slbit := '0';
|
||||
|
||||
signal CE_USEC : slbit := '0';
|
||||
signal CE_MSEC : slbit := '0';
|
||||
|
||||
signal RXSD : slbit := '0';
|
||||
signal TXSD : slbit := '0';
|
||||
signal CTS_N : slbit := '0';
|
||||
signal RTS_N : slbit := '0';
|
||||
|
||||
signal SWI : slv8 := (others=>'0');
|
||||
signal BTN : slv4 := (others=>'0');
|
||||
signal LED : slv8 := (others=>'0');
|
||||
signal DSP_DAT : slv16 := (others=>'0');
|
||||
signal DSP_DP : slv4 := (others=>'0');
|
||||
|
||||
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
|
||||
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
|
||||
|
||||
signal FX2_RXDATA : slv8 := (others=>'0');
|
||||
signal FX2_RXVAL : slbit := '0';
|
||||
signal FX2_RXHOLD : slbit := '0';
|
||||
signal FX2_RXAEMPTY : slbit := '0';
|
||||
signal FX2_TXDATA : slv8 := (others=>'0');
|
||||
signal FX2_TXENA : slbit := '0';
|
||||
signal FX2_TXBUSY : slbit := '0';
|
||||
signal FX2_TXAFULL : slbit := '0';
|
||||
signal FX2_TX2DATA : slv8 := (others=>'0');
|
||||
signal FX2_TX2ENA : slbit := '0';
|
||||
signal FX2_TX2BUSY : slbit := '0';
|
||||
signal FX2_TX2AFULL : slbit := '0';
|
||||
signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init;
|
||||
|
||||
constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx
|
||||
|
||||
begin
|
||||
|
||||
assert (sys_conf_clksys mod 1000000) = 0
|
||||
report "assert sys_conf_clksys on MHz grid"
|
||||
severity failure;
|
||||
|
||||
DCM : dcm_sfs
|
||||
generic map (
|
||||
CLKFX_DIVIDE => sys_conf_clkfx_divide,
|
||||
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
|
||||
CLKIN_PERIOD => 10.0)
|
||||
port map (
|
||||
CLKIN => I_CLK100,
|
||||
CLKFX => CLK,
|
||||
LOCKED => open
|
||||
);
|
||||
|
||||
CLKDIV : clkdivce
|
||||
generic map (
|
||||
CDUWIDTH => 7, -- good for up to 127 MHz !
|
||||
USECDIV => sys_conf_clksys_mhz,
|
||||
MSECDIV => 1000)
|
||||
port map (
|
||||
CLK => CLK,
|
||||
CE_USEC => CE_USEC,
|
||||
CE_MSEC => CE_MSEC
|
||||
);
|
||||
|
||||
IOB_RS232 : bp_rs232_2l4l_iob
|
||||
port map (
|
||||
CLK => CLK,
|
||||
RESET => '0',
|
||||
SEL => SWI(0),
|
||||
RXD => RXSD,
|
||||
TXD => TXSD,
|
||||
CTS_N => CTS_N,
|
||||
RTS_N => RTS_N,
|
||||
I_RXD0 => I_USB_RXD,
|
||||
O_TXD0 => O_USB_TXD,
|
||||
I_RXD1 => I_FUSP_RXD,
|
||||
O_TXD1 => O_FUSP_TXD,
|
||||
I_CTS1_N => I_FUSP_CTS_N,
|
||||
O_RTS1_N => O_FUSP_RTS_N
|
||||
);
|
||||
|
||||
HIO : sn_humanio_demu_rbus
|
||||
generic map (
|
||||
DEBOUNCE => sys_conf_hio_debounce,
|
||||
RB_ADDR => rbaddr_hio)
|
||||
port map (
|
||||
CLK => CLK,
|
||||
RESET => RESET,
|
||||
CE_MSEC => CE_MSEC,
|
||||
RB_MREQ => RB_MREQ,
|
||||
RB_SRES => RB_SRES_HIO,
|
||||
SWI => SWI,
|
||||
BTN => BTN,
|
||||
LED => LED,
|
||||
DSP_DAT => DSP_DAT,
|
||||
DSP_DP => DSP_DP,
|
||||
I_SWI => I_HIO_SWI,
|
||||
I_BTN => I_HIO_BTN,
|
||||
O_LED => O_HIO_LED
|
||||
);
|
||||
|
||||
FX2_CNTL_IC : if sys_conf_fx2_type = "ic2" generate
|
||||
CNTL : fx2_2fifoctl_ic
|
||||
generic map (
|
||||
RXFAWIDTH => 5,
|
||||
TXFAWIDTH => 5,
|
||||
PETOWIDTH => sys_conf_fx2_petowidth,
|
||||
CCWIDTH => sys_conf_fx2_ccwidth,
|
||||
RXAEMPTY_THRES => 1,
|
||||
TXAFULL_THRES => 1)
|
||||
port map (
|
||||
CLK => CLK,
|
||||
RESET => RESET,
|
||||
RXDATA => FX2_RXDATA,
|
||||
RXVAL => FX2_RXVAL,
|
||||
RXHOLD => FX2_RXHOLD,
|
||||
RXAEMPTY => FX2_RXAEMPTY,
|
||||
TXDATA => FX2_TXDATA,
|
||||
TXENA => FX2_TXENA,
|
||||
TXBUSY => FX2_TXBUSY,
|
||||
TXAFULL => FX2_TXAFULL,
|
||||
MONI => FX2_MONI,
|
||||
I_FX2_IFCLK => I_FX2_IFCLK,
|
||||
O_FX2_FIFO => O_FX2_FIFO,
|
||||
I_FX2_FLAG => I_FX2_FLAG,
|
||||
O_FX2_SLRD_N => O_FX2_SLRD_N,
|
||||
O_FX2_SLWR_N => O_FX2_SLWR_N,
|
||||
O_FX2_SLOE_N => O_FX2_SLOE_N,
|
||||
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
|
||||
IO_FX2_DATA => IO_FX2_DATA
|
||||
);
|
||||
end generate FX2_CNTL_IC;
|
||||
|
||||
FX2_CNTL_IC3 : if sys_conf_fx2_type = "ic3" generate
|
||||
CNTL : fx2_3fifoctl_ic
|
||||
generic map (
|
||||
RXFAWIDTH => 5,
|
||||
TXFAWIDTH => 5,
|
||||
PETOWIDTH => sys_conf_fx2_petowidth,
|
||||
CCWIDTH => sys_conf_fx2_ccwidth,
|
||||
RXAEMPTY_THRES => 1,
|
||||
TXAFULL_THRES => 1,
|
||||
TX2AFULL_THRES => 1)
|
||||
port map (
|
||||
CLK => CLK,
|
||||
RESET => RESET,
|
||||
RXDATA => FX2_RXDATA,
|
||||
RXVAL => FX2_RXVAL,
|
||||
RXHOLD => FX2_RXHOLD,
|
||||
RXAEMPTY => FX2_RXAEMPTY,
|
||||
TXDATA => FX2_TXDATA,
|
||||
TXENA => FX2_TXENA,
|
||||
TXBUSY => FX2_TXBUSY,
|
||||
TXAFULL => FX2_TXAFULL,
|
||||
TX2DATA => FX2_TX2DATA,
|
||||
TX2ENA => FX2_TX2ENA,
|
||||
TX2BUSY => FX2_TX2BUSY,
|
||||
TX2AFULL => FX2_TX2AFULL,
|
||||
MONI => FX2_MONI,
|
||||
I_FX2_IFCLK => I_FX2_IFCLK,
|
||||
O_FX2_FIFO => O_FX2_FIFO,
|
||||
I_FX2_FLAG => I_FX2_FLAG,
|
||||
O_FX2_SLRD_N => O_FX2_SLRD_N,
|
||||
O_FX2_SLWR_N => O_FX2_SLWR_N,
|
||||
O_FX2_SLOE_N => O_FX2_SLOE_N,
|
||||
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
|
||||
IO_FX2_DATA => IO_FX2_DATA
|
||||
);
|
||||
end generate FX2_CNTL_IC3;
|
||||
|
||||
TST : entity work.tst_rlink_cuff
|
||||
port map (
|
||||
CLK => CLK,
|
||||
RESET => '0',
|
||||
CE_USEC => CE_USEC,
|
||||
CE_MSEC => CE_MSEC,
|
||||
RB_MREQ_TOP => RB_MREQ,
|
||||
RB_SRES_TOP => RB_SRES_HIO,
|
||||
SWI => SWI,
|
||||
BTN => BTN(3 downto 0),
|
||||
LED => LED,
|
||||
DSP_DAT => DSP_DAT,
|
||||
DSP_DP => DSP_DP,
|
||||
RXSD => RXSD,
|
||||
TXSD => TXSD,
|
||||
RTS_N => RTS_N,
|
||||
CTS_N => CTS_N,
|
||||
FX2_RXDATA => FX2_RXDATA,
|
||||
FX2_RXVAL => FX2_RXVAL,
|
||||
FX2_RXHOLD => FX2_RXHOLD,
|
||||
FX2_TXDATA => FX2_TXDATA,
|
||||
FX2_TXENA => FX2_TXENA,
|
||||
FX2_TXBUSY => FX2_TXBUSY,
|
||||
FX2_TX2DATA => FX2_TX2DATA,
|
||||
FX2_TX2ENA => FX2_TX2ENA,
|
||||
FX2_TX2BUSY => FX2_TX2BUSY,
|
||||
FX2_MONI => FX2_MONI
|
||||
);
|
||||
|
||||
end syn;
|
||||
|
||||
@ -3,7 +3,6 @@ and is organized in
|
||||
|
||||
| Directory | Content |
|
||||
| --------- | ------- |
|
||||
| [atlys](atlys) | design for Digilent Atlys |
|
||||
| [basys3](basys3) | design for Digilent Basys3 |
|
||||
| [nexys2](nexys2) | design for Digilent Nexys2 |
|
||||
| [nexys3](nexys3) | design for Digilent Nexys3 |
|
||||
|
||||
1
rtl/sys_gen/tst_snhumanio/atlys/.gitignore
vendored
1
rtl/sys_gen/tst_snhumanio/atlys/.gitignore
vendored
@ -1 +0,0 @@
|
||||
sys_tst_snhumanio_atlys.ucf
|
||||
@ -1,30 +0,0 @@
|
||||
# $Id: Makefile 1176 2019-06-30 07:16:06Z mueller $
|
||||
# SPDX-License-Identifier: GPL-3.0-or-later
|
||||
# Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
||||
#
|
||||
# Revision History:
|
||||
# Date Rev Version Comment
|
||||
# 2011-10-11 414 1.0 Initial version
|
||||
#
|
||||
VBOM_all = $(wildcard *.vbom)
|
||||
BIT_all = $(VBOM_all:.vbom=.bit)
|
||||
#
|
||||
include ${RETROBASE}/rtl/make_ise/xflow_default_atlys.mk
|
||||
#
|
||||
.PHONY : all clean
|
||||
#
|
||||
all : $(BIT_all)
|
||||
#
|
||||
clean : ise_clean
|
||||
rm -f $(VBOM_all:.vbom=.ucf)
|
||||
#
|
||||
#----
|
||||
#
|
||||
include ${RETROBASE}/rtl/make_ise/generic_xflow.mk
|
||||
include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk
|
||||
#
|
||||
ifndef DONTINCDEP
|
||||
include $(VBOM_all:.vbom=.dep_xst)
|
||||
include $(VBOM_all:.vbom=.dep_ghdl)
|
||||
endif
|
||||
#
|
||||
@ -1,26 +0,0 @@
|
||||
-- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
|
||||
-- SPDX-License-Identifier: GPL-3.0-or-later
|
||||
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
||||
--
|
||||
------------------------------------------------------------------------------
|
||||
-- Package Name: sys_conf
|
||||
-- Description: Definitions for sys_tst_snhumanio_atlys (for synthesis)
|
||||
--
|
||||
-- Dependencies: -
|
||||
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31
|
||||
-- Revision History:
|
||||
-- Date Rev Version Comment
|
||||
-- 2011-10-11 414 1.0 Initial version
|
||||
------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
use work.slvtypes.all;
|
||||
|
||||
package sys_conf is
|
||||
|
||||
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
|
||||
|
||||
end package sys_conf;
|
||||
|
||||
@ -1,29 +0,0 @@
|
||||
# $Id: sys_tst_snhumanio_atlys.imfset 769 2016-05-28 11:36:22Z mueller $
|
||||
#
|
||||
# ----------------------------------------------------------------------------
|
||||
[xst]
|
||||
INFO:.*Case statement is complete. others clause is never selected
|
||||
|
||||
sys_tst_snhumanio_atlys\..*Output port <CE_USEC> of the instance <CLKDIV> is unconnected
|
||||
|
||||
Node <CLKDIV/R_REGS_usec> of sequential type is unconnected
|
||||
|
||||
The FF/Latch <HIO/HIO/DEB.DEB_SWI/R_REGS_cecnt_[0-1]> in Unit <.*> is equivalent
|
||||
The small RAM <.*> will be implemented on LUTs
|
||||
|
||||
#
|
||||
# ----------------------------------------------------------------------------
|
||||
[tra]
|
||||
|
||||
#
|
||||
# ----------------------------------------------------------------------------
|
||||
[map]
|
||||
INFO:.*
|
||||
|
||||
#
|
||||
# ----------------------------------------------------------------------------
|
||||
[par]
|
||||
|
||||
#
|
||||
# ----------------------------------------------------------------------------
|
||||
[bgn]
|
||||
@ -1,16 +0,0 @@
|
||||
## $Id: sys_tst_snhumanio_atlys.ucf_cpp 414 2011-10-11 19:38:12Z mueller $
|
||||
##
|
||||
## Revision History:
|
||||
## Date Rev Version Comment
|
||||
## 2011-10-11 414 1.0 Initial version
|
||||
##
|
||||
|
||||
NET "I_CLK100" TNM_NET = "I_CLK100";
|
||||
TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %;
|
||||
OFFSET = IN 10 ns BEFORE "I_CLK100";
|
||||
OFFSET = OUT 20 ns AFTER "I_CLK100";
|
||||
|
||||
## std board
|
||||
##
|
||||
#include "bplib/atlys/atlys_pins.ucf"
|
||||
#include "bplib/atlys/atlys_pins_pma0_rs232.ucf"
|
||||
@ -1,12 +0,0 @@
|
||||
# libs
|
||||
../../../vlib/slvtypes.vhd
|
||||
../../../vlib/genlib/genlib.vhd
|
||||
../../../bplib/bpgen/bpgenlib.vbom
|
||||
${sys_conf := sys_conf.vhd}
|
||||
# components
|
||||
../../../vlib/genlib/clkdivce.vbom
|
||||
../../../bplib/bpgen/sn_humanio_demu.vbom
|
||||
../tst_snhumanio.vbom
|
||||
# design
|
||||
sys_tst_snhumanio_atlys.vhd
|
||||
@ucf_cpp: sys_tst_snhumanio_atlys.ucf
|
||||
@ -1,121 +0,0 @@
|
||||
-- $Id: sys_tst_snhumanio_atlys.vhd 1181 2019-07-08 17:00:50Z mueller $
|
||||
-- SPDX-License-Identifier: GPL-3.0-or-later
|
||||
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
||||
--
|
||||
------------------------------------------------------------------------------
|
||||
-- Module Name: sys_tst_snhumanio_atlys - syn
|
||||
-- Description: snhumanio tester design for atlys
|
||||
--
|
||||
-- Dependencies: vlib/genlib/clkdivce
|
||||
-- bplib/bpgen/sn_humanio_demu
|
||||
-- tst_snhumanio
|
||||
--
|
||||
-- Test bench: -
|
||||
--
|
||||
-- Target Devices: generic
|
||||
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31
|
||||
--
|
||||
-- Synthesized (xst):
|
||||
-- Date Rev ise Target flop lutl lutm slic t peri
|
||||
-- 2011-10-11 414 13.1 O40d xc6slx45 166 196 - 60 t 4.9
|
||||
--
|
||||
-- Revision History:
|
||||
-- Date Rev Version Comment
|
||||
-- 2011-10-11 414 1.0 Initial version
|
||||
------------------------------------------------------------------------------
|
||||
-- Usage of Atlys Switches, Buttons, LEDs:
|
||||
--
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
use work.slvtypes.all;
|
||||
use work.genlib.all;
|
||||
use work.bpgenlib.all;
|
||||
use work.sys_conf.all;
|
||||
|
||||
-- ----------------------------------------------------------------------------
|
||||
|
||||
entity sys_tst_snhumanio_atlys is -- top level
|
||||
-- implements atlys_aif
|
||||
port (
|
||||
I_CLK100 : in slbit; -- 100 MHz clock
|
||||
-- O_CLKSYS : out slbit; -- DCM derived system clock
|
||||
I_USB_RXD : in slbit; -- USB UART receive data (board view)
|
||||
O_USB_TXD : out slbit; -- USB UART transmit data (board view)
|
||||
I_HIO_SWI : in slv8; -- atlys hio switches
|
||||
I_HIO_BTN : in slv6; -- atlys hio buttons
|
||||
O_HIO_LED: out slv8; -- atlys hio leds
|
||||
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
|
||||
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
|
||||
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
|
||||
O_FUSP_TXD : out slbit -- fusp: rs232 tx
|
||||
);
|
||||
end sys_tst_snhumanio_atlys;
|
||||
|
||||
architecture syn of sys_tst_snhumanio_atlys is
|
||||
|
||||
signal CLK : slbit := '0';
|
||||
|
||||
signal SWI : slv8 := (others=>'0');
|
||||
signal BTN : slv4 := (others=>'0');
|
||||
signal LED : slv8 := (others=>'0');
|
||||
signal DSP_DAT : slv16 := (others=>'0');
|
||||
signal DSP_DP : slv4 := (others=>'0');
|
||||
|
||||
signal RESET : slbit := '0';
|
||||
signal CE_MSEC : slbit := '0';
|
||||
|
||||
begin
|
||||
|
||||
RESET <= '0'; -- so far not used
|
||||
|
||||
CLK <= I_CLK100;
|
||||
|
||||
CLKDIV : clkdivce
|
||||
generic map (
|
||||
CDUWIDTH => 7,
|
||||
USECDIV => 100,
|
||||
MSECDIV => 1000)
|
||||
port map (
|
||||
CLK => CLK,
|
||||
CE_USEC => open,
|
||||
CE_MSEC => CE_MSEC
|
||||
);
|
||||
|
||||
HIO : sn_humanio_demu
|
||||
generic map (
|
||||
DEBOUNCE => sys_conf_hio_debounce)
|
||||
port map (
|
||||
CLK => CLK,
|
||||
RESET => RESET,
|
||||
CE_MSEC => CE_MSEC,
|
||||
SWI => SWI,
|
||||
BTN => BTN,
|
||||
LED => LED,
|
||||
DSP_DAT => DSP_DAT,
|
||||
DSP_DP => DSP_DP,
|
||||
I_SWI => I_HIO_SWI,
|
||||
I_BTN => I_HIO_BTN,
|
||||
O_LED => O_HIO_LED
|
||||
);
|
||||
|
||||
HIOTEST : entity work.tst_snhumanio
|
||||
generic map (
|
||||
BWIDTH => 4)
|
||||
port map (
|
||||
CLK => CLK,
|
||||
RESET => RESET,
|
||||
CE_MSEC => CE_MSEC,
|
||||
SWI => SWI,
|
||||
BTN => BTN,
|
||||
LED => LED,
|
||||
DSP_DAT => DSP_DAT,
|
||||
DSP_DP => DSP_DP
|
||||
);
|
||||
|
||||
O_USB_TXD <= I_USB_RXD;
|
||||
O_FUSP_TXD <= I_FUSP_RXD;
|
||||
O_FUSP_RTS_N <= I_FUSP_CTS_N;
|
||||
|
||||
end syn;
|
||||
@ -1,7 +1,6 @@
|
||||
This directory contains udev rules which ensure that the Cypress FX2 on
|
||||
- Digilent Nexys2
|
||||
- Digilent Nexys3
|
||||
- Digilent Atlys
|
||||
|
||||
is read/write accessible for user land processes, either in
|
||||
- original power on state _(thus Digilent VID/PID)_
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user