diff --git a/doc/README.txt b/doc/README.txt
index ee186d19..f119a982 100644
--- a/doc/README.txt
+++ b/doc/README.txt
@@ -1,4 +1,4 @@
-# $Id: README.txt 341 2010-11-27 23:05:43Z mueller $
+# $Id: README.txt 351 2010-12-30 21:50:54Z mueller $
 
 Release notes for w11a
 
@@ -9,7 +9,7 @@ Release notes for w11a
   3. Change Log
 
 
-1. Documentation ----------------------------------------------------------
+1. Documentation -------------------------------------------------------------
 
   More detailed information on installation, build and test can be found 
   in the doc directory, specifically
@@ -20,7 +20,7 @@ Release notes for w11a
     * w11a_os_guide.txt: booting operating systems 
     * w11a_known_issues.txt: known differences, limitations and issues
 
-2. Files ------------------------------------------------------------------
+2. Files ---------------------------------------------------------------------
 
    doc                          Documentation
    rtl                          VHDL sources
@@ -38,7 +38,8 @@ Release notes for w11a
    rtl/vlib/comlib                - communication
    rtl/vlib/genlib                - general
    rtl/vlib/memlib                - memory
-   rtl/vlib/rri                   - remote-register-interface
+   rtl/vlib/rbus                  - rri: rbus
+   rtl/vlib/rlink                 - rri: rlink
    rtl/vlib/serport               - serial port (UART)
    rtl/vlib/simlib                - simulation helper lib
    rtl/vlib/xlib                  - Xilinx specific components
@@ -46,9 +47,86 @@ Release notes for w11a
    tools                        helper programs
    tools/bin                    - scripts and binaries
 
-3. Change Log -------------------------------------------------------------
+3. Change Log ----------------------------------------------------------------
 
-- trunk (2010-11-28: svn rev 8(oc) 341(wfjm); untagged w11a_V0.51)
+- trunk (2011-01-02: svn rev 9(oc) 352(wfjm); untagged w11a_V0.52) +++++++++
+
+  - Summary
+    - Introduced rbus protocol V3
+    - reorganize rbus and rlink modules, many renames
+
+  - Changes
+    - module renames:
+      - the rri (remote-register-interface) components were re-organized and
+        cleanly separated into rbus and rlink components:
+          rri/rb_sres_or_*              -> rbus/rb_sres_or_*     
+          rri/rri_core                  -> rlink/rlink_core    
+          rri/rri_base_serport          -> rlink/rlink_base_serport    
+          rri/rrilib                    -> rbus/rblib    
+                                        -> rlink/rlinklib    
+          rri/rri_serport               -> rlink/rlink_serport    
+          rri/tb/rritb_sres_or_mon      -> rbus/rb_sres_or_mon    
+      - the rri test bench monitors were reorganized and renamed
+          rri/tb/rritb_cpmon            -> rlink/rlink_mon    
+          rri/tb/rritb_cpmon_sb         -> rlink/rlink_mon_sb    
+          rri/tb/rritb_rbmon            -> rbus/rb_mon    
+          rri/tb/rritb_rbmon_sb         -> rbus/rb_mon_sb    
+      - the rri low level test bench were also renamed
+          rri/tb/tb_rri                 -> rlink/tb/tb_rlink    
+          rri/tb/tb_rri_core            -> rlink/tb/tb_rlink_direct    
+          rri/tb/tb_rri_serport         -> rlink/tb/tb_rlink_serport    
+      - the base modules for rlink+cext based test benches were renamed
+          rri/tb/rritb_core_cm          -> rlink/tb/tbcore_rlink_dcm
+          rri/tb/rritb_core             -> rlink/tb/tbcore_rlink
+          rri/tb/vhpi_rriext            -> rlink/tb/rlink_cext_vhpi
+          rri/tb/cext_rriext.c          -> rlink/tb/rlink_cext.c
+
+      - other rri/rbus related renames
+          bplib/s3board/s3_humanio_rri  -> s3_humanio_rbus
+          w11a/pdp11_core_rri           -> pdp11_core_rbus
+
+      - other renames
+          w11a/tb/tb_pdp11_core         -> tb_pdp11core
+
+    - signal renames:
+      - rlink interface (defined in rlink/rlinklib.vhd): 
+        - rename rlink port signals:
+          CP_*  -> RL_*
+        - rename status bit names to better reflect their usage in v3:
+          ccrc  -> cerr   - indicates cmd crc error or other cmd level abort
+          dcrc  -> derr   - indicates data crc error or other data level abort
+          ioto  -> rbnak  - indicates rbus abort, either no ack or timeout
+          ioerr -> rberr  - indicates that rbus err flag was set
+
+    - migrate to rbus protocol verion 3
+      - in rb_mreq use now aval,re,we instead of req,we
+      - basic rbus transaction now takes 2 cycles, one for address select, one
+        for data exchange. Same concept and reasoning behind as in ibus V2.
+
+    - vlib/rlink/rlink_core
+      - cerr and derr state flags now set on command or data crc errors as well
+        as on eop/nak aborts when command or wblk data is received.
+      - has now 'monitor port', RL_MONI.
+      - RL_FLUSH port removed, the flush logic is now in rlink_serport
+
+    - restructured rlink modules
+      - rlink_core is the rlink protocol engine with a 9 bit wide interface
+      - rlink_rlb2rl (new) is an adapter to a byte wide interface
+      - rlink_base (new) combines rlink_core and rlink_rlb2rl
+      - rlink_serport (re-written) is an adapter to a serial interface
+      - rlink_base_serport (renamed) combines rlink_base and rlink_serport
+
+  - New features
+    - vlib/rbus
+      - added several rbus devices useful for debugging
+        - rbd_tester: test target, used for example in test benches
+
+- trunk (2010-11-28: svn rev 8(oc) 341(wfjm); untagged w11a_V0.51) ++++++++
+
+  - Summary 
+    - Introduced ibus protocol V2
+    - Nexys2 systems use DCM
+    - sys_w11a_n2 now runs with 58 MHz
 
   - Changes
     - module renames:
@@ -66,7 +144,7 @@ Release notes for w11a
     - migrate to ibus protocol verion 2
       - in ib_mreq use now aval,re,we,rmw instead of req,we,dip
       - basic ibus transaction now takes 2 cycles, one for address select, one
-        for data exchange. This avoids too long logic paths in ibus sector.
+        for data exchange. This avoids too long logic paths in the ibus logic.
 
   - New features
     - ibus
@@ -80,7 +158,7 @@ Release notes for w11a
   - Bug fixes
     - rtl/vlib/Makefile.xflow: use default .opt files under rtl/vlib again.
 
-- w11a_V0.5 (2010-07-23) -------------------------------------
+- w11a_V0.5 (2010-07-23) ++++++++++++++++++++++++++++++++++++++++++++++++++
 
   Initial release with 
   - w11a CPU core
diff --git a/doc/w11a_seq_flow.DOT b/doc/w11a_seq_flow.DOT
index 257822d8..803f203f 100644
--- a/doc/w11a_seq_flow.DOT
+++ b/doc/w11a_seq_flow.DOT
@@ -1,10 +1,15 @@
-// $Id: w11a_seq_flow.DOT 315 2010-07-11 22:18:39Z mueller $
+// $Id: w11a_seq_flow.DOT 343 2010-12-05 21:24:38Z mueller $
 //
 // The create pdf use
 //
 //  cpp w11a_seq_flow.DOT w11a_seq_flow.dot
-//  dot -Tps2 w11a_seq_flow.dot > w11a_seq_flow.ps
-//  ps2pdf w11a_seq_flow.ps
+//  dot -Tpdf w11a_seq_flow.dot > w11a_seq_flow.pdf
+//  xpdf w11a_seq_flow.pdf
+//  -> gives 30.54 x 43.92 in page size
+//
+//  pdflatex w11a_seq_flow_a4wrap.tex
+//  xpdf w11a_seq_flow_a4wrap.pdf
+//  --> gives 8.27 x 11.69 in page size (A4)
 //
 
 #define FORKSTATE
diff --git a/doc/w11a_tb_guide.txt b/doc/w11a_tb_guide.txt
index 39421835..29fba0f1 100644
--- a/doc/w11a_tb_guide.txt
+++ b/doc/w11a_tb_guide.txt
@@ -1,4 +1,4 @@
-# $Id: w11a_tb_guide.txt 317 2010-07-22 19:36:56Z mueller $
+# $Id: w11a_tb_guide.txt 352 2011-01-02 13:01:37Z mueller $
 
 Guide to running w11a test benches
 
@@ -65,66 +65,75 @@ Guide to running w11a test benches
      make tb_serport_uart_rx
      time tbw tb_serport_uart_rx |\
        tee tb_serport_uart_rx_dsim.log | egrep "(FAIL|DONE)"
-     -> 1269955 ns  63488: DONE 
+     -> 1269955.0 ns  63488: DONE 
+     -> real    0m1.178s   user    0m1.172s   sys     0m0.020s
+
 
    - serport receiver/transmitter test
      make tb_serport_uart_rxtx
      time tbw tb_serport_uart_rxtx |\
        tee tb_serport_uart_rxtx_dsim.log | egrep "(FAIL|DONE)"
-     ->  52335 ns   2607: DONE 
+     ->  52335.0 ns   2607: DONE 
+     -> real    0m0.094s   user    0m0.092s   sys     0m0.008s
 
    - serport autobauder test
      make tb_serport_autobaud
      time tbw tb_serport_autobaud |\
        tee tb_serport_autobaud_dsim.log | egrep "(FAIL|DONE)"
-     -> 367475 ns  18364: DONE 
+     -> 367475.0 ns  18364: DONE 
+     -> real    0m0.610s   user    0m0.612s   sys     0m0.004s
 
-   - rri core test
+   - rlink core test
 
-     cd $RETROBASE/rtl/vlib/rri/tb
-     make tb_rri_core
-     time tbw tb_rri_core |\
-       tee tb_rri_core_dsim.log | egrep "(FAIL|DONE)"
-     ->  61855 ns   3083: DONE
-     -> real    0m0.163s   user    0m0.128s   sys     0m0.020s
+     cd $RETROBASE/rtl/vlib/rlink/tb
+     make tb_rlink_direct
+     time tbw tb_rlink_direct |\
+       tee tb_rlink_direct_dsim.log | egrep "(FAIL|DONE)"
+     ->  142355.0 ns   7108: DONE 
+     -> real    0m0.317s   user    0m0.324s   sys     0m0.028s
 
-   - rri core test via serial port interface
+   - rlink core test via serial port interface
 
-     make tb_rri_serport
-     time tbw tb_rri_serport |\
-       tee tb_rri_serport_dsim.log | egrep "(FAIL|DONE)"
-     -> 273355 ns  13658: DONE
-     -> real    0m0.939s   user    0m0.924s   sys     0m0.008s
+     make tb_rlink_serport
+     time tbw tb_rlink_serport tb_rlink_serport_stim.dat |\
+       tee tb_rlink_serport_stim2_dsim.log | egrep "(FAIL|DONE)"
+     ->   72735.0 ns   3627: DONE 
+     -> real    0m0.266s   user    0m0.264s   sys     0m0.008s
+
+     time tbw tb_rlink_serport tb_rlink_stim.dat |\
+       tee tb_rlink_serport_dsim.log | egrep "(FAIL|DONE)"
+     -> 536155.0 ns  26798: DONE 
+     -> real    0m1.714s   user    0m1.704s   sys     0m0.044s
 
    - w11a core test (using behavioural model)
 
      cd $RETROBASE/rtl/w11a/tb
-     make tb_pdp11_core
-     time tbw tb_pdp11_core |\
-       tee tb_pdp11_core_dsim.log | egrep "(FAIL|DONE)"
-     -> 1220255 ns  61003: DONE 
-     -> real    0m14.964s   user    0m14.977s   sys     0m0.108s
+     make tb_pdp11core
+     time tbw tb_pdp11core |\
+       tee tb_pdp11core_dsim.log | egrep "(FAIL|DONE)"
+     -> 1220255.0 ns  61003: DONE 
+     -> real    0m10.736s   user    0m10.713s   sys     0m0.060s
 
    - w11a core test (using post-synthesis model)
 
-     make ghdl_tmp_clean tb_pdp11_core_ssim
-     time tbw tb_pdp11_core_ssim |\
-       tee tb_pdp11_core_ssim.log | egrep "(FAIL|DONE)"
-     ->  1220255 ns  61003: DONE 
-     -> real    1m8.230s   user    1m8.144s   sys     0m0.124s
+     make ghdl_tmp_clean tb_pdp11core_ssim
+     time tbw tb_pdp11core_ssim |\
+       tee tb_pdp11core_ssim.log | egrep "(FAIL|DONE)"
+     ->  1220255.0 ns  61003: DONE 
+     -> real    1m9.738s   user    1m9.588s   sys     0m0.096s
 
 3. System tests benches ---------------------------------------------------
 
    The system tests allow to verify to verify the full 11/70 SoC design.
    In this case vhdl test bench code contains
      - (simple) models of the memories used on the FPGA boards
-     - drivers for the rri connection (currently just serialport)
-     - code to interface the rri data stream to a UNIX 'named pipe',
+     - drivers for the rlink connection (currently just serialport)
+     - code to interface the rlink data stream to a UNIX 'named pipe',
        implemented with a C routine which is called via VHPI from VHDL.
    This way the whole ghdl simulation can be controlled via a di-directional
    byte stream. 
 
-   The rri backend process, currently a perl script named pi_rri, can connect
+   The rlink backend process, currently a perl script named pi_rri, can connect
    either via a named pipe to a ghdl simulation, or via a serial port to a 
    FPGA board. This way the same tests can be executed in simulation and
    on real hardware.
@@ -134,7 +143,7 @@ Guide to running w11a test benches
    The stimulus file used in the w11a core test can be executed in the
    full system context (both s3board and nexys2 versions) with the 
    following commands. Note that the cycle number printed in the DONE
-   line can now vary slightly because the response time of the rri
+   line can now vary slightly because the response time of the rlink
    backend process and thus scheduling of backend vs. ghdl process
    can affect the result.
 
@@ -144,10 +153,10 @@ Guide to running w11a test benches
      make tb_w11a_s3
      time pi_rri --fifo --timeout=40. --cmax=3 \
         --run="tbw tb_w11a_s3" -- \
-   	 @../../../../w11a/tb/tb_pdp11_core_stim.dat |\
+   	 @../../../../w11a/tb/tb_pdp11core_stim.dat |\
        tee tb_w11a_s3_stim2_dsim.log | egrep "(-[EW]:|FAIL|PEND|DONE)"
-     ->   7766215 ns 388301: DONE 
-     -> real    0m51.300s   user    0m51.711s   sys     0m0.772s
+     -> 7757655.0 ns 387873: DONE
+     -> real    0m49.835s   user    0m50.203s   sys     0m0.696s
 
    - sys_w11a_n2 system test
 
@@ -155,7 +164,7 @@ Guide to running w11a test benches
      make tb_w11a_n2
      time pi_rri --fifo --timeout=40. --cmax=3 \
         --run="tbw tb_w11a_n2" -- \
-   	 @../../../../w11a/tb/tb_pdp11_core_stim.dat |\
+   	 @../../../../w11a/tb/tb_pdp11core_stim.dat |\
        tee tb_w11a_n2_stim2_dsim.log | egrep "(-[EW]:|FAIL|PEND|DONE)"
-     -> 7766855 ns 388333: DONE 
-     -> real    0m51.243s   user    0m51.647s   sys     0m0.776s
+     -> 6673237.2 ns 387035: DONE
+     -> real    0m56.173s   user    0m56.612s   sys     0m0.604s
diff --git a/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vbom b/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vbom
index f42ff308..1fca3bcc 100644
--- a/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vbom
+++ b/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vbom
@@ -4,14 +4,14 @@
 #
 # libs
 ../../../vlib/slvtypes.vhd
-../../../vlib/rri/rrilib.vhd
-../../../vlib/rri/tb/rritblib.vhd
+../../../vlib/rlink/rlinklib.vbom
+../../../vlib/rlink/tb/rlinktblib.vhd
 ../../../vlib/serport/serport.vhd
 ../nexys2lib.vhd
 ../../../vlib/simlib/simlib.vhd
 ../../../vlib/simlib/simbus.vhd
 # components
-../../../vlib/rri/tb/rritb_core_dcm.vbom
+../../../vlib/rlink/tb/tbcore_rlink_dcm.vbom
 tb_nexys2_core.vbom
 ../../../vlib/serport/serport_uart_rxtx.vbom
 nexys2_fusp_aif : nexys2_fusp_dummy.vbom
diff --git a/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vhd b/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vhd
index b63d0ec6..5a65023e 100644
--- a/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vhd
+++ b/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vhd
@@ -1,4 +1,4 @@
--- $Id: tb_nexys2_fusp.vhd 339 2010-11-22 21:20:51Z mueller $
+-- $Id: tb_nexys2_fusp.vhd 351 2010-12-30 21:50:54Z mueller $
 --
 -- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -15,7 +15,7 @@
 -- Module Name:    tb_nexys2_fusp - sim
 -- Description:    Test bench for nexys2 (base+fusp)
 --
--- Dependencies:   vlib/rri/tb/rritb_core_dcm
+-- Dependencies:   vlib/rlink/tb/tbcore_rlink_dcm
 --                 tb_nexys2_core
 --                 vlib/serport/serport_uart_rxtx
 --                 nexys2_fusp_aif [UUT]
@@ -27,6 +27,7 @@
 --
 -- Revision History: 
 -- Date         Rev Version  Comment
+-- 2010-12-29   351   3.0    use rlink/tb now
 -- 2010-11-13   338   1.0.2  now dcm aware: add O_CLKSYS, use rritb_core_dcm
 -- 2010-11-06   336   1.0.1  rename input pin CLK -> I_CLK50
 -- 2010-05-28   295   1.0    Initial version (derived from tb_s3board_fusp)
@@ -39,8 +40,8 @@ use ieee.std_logic_textio.all;
 use std.textio.all;
 
 use work.slvtypes.all;
-use work.rrilib.all;
-use work.rritblib.all;
+use work.rlinklib.all;
+use work.rlinktblib.all;
 use work.serport.all;
 use work.nexys2lib.all;
 use work.simlib.all;
@@ -108,7 +109,7 @@ architecture sim of tb_nexys2_fusp is
 
 begin
   
-  TBCORE : rritb_core_dcm
+  TBCORE : tbcore_rlink_dcm
     generic map (
       CLKOSC_PERIOD => clockosc_period,
       CLKOSC_OFFSET => clockosc_offset,
diff --git a/rtl/bplib/s3board/s3_humanio_rri.vbom b/rtl/bplib/s3board/s3_humanio_rbus.vbom
similarity index 64%
rename from rtl/bplib/s3board/s3_humanio_rri.vbom
rename to rtl/bplib/s3board/s3_humanio_rbus.vbom
index a6246abe..5cf3d7f7 100644
--- a/rtl/bplib/s3board/s3_humanio_rri.vbom
+++ b/rtl/bplib/s3board/s3_humanio_rbus.vbom
@@ -1,8 +1,8 @@
 # libs
 ../../vlib/slvtypes.vhd
-../../vlib/rri/rrilib.vhd
+../../vlib/rbus/rblib.vhd
 s3boardlib.vbom
 # components
 s3_humanio.vbom
 # design
-s3_humanio_rri.vhd
+s3_humanio_rbus.vhd
diff --git a/rtl/bplib/s3board/s3_humanio_rri.vhd b/rtl/bplib/s3board/s3_humanio_rbus.vhd
similarity index 86%
rename from rtl/bplib/s3board/s3_humanio_rri.vhd
rename to rtl/bplib/s3board/s3_humanio_rbus.vhd
index e38b2a20..af060861 100644
--- a/rtl/bplib/s3board/s3_humanio_rri.vhd
+++ b/rtl/bplib/s3board/s3_humanio_rbus.vhd
@@ -1,4 +1,4 @@
--- $Id: s3_humanio_rri.vhd 314 2010-07-09 17:38:41Z mueller $
+-- $Id: s3_humanio_rbus.vhd 352 2011-01-02 13:01:37Z mueller $
 --
 -- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -12,22 +12,24 @@
 -- for complete details.
 --
 ------------------------------------------------------------------------------
--- Module Name:    s3_humanio_rri - syn
--- Description:    s3_humanio with rri interceptor
+-- Module Name:    s3_humanio_rbus - syn
+-- Description:    s3_humanio with rbus interceptor
 --
 -- Dependencies:   s3board/s3_humanio
 --
 -- Test bench:     -
 --
 -- Target Devices: generic
--- Tool versions:  xst 11.4; ghdl 0.26
+-- Tool versions:  xst 11.4, 12.1; ghdl 0.26-0.29
 --
 -- Synthesized (xst):
 -- Date         Rev  ise         Target      flop lutl lutm slic t peri
+-- 2010-12-29   300 12.1    M53d xc3s1000-4    93  138    0  111 s  6.8 ns 
 -- 2010-06-03   300 11.4    L68  xc3s1000-4    92  137    0  111 s  6.7 ns 
 --
 -- Revision History: 
 -- Date         Rev Version  Comment
+-- 2010-12-29   351   1.1    renamed from s3_humanio_rri; ported to rbv3
 -- 2010-06-18   306   1.0.1  rename rbus data fields to _rbf_
 -- 2010-06-03   300   1.0    Initial version
 ------------------------------------------------------------------------------
@@ -46,7 +48,7 @@
 -- bbbbbb01  7:00   swi       r/w/-    r: return hio SWI status
 --                                     w: will drive SWI when swi_en=1
 --
--- bbbbbb10         leddp     r/w/-    interface to LED and DSP_DP
+-- bbbbbb10         leddp     r/w/-  Interface to LED and DSP_DP
 --          11:09     dsp_dp  r/w/-    r: returns DSP_DP status
 --                                     w: will drive display dp's when dp_en=1
 --           7:00     led     r/w/-    r: returns LED status
@@ -61,12 +63,12 @@ use ieee.std_logic_1164.all;
 use ieee.std_logic_arith.all;
 
 use work.slvtypes.all;
-use work.rrilib.all;
+use work.rblib.all;
 use work.s3boardlib.all;
 
 -- ----------------------------------------------------------------------------
 
-entity s3_humanio_rri is                -- human i/o handling with rri intercept
+entity s3_humanio_rbus is               -- human i/o handling /w rbus intercept
   generic (
     DEBOUNCE : boolean := true;         -- instantiate debouncer for SWI,BTN
     RB_ADDR : slv8 := conv_std_logic_vector(2#10000000#,8));
@@ -87,16 +89,17 @@ entity s3_humanio_rri is                -- human i/o handling with rri intercept
     O_ANO_N : out slv4;                 -- pad-o: 7 seg disp: anodes   (act.low)
     O_SEG_N : out slv8                  -- pad-o: 7 seg disp: segments (act.low)
   );
-end s3_humanio_rri;
+end s3_humanio_rbus;
 
-architecture syn of s3_humanio_rri is
+architecture syn of s3_humanio_rbus is
   
   type regs_type is record
-    swi : slv8;                         -- rri swi
-    btn : slv4;                         -- rri btn
-    led : slv8;                         -- rri led
-    dsp_dat : slv16;                    -- rri dsp_dat
-    dsp_dp  : slv4;                     -- rri dsp_dp
+    rbsel : slbit;                      -- rbus select
+    swi : slv8;                         -- rbus swi
+    btn : slv4;                         -- rbus btn
+    led : slv8;                         -- rbus led
+    dsp_dat : slv16;                    -- rbus dsp_dat
+    dsp_dp  : slv4;                     -- rbus dsp_dp
     swi_en : slbit;                     -- enable: swi from rri
     led_en : slbit;                     -- enable: led from rri
     dat_en : slbit;                     -- enable: dsp_dat from rri
@@ -104,6 +107,7 @@ architecture syn of s3_humanio_rri is
   end record regs_type;
   
   constant regs_init : regs_type := (
+    '0',                                -- rbsel
     (others=>'0'),                      -- swi
     (others=>'0'),                      -- btn
     (others=>'0'),                      -- led
@@ -174,29 +178,34 @@ begin
     variable r : regs_type := regs_init;
     variable n : regs_type := regs_init;
 
-    variable irb_sel  : slbit := '0';
     variable irb_ack  : slbit := '0';
     variable irb_busy : slbit := '0';
     variable irb_err  : slbit := '0';
     variable irb_dout : slv16 := (others=>'0');
+    variable irbena   : slbit := '0';
     
   begin
 
     r := R_REGS;
     n := R_REGS;
 
-    irb_sel  := '0';
     irb_ack  := '0';
     irb_busy := '0';
     irb_err  := '0';
     irb_dout := (others=>'0');
 
-    if RB_MREQ.req='1' and RB_MREQ.addr(7 downto 2)=RB_ADDR(7 downto 2)  then
-      irb_sel := '1';
-      irb_ack := '1';
+    irbena  := RB_MREQ.re or RB_MREQ.we;
+
+    -- rbus address decoder
+    n.rbsel := '0';
+    if RB_MREQ.aval='1' and RB_MREQ.addr(7 downto 2)=RB_ADDR(7 downto 2) then
+      n.rbsel := '1';
     end if;
 
-    if irb_sel = '1' then
+    -- rbus transactions
+    if r.rbsel = '1' then
+      irb_ack := irbena;                  -- ack all accesses
+
       case RB_MREQ.addr(1 downto 0) is
 
         when rbaddr_cntl =>
diff --git a/rtl/bplib/s3board/s3boardlib.vbom b/rtl/bplib/s3board/s3boardlib.vbom
index 0a29ebd3..bad5fc0d 100644
--- a/rtl/bplib/s3board/s3boardlib.vbom
+++ b/rtl/bplib/s3board/s3boardlib.vbom
@@ -1,4 +1,4 @@
 # libs
 ../../vlib/slvtypes.vhd
-../../vlib/rri/rrilib.vhd
+../../vlib/rbus/rblib.vhd
 s3boardlib.vhd
diff --git a/rtl/bplib/s3board/s3boardlib.vhd b/rtl/bplib/s3board/s3boardlib.vhd
index 0509ffa7..78c89521 100644
--- a/rtl/bplib/s3board/s3boardlib.vhd
+++ b/rtl/bplib/s3board/s3boardlib.vhd
@@ -1,4 +1,4 @@
--- $Id: s3boardlib.vhd 336 2010-11-06 18:28:27Z mueller $
+-- $Id: s3boardlib.vhd 351 2010-12-30 21:50:54Z mueller $
 --
 -- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -16,9 +16,10 @@
 -- Description:    S3BOARD components
 -- 
 -- Dependencies:   -
--- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
+-- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
 -- Revision History: 
 -- Date         Rev Version  Comment
+-- 2010-12-30   351   1.3.2  use rblib; rename human s3_humanio_rri -> _rbus
 -- 2010-11-06   336   1.3.1  rename input pin CLK -> I_CLK50
 -- 2010-06-03   300   1.3    add s3_humanio_rri (now needs rrilib)
 -- 2010-05-21   292   1.2.2  rename _PM1_ -> _FUSP_
@@ -40,7 +41,7 @@ use ieee.std_logic_1164.all;
 use ieee.std_logic_arith.all;
 
 use work.slvtypes.all;
-use work.rrilib.all;
+use work.rblib.all;
 
 package s3boardlib is
 
@@ -118,7 +119,7 @@ component s3_humanio is                 -- human i/o handling: swi,btn,led,dsp
   );
 end component;
 
-component s3_humanio_rri is             -- human i/o handling with rri intercept
+component s3_humanio_rbus is            -- human i/o handling /w rbus intercept
   generic (
     DEBOUNCE : boolean := true;         -- instantiate debouncer for SWI,BTN
     RB_ADDR : slv8 := conv_std_logic_vector(2#10000000#,8));
diff --git a/rtl/bplib/s3board/tb/tb_s3board_fusp.vbom b/rtl/bplib/s3board/tb/tb_s3board_fusp.vbom
index 4234c89d..23161a0f 100644
--- a/rtl/bplib/s3board/tb/tb_s3board_fusp.vbom
+++ b/rtl/bplib/s3board/tb/tb_s3board_fusp.vbom
@@ -4,14 +4,14 @@
 #
 # libs
 ../../../vlib/slvtypes.vhd
-../../../vlib/rri/rrilib.vhd
-../../../vlib/rri/tb/rritblib.vhd
+../../../vlib/rlink/rlinklib.vbom
+../../../vlib/rlink/tb/rlinktblib.vhd
 ../../../vlib/serport/serport.vhd
 ../s3boardlib.vbom
 ../../../vlib/simlib/simlib.vhd
 ../../../vlib/simlib/simbus.vhd
 # components
-../../../vlib/rri/tb/rritb_core.vbom
+../../../vlib/rlink/tb/tbcore_rlink.vbom
 tb_s3board_core.vbom
 ../../../vlib/serport/serport_uart_rxtx.vbom
 s3board_fusp_aif : s3board_fusp_dummy.vbom
diff --git a/rtl/bplib/s3board/tb/tb_s3board_fusp.vhd b/rtl/bplib/s3board/tb/tb_s3board_fusp.vhd
index 5e1a7932..1cb907ab 100644
--- a/rtl/bplib/s3board/tb/tb_s3board_fusp.vhd
+++ b/rtl/bplib/s3board/tb/tb_s3board_fusp.vhd
@@ -1,4 +1,4 @@
--- $Id: tb_s3board_fusp.vhd 336 2010-11-06 18:28:27Z mueller $
+-- $Id: tb_s3board_fusp.vhd 351 2010-12-30 21:50:54Z mueller $
 --
 -- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -15,7 +15,7 @@
 -- Module Name:    tb_s3board_fusp - sim
 -- Description:    Test bench for s3board (base+fusp)
 --
--- Dependencies:   vlib/rri/tb/rritb_core
+-- Dependencies:   vlib/rlink/tb/tbcore_rlink_dcm
 --                 tb_s3board_core
 --                 vlib/serport/serport_uart_rxtx
 --                 s3board_fusp_aif [UUT]
@@ -23,9 +23,10 @@
 -- To test:        generic, any s3board_fusp_aif target
 --
 -- Target Devices: generic
--- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
+-- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
 -- Revision History: 
 -- Date         Rev Version  Comment
+-- 2010-12-30   351   3.0    use rlink/tb now
 -- 2010-11-06   336   1.0.4  rename input pin CLK -> I_CLK50
 -- 2010-05-21   292   1.0.3  rename _PM1_ -> _FUSP_
 -- 2010-05-16   291   1.0.2  rename tb_s3board_usp->tb_s3board_fusp
@@ -40,8 +41,8 @@ use ieee.std_logic_textio.all;
 use std.textio.all;
 
 use work.slvtypes.all;
-use work.rrilib.all;
-use work.rritblib.all;
+use work.rlinklib.all;
+use work.rlinktblib.all;
 use work.serport.all;
 use work.s3boardlib.all;
 use work.simlib.all;
@@ -103,7 +104,7 @@ architecture sim of tb_s3board_fusp is
 
 begin
   
-  TBCORE : rritb_core
+  TBCORE : tbcore_rlink
     generic map (
       CLK_PERIOD => clock_period,
       CLK_OFFSET => clock_offset,
diff --git a/rtl/ibus/ibd_iist.vhd b/rtl/ibus/ibd_iist.vhd
index 18f58bdc..0454570f 100644
--- a/rtl/ibus/ibd_iist.vhd
+++ b/rtl/ibus/ibd_iist.vhd
@@ -1,4 +1,4 @@
--- $Id: ibd_iist.vhd 335 2010-10-24 22:24:23Z mueller $
+-- $Id: ibd_iist.vhd 350 2010-12-28 16:40:11Z mueller $
 --
 -- Copyright 2009-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -22,10 +22,10 @@
 --
 -- Synthesized (xst):
 -- Date         Rev  ise         Target      flop lutl lutm slic t peri
--- 2010-10-17   333  12.1    M53 xc3s1000-4   112  510    0  291 s 15.8
--- 2010-10-17   314  12.1    M53 xc3s1000-4   111  504    0  290 s 15.6
--- 2009-06-01   223  10.1.03 K39 xc3s1000-4   111  439    0  256 s  9.8
--- 2009-06-01   221  10.1.03 K39 xc3s1000-4   111  449    0  258 s 13.3
+-- 2010-10-17   333 12.1    M53d xc3s1000-4   112  510    0  291 s 15.8
+-- 2010-10-17   314 12.1    M53d xc3s1000-4   111  504    0  290 s 15.6
+-- 2009-06-01   223 10.1.03 K39  xc3s1000-4   111  439    0  256 s  9.8
+-- 2009-06-01   221 10.1.03 K39  xc3s1000-4   111  449    0  258 s 13.3
 --
 -- Revision History: 
 -- Date         Rev Version  Comment
diff --git a/rtl/ibus/ibd_kw11l.vhd b/rtl/ibus/ibd_kw11l.vhd
index b9f58d3c..ffbaae64 100644
--- a/rtl/ibus/ibd_kw11l.vhd
+++ b/rtl/ibus/ibd_kw11l.vhd
@@ -1,4 +1,4 @@
--- $Id: ibd_kw11l.vhd 335 2010-10-24 22:24:23Z mueller $
+-- $Id: ibd_kw11l.vhd 350 2010-12-28 16:40:11Z mueller $
 --
 -- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -22,8 +22,8 @@
 --
 -- Synthesized (xst):
 -- Date         Rev  ise         Target      flop lutl lutm slic t peri
--- 2010-10-17   333  12.1    M53 xc3s1000-4     9   23    0   14 s  5.3
--- 2009-07-11   232  10.1.03 K39 xc3s1000-4     8   25    0   15 s  5.3
+-- 2010-10-17   333 12.1    M53d xc3s1000-4     9   23    0   14 s  5.3
+-- 2009-07-11   232 10.1.03 K39  xc3s1000-4     8   25    0   15 s  5.3
 --
 -- Revision History: 
 -- Date         Rev Version  Comment
diff --git a/rtl/ibus/ibdr_dl11.vhd b/rtl/ibus/ibdr_dl11.vhd
index 0a7b06c6..bb4a07ee 100644
--- a/rtl/ibus/ibdr_dl11.vhd
+++ b/rtl/ibus/ibdr_dl11.vhd
@@ -1,4 +1,4 @@
--- $Id: ibdr_dl11.vhd 335 2010-10-24 22:24:23Z mueller $
+-- $Id: ibdr_dl11.vhd 350 2010-12-28 16:40:11Z mueller $
 --
 -- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -22,9 +22,9 @@
 --
 -- Synthesized (xst):
 -- Date         Rev  ise         Target      flop lutl lutm slic t peri
--- 2010-10-17   333  12.1    M53 xc3s1000-4    39  126    0   72 s  7.6
--- 2009-07-12   233  10.1.03 K39 xc3s1000-4    38  119    0   69 s  6.3
--- 2009-07-11   232  10.1.03 K39 xc3s1000-4    23   61    0   40 s  5.5
+-- 2010-10-17   333 12.1    M53d xc3s1000-4    39  126    0   72 s  7.6
+-- 2009-07-12   233 10.1.03 K39  xc3s1000-4    38  119    0   69 s  6.3
+-- 2009-07-11   232 10.1.03 K39  xc3s1000-4    23   61    0   40 s  5.5
 --
 -- Revision History: 
 -- Date         Rev Version  Comment
diff --git a/rtl/ibus/ibdr_lp11.vhd b/rtl/ibus/ibdr_lp11.vhd
index 995d150c..7aadfbd8 100644
--- a/rtl/ibus/ibdr_lp11.vhd
+++ b/rtl/ibus/ibdr_lp11.vhd
@@ -1,4 +1,4 @@
--- $Id: ibdr_lp11.vhd 335 2010-10-24 22:24:23Z mueller $
+-- $Id: ibdr_lp11.vhd 350 2010-12-28 16:40:11Z mueller $
 --
 -- Copyright 2009-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -22,8 +22,8 @@
 --
 -- Synthesized (xst):
 -- Date         Rev  ise         Target      flop lutl lutm slic t peri
--- 2010-10-17   333  12.1    M53 xc3s1000-4    12   35    0   24 s  5.6
--- 2009-07-11   232  10.1.03 K39 xc3s1000-4    11   30    0   19 s  5.8
+-- 2010-10-17   333 12.1    M53d xc3s1000-4    12   35    0   24 s  5.6
+-- 2009-07-11   232 10.1.03 K39  xc3s1000-4    11   30    0   19 s  5.8
 --
 -- Revision History: 
 -- Date         Rev Version  Comment
diff --git a/rtl/ibus/ibdr_maxisys.vhd b/rtl/ibus/ibdr_maxisys.vhd
index 239b999e..846d3c4f 100644
--- a/rtl/ibus/ibdr_maxisys.vhd
+++ b/rtl/ibus/ibdr_maxisys.vhd
@@ -1,4 +1,4 @@
--- $Id: ibdr_maxisys.vhd 335 2010-10-24 22:24:23Z mueller $
+-- $Id: ibdr_maxisys.vhd 350 2010-12-28 16:40:11Z mueller $
 --
 -- Copyright 2009-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -31,8 +31,8 @@
 --
 -- Synthesized (xst):
 -- Date         Rev  ise         Target      flop lutl lutm slic t peri
--- 2010-10-17   333  12.1    M53 xc3s1000-4   312 1058   16  617 s 10.3
--- 2010-10-17   314  12.1    M53 xc3s1000-4   300 1094   16  626 s 10.4
+-- 2010-10-17   333 12.1    M53d xc3s1000-4   312 1058   16  617 s 10.3
+-- 2010-10-17   314 12.1    M53d xc3s1000-4   300 1094   16  626 s 10.4
 --
 -- Revision History: 
 -- Date         Rev Version  Comment
diff --git a/rtl/ibus/ibdr_minisys.vhd b/rtl/ibus/ibdr_minisys.vhd
index 4b32f337..43169ccb 100644
--- a/rtl/ibus/ibdr_minisys.vhd
+++ b/rtl/ibus/ibdr_minisys.vhd
@@ -1,4 +1,4 @@
--- $Id: ibdr_minisys.vhd 335 2010-10-24 22:24:23Z mueller $
+-- $Id: ibdr_minisys.vhd 350 2010-12-28 16:40:11Z mueller $
 --
 -- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -27,8 +27,8 @@
 --
 -- Synthesized (xst):
 -- Date         Rev  ise         Target      flop lutl lutm slic t peri
--- 2010-10-17   333  12.1    M53 xc3s1000-4   128  469   16  265 s  7.8
--- 2010-10-17   314  12.1    M53 xc3s1000-4   122  472   16  269 s  7.6
+-- 2010-10-17   333 12.1    M53d xc3s1000-4   128  469   16  265 s  7.8
+-- 2010-10-17   314 12.1    M53d xc3s1000-4   122  472   16  269 s  7.6
 --
 -- Revision History: 
 -- Date         Rev Version  Comment
diff --git a/rtl/ibus/ibdr_pc11.vhd b/rtl/ibus/ibdr_pc11.vhd
index fbafbad9..0d6ad75a 100644
--- a/rtl/ibus/ibdr_pc11.vhd
+++ b/rtl/ibus/ibdr_pc11.vhd
@@ -1,4 +1,4 @@
--- $Id: ibdr_pc11.vhd 335 2010-10-24 22:24:23Z mueller $
+-- $Id: ibdr_pc11.vhd 350 2010-12-28 16:40:11Z mueller $
 --
 -- Copyright 2009-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -22,8 +22,8 @@
 --
 -- Synthesized (xst):
 -- Date         Rev  ise         Target      flop lutl lutm slic t peri
--- 2010-10-17   333  12.1    M53 xc3s1000-4    26   97    0   57 s  6.0
--- 2009-06-28   230  10.1.03 K39 xc3s1000-4    25   92    0   54 s  4.9
+-- 2010-10-17   333 12.1    M53d xc3s1000-4    26   97    0   57 s  6.0
+-- 2009-06-28   230 10.1.03 K39  xc3s1000-4    25   92    0   54 s  4.9
 --
 -- Revision History: 
 -- Date         Rev Version  Comment
diff --git a/rtl/ibus/ibdr_rk11.vhd b/rtl/ibus/ibdr_rk11.vhd
index 043eb974..4b147a4e 100644
--- a/rtl/ibus/ibdr_rk11.vhd
+++ b/rtl/ibus/ibdr_rk11.vhd
@@ -1,4 +1,4 @@
--- $Id: ibdr_rk11.vhd 335 2010-10-24 22:24:23Z mueller $
+-- $Id: ibdr_rk11.vhd 350 2010-12-28 16:40:11Z mueller $
 --
 -- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -22,9 +22,9 @@
 --
 -- Synthesized (xst):
 -- Date         Rev  ise         Target      flop lutl lutm slic t peri
--- 2010-10-17   333  12.1    M53 xc3s1000-4    46  248   16  137 s  7.2
--- 2009-06-01   221  10.1.03 K39 xc3s1000-4    46  249   16  148 s  7.1
--- 2008-01-06   111   8.2.03 I34 xc3s1000-4    36  189   16  111 s  6.0
+-- 2010-10-17   333 12.1    M53d xc3s1000-4    46  248   16  137 s  7.2
+-- 2009-06-01   221 10.1.03 K39  xc3s1000-4    46  249   16  148 s  7.1
+-- 2008-01-06   111  8.2.03 I34  xc3s1000-4    36  189   16  111 s  6.0
 --
 -- Revision History: 
 -- Date         Rev Version  Comment
diff --git a/rtl/ibus/ibdr_sdreg.vhd b/rtl/ibus/ibdr_sdreg.vhd
index f6f10587..92d8eb7c 100644
--- a/rtl/ibus/ibdr_sdreg.vhd
+++ b/rtl/ibus/ibdr_sdreg.vhd
@@ -1,4 +1,4 @@
--- $Id: ibdr_sdreg.vhd 335 2010-10-24 22:24:23Z mueller $
+-- $Id: ibdr_sdreg.vhd 350 2010-12-28 16:40:11Z mueller $
 --
 -- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -22,8 +22,8 @@
 --
 -- Synthesized (xst):
 -- Date         Rev  ise         Target      flop lutl lutm slic t peri
--- 2010-10-17   333  12.1    M53 xc3s1000-4    34   40    0   30 s  4.0
--- 2009-07-11   232  10.1.03 K39 xc3s1000-4    32   39    0   29 s  2.5
+-- 2010-10-17   333 12.1    M53d xc3s1000-4    34   40    0   30 s  4.0
+-- 2009-07-11   232 10.1.03 K39  xc3s1000-4    32   39    0   29 s  2.5
 --
 -- Revision History: 
 -- Date         Rev Version  Comment
diff --git a/rtl/ibus/iblib.vhd b/rtl/ibus/iblib.vhd
index 79245d14..5aedde2d 100644
--- a/rtl/ibus/iblib.vhd
+++ b/rtl/ibus/iblib.vhd
@@ -1,4 +1,4 @@
--- $Id: iblib.vhd 335 2010-10-24 22:24:23Z mueller $
+-- $Id: iblib.vhd 346 2010-12-22 22:59:26Z mueller $
 --
 -- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -113,15 +113,6 @@ component ib_sres_or_gen is             -- ibus result or, generic
   );
 end component;
 
-component ib_sres_or_mon is             -- ibus result or monitor
-  port (
-    IB_SRES_1 :  in ib_sres_type;                 -- ib_sres input 1
-    IB_SRES_2 :  in ib_sres_type := ib_sres_init; -- ib_sres input 2
-    IB_SRES_3 :  in ib_sres_type := ib_sres_init; -- ib_sres input 3
-    IB_SRES_4 :  in ib_sres_type := ib_sres_init  -- ib_sres input 4
-  );
-end component;
-
 type intmap_type is record              -- interrupt map entry type
   vec : integer;                        -- vector address
   pri : integer;                        -- priority
@@ -142,5 +133,18 @@ component ib_intmap is                  -- external interrupt mapper
     EI_VECT : out slv9_2                -- interrupt vector
   );
 end component;
+
+--
+-- components for use in test benches (not synthesizable)
+--
   
+component ib_sres_or_mon is             -- ibus result or monitor
+  port (
+    IB_SRES_1 :  in ib_sres_type;                 -- ib_sres input 1
+    IB_SRES_2 :  in ib_sres_type := ib_sres_init; -- ib_sres input 2
+    IB_SRES_3 :  in ib_sres_type := ib_sres_init; -- ib_sres input 3
+    IB_SRES_4 :  in ib_sres_type := ib_sres_init  -- ib_sres input 4
+  );
+end component;
+
 end package iblib;
diff --git a/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vbom b/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vbom
index 026b27d3..64cc6327 100644
--- a/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vbom
+++ b/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vbom
@@ -2,7 +2,8 @@
 ../../../vlib/slvtypes.vhd
 ../../../vlib/xlib/xlib.vhd
 ../../../vlib/genlib/genlib.vhd
-../../../vlib/rri/rrilib.vhd
+../../../vlib/rbus/rblib.vhd
+../../../vlib/rlink/rlinklib.vbom
 ../../../bplib/s3board/s3boardlib.vbom
 ../../../bplib/nexys2/nexys2lib.vhd
 ../../../ibus/iblib.vhd
@@ -14,10 +15,10 @@ sys_conf = sys_conf.vhd
 [ghdl]../../../vlib/xlib/dcm_sp_sfs_gsim.vbom
 ../../../vlib/genlib/clkdivce.vbom
 ../../../bplib/s3board/s3_rs232_iob_int_ext.vbom
-../../../bplib/s3board/s3_humanio_rri.vbom
-../../../vlib/rri/rri_core_serport.vbom
-../../../vlib/rri/rb_sres_or_3.vbom
-../../../w11a/pdp11_core_rri.vbom
+../../../bplib/s3board/s3_humanio_rbus.vbom
+../../../vlib/rlink/rlink_base_serport.vbom
+../../../vlib/rbus/rb_sres_or_3.vbom
+../../../w11a/pdp11_core_rbus.vbom
 ../../../w11a/pdp11_core.vbom
 ../../../w11a/pdp11_bram.vbom
 ../../../bplib/nexys2/n2_cram_dummy.vbom
diff --git a/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd b/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd
index e6150d5a..90d0449d 100644
--- a/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd
+++ b/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd
@@ -1,4 +1,4 @@
--- $Id: sys_w11a_n2.vhd 341 2010-11-27 23:05:43Z mueller $
+-- $Id: sys_w11a_n2.vhd 351 2010-12-30 21:50:54Z mueller $
 --
 -- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -18,10 +18,10 @@
 -- Dependencies:   vlib/xlib/dcm_sp_sfs
 --                 vlib/genlib/clkdivce
 --                 bplib/s3board/s3_rs232_iob_int_ext
---                 bplib/s3board/s3_humanio_rri
---                 vlib/rri/rri_core_serport
+--                 bplib/s3board/s3_humanio_rbus
+--                 vlib/rlink/rlink_base_serport
 --                 vlib/rri/rb_sres_or_3
---                 w11a/pdp11_core_rri
+--                 w11a/pdp11_core_rbus
 --                 w11a/pdp11_core
 --                 w11a/pdp11_bram
 --                 vlib/nexys2/n2_cram_dummy
@@ -40,6 +40,7 @@
 --
 -- Synthesized (xst):
 -- Date         Rev  ise         Target      flop lutl lutm slic t peri
+-- 2010-12-30   351 12.1    M53d xc3s1200e-4 1389 4368  242 2674 ok: LP+PC+DL+II
 -- 2010-11-06   336 12.1    M53d xc3s1200e-4 1357 4304* 242 2618 ok: LP+PC+DL+II
 -- 2010-10-24   335 12.1    M53d xc3s1200e-4 1357 4546  242 2618 ok: LP+PC+DL+II
 -- 2010-10-17   333 12.1    M53d xc3s1200e-4 1350 4541  242 2617 ok: LP+PC+DL+II
@@ -61,6 +62,7 @@
 --
 -- Revision History: 
 -- Date         Rev Version  Comment
+-- 2010-12-30   351   1.2    ported to rbv3
 -- 2010-11-27   341   1.1.8  add DCM; new sys_conf consts for mem and clkdiv
 -- 2010-11-13   338   1.1.7  add O_CLKSYS (for DCM derived system clock)
 -- 2010-11-06   336   1.1.6  rename input pin CLK -> I_CLK50
@@ -80,7 +82,7 @@
 ------------------------------------------------------------------------------
 --
 -- w11a test design for nexys2
---    w11a + rri + serport
+--    w11a + rlink + serport
 --
 -- Usage of Nexys 2 Switches, Buttons, LEDs:
 --
@@ -96,7 +98,7 @@
 --              if cpugo=0 shows cpurust
 --                (3:0) cpurust code
 --                  (4) '1'
---         (5)  cmdbusy (all rri access, mostly rdma)
+--         (5)  cmdbusy (all rlink access, mostly rdma)
 --         (6)  MEM_ACT_R
 --         (7)  MEM_ACT_W
 --
@@ -112,7 +114,8 @@ use ieee.std_logic_arith.all;
 use work.slvtypes.all;
 use work.xlib.all;
 use work.genlib.all;
-use work.rrilib.all;
+use work.rblib.all;
+use work.rlinklib.all;
 use work.s3boardlib.all;
 use work.nexys2lib.all;
 use work.iblib.all;
@@ -276,7 +279,7 @@ begin
       O_RTS1_N => O_FUSP_RTS_N
     );
 
-  HIO : s3_humanio_rri
+  HIO : s3_humanio_rbus
     generic map (
       DEBOUNCE => sys_conf_hio_debounce,
       RB_ADDR  => rbaddr_hio)
@@ -298,10 +301,12 @@ begin
       O_SEG_N => O_SEG_N
     );
 
-  RRI : rri_core_serport
+  RLINK : rlink_base_serport
     generic map (
       ATOWIDTH =>  6,                   -- 64 cycles access timeout
       ITOWIDTH =>  6,                   -- 64 periods max idle timeout
+      IFAWIDTH =>  5,                   -- 32 word input fifo
+      OFAWIDTH =>  0,                   -- no output fifo
       CDWIDTH  => 13,
       CDINIT   => sys_conf_ser2rri_cdinit)
     port map (
@@ -317,7 +322,9 @@ begin
       RB_MREQ  => RB_MREQ,
       RB_SRES  => RB_SRES,
       RB_LAM   => RB_LAM,
-      RB_STAT  => RB_STAT
+      RB_STAT  => RB_STAT,
+      RL_MONI  => open,
+      RL_SER_MONI => open
     );
 
   RB_SRES_OR : rb_sres_or_3
@@ -328,7 +335,7 @@ begin
       RB_SRES_OR => RB_SRES
     );
   
-  RB2CP : pdp11_core_rri
+  RB2CP : pdp11_core_rbus
     generic map (
       RB_ADDR_CORE => rbaddr_core0,
       RB_ADDR_IBUS => rbaddr_ibus)
diff --git a/rtl/sys_gen/w11a/nexys2/tb/.cvsignore b/rtl/sys_gen/w11a/nexys2/tb/.cvsignore
index 508fb898..4f22b0cd 100644
--- a/rtl/sys_gen/w11a/nexys2/tb/.cvsignore
+++ b/rtl/sys_gen/w11a/nexys2/tb/.cvsignore
@@ -1,8 +1,8 @@
 tb_w11a_n2
 tb_w11a_n2_[sft]sim
-tb_rriext_fifo_rx
-tb_rriext_fifo_tx
-tb_rriext_conf
+rlink_cext_fifo_rx
+rlink_cext_fifo_tx
+rlink_cext_conf
 tmu_ofile
 sys_w11a_n2.ucf
 *.dep_ucf_cpp
diff --git a/rtl/sys_gen/w11a/nexys2/tb/tb_w11a_n2_ssim.vbom b/rtl/sys_gen/w11a/nexys2/tb/tb_w11a_n2_ssim.vbom
new file mode 100644
index 00000000..42eb6b32
--- /dev/null
+++ b/rtl/sys_gen/w11a/nexys2/tb/tb_w11a_n2_ssim.vbom
@@ -0,0 +1,6 @@
+# configure for _*sim case
+# Note: this tb uses sys_w11a_n2.vbom in local directory
+#       (not in .. as usual) to allow a tb specific configure !!!
+nexys2_fusp_aif = sys_w11a_n2_ssim.vhd
+tb_w11a_n2.vbom
+@top:tb_w11a_n2
diff --git a/rtl/sys_gen/w11a/nexys2/tb/tbw.dat b/rtl/sys_gen/w11a/nexys2/tb/tbw.dat
index 28c9996b..debd28c6 100644
--- a/rtl/sys_gen/w11a/nexys2/tb/tbw.dat
+++ b/rtl/sys_gen/w11a/nexys2/tb/tbw.dat
@@ -1,6 +1,6 @@
-# $Id: tbw.dat 295 2010-05-29 16:58:01Z mueller $
+# $Id: tbw.dat 351 2010-12-30 21:50:54Z mueller $
 #
 [tb_w11a_n2]
-tb_rriext_fifo_rx = <fifo>
-tb_rriext_fifo_tx = <fifo>
-tb_rriext_conf = <null>
+rlink_cext_fifo_rx = <fifo>
+rlink_cext_fifo_tx = <fifo>
+rlink_cext_conf = <null>
diff --git a/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vbom b/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vbom
index dac05208..96c7cdb8 100644
--- a/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vbom
+++ b/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vbom
@@ -1,7 +1,8 @@
 # libs
 ../../../vlib/slvtypes.vhd
 ../../../vlib/genlib/genlib.vhd
-../../../vlib/rri/rrilib.vhd
+../../../vlib/rbus/rblib.vhd
+../../../vlib/rlink/rlinklib.vbom
 ../../../bplib/s3board/s3boardlib.vbom
 ../../../ibus/iblib.vhd
 ../../../ibus/ibdlib.vhd
@@ -11,9 +12,9 @@ sys_conf = sys_conf.vhd
 ../../../vlib/genlib/clkdivce.vbom
 ../../../bplib/s3board/s3_rs232_iob_int_ext.vbom
 ../../../bplib/s3board/s3_humanio.vbom
-../../../vlib/rri/rri_core_serport.vbom
-../../../vlib/rri/rb_sres_or_2.vbom
-../../../w11a/pdp11_core_rri.vbom
+../../../vlib/rlink/rlink_base_serport.vbom
+../../../vlib/rbus/rb_sres_or_2.vbom
+../../../w11a/pdp11_core_rbus.vbom
 ../../../w11a/pdp11_core.vbom
 ../../../w11a/pdp11_bram.vbom
 ../../../bplib/s3board/s3_sram_dummy.vbom
diff --git a/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd b/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd
index 60c13610..7cf3711d 100644
--- a/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd
+++ b/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd
@@ -1,4 +1,4 @@
--- $Id: sys_w11a_s3.vhd 336 2010-11-06 18:28:27Z mueller $
+-- $Id: sys_w11a_s3.vhd 351 2010-12-30 21:50:54Z mueller $
 --
 -- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -18,9 +18,9 @@
 -- Dependencies:   vlib/genlib/clkdivce
 --                 bplib/s3board/s3_rs232_iob_int_ext
 --                 bplib/s3board/s3_humanio
---                 vlib/rri/rri_core_serport
---                 vlib/rri/rb_sres_or_2
---                 w11a/pdp11_core_rri
+--                 vlib/rlink/rlink_base_serport
+--                 vlib/rbus/rb_sres_or_2
+--                 w11a/pdp11_core_rbus
 --                 w11a/pdp11_core
 --                 w11a/pdp11_bram
 --                 vlib/s3board/s3_sram_dummy
@@ -39,6 +39,7 @@
 --
 -- Synthesized (xst):
 -- Date         Rev  ise         Target      flop lutl lutm slic t peri
+-- 2010-12-30   351 12.1    M53d xc3s1000-4  1316 4291  242 2609 OK: LP+PC+DL+II
 -- 2010-11-06   336 12.1    M53d xc3s1000-4  1284 4253* 242 2575 OK: LP+PC+DL+II
 -- 2010-10-24   335 12.1    M53d xc3s1000-4  1284 4495  242 2575 OK: LP+PC+DL+II
 -- 2010-05-01   285 11.4    L68  xc3s1000-4  1239 4086  224 2471 OK: LP+PC+DL+II
@@ -70,6 +71,7 @@
 --
 -- Revision History: 
 -- Date         Rev Version  Comment
+-- 2010-12-30   351   1.4    ported to rbv3
 -- 2010-11-06   336   1.3.7  rename input pin CLK -> I_CLK50
 -- 2010-10-23   335   1.3.3  rename RRI_LAM->RB_LAM;
 -- 2010-06-26   309   1.3.2  use constants for rbus addresses (rbaddr_...)
@@ -113,7 +115,7 @@
 ------------------------------------------------------------------------------
 --
 -- w11a test design for s3board
---    w11a + rri + serport
+--    w11a + rlink + serport
 --
 -- Usage of S3BOARD Switches, Buttons, LEDs:
 --    LED(7..0):last RXDATA
@@ -129,7 +131,8 @@ use ieee.std_logic_arith.all;
 
 use work.slvtypes.all;
 use work.genlib.all;
-use work.rrilib.all;
+use work.rblib.all;
+use work.rlinklib.all;
 use work.s3boardlib.all;
 use work.iblib.all;
 use work.ibdlib.all;
@@ -285,10 +288,12 @@ begin
       O_SEG_N => O_SEG_N
     );
 
-  RRI : rri_core_serport
+  RLINK : rlink_base_serport
     generic map (
       ATOWIDTH =>  6,                   -- 64 cycles access timeout
       ITOWIDTH =>  6,                   -- 64 periods max idle timeout
+      IFAWIDTH =>  5,                   -- 32 word input fifo
+      OFAWIDTH =>  0,                   -- no output fifo
       CDWIDTH  => 13,
       CDINIT   => sys_conf_ser2rri_cdinit)
     port map (
@@ -304,7 +309,9 @@ begin
       RB_MREQ  => RB_MREQ,
       RB_SRES  => RB_SRES,
       RB_LAM   => RB_LAM,
-      RB_STAT  => RB_STAT
+      RB_STAT  => RB_STAT,
+      RL_MONI  => open,
+      RL_SER_MONI => open
     );
 
   RB_SRES_OR : rb_sres_or_2
@@ -314,7 +321,7 @@ begin
       RB_SRES_OR => RB_SRES
     );
   
-  RP2CP : pdp11_core_rri
+  RP2CP : pdp11_core_rbus
     generic map (
       RB_ADDR_CORE => rbaddr_core0,
       RB_ADDR_IBUS => rbaddr_ibus)
diff --git a/rtl/sys_gen/w11a/s3board/tb/.cvsignore b/rtl/sys_gen/w11a/s3board/tb/.cvsignore
index bc320f4c..f9e04eed 100644
--- a/rtl/sys_gen/w11a/s3board/tb/.cvsignore
+++ b/rtl/sys_gen/w11a/s3board/tb/.cvsignore
@@ -1,8 +1,8 @@
 tb_w11a_s3
 tb_w11a_s3_[sft]sim
-tb_rriext_fifo_rx
-tb_rriext_fifo_tx
-tb_rriext_conf
+rlink_cext_fifo_rx
+rlink_cext_fifo_tx
+rlink_cext_conf
 tmu_ofile
 sys_w11a_s3.ucf
 *.dep_ucf_cpp
diff --git a/rtl/sys_gen/w11a/s3board/tb/tb_w11a_s3_ssim.vbom b/rtl/sys_gen/w11a/s3board/tb/tb_w11a_s3_ssim.vbom
new file mode 100644
index 00000000..a3d0e90d
--- /dev/null
+++ b/rtl/sys_gen/w11a/s3board/tb/tb_w11a_s3_ssim.vbom
@@ -0,0 +1,6 @@
+# configure for _*sim case
+# Note: this tb uses sys_w11a_s3.vbom in local directory
+#       (not in .. as usual) to allow a tb specific configure !!!
+s3board_fusp_aif = sys_w11a_s3_ssim.vhd
+tb_w11a_s3.vbom
+@top:tb_w11a_s3
diff --git a/rtl/sys_gen/w11a/s3board/tb/tbw.dat b/rtl/sys_gen/w11a/s3board/tb/tbw.dat
index 9c2333c5..b30113d8 100644
--- a/rtl/sys_gen/w11a/s3board/tb/tbw.dat
+++ b/rtl/sys_gen/w11a/s3board/tb/tbw.dat
@@ -1,6 +1,6 @@
-# $Id: tbw.dat 295 2010-05-29 16:58:01Z mueller $
+# $Id: tbw.dat 351 2010-12-30 21:50:54Z mueller $
 #
 [tb_w11a_s3]
-tb_rriext_fifo_rx = <fifo>
-tb_rriext_fifo_tx = <fifo>
-tb_rriext_conf = <null>
+rlink_cext_fifo_rx = <fifo>
+rlink_cext_fifo_tx = <fifo>
+rlink_cext_conf = <null>
diff --git a/rtl/vlib/comlib/byte2cdata.vhd b/rtl/vlib/comlib/byte2cdata.vhd
index c14daab6..2fc334aa 100644
--- a/rtl/vlib/comlib/byte2cdata.vhd
+++ b/rtl/vlib/comlib/byte2cdata.vhd
@@ -1,4 +1,4 @@
--- $Id: byte2cdata.vhd 314 2010-07-09 17:38:41Z mueller $
+-- $Id: byte2cdata.vhd 348 2010-12-26 15:23:44Z mueller $
 --
 -- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -18,7 +18,8 @@
 -- Dependencies:   -
 -- Test bench:     -
 -- Target Devices: generic
--- Tool versions:  xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+-- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
+--
 -- Revision History: 
 -- Date         Rev Version  Comment
 -- 2007-10-12    88   1.0.1  avoid ieee.std_logic_unsigned, use cast to unsigned
@@ -41,7 +42,7 @@ entity byte2cdata is                    -- byte stream -> 9bit comma,data
     DI : in slv8;                       -- input data
     ENA : in slbit;                     -- write enable
     BUSY : out slbit;                   -- write port hold    
-    DO : out slv9;                      -- output data; bit 8 = komma flag
+    DO : out slv9;                      -- output data; bit 8 = comma flag
     VAL : out slbit;                    -- read valid
     HOLD : in slbit                     -- read hold
   );
diff --git a/rtl/vlib/comlib/cdata2byte.vhd b/rtl/vlib/comlib/cdata2byte.vhd
index 5b767497..8ae9fa9b 100644
--- a/rtl/vlib/comlib/cdata2byte.vhd
+++ b/rtl/vlib/comlib/cdata2byte.vhd
@@ -1,4 +1,4 @@
--- $Id: cdata2byte.vhd 314 2010-07-09 17:38:41Z mueller $
+-- $Id: cdata2byte.vhd 348 2010-12-26 15:23:44Z mueller $
 --
 -- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -18,7 +18,8 @@
 -- Dependencies:   -
 -- Test bench:     -
 -- Target Devices: generic
--- Tool versions:  xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+-- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
+--
 -- Revision History: 
 -- Date         Rev Version  Comment
 -- 2007-10-12    88   1.0.1  avoid ieee.std_logic_unsigned, use cast to unsigned
@@ -38,7 +39,7 @@ entity cdata2byte is                    -- 9bit comma,data -> byte stream
   port (
     CLK : in slbit;                     -- clock
     RESET : in slbit;                   -- reset
-    DI : in slv9;                       -- input data; bit 8 = komma flag
+    DI : in slv9;                       -- input data; bit 8 = comma flag
     ENA : in slbit;                     -- write enable
     BUSY : out slbit;                   -- write port hold    
     DO : out slv8;                      -- output data
diff --git a/rtl/vlib/rri/Makefile b/rtl/vlib/rbus/Makefile
similarity index 88%
rename from rtl/vlib/rri/Makefile
rename to rtl/vlib/rbus/Makefile
index d4cefdf7..fed95661 100644
--- a/rtl/vlib/rri/Makefile
+++ b/rtl/vlib/rbus/Makefile
@@ -1,4 +1,4 @@
-# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $
+# $Id: Makefile 343 2010-12-05 21:24:38Z mueller $
 #
 #  Revision History: 
 # Date         Rev Version  Comment
diff --git a/rtl/vlib/rbus/rb_mon.vbom b/rtl/vlib/rbus/rb_mon.vbom
new file mode 100644
index 00000000..871a519f
--- /dev/null
+++ b/rtl/vlib/rbus/rb_mon.vbom
@@ -0,0 +1,7 @@
+# libs
+../slvtypes.vhd
+../simlib/simlib.vhd
+rblib.vhd
+# components
+# design
+rb_mon.vhd
diff --git a/rtl/vlib/rri/tb/rritb_rbmon.vhd b/rtl/vlib/rbus/rb_mon.vhd
similarity index 83%
rename from rtl/vlib/rri/tb/rritb_rbmon.vhd
rename to rtl/vlib/rbus/rb_mon.vhd
index 767e403a..56babf31 100644
--- a/rtl/vlib/rri/tb/rritb_rbmon.vhd
+++ b/rtl/vlib/rbus/rb_mon.vhd
@@ -1,4 +1,4 @@
--- $Id: rritb_rbmon.vhd 314 2010-07-09 17:38:41Z mueller $
+-- $Id: rb_mon.vhd 346 2010-12-22 22:59:26Z mueller $
 --
 -- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -12,14 +12,16 @@
 -- for complete details.
 --
 ------------------------------------------------------------------------------
--- Module Name:    rritb_rbmon - sim
--- Description:    rritb: rri rbus monitor
+-- Module Name:    rb_mon - sim
+-- Description:    rbus monitor (for tb's)
 --
 -- Dependencies:   -
 -- Test bench:     -
--- Tool versions:  xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+-- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
+--
 -- Revision History: 
 -- Date         Rev Version  Comment
+-- 2010-12-22   346   3.0    renamed rritb_rbmon -> rb_mon
 -- 2010-06-05   301   2.1.1  renamed _rpmon -> _rbmon
 -- 2010-06-03   299   2.1    new init encoding (WE=0/1 int/ext)
 -- 2010-05-02   287   2.0.1  rename RP_STAT->RB_STAT,AP_LAM->RB_LAM
@@ -39,9 +41,9 @@ use std.textio.all;
 
 use work.slvtypes.all;
 use work.simlib.all;
-use work.rrilib.all;
+use work.rblib.all;
 
-entity rritb_rbmon is                   -- rritb, rri rbus monitor
+entity rb_mon is                        -- rbus monitor (for tb's)
   generic (
     DBASE : positive :=  2);            -- base for writing data values
   port (
@@ -53,14 +55,14 @@ entity rritb_rbmon is                   -- rritb, rri rbus monitor
     RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me
     RB_STAT : in slv3                   -- rbus: status flags
   );
-end rritb_rbmon;
+end rb_mon;
 
 
-architecture sim of rritb_rbmon is
+architecture sim of rb_mon is
   
 begin
 
-  proc_rbmoni: process
+  proc_moni: process
     variable oline : line;
     variable nhold : integer := 0;
     variable data : slv16 := (others=>'0');
@@ -99,21 +101,22 @@ begin
 
       wait until CLK'event and CLK='1'; -- check at end of clock cycle
 
-      if RB_MREQ.req = '1' then
+      if RB_MREQ.aval='1' and (RB_MREQ.re='1' or RB_MREQ.we='1') then
         if RB_SRES.err = '1' then
           err := '1';
         end if;
         if RB_SRES.busy = '1' then
           nhold := nhold + 1;
         else
-          if RB_MREQ.req = '1' then
-            if RB_MREQ.we = '0' then
-              data := RB_SRES.dout;
-              tag  :=  ": rbre  ";
-            else
-              data := RB_MREQ.din;
-              tag  :=  ": rbwe  ";
-            end if;
+          data := (others=>'0');
+          tag  := ": ????  ";
+          if RB_MREQ.re = '1' then
+            data := RB_SRES.dout;
+            tag  :=  ": rbre  ";
+          end if;
+          if RB_MREQ.we = '1' then
+            data := RB_MREQ.din;
+            tag  :=  ": rbwe  ";
           end if;
 
           write_data(oline, tag, data, nhold, err='1', "  ERR='1'");
@@ -141,6 +144,6 @@ begin
       end if;
                   
     end loop;
-  end process proc_rbmoni;
+  end process proc_moni;
   
 end sim;
diff --git a/rtl/vlib/rbus/rb_mon_sb.vbom b/rtl/vlib/rbus/rb_mon_sb.vbom
new file mode 100644
index 00000000..535bcfba
--- /dev/null
+++ b/rtl/vlib/rbus/rb_mon_sb.vbom
@@ -0,0 +1,9 @@
+# libs
+../slvtypes.vhd
+../simlib/simlib.vhd
+../simlib/simbus.vhd
+rblib.vhd
+# components
+rb_mon.vbom
+# design
+rb_mon_sb.vhd
diff --git a/rtl/vlib/rri/tb/rritb_rbmon_sb.vhd b/rtl/vlib/rbus/rb_mon_sb.vhd
similarity index 86%
rename from rtl/vlib/rri/tb/rritb_rbmon_sb.vhd
rename to rtl/vlib/rbus/rb_mon_sb.vhd
index 718e3d08..3da3ffde 100644
--- a/rtl/vlib/rri/tb/rritb_rbmon_sb.vhd
+++ b/rtl/vlib/rbus/rb_mon_sb.vhd
@@ -1,4 +1,4 @@
--- $Id: rritb_rbmon_sb.vhd 314 2010-07-09 17:38:41Z mueller $
+-- $Id: rb_mon_sb.vhd 346 2010-12-22 22:59:26Z mueller $
 --
 -- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -12,14 +12,16 @@
 -- for complete details.
 --
 ------------------------------------------------------------------------------
--- Module Name:    rritb_rbmon_sb - sim
--- Description:    rritb: rri reg port monitor; simbus wrapper
+-- Module Name:    rb_mon_sb - sim
+-- Description:    simbus wrapper for rbus monitor (for tb's)
 --
 -- Dependencies:   simbus
 -- Test bench:     -
 -- Tool versions:  xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+--
 -- Revision History: 
 -- Date         Rev Version  Comment
+-- 2010-12-22   346   3.0    renamed rritb_rbmon_sb -> rb_mon_sb
 -- 2010-06-05   301   2.0.2  renamed _rpmon -> _rbmon
 -- 2010-05-02   287   2.0.1  rename RP_STAT->RB_STAT,AP_LAM->RB_LAM
 --                           drop RP_IINT signal from interfaces
@@ -36,10 +38,9 @@ use ieee.std_logic_1164.all;
 use work.slvtypes.all;
 use work.simlib.all;
 use work.simbus.all;
-use work.rrilib.all;
-use work.rritblib.all;
+use work.rblib.all;
 
-entity rritb_rbmon_sb is                -- simbus wrap for rri rbus monitor
+entity rb_mon_sb is                     -- simbus wrapper for rbus monitor
   generic (
     DBASE : positive :=  2;             -- base for writing data values
     ENAPIN : integer := sbcntl_sbf_rbmon); -- SB_CNTL signal to use for enable
@@ -50,10 +51,10 @@ entity rritb_rbmon_sb is                -- simbus wrap for rri rbus monitor
     RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me
     RB_STAT : in slv3                   -- rbus: status flags
   );
-end rritb_rbmon_sb;
+end rb_mon_sb;
 
 
-architecture sim of rritb_rbmon_sb is
+architecture sim of rb_mon_sb is
 
   signal ENA : slbit := '0';
   
@@ -64,7 +65,7 @@ begin
 
   ENA <= to_x01(SB_CNTL(ENAPIN));
   
-  RBMON : rritb_rbmon
+  RBMON : rb_mon
     generic map (
       DBASE => DBASE)
     port map (
diff --git a/rtl/vlib/rbus/rb_sres_or_2.vbom b/rtl/vlib/rbus/rb_sres_or_2.vbom
new file mode 100644
index 00000000..31f92bd1
--- /dev/null
+++ b/rtl/vlib/rbus/rb_sres_or_2.vbom
@@ -0,0 +1,7 @@
+# libs
+../slvtypes.vhd
+rblib.vhd
+# components
+[ghdl,isim]rb_sres_or_mon.vbom
+# design
+rb_sres_or_2.vhd
diff --git a/rtl/vlib/rri/rb_sres_or_2.vhd b/rtl/vlib/rbus/rb_sres_or_2.vhd
similarity index 83%
rename from rtl/vlib/rri/rb_sres_or_2.vhd
rename to rtl/vlib/rbus/rb_sres_or_2.vhd
index a51376f2..3bd7e651 100644
--- a/rtl/vlib/rri/rb_sres_or_2.vhd
+++ b/rtl/vlib/rbus/rb_sres_or_2.vhd
@@ -1,4 +1,4 @@
--- $Id: rb_sres_or_2.vhd 314 2010-07-09 17:38:41Z mueller $
+-- $Id: rb_sres_or_2.vhd 343 2010-12-05 21:24:38Z mueller $
 --
 -- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -13,14 +13,16 @@
 --
 ------------------------------------------------------------------------------
 -- Module Name:    rb_sres_or_2 - syn
--- Description:    rribus result or, 2 input
+-- Description:    rbus result or, 2 input
 --
--- Dependencies:   rritb_sres_or_mon    [sim only]
+-- Dependencies:   rb_sres_or_mon    [sim only]
 -- Test bench:     -
 -- Target Devices: generic
--- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.29
+-- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
+--
 -- Revision History: 
 -- Date         Rev Version  Comment
+-- 2010-12-04   343   1.1.1  use now rb_sres_or_mon
 -- 2010-06-26   309   1.1    add rritb_sres_or_mon
 -- 2008-08-22   161   1.0.1  renamed rri_rbres_ -> rb_sres_
 -- 2008-01-20   113   1.0    Initial version 
@@ -30,14 +32,11 @@ library ieee;
 use ieee.std_logic_1164.all;
 
 use work.slvtypes.all;
-use work.rrilib.all;
--- synthesis translate_off
-use work.rritblib.all;
--- synthesis translate_on
+use work.rblib.all;
 
 -- ----------------------------------------------------------------------------
 
-entity rb_sres_or_2 is                  -- rribus result or, 2 input
+entity rb_sres_or_2 is                  -- rbus result or, 2 input
   port (
     RB_SRES_1  :  in rb_sres_type;                 -- rb_sres input 1
     RB_SRES_2  :  in rb_sres_type := rb_sres_init; -- rb_sres input 2
@@ -64,7 +63,7 @@ begin
   end process proc_comb;
 
 -- synthesis translate_off
-  ORMON : rritb_sres_or_mon
+  ORMON : rb_sres_or_mon
     port map (
       RB_SRES_1 => RB_SRES_1,
       RB_SRES_2 => RB_SRES_2,
diff --git a/rtl/vlib/rbus/rb_sres_or_3.vbom b/rtl/vlib/rbus/rb_sres_or_3.vbom
new file mode 100644
index 00000000..51df0b70
--- /dev/null
+++ b/rtl/vlib/rbus/rb_sres_or_3.vbom
@@ -0,0 +1,7 @@
+# libs
+../slvtypes.vhd
+rblib.vhd
+# components
+[ghdl,isim]rb_sres_or_mon.vbom
+# design
+rb_sres_or_3.vhd
diff --git a/rtl/vlib/rri/rb_sres_or_3.vhd b/rtl/vlib/rbus/rb_sres_or_3.vhd
similarity index 84%
rename from rtl/vlib/rri/rb_sres_or_3.vhd
rename to rtl/vlib/rbus/rb_sres_or_3.vhd
index cac90e26..0824bfa1 100644
--- a/rtl/vlib/rri/rb_sres_or_3.vhd
+++ b/rtl/vlib/rbus/rb_sres_or_3.vhd
@@ -1,4 +1,4 @@
--- $Id: rb_sres_or_3.vhd 314 2010-07-09 17:38:41Z mueller $
+-- $Id: rb_sres_or_3.vhd 343 2010-12-05 21:24:38Z mueller $
 --
 -- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -13,14 +13,16 @@
 --
 ------------------------------------------------------------------------------
 -- Module Name:    rb_sres_or_3 - syn
--- Description:    rribus result or, 3 input
+-- Description:    rbus result or, 3 input
 --
--- Dependencies:   rritb_sres_or_mon    [sim only]
+-- Dependencies:   rb_sres_or_mon    [sim only]
 -- Test bench:     -
 -- Target Devices: generic
--- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.29
+-- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
+--
 -- Revision History: 
 -- Date         Rev Version  Comment
+-- 2010-12-04   343   1.1.1  use now rb_sres_or_mon
 -- 2010-06-26   309   1.1    add rritb_sres_or_mon
 -- 2008-08-22   161   1.0.1  renamed rri_rbres_ -> rb_sres_
 -- 2008-01-20   113   1.0    Initial version 
@@ -30,14 +32,11 @@ library ieee;
 use ieee.std_logic_1164.all;
 
 use work.slvtypes.all;
-use work.rrilib.all;
--- synthesis translate_off
-use work.rritblib.all;
--- synthesis translate_on
+use work.rblib.all;
 
 -- ----------------------------------------------------------------------------
 
-entity rb_sres_or_3 is                  -- rribus result or, 3 input
+entity rb_sres_or_3 is                  -- rbus result or, 3 input
   port (
     RB_SRES_1  :  in rb_sres_type;                 -- rb_sres input 1
     RB_SRES_2  :  in rb_sres_type := rb_sres_init; -- rb_sres input 2
@@ -69,7 +68,7 @@ begin
   end process proc_comb;
   
 -- synthesis translate_off
-  ORMON : rritb_sres_or_mon
+  ORMON : rb_sres_or_mon
     port map (
       RB_SRES_1 => RB_SRES_1,
       RB_SRES_2 => RB_SRES_2,
diff --git a/rtl/vlib/rbus/rb_sres_or_mon.vbom b/rtl/vlib/rbus/rb_sres_or_mon.vbom
new file mode 100644
index 00000000..28d6bbaa
--- /dev/null
+++ b/rtl/vlib/rbus/rb_sres_or_mon.vbom
@@ -0,0 +1,5 @@
+# libs
+../slvtypes.vhd
+rblib.vhd
+# design
+rb_sres_or_mon.vhd
diff --git a/rtl/vlib/rri/tb/rritb_sres_or_mon.vhd b/rtl/vlib/rbus/rb_sres_or_mon.vhd
similarity index 89%
rename from rtl/vlib/rri/tb/rritb_sres_or_mon.vhd
rename to rtl/vlib/rbus/rb_sres_or_mon.vhd
index 0b72bd05..ca394454 100644
--- a/rtl/vlib/rri/tb/rritb_sres_or_mon.vhd
+++ b/rtl/vlib/rbus/rb_sres_or_mon.vhd
@@ -1,4 +1,4 @@
--- $Id: rritb_sres_or_mon.vhd 336 2010-11-06 18:28:27Z mueller $
+-- $Id: rb_sres_or_mon.vhd 347 2010-12-24 12:10:42Z mueller $
 --
 -- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -12,14 +12,16 @@
 -- for complete details.
 --
 ------------------------------------------------------------------------------
--- Module Name:    rritb_sres_or_mon - sim
--- Description:    rribus result or monitor
+-- Module Name:    rb_sres_or_mon - sim
+-- Description:    rbus result or monitor
 --
 -- Dependencies:   -
 -- Test bench:     -
 -- Tool versions:  ghdl 0.29
+--
 -- Revision History: 
 -- Date         Rev Version  Comment
+-- 2010-12-23   347   3.0    rename rritb_sres_or_mon->rb_sres_or_mon
 -- 2010-10-28   336   1.0.1  log errors only if now>0ns (drop startup glitches)
 -- 2010-06-26   309   1.0    Initial version 
 ------------------------------------------------------------------------------
@@ -30,20 +32,20 @@ use ieee.std_logic_textio.all;
 use std.textio.all;
 
 use work.slvtypes.all;
-use work.rrilib.all;
+use work.rblib.all;
 
 -- ----------------------------------------------------------------------------
 
-entity rritb_sres_or_mon is             -- rribus result or monitor
+entity rb_sres_or_mon is                -- rbus result or monitor
   port (
     RB_SRES_1  :  in rb_sres_type;                 -- rb_sres input 1
     RB_SRES_2  :  in rb_sres_type;                 -- rb_sres input 2
     RB_SRES_3  :  in rb_sres_type := rb_sres_init; -- rb_sres input 3
     RB_SRES_4  :  in rb_sres_type := rb_sres_init  -- rb_sres input 4
   );
-end rritb_sres_or_mon;
+end rb_sres_or_mon;
 
-architecture sim of rritb_sres_or_mon is
+architecture sim of rb_sres_or_mon is
   
 begin
 
@@ -100,7 +102,7 @@ begin
         write(oline, ndout);
       end if;
       write(oline, string'(" FAIL in "));
-      write(oline, rritb_sres_or_mon'path_name);
+      write(oline, rb_sres_or_mon'path_name);
       writeline(output, oline);
     end if;
     
diff --git a/rtl/vlib/rbus/rbd_tester.vbom b/rtl/vlib/rbus/rbd_tester.vbom
new file mode 100644
index 00000000..aed140df
--- /dev/null
+++ b/rtl/vlib/rbus/rbd_tester.vbom
@@ -0,0 +1,8 @@
+# libs
+../slvtypes.vhd
+../memlib/memlib.vhd
+rblib.vhd
+# components
+../memlib/fifo_1c_dram_raw.vbom
+# design
+rbd_tester.vhd
diff --git a/rtl/vlib/rbus/rbd_tester.vhd b/rtl/vlib/rbus/rbd_tester.vhd
new file mode 100644
index 00000000..ea7d3fe8
--- /dev/null
+++ b/rtl/vlib/rbus/rbd_tester.vhd
@@ -0,0 +1,337 @@
+-- $Id: rbd_tester.vhd 352 2011-01-02 13:01:37Z mueller $
+--
+-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name:    rbd_tester - syn
+-- Description:    rbus dev: rbus tester
+--
+-- Dependencies:   memlib/fifo_1c_dram_raw
+--
+-- Test bench:     rlink/tb/tb_rlink (used as test target)
+--
+-- Target Devices: generic
+-- Tool versions:  xst 12.1; ghdl 0.29
+--
+-- Synthesized (xst):
+-- Date         Rev  ise         Target      flop lutl lutm slic t peri
+-- 2010-12-12   344 12.1    M53d xc3s1000-4    78  204   32  133 s  8.0
+-- 2010-12-04   343 12.1    M53d xc3s1000-4    75  214   32  136 s  9.3
+--
+-- Revision History: 
+-- Date         Rev Version  Comment
+-- 2010-12-31   352   1.0.3  simplify irb_ack logic
+-- 2010-12-29   351   1.0.2  default addr 111101xx->111100xx
+-- 2010-12-12   344   1.0.1  send 0101.. on busy or err; fix init and busy logic
+-- 2010-12-04   343   1.0    Initial version 
+------------------------------------------------------------------------------
+--
+-- rbus registers:
+--
+-- Address   Bits Name        r/w/f  Function
+-- bbbbbb00       cntl        r/w/-  Control register
+--             15   nofifo    r/w/-    a 1 disables fifo, to test delayed aborts
+--          14:12   stat      r/w/-    echo'ed on RB_STAT
+--          11:00   nbusy     r/w/-    busy cycles (for data and fifo access)
+--             00   go        r/w/-    enables monitor
+-- bbbbbb01 15:00 data        r/w/-  Data register (just w/r reg, no function)
+-- bbbbbb10 15:00 fifo        r/w/-  Fifo interface register
+-- bbbbbb11       attn        r/w/-  Attn/Length register
+--          15:00                    w: ping RB_LAM lines
+--           9:00                    r: return cycle length of last access
+-- 
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+use work.slvtypes.all;
+use work.memlib.all;
+use work.rblib.all;
+
+entity rbd_tester is                    -- rbus dev: rbus tester
+                                        -- complete rrirp_aif interface
+  generic (
+    RB_ADDR : slv8 := conv_std_logic_vector(2#11110000#,8));
+  port (
+    CLK  : in slbit;                    -- clock
+    RESET : in slbit;                   -- reset
+    RB_MREQ : in rb_mreq_type;          -- rbus: request
+    RB_SRES : out rb_sres_type;         -- rbus: response
+    RB_LAM : out slv16;                 -- rbus: look at me
+    RB_STAT : out slv3                  -- rbus: status flags
+  );
+end entity rbd_tester;
+
+
+architecture syn of rbd_tester is
+
+  constant awidth : positive := 4;      -- fifo address width
+
+  constant rbaddr_cntl : slv2 := "00";  -- cntl address offset
+  constant rbaddr_data : slv2 := "01";  -- data address offset
+  constant rbaddr_fifo : slv2 := "10";  -- fifo address offset
+  constant rbaddr_attn : slv2 := "11";  -- attn address offset
+
+  constant cntl_rbf_nofifo  : integer := 15;
+  subtype  cntl_rbf_stat    is integer range 14 downto 12;
+  subtype  cntl_rbf_nbusy   is integer range  9 downto  0;
+
+  constant init_rbf_cntl  : integer :=  0;
+  constant init_rbf_data  : integer :=  1;
+  constant init_rbf_fifo  : integer :=  2;
+  
+  type regs_type is record              -- state registers
+    rbsel : slbit;                      -- rbus select
+    nofifo : slbit;                     -- disable fifo flag
+    stat : slv3;                        -- stat setting
+    nbusy : slv10;                      -- nbusy setting
+    data : slv16;                       -- data register
+    act_1 : slbit;                      -- rbsel and (re or we) in last cycle
+    ncyc : slv10;                       -- cycle length of last access
+    cntbusy : slv10;                    -- busy timer
+    cntcyc : slv10;                     -- cycle length counter
+  end record regs_type;
+
+  constant regs_init : regs_type := (
+    '0',                                -- rbsel
+    '0',                                -- nofifo
+    (others=>'0'),                      -- stat
+    (others=>'0'),                      -- nbusy
+    (others=>'0'),                      -- data
+    '0',                                -- act_1
+    (others=>'0'),                      -- ncyc
+    (others=>'0'),                      -- cntbusy
+    (others=>'0')                       -- cntcyc
+  );
+
+  constant cntcyc_max : slv(regs_init.cntcyc'range) := (others=>'1');
+
+  signal R_REGS : regs_type := regs_init;
+  signal N_REGS : regs_type := regs_init;
+   
+  signal FIFO_RESET : slbit := '0';
+  signal FIFO_RE : slbit := '0';
+  signal FIFO_WE : slbit := '0';
+  signal FIFO_EMPTY : slbit := '0';
+  signal FIFO_FULL : slbit := '0';
+  signal FIFO_SIZE : slv(awidth-1 downto 0) := (others=>'0');
+  signal FIFO_DO : slv16 := (others=>'0');
+  
+begin
+
+  FIFO : fifo_1c_dram_raw
+    generic map (
+      AWIDTH => awidth,
+      DWIDTH => 16)
+    port map (
+      CLK   => CLK,
+      RESET => FIFO_RESET,
+      RE    => FIFO_RE,
+      WE    => FIFO_WE,
+      DI    => RB_MREQ.din,
+      DO    => FIFO_DO,
+      SIZE  => FIFO_SIZE,      
+      EMPTY => FIFO_EMPTY,
+      FULL  => FIFO_FULL
+    );
+
+  proc_regs: process (CLK)
+  begin
+    if CLK'event and CLK='1' then
+      if RESET = '1' then
+        R_REGS <= regs_init;
+      else
+        R_REGS <= N_REGS;
+      end if;
+    end if;
+  end process proc_regs;
+
+  proc_next : process (R_REGS, RB_MREQ, FIFO_EMPTY, FIFO_FULL, FIFO_DO)
+    variable r : regs_type := regs_init;
+    variable n : regs_type := regs_init;
+    variable irb_ack  : slbit := '0';
+    variable irb_busy : slbit := '0';
+    variable irb_err  : slbit := '0';
+    variable irb_dout : slv16 := (others=>'0');
+    variable irbena : slbit := '0';
+    variable irblam : slv16 := (others=>'0');
+    variable ififo_re : slbit := '0';
+    variable ififo_we : slbit := '0';
+    variable ififo_reset : slbit := '0';
+    variable isbusy : slbit := '0';
+  begin
+
+    r := R_REGS;
+    n := R_REGS;
+
+    irb_ack  := '0';
+    irb_busy := '0';
+    irb_err  := '0';
+    irb_dout := (others=>'0');
+    irblam   := (others=>'0');
+
+    irbena  := RB_MREQ.re or RB_MREQ.we;
+        
+    ififo_re := '0';
+    ififo_we := '0';
+    ififo_reset := '0';
+
+    isbusy := '0';
+    if unsigned(r.cntbusy) /= 0 then
+      isbusy := '1';
+    end if;
+
+    -- rbus address decoder
+    n.rbsel := '0';
+    if RB_MREQ.aval='1' and RB_MREQ.addr(7 downto 2)=RB_ADDR(7 downto 2) then
+
+      n.rbsel := '1';
+
+      if irbena = '0' then              -- addr valid and selected, but no req
+        n.cntbusy := r.nbusy;             -- preset busy timer
+        n.cntcyc  := (others=>'0');       -- clear cycle length counter
+      end if;
+
+    end if;
+
+    -- rbus transactions
+    if r.rbsel = '1' then
+      
+      if irbena = '1' then              -- if request active
+        if unsigned(r.cntbusy) /= 0 then  -- if busy timer > 0
+          n.cntbusy := unsigned(r.cntbusy) - 1; -- decrement busy timer
+        end if;
+        if r.cntcyc /= cntcyc_max then    -- if cycle counter < max
+          n.cntcyc  := unsigned(r.cntcyc) + 1;  -- increment cycle counter
+        end if;
+      end if;
+      
+      irb_ack := irbena;                  -- ack all (some rejects later)
+
+      case RB_MREQ.addr(1 downto 0) is
+
+        when rbaddr_cntl =>
+          if RB_MREQ.we='1' then 
+            n.nofifo := RB_MREQ.din(cntl_rbf_nofifo);
+            n.stat   := RB_MREQ.din(cntl_rbf_stat);
+            n.nbusy  := RB_MREQ.din(cntl_rbf_nbusy);
+            if r.nofifo='1' and RB_MREQ.din(cntl_rbf_nofifo)='0' then
+              ififo_reset := '1';
+            end if;
+          end if;
+          
+        when rbaddr_data =>
+          irb_busy := irbena and isbusy;
+          if RB_MREQ.we='1' and isbusy='0' then
+            n.data := RB_MREQ.din;
+          end if;
+          
+        when rbaddr_fifo =>
+          if r.nofifo = '0' then            -- if fifo enabled
+            irb_busy := irbena and isbusy;
+            if RB_MREQ.re='1' and isbusy='0' then
+              if FIFO_EMPTY = '1' then
+                irb_err := '1';
+              else
+                ififo_re := '1';
+              end if;
+            end if;
+            if RB_MREQ.we='1' and isbusy='0' then
+              if FIFO_FULL = '1' then
+                irb_err := '1';
+              else
+                ififo_we := '1';
+              end if;
+            end if;
+
+          else                              -- else: if fifo disabled
+            irb_ack := '0';                   -- nak it
+            if isbusy = '1' then              -- or do a delayed nak
+              irb_ack  := irbena;
+              irb_busy := irbena;
+            end if;
+          end if;
+
+        when rbaddr_attn =>
+          if RB_MREQ.we = '1' then
+            irblam := RB_MREQ.din;
+          end if;
+          
+        when others => null;
+      end case;
+    end if;
+
+    -- rbus output driver
+    --   send a '0101...' pattern when selected and busy or err
+    --   send data only when busy=0 and err=0
+    --   this extra logic allows to debug rlink state machine
+    if r.rbsel = '1' then
+      if RB_MREQ.re='1' and irb_busy='0' and irb_err='0' then
+        case RB_MREQ.addr(1 downto 0) is
+          when rbaddr_cntl =>
+            irb_dout(cntl_rbf_stat)   := r.stat;
+            irb_dout(cntl_rbf_nofifo) := r.nofifo;
+            irb_dout(cntl_rbf_nbusy)  := r.nbusy;
+          when rbaddr_data =>
+            irb_dout := r.data;
+          when rbaddr_fifo =>
+            if r.nofifo='0' and FIFO_EMPTY = '0' then
+              irb_dout := FIFO_DO;
+            end if;
+          when rbaddr_attn =>
+            irb_dout(r.cntcyc'range) := r.ncyc;
+          when others => null;
+        end case;
+      else
+        irb_dout := "0101010101010101";
+      end if;
+    end if;
+
+    -- init transactions
+    if RB_MREQ.init='1' and RB_MREQ.we='1' and RB_MREQ.addr=RB_ADDR then
+      if RB_MREQ.din(init_rbf_cntl) = '1' then
+        n.nofifo := '0';
+        n.stat   := (others=>'0');
+        n.nbusy  := (others=>'0');
+      end if;
+      if RB_MREQ.din(init_rbf_data) = '1' then
+        n.data   := (others=>'0');
+      end if;
+      if RB_MREQ.din(init_rbf_fifo) = '1' then
+        ififo_reset := '1';
+      end if;
+    end if;
+    
+    -- other transactions
+    if irbena='0' and r.act_1='1' then
+      n.ncyc := r.cntcyc;
+    end if;
+    n.act_1 := irbena;
+    
+    N_REGS <= n;
+
+    FIFO_RE    <= ififo_re;
+    FIFO_WE    <= ififo_we;
+    FIFO_RESET <= ififo_reset;
+      
+    RB_SRES.dout <= irb_dout;
+    RB_SRES.ack  <= irb_ack;
+    RB_SRES.err  <= irb_err;
+    RB_SRES.busy <= irb_busy;
+
+    RB_LAM  <= irblam;
+    RB_STAT <= r.stat;
+      
+  end process proc_next;
+
+end syn;
diff --git a/rtl/vlib/rbus/rbdlib.vhd b/rtl/vlib/rbus/rbdlib.vhd
new file mode 100644
index 00000000..cd8631b6
--- /dev/null
+++ b/rtl/vlib/rbus/rbdlib.vhd
@@ -0,0 +1,114 @@
+-- $Id: rbdlib.vhd 351 2010-12-30 21:50:54Z mueller $
+--
+-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name:   rbdlib
+-- Description:    Definitions for rbus devices
+--
+-- Dependencies:   -
+-- Tool versions:  xst 12.1; ghdl 0.29
+--
+-- Revision History: 
+-- Date         Rev Version  Comment
+-- 2010-12-29   351   1.2    new address layout; add rbd_timer
+-- 2010-12-27   349   1.1    now correct defs for _rbmon and _eyemon
+-- 2010-12-04   343   1.0    Initial version
+------------------------------------------------------------------------------
+--
+-- base addresses of some standard rbus devices
+--
+--   rbd_rbmon     111111xx  -++--   these three used as monitors
+--   rbd_eyemon    111110xx   / 
+--   rbd_rlstat    1111011x  /   
+--   rbd_bram      1111010x      \
+--   rbd_tester    111100xx       +- all five used in test benchs
+--
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+use work.slvtypes.all;
+use work.rblib.all;
+
+package rbdlib is
+
+component rbd_tester is                 -- rbus dev: rbus tester
+                                        -- complete rbus_aif interface
+  generic (
+    RB_ADDR : slv8 := conv_std_logic_vector(2#11110000#,8));
+  port (
+    CLK  : in slbit;                    -- clock
+    RESET : in slbit;                   -- reset
+    RB_MREQ : in rb_mreq_type;          -- rbus: request
+    RB_SRES : out rb_sres_type;         -- rbus: response
+    RB_LAM : out slv16;                 -- rbus: look at me
+    RB_STAT : out slv3                  -- rbus: status flags
+  );
+end component;
+
+component rbd_bram is                   -- rbus dev: bram test target
+                                        -- incomplete rbus_aif interface
+  generic (
+    RB_ADDR : slv8 := conv_std_logic_vector(2#11110100#,8));
+  port (
+    CLK  : in slbit;                    -- clock
+    RESET : in slbit;                   -- reset
+    RB_MREQ : in rb_mreq_type;          -- rbus: request
+    RB_SRES : out rb_sres_type          -- rbus: response
+  );
+end component;
+
+component rbd_rbmon is                  -- rbus dev: rbus monitor
+  generic (
+    RB_ADDR : slv8 := conv_std_logic_vector(2#11111100#,8);
+    AWIDTH : positive := 9);
+  port (
+    CLK  : in slbit;                    -- clock
+    RESET : in slbit;                   -- reset
+    RB_MREQ : in rb_mreq_type;          -- rbus: request
+    RB_SRES : out rb_sres_type;         -- rbus: response
+    RB_SRES_SUM : in rb_sres_type       -- rbus: response (sum for monitor)
+  );
+end component;
+
+component rbd_eyemon is                 -- rbus dev: eye monitor for serport's
+  generic (
+    RB_ADDR : slv8 := conv_std_logic_vector(2#11111000#,8);
+    RDIV : slv8 := conv_std_logic_vector(0,8));
+  port (
+    CLK  : in slbit;                    -- clock
+    RESET : in slbit;                   -- reset
+    RB_MREQ : in rb_mreq_type;          -- rbus: request
+    RB_SRES : out rb_sres_type;         -- rbus: response
+    RXSD : in slbit;                    -- rx: serial data
+    RXACT : in slbit                    -- rx: active (start seen)
+  );
+end component;
+
+component rbd_timer is                  -- rbus dev: usec precision timer
+  generic (
+    RB_ADDR : slv8 := conv_std_logic_vector(2#00000000#,8));
+  port (
+    CLK  : in slbit;                    -- clock
+    CE_USEC : in slbit;                 -- usec pulse
+    RESET : in slbit;                   -- reset
+    RB_MREQ : in rb_mreq_type;          -- rbus: request
+    RB_SRES : out rb_sres_type;         -- rbus: response
+    DONE : out slbit;                   -- mark last timer cycle
+    BUSY : out slbit                    -- timer running
+  );
+end component;
+
+end package rbdlib;
diff --git a/rtl/vlib/rbus/rblib.vhd b/rtl/vlib/rbus/rblib.vhd
new file mode 100644
index 00000000..a8faf80c
--- /dev/null
+++ b/rtl/vlib/rbus/rblib.vhd
@@ -0,0 +1,193 @@
+-- $Id: rblib.vhd 349 2010-12-28 14:02:13Z mueller $
+--
+-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name:   rblib
+-- Description:    Definitions for rbus interface and bus entities
+--
+-- Dependencies:   -
+-- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
+--
+-- Revision History: 
+-- Date         Rev Version  Comment
+-- 2010-12-26   349   3.0.2  add rb_sel
+-- 2010-12-22   346   3.0.1  add rb_mon and rb_mon_sb;
+-- 2010-12-04   343   3.0    extracted from rrilib and rritblib;
+--                           rbus V3 interface: use aval,re,we
+--                           ... rrilib history removed ...
+-- 2007-09-09    81   1.0    Initial version 
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+
+package rblib is
+
+type rb_mreq_type is record             -- rbus - master request
+  aval : slbit;                         -- address valid
+  re   : slbit;                         -- read enable
+  we   : slbit;                         -- write enable
+  init : slbit;                         -- init
+  addr : slv8;                          -- address
+  din  : slv16;                         -- data (input to slave)
+end record rb_mreq_type;
+
+constant rb_mreq_init : rb_mreq_type :=
+  ('0','0','0','0',                     -- aval, re, we, init
+   (others=>'0'),                       -- addr
+   (others=>'0'));                      -- din
+
+type rb_sres_type is record             -- rbus - slave response
+  ack  : slbit;                         -- acknowledge
+  busy : slbit;                         -- busy
+  err  : slbit;                         -- error
+  dout : slv16;                         -- data (output from slave)
+end record rb_sres_type;
+
+constant rb_sres_init : rb_sres_type :=
+  ('0','0','0',                         -- ack, busy, err
+   (others=>'0'));                      -- dout
+
+component rb_sel is                     -- rbus address select logic
+  generic (
+    RB_ADDR : slv8;                     -- rbus address base
+    SAWIDTH : natural := 0);            -- device subaddress space width
+  port (
+    CLK : in slbit;                     -- clock
+    RB_MREQ : in rb_mreq_type;          -- rbus request
+    SEL : out slbit                     -- select state bit
+  );
+end component;
+
+component rb_sres_or_2 is               -- rbus result or, 2 input
+  port (
+    RB_SRES_1  :  in rb_sres_type;                 -- rb_sres input 1
+    RB_SRES_2  :  in rb_sres_type := rb_sres_init; -- rb_sres input 2
+    RB_SRES_OR : out rb_sres_type       -- rb_sres or'ed output
+  );
+end component;
+component rb_sres_or_3 is               -- rbus result or, 3 input
+  port (
+    RB_SRES_1  :  in rb_sres_type;                 -- rb_sres input 1
+    RB_SRES_2  :  in rb_sres_type := rb_sres_init; -- rb_sres input 2
+    RB_SRES_3  :  in rb_sres_type := rb_sres_init; -- rb_sres input 3
+    RB_SRES_OR : out rb_sres_type       -- rb_sres or'ed output
+  );
+end component;
+component rb_sres_or_4 is               -- rbus result or, 4 input
+  port (
+    RB_SRES_1  :  in rb_sres_type;                 -- rb_sres input 1
+    RB_SRES_2  :  in rb_sres_type := rb_sres_init; -- rb_sres input 2
+    RB_SRES_3  :  in rb_sres_type := rb_sres_init; -- rb_sres input 3
+    RB_SRES_4  :  in rb_sres_type := rb_sres_init; -- rb_sres input 4
+    RB_SRES_OR : out rb_sres_type       -- rb_sres or'ed output
+  );
+end component;
+
+component rbus_aif is                   -- rbus, abstract interface
+  port (
+    CLK  : in slbit;                    -- clock
+    RESET  : in slbit := '0';           -- reset
+    RB_MREQ : in rb_mreq_type;          -- rbus: request
+    RB_SRES : out rb_sres_type;         -- rbus: response
+    RB_LAM : out slv16;                 -- rbus: look at me
+    RB_STAT : out slv3                  -- rbus: status flags
+  );
+end component;
+
+component rb_wreg_rw_3 is               -- rbus: wide register r/w 3 bit select
+  generic (
+    DWIDTH : positive := 16);
+  port (
+    CLK  : in slbit;                    -- clock
+    RESET  : in slbit;                  -- reset
+    FADDR : slv3;                       -- field address
+    SEL : slbit;                        -- select
+    DATA : out slv(DWIDTH-1 downto 0);  -- data
+    RB_MREQ :  in rb_mreq_type;         -- rbus request
+    RB_SRES : out rb_sres_type          -- rbus response
+  );
+end component;
+
+component rb_wreg_w_3 is                -- rbus: wide register w-o 3 bit select
+  generic (
+    DWIDTH : positive := 16);
+  port (
+    CLK  : in slbit;                    -- clock
+    RESET  : in slbit;                  -- reset
+    FADDR : slv3;                       -- field address
+    SEL : slbit;                        -- select
+    DATA : out slv(DWIDTH-1 downto 0);  -- data
+    RB_MREQ :  in rb_mreq_type;         -- rbus request
+    RB_SRES : out rb_sres_type          -- rbus response
+  );
+end component;
+
+component rb_wreg_r_3 is                -- rbus: wide register r-o 3 bit select
+  generic (
+    DWIDTH : positive := 16);
+  port (
+    FADDR : slv3;                       -- field address
+    SEL : slbit;                        -- select
+    DATA : in slv(DWIDTH-1 downto 0);   -- data
+    RB_SRES : out rb_sres_type          -- rbus response
+  );
+end component;
+
+--
+-- components for use in test benches (not synthesizable)
+--
+
+component rb_sres_or_mon is             -- rbus result or monitor
+  port (
+    RB_SRES_1  :  in rb_sres_type;      -- rb_sres input 1
+    RB_SRES_2  :  in rb_sres_type;      -- rb_sres input 2
+    RB_SRES_3  :  in rb_sres_type := rb_sres_init; -- rb_sres input 3
+    RB_SRES_4  :  in rb_sres_type := rb_sres_init  -- rb_sres input 4
+  );
+end component;
+
+-- simbus sb_cntl field usage for rbus
+constant sbcntl_sbf_rbmon : integer := 14;
+
+component rb_mon is                     -- rbus monitor
+  generic (
+    DBASE : positive :=  2);            -- base for writing data values
+  port (
+    CLK  : in slbit;                    -- clock
+    CLK_CYCLE : in slv31 := (others=>'0');  -- clock cycle number
+    ENA  : in slbit := '1';             -- enable monitor output
+    RB_MREQ : in rb_mreq_type;          -- rbus: request
+    RB_SRES : in rb_sres_type;          -- rbus: response
+    RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me
+    RB_STAT : in slv3                   -- rbus: status flags
+  ); 
+end component;
+
+component rb_mon_sb is                  -- simbus wrapper for rbus monitor
+  generic (
+    DBASE : positive :=  2;             -- base for writing data values
+    ENAPIN : integer := sbcntl_sbf_rbmon); -- SB_CNTL signal to use for enable
+  port (
+    CLK  : in slbit;                    -- clock
+    RB_MREQ : in rb_mreq_type;          -- rbus: request
+    RB_SRES : in rb_sres_type;          -- rbus: response
+    RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me
+    RB_STAT : in slv3                   -- rbus: status flags
+  );
+end component;
+
+
+end rblib;
diff --git a/rtl/vlib/rlink/Makefile b/rtl/vlib/rlink/Makefile
new file mode 100644
index 00000000..fed95661
--- /dev/null
+++ b/rtl/vlib/rlink/Makefile
@@ -0,0 +1,22 @@
+# $Id: Makefile 343 2010-12-05 21:24:38Z mueller $
+#
+#  Revision History: 
+# Date         Rev Version  Comment
+# 2007-12-09   100   1.0.1  drop ISE_p definition
+# 2007-07-06    64   1.0    Initial version
+#
+VBOM_all = $(wildcard *.vbom)
+NGC_all  = $(VBOM_all:.vbom=.ngc)
+#
+.phony : all clean
+#
+all : $(NGC_all)
+#
+clean : ise_clean
+#
+#----
+#
+include $(RETROBASE)/rtl/vlib/Makefile.xflow
+#
+include $(VBOM_all:.vbom=.dep_xst)
+#
diff --git a/rtl/vlib/rlink/rlink_base.vbom b/rtl/vlib/rlink/rlink_base.vbom
new file mode 100644
index 00000000..b2e9d526
--- /dev/null
+++ b/rtl/vlib/rlink/rlink_base.vbom
@@ -0,0 +1,11 @@
+# libs
+../slvtypes.vhd
+../rbus/rblib.vhd
+rlinklib.vbom
+# components
+rlink_core.vbom
+rlink_rlb2rl.vbom
+[ghdl,isim]rlink_mon_sb.vbom
+[ghdl,isim]../rbus/rb_mon_sb.vbom
+# design
+rlink_base.vhd
diff --git a/rtl/vlib/rlink/rlink_base.vhd b/rtl/vlib/rlink/rlink_base.vhd
new file mode 100644
index 00000000..a08130f6
--- /dev/null
+++ b/rtl/vlib/rlink/rlink_base.vhd
@@ -0,0 +1,174 @@
+-- $Id: rlink_base.vhd 350 2010-12-28 16:40:11Z mueller $
+--
+-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for complete details.
+-- 
+------------------------------------------------------------------------------
+-- Module Name:    rlink_base - syn
+-- Description:    rlink base: core+rl2rlb+rlmon+rbmon - w/ buffered 8bit iface
+--
+-- Dependencies:   rlink_core
+--                 rlink_rlb2rl
+--                 rlink_mon_sb    [sim only]
+--                 rbus/rb_mon_sb  [sim only]
+--
+-- Test bench:     tb/tb_rlink_serport
+--                 tb/tb_rlink_tba_ttcombo
+--
+-- Target Devices: generic
+-- Tool versions:  xst 12.1; ghdl 0.29
+--
+-- Synthesized (xst):
+-- Date         Rev  ise         Target      flop lutl lutm slic t peri ifa ofa
+-- 2010-12-25   348 12.1    M53d xc3s1000-4   206  451   72  304 s 10.5   5   5
+-- 2010-12-25   348 12.1    M53d xc3s1000-4   194  407   36  262 s 10.4   5   0
+--
+-- Revision History: 
+-- Date         Rev Version  Comment
+-- 2010-12-25   348   1.0    Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+use work.slvtypes.all;
+use work.rblib.all;
+use work.rlinklib.all;
+
+entity rlink_base is                    -- rlink base: core+rlb2rl+rlmon+rbmon
+                                        -- with buffered 8bit interface
+  generic (
+    ATOWIDTH : positive :=  5;          -- access timeout counter width
+    ITOWIDTH : positive :=  6;          -- idle timeout counter width
+    CPREF : slv4 := c_rlink_cpref;      -- comma prefix
+    IFAWIDTH : natural :=  5;           -- input fifo address width  (0=none)
+    OFAWIDTH : natural :=  5;           -- output fifo address width (0=none)
+    ENAPIN_RLMON : integer := sbcntl_sbf_rlmon;  -- SB_CNTL for rlmon (-1=none)
+    ENAPIN_RBMON : integer := sbcntl_sbf_rbmon); -- SB_CNTL for rbmon (-1=none)
+  port (
+    CLK  : in slbit;                    -- clock
+    CE_INT : in slbit := '0';           -- rlink ito time unit clock enable
+    RESET  : in slbit;                  -- reset
+    RLB_DI : in slv8;                   -- rlink 8b: data in
+    RLB_ENA : in slbit;                 -- rlink 8b: data enable
+    RLB_BUSY : out slbit;               -- rlink 8b: data busy
+    RLB_DO : out slv8;                  -- rlink 8b: data out
+    RLB_VAL : out slbit;                -- rlink 8b: data valid
+    RLB_HOLD : in slbit;                -- rlink 8b: data hold
+    IFIFO_SIZE : out slv4;              --  input fifo size (4 msb's)
+    OFIFO_SIZE : out slv4;              -- output fifo fill (4 msb's)
+    RL_MONI : out rl_moni_type;         -- rlink: monitor port
+    RB_MREQ : out rb_mreq_type;         -- rbus: request
+    RB_SRES : in rb_sres_type;          -- rbus: response
+    RB_LAM : in slv16;                  -- rbus: look at me
+    RB_STAT : in slv3                   -- rbus: status flags
+  );
+end entity rlink_base;  
+
+
+architecture syn of rlink_base is
+
+  signal RL_DI : slv9 := (others=>'0');
+  signal RL_ENA : slbit := '0';
+  signal RL_BUSY : slbit := '0';
+  signal RL_DO : slv9 := (others=>'0');
+  signal RL_VAL : slbit := '0';
+  signal RL_HOLD : slbit := '0';
+  signal RB_MREQ_L : rb_mreq_type := rb_mreq_init;  -- local, readable RB_MREQ
+
+begin
+
+  RL : rlink_core
+    generic map (
+      ATOWIDTH => ATOWIDTH,
+      ITOWIDTH => ITOWIDTH)
+    port map (
+      CLK      => CLK,
+      CE_INT   => CE_INT,
+      RESET    => RESET,
+      RL_DI    => RL_DI,
+      RL_ENA   => RL_ENA,
+      RL_BUSY  => RL_BUSY,
+      RL_DO    => RL_DO,
+      RL_VAL   => RL_VAL,
+      RL_HOLD  => RL_HOLD,
+      RL_MONI  => RL_MONI,
+      RB_MREQ  => RB_MREQ_L,
+      RB_SRES  => RB_SRES,
+      RB_LAM   => RB_LAM,
+      RB_STAT  => RB_STAT
+    );
+  -- vhdl'93 unfortunately doesn't allow to read a signal bound to an out port
+  -- because RB_MREQ is read by the monitors, an extra internal
+  -- signal must be used. This will not be needed with vhdl'2000 anymore
+  
+  RB_MREQ <= RB_MREQ_L;
+
+  RLB2RL : rlink_rlb2rl
+    generic map (
+      CPREF    => CPREF,
+      IFAWIDTH => IFAWIDTH,
+      OFAWIDTH => OFAWIDTH)
+    port map (
+      CLK        => CLK,
+      RESET      => RESET,
+      RLB_DI     => RLB_DI,
+      RLB_ENA    => RLB_ENA,
+      RLB_BUSY   => RLB_BUSY,
+      RLB_DO     => RLB_DO,
+      RLB_VAL    => RLB_VAL,
+      RLB_HOLD   => RLB_HOLD,
+      IFIFO_SIZE => IFIFO_SIZE,
+      OFIFO_SIZE => OFIFO_SIZE,
+      RL_DI      => RL_DI,
+      RL_ENA     => RL_ENA,
+      RL_BUSY    => RL_BUSY,
+      RL_DO      => RL_DO,
+      RL_VAL     => RL_VAL,
+      RL_HOLD    => RL_HOLD
+    );
+  
+-- synthesis translate_off
+
+  RLMON: if ENAPIN_RLMON >= 0  generate
+    MON : rlink_mon_sb
+      generic map (
+        DWIDTH => RL_DI'length,
+        ENAPIN => ENAPIN_RLMON)
+      port map (
+        CLK     => CLK,
+        RL_DI   => RL_DI,
+        RL_ENA  => RL_ENA,
+        RL_BUSY => RL_BUSY,
+        RL_DO   => RL_DO,
+        RL_VAL  => RL_VAL,
+        RL_HOLD => RL_HOLD
+      );
+  end generate RLMON;
+
+  RBMON: if ENAPIN_RBMON >= 0  generate
+    MON : rb_mon_sb
+      generic map (
+        DBASE  => 8,
+        ENAPIN => ENAPIN_RBMON)
+      port map (
+        CLK     => CLK,
+        RB_MREQ => RB_MREQ_L,
+        RB_SRES => RB_SRES,
+        RB_LAM  => RB_LAM,
+        RB_STAT => RB_STAT
+      );
+  end generate RBMON;
+  
+-- synthesis translate_on
+
+end syn;
diff --git a/rtl/vlib/rlink/rlink_base_serport.vbom b/rtl/vlib/rlink/rlink_base_serport.vbom
new file mode 100644
index 00000000..7ab61fa2
--- /dev/null
+++ b/rtl/vlib/rlink/rlink_base_serport.vbom
@@ -0,0 +1,9 @@
+# libs
+../slvtypes.vhd
+../rbus/rblib.vhd
+rlinklib.vbom
+# components
+rlink_base.vbom
+rlink_serport.vbom
+# design
+rlink_base_serport.vhd
diff --git a/rtl/vlib/rlink/rlink_base_serport.vhd b/rtl/vlib/rlink/rlink_base_serport.vhd
new file mode 100644
index 00000000..917f0bc6
--- /dev/null
+++ b/rtl/vlib/rlink/rlink_base_serport.vhd
@@ -0,0 +1,158 @@
+-- $Id: rlink_base_serport.vhd 350 2010-12-28 16:40:11Z mueller $
+--
+-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for complete details.
+-- 
+------------------------------------------------------------------------------
+-- Module Name:    rlink_base_serport - syn
+-- Description:    rlink base + serport combo
+--
+-- Dependencies:   rlink_base
+--                 rlink_serport
+--
+-- Test bench:     -
+--
+-- Target Devices: generic
+-- Tool versions:  xst 11.4, 12.1; ghdl 0.26-0.29
+--
+-- Synthesized (xst):
+-- Date         Rev  ise         Target      flop lutl lutm slic t peri ifa ofa
+-- 2010-12-26   348 12.1    M53d xc3s1000-4   332  687   72  463 s 10.2   5   5
+-- 2010-12-26   348 12.1    M53d xc3s1000-4   320  651   36  425 s 10.2   5   0
+-- 2010-12-26   301 12.1    M53d xc3s1000-4   289  619   36  394 s  9.9   -   -
+-- 2010-04-03   275 11.4    L68  xc3s1000-4   280  600   18  375 s  8.9   -   -
+--
+-- Revision History: 
+-- Date         Rev Version  Comment
+-- 2010-12-26   348   3.1    rename from rlink_core_serport, use now rlink_base
+-- 2010-12-24   347   3.0.1  rename: CP_*->RL->*
+-- 2010-12-04   343   3.0    renamed rri_ -> rlink_
+-- 2010-06-05   301   1.2.2  renamed _rpmon -> _rbmon
+-- 2010-06-03   300   1.2.1  use FAWIDTH=5 
+-- 2010-05-02   287   1.2    ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
+--                           drop RP_IINT from interfaces; drop RTSFLUSH generic
+-- 2010-04-18   279   1.1    drop RTSFBUF generic
+-- 2010-04-10   275   1.0    Initial version 
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+use work.slvtypes.all;
+use work.rblib.all;
+use work.rlinklib.all;
+
+entity rlink_base_serport is            -- rlink base+serport combo
+  generic (
+    ATOWIDTH : positive :=  5;          -- access timeout counter width
+    ITOWIDTH : positive :=  6;          -- idle timeout counter width
+    CPREF : slv4 := c_rlink_cpref;      -- comma prefix
+    IFAWIDTH : natural :=  5;           -- input fifo address width  (0=none)
+    OFAWIDTH : natural :=  5;           -- output fifo address width (0=none)
+    ENAPIN_RLMON : integer := sbcntl_sbf_rlmon;  -- SB_CNTL for rlmon (-1=none)
+    ENAPIN_RBMON : integer := sbcntl_sbf_rbmon;  -- SB_CNTL for rbmon (-1=none)
+    RB_ADDR : slv8 := conv_std_logic_vector(2#11111110#,8);
+    CDWIDTH : positive := 13;           -- clk divider width
+    CDINIT : natural   := 15);          -- clk divider initial/reset setting
+  port (
+    CLK  : in slbit;                    -- clock
+    CE_USEC : in slbit;                 -- 1 usec clock enable
+    CE_MSEC : in slbit;                 -- 1 msec clock enable
+    CE_INT : in slbit := '0';           -- rlink ito time unit clock enable
+    RESET  : in slbit;                  -- reset
+    RXSD : in slbit;                    -- receive serial data      (board view)
+    TXSD : out slbit;                   -- transmit serial data     (board view)
+    CTS_N : in slbit := '0';            -- clear to send   (act.low, board view)
+    RTS_N : out slbit;                  -- request to send (act.low, board view)
+    RB_MREQ : out rb_mreq_type;         -- rbus: request
+    RB_SRES : in rb_sres_type;          -- rbus: response
+    RB_LAM : in slv16;                  -- rbus: look at me
+    RB_STAT : in slv3;                  -- rbus: status flags
+    RL_MONI : out rl_moni_type;         -- rlink_core: monitor port
+    RL_SER_MONI : out rl_ser_moni_type  -- rlink_serport: monitor port
+  );
+end entity rlink_base_serport;
+
+
+architecture syn of rlink_base_serport is
+
+  signal RLB_DI : slv8 := (others=>'0');
+  signal RLB_ENA : slbit := '0';
+  signal RLB_BUSY : slbit := '0';
+  signal RLB_DO : slv8 := (others=>'0');
+  signal RLB_VAL : slbit := '0';
+  signal RLB_HOLD : slbit := '0';
+  signal IFIFO_SIZE : slv4 := (others=>'0');
+
+  signal RL_MONI_L : rl_moni_type := rl_moni_init;  -- local, readable RL_MONI
+  signal RB_MREQ_L : rb_mreq_type := rb_mreq_init;  -- local, readable RB_MREQ
+
+begin
+  
+  BASE : rlink_base
+    generic map (
+      ATOWIDTH     => ATOWIDTH,
+      ITOWIDTH     => ITOWIDTH,
+      CPREF        => CPREF,
+      IFAWIDTH     => IFAWIDTH,
+      OFAWIDTH     => OFAWIDTH,
+      ENAPIN_RLMON => ENAPIN_RLMON,
+      ENAPIN_RBMON => ENAPIN_RBMON)
+    port map (
+      CLK        => CLK,
+      CE_INT     => CE_INT,
+      RESET      => RESET,
+      RLB_DI     => RLB_DI,
+      RLB_ENA    => RLB_ENA,
+      RLB_BUSY   => RLB_BUSY,
+      RLB_DO     => RLB_DO,
+      RLB_VAL    => RLB_VAL,
+      RLB_HOLD   => RLB_HOLD,
+      IFIFO_SIZE => IFIFO_SIZE,
+      OFIFO_SIZE => open,
+      RL_MONI    => RL_MONI_L,
+      RB_MREQ    => RB_MREQ_L,
+      RB_SRES    => RB_SRES,
+      RB_LAM     => RB_LAM,
+      RB_STAT    => RB_STAT
+    );
+
+  RL_MONI <= RL_MONI_L;
+  RB_MREQ <= RB_MREQ_L;
+  
+  SERPORT : rlink_serport
+    generic map (
+      RB_ADDR  => RB_ADDR,
+      CDWIDTH  => CDWIDTH,
+      CDINIT   => CDINIT)
+    port map (
+      CLK        => CLK,
+      CE_USEC    => CE_USEC,
+      CE_MSEC    => CE_MSEC,
+      RESET      => RESET,
+      RXSD       => RXSD,
+      TXSD       => TXSD,
+      CTS_N      => CTS_N,
+      RTS_N      => RTS_N,
+      RLB_DI     => RLB_DI,
+      RLB_ENA    => RLB_ENA,
+      RLB_BUSY   => RLB_BUSY,
+      RLB_DO     => RLB_DO,
+      RLB_VAL    => RLB_VAL,
+      RLB_HOLD   => RLB_HOLD,
+      RB_MREQ    => RB_MREQ_L,
+      IFIFO_SIZE => IFIFO_SIZE,
+      RL_MONI    => RL_MONI_L,
+      RL_SER_MONI=> RL_SER_MONI
+    );
+  
+end syn;
diff --git a/rtl/vlib/rri/rri_core.vbom b/rtl/vlib/rlink/rlink_core.vbom
similarity index 64%
rename from rtl/vlib/rri/rri_core.vbom
rename to rtl/vlib/rlink/rlink_core.vbom
index bfcf2c34..a6480499 100644
--- a/rtl/vlib/rri/rri_core.vbom
+++ b/rtl/vlib/rlink/rlink_core.vbom
@@ -1,8 +1,9 @@
 # libs
 ../slvtypes.vhd
 ../comlib/comlib.vhd
-rrilib.vhd
+../rbus/rblib.vhd
+rlinklib.vbom
 # components
 ../comlib/crc8.vbom
 # design
-rri_core.vhd
+rlink_core.vhd
diff --git a/rtl/vlib/rri/rri_core.vhd b/rtl/vlib/rlink/rlink_core.vhd
similarity index 64%
rename from rtl/vlib/rri/rri_core.vhd
rename to rtl/vlib/rlink/rlink_core.vhd
index e4e0a89a..0fd792cc 100644
--- a/rtl/vlib/rri/rri_core.vhd
+++ b/rtl/vlib/rlink/rlink_core.vhd
@@ -1,4 +1,4 @@
--- $Id: rri_core.vhd 314 2010-07-09 17:38:41Z mueller $
+-- $Id: rlink_core.vhd 350 2010-12-28 16:40:11Z mueller $
 --
 -- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -12,26 +12,35 @@
 -- for complete details.
 -- 
 ------------------------------------------------------------------------------
--- Module Name:    rri_core - syn
--- Description:    rri: core interface
+-- Module Name:    rlink_core - syn
+-- Description:    rlink core with 9bit interface
 --
 -- Dependencies:   comlib/crc8
 --
--- Test bench:     tb/tb_rri_core
---                 tb/tb_rritba_ttcombo
---                 tb/tb_rriext_ttcombo
+-- Test bench:     tb/tb_rlink_direct
+--                 tb/tb_rlink_serport
+--                 tb/tb_rlink_tba_ttcombo
 --
 -- Target Devices: generic
--- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
+-- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
 --
 -- Synthesized (xst):
 -- Date         Rev  ise         Target      flop lutl lutm slic t peri
--- 2010-06-06   302  11.4    L68 xc3s1000-4   151  323    0  197 s  8.9
--- 2010-04-03   274  11.4    L68 xc3s1000-4   148  313    0  190 s  8.0
--- 2009-07-11   232  10.1.03 K39 xc3s1000-4   147  321    0  197 s  8.3
+-- 2010-12-04   343 12.1    M53d xc3s1000-4   155  322    0  199 s  8.9
+-- 2010-06-06   302 11.4    L68  xc3s1000-4   151  323    0  197 s  8.9
+-- 2010-04-03   274 11.4    L68  xc3s1000-4   148  313    0  190 s  8.0
+-- 2009-07-11   232 10.1.03 K39  xc3s1000-4   147  321    0  197 s  8.3
 --
 -- Revision History: 
 -- Date         Rev Version  Comment
+-- 2010-12-25   348   3.1.2  drop RL_FLUSH support, add RL_MONI for rlink_core;
+-- 2010-12-24   347   3.1.1  rename: CP_*->RL->*
+-- 2010-12-22   346   3.1    wblk dcrc error: send nak, transit to s_error now;
+--                           rename stat flags: [cd]crc->[cd]err, ioto->rbnak,
+--                           ioerr->rberr; '111' cmd now aborts via s_txnak and
+--                           sets cerr flag; set [cd]err on eop/nak aborts;
+-- 2010-12-04   343   3.0    renamed rri_ -> rlink_; rbus V3 interface: use now
+--                           aval,re,we; add new states: s_rstart, s_wstart
 -- 2010-06-20   308   2.6    use rbinit,rbreq,rbwe state flops to drive rb_mreq;
 --                           now nak on reserved cmd 111; use do_comma_abort();
 -- 2010-06-18   306   2.5.1  rename rbus data fields to _rbf_
@@ -81,59 +90,74 @@
 --        rx: cmd addr ccrc
 --        tx: cmd dl dh stat crc
 --       seq: _rxcmd _rxaddr _rxccrc (_txcmd|_txnak)
---            _rreg _txdatl _txdath _txstat _txcrc (_rxcmd|_idle)
+--            _rstart _rreg _txdatl _txdath _txstat _txcrc -> _rxcmd
 --
 --   001 read blk (rblk):
 --        rx: cmd addr cnt ccrc
 --        tx: cmd cnt dl dh ... stat crc
 --       seq: _rxcmd _rxaddr _rxcnt _rxccrc (_txcmd|_txnak) _txcnt
---            {_rreg _txdatl _txdath _blk}* _txstat _txcrc (_rxcmd|_idle)
+--            {_rstart _rreg _txdatl _txdath _blk}*
+--            _txstat _txcrc -> _rxcmd
 --
 --   010 write reg (wreg):
 --        rx: cmd addr dl dh ccrc
 --        tx: cmd stat crc
 --       seq: _rxcmd _rxaddr _rxdatl _rxdath _rxccrc (_txcmd|_txnak)
---       seq: _wreg _txstat _txcrc  (_rxcmd|_idle)
+--            _wstart _wreg _txstat _txcrc -> _rxcmd
 --
 --   011 write blk (wblk):
 --        rx: cmd addr cnt ccrc dl dh ... dcrc
 --        tx: cmd stat crc
 --       seq: _rxcmd _rxaddr _rxcnt _rxccrc (_txcmd|_txnak)
---           {_rxdatl _rxdath _wreg _blk}* _rxdcrc _txstat _txcrc (_rxcmd|_idle)
+--            {_rxdatl _rxdath _wstart _wreg _blk}*
+--            _rxdcrc _txstat _txcrc -> (_rxcmd|_txnak)
 --
 --   100 read stat (stat):
 --        rx: cmd ccrc
 --        tx: cmd ccmd dl dh stat crc
 --       seq: _rxcmd _rxccrc (_txcmd|_txnak)
---            _txccmd _txdatl _txdath _txstat _txcrc (_rxcmd|_idle)
+--            _txccmd _txdatl _txdath _txstat _txcrc -> _rxcmd
 --
 --   101 read attn (attn):
 --        rx: cmd ccrc
 --        tx: cmd dl dh stat crc
 --       seq: _rxcmd _rxccrc (_txcmd|_txnak)
---            _attn _txdatl _txdath _txstat _txcrc (_rxcmd|_idle)
+--            _attn _txdatl _txdath _txstat _txcrc -> _rxcmd
 --
 --   110 write init (init):
 --        rx: cmd addr dl dh ccrc
 --        tx: cmd stat crc
 --       seq: _rxcmd _rxaddr _rxdatl _rxdath _rxccrc (_txcmd|_txnak)
---       seq: _txstat _txcrc  (_rxcmd|_idle)
+--            _txstat _txcrc -> _rxcmd
 --       like wreg, but no rp_we - rp_hold, just a 1 cycle rp_init pulse
 --
 --   111 is currently not a legal command and causes a nak
 --       seq: _txnak
 --
+-- The state bits nakcerr and nakderr determine whether cerr/derr is set
+-- when s_txnak is entered. cerr is '1' during command receive, derr is '1'
+-- during data wblk data receive phase:
+--   nakcerr set in s_rxcmd  (when command received, unless it's stat)
+--           clr in s_txcmd  (when wblk)
+--           clr in s_txnak
+--           clr in s_txcrc  (for sucessful completion)
+--   nakderr set in s_txcmd  (when wblk)
+--           clr in s_txnak
+--           clr in s_txcrc  (for sucessful completion)
+--
 -- The different rbus cycle types are encoded as:
 --
---        init ack  we
---          0    0   0   idle
---          0    0   1   idle
---          0    1   0   read 
---          0    1   1   write
---          1    0   0   internal init
---          1    0   1   external init
---          1    1   0   not allowed
---          1    1   1   not allowed
+--        init aval re we
+--          0    0   0  0   idle
+--          0    0   1  0   not allowed
+--          0    0   0  1   not allowed
+--          0    1   1  0   read 
+--          0    1   0  1   write
+--          1    0   0  0   internal init
+--          1    0   0  1   external init
+--          1    0   1  0   not allowed
+--          *    *   1  1   not allowed
+--          1    1   *  *   not allowed
 --
 
 library ieee;
@@ -142,9 +166,10 @@ use ieee.std_logic_arith.all;
 
 use work.slvtypes.all;
 use work.comlib.all;
-use work.rrilib.all;
+use work.rblib.all;
+use work.rlinklib.all;
 
-entity rri_core is                      -- rri, core interface
+entity rlink_core is                    -- rlink core with 9bit interface
   generic (
     ATOWIDTH : positive :=  5;          -- access timeout counter width
     ITOWIDTH : positive :=  6);         -- idle timeout counter width
@@ -152,22 +177,22 @@ entity rri_core is                      -- rri, core interface
     CLK  : in slbit;                    -- clock      
     CE_INT : in slbit := '0';           -- rri ito time unit clock enable
     RESET  : in slbit;                  -- reset
-    CP_DI : in slv9;                    -- comm port: data in
-    CP_ENA : in slbit;                  -- comm port: data enable
-    CP_BUSY : out slbit;                -- comm port: data busy
-    CP_DO : out slv9;                   -- comm port: data out
-    CP_VAL : out slbit;                 -- comm port: data valid
-    CP_HOLD : in slbit;                 -- comm port: data hold
-    CP_FLUSH : out slbit;               -- comm port: data flush
+    RL_DI : in slv9;                    -- rlink 9b: data in
+    RL_ENA : in slbit;                  -- rlink 9b: data enable
+    RL_BUSY : out slbit;                -- rlink 9b: data busy
+    RL_DO : out slv9;                   -- rlink 9b: data out
+    RL_VAL : out slbit;                 -- rlink 9b: data valid
+    RL_HOLD : in slbit;                 -- rlink 9b: data hold
+    RL_MONI : out rl_moni_type;         -- rlink: monitor port
     RB_MREQ : out rb_mreq_type;         -- rbus: request
     RB_SRES : in rb_sres_type;          -- rbus: response
     RB_LAM : in slv16;                  -- rbus: look at me
     RB_STAT : in slv3                   -- rbus: status flags
   );
-end entity rri_core;  
+end entity rlink_core;  
 
 
-architecture syn of rri_core is
+architecture syn of rlink_core is
 
   type state_type is (
     s_idle,                             -- s_idle: wait for sop
@@ -184,10 +209,12 @@ architecture syn of rri_core is
     s_rxccrc,                           -- s_rxccrc: wait for command crc
     s_txcmd,                            -- s_txcmd: send cmd
     s_txcnt,                            -- s_txcnt: send cnt
-    s_rreg,                             -- s_rreg: reg or blk read
+    s_rstart,                           -- s_rstart: start reg or blk read
+    s_rreg,                             -- s_rreg:   do reg or blk read
     s_txdatl,                           -- s_txdatl: send data low
     s_txdath,                           -- s_txdath: send data high
-    s_wreg,                             -- s_wreg: reg or blk write
+    s_wstart,                           -- s_wstart: start reg or blk write
+    s_wreg,                             -- s_wreg:   do reg or blk write
     s_blk,                              -- s_blk: block count handling
     s_rxdcrc,                           -- s_rxdcrc: wait for data crc
     s_attn,                             -- s_attn: handle attention flags
@@ -213,15 +240,20 @@ architecture syn of rri_core is
     itoena : slbit;                     -- idle timeout enable flag
     anena : slbit;                      -- attn notification enable flag
     andone : slbit;                     -- attn notification done
-    ccrc : slbit;                       -- stat: command crc error
-    dcrc : slbit;                       -- stat: data crc error
-    ioto : slbit;                       -- stat: i/o time out
-    ioerr : slbit;                      -- stat: i/o time error
+    cerr : slbit;                       -- stat: command error
+    derr : slbit;                       -- stat: data error
+    rbnak: slbit;                       -- stat: rbus no ack or timeout
+    rberr : slbit;                      -- stat: rbus err bit set
     nakeop : slbit;                     -- send eop after nak
+    nakcerr : slbit;                    -- set cerr after nak
+    nakderr : slbit;                    -- set derr after nak
     rbinit : slbit;                     -- rbus init signal
-    rbreq : slbit;                      -- rbus req signal
+    rbaval : slbit;                     -- rbus aval signal
+    rbre : slbit;                       -- rbus re signal
     rbwe : slbit;                       -- rbus we signal
-    flush : slbit;                      -- flush pulse
+    moneop : slbit;                     -- rl_moni: eop send pulse
+    monattn : slbit;                    -- rl_moni: attn send pulse
+    monlamp : slbit;                    -- rl_moni: attn pending state
     stat : slv3;                        -- external status flags
   end record regs_type;
 
@@ -251,9 +283,9 @@ architecture syn of rri_core is
     '0',                                -- itoena
     '0','0',                            -- anena, andone
     '0','0','0','0',                    -- stat flags
-    '0',                                -- nakeop
-    '0','0','0',                        -- rbinit,rbreq,rbwe
-    '0',                                -- flush
+    '0','0','0',                        -- nakeop,nakcerr,nakderr
+    '0','0','0','0',                    -- rbinit,rbaval,rbre,rbwe
+    '0','0','0',                        -- moneop,monattn,monlamp
     (others=>'0')                       -- stat
   );
 
@@ -278,7 +310,7 @@ begin
     CLK   => CLK,
     RESET => CRC_RESET,
     ENA   => ICRC_ENA,
-    DI    => CP_DI(7 downto 0),
+    DI    => RL_DI(7 downto 0),
     CRC   => ICRC_OUT
   );
 
@@ -304,7 +336,7 @@ begin
 
   end process proc_regs;
 
-  proc_next: process (R_REGS, CE_INT, CP_DI, CP_ENA, CP_HOLD, RB_LAM,
+  proc_next: process (R_REGS, CE_INT, RL_DI, RL_ENA, RL_HOLD, RB_LAM,
                       RB_SRES, RB_STAT, ICRC_OUT, OCRC_OUT)
 
     variable r : regs_type := regs_init;
@@ -321,6 +353,7 @@ begin
     variable icrcena : slbit := '0';
     variable ocrcena : slbit := '0';
     variable has_attn : slbit := '0';
+    variable snd_attn : slbit := '0';
     variable idi8 : slv8 := (others=>'0');
     variable is_comma : slbit := '0';
     variable comma_typ : slv4 := "0000";
@@ -342,15 +375,18 @@ begin
     r := R_REGS;
     n := R_REGS;
 
-    idi8      := CP_DI(7 downto 0);     -- get data part of CP_DI
-    is_comma  := CP_DI(8);              -- get comma marker
-    comma_typ := CP_DI(3 downto 0);     -- get comma type
+    idi8      := RL_DI(7 downto 0);     -- get data part of RL_DI
+    is_comma  := RL_DI(8);              -- get comma marker
+    comma_typ := RL_DI(3 downto 0);     -- get comma type
 
-    n.rbinit  := '0';                   -- clear rbinit,rbreq,rbwe by default
-    n.rbreq   := '0';                   --   they must always be set by the
-    n.rbwe    := '0';                   --   'previous state'
+    n.rbinit  := '0';                   -- clear rb(init|aval|re|we) by default
+    n.rbaval  := '0';                   --   they must always be set by the
+    n.rbre    := '0';                   --   'previous state'
+    n.rbwe    := '0';                   -- 
     
-    n.flush   := '0';                   -- dito for flush
+    n.moneop  := '0';                   -- default '0', only set by states
+    n.monattn := '0';                   -- "
+    n.monlamp := '0';                   -- 
 
     ibusy := '1';                       -- default is to hold input
     ival := '0';
@@ -367,10 +403,16 @@ begin
     end loop;
 
     has_attn := '0';
-    if unsigned(r.attn) /= 0 then       -- is any of the attn bits set ?
-      has_attn := '1';
-    end if;
+    snd_attn := '0';
     
+    if unsigned(r.attn) /= 0 then       -- is any of the attn bits set ?
+      has_attn  := '1';
+      if r.anena='1' and r.andone='0' then -- is attn notification to be send ?
+        snd_attn := '1';
+        n.monlamp := '1';                    -- set lamp flag in rl_moni
+      end if;
+    end if;
+
     ato_go := '0';                      -- default: keep access timeout in reset
     ato_end := '0';
     if unsigned(r.atocnt) = 0 then      -- if access timeout count at zero
@@ -386,12 +428,11 @@ begin
     case r.state is
       when s_idle =>                    -- s_idle: wait for sop --------------
         ito_go := '1';                    -- idle timeout active
-        if (r.anena='1' and               -- if attn notification to send
-            has_attn='1' and r.andone='0') then
-            n.state := s_txito;           -- next send ito byte
+        if snd_attn = '1' then            -- if attn notification to be send
+          n.state := s_txito;               -- next: send ito byte
         else
           ibusy := '0';                   -- accept input
-          if CP_ENA = '1' then            -- if input
+          if RL_ENA = '1' then            -- if input
             if is_comma = '1' then          -- if comma
               case comma_typ is
                 when c_sop =>                 -- if sop
@@ -399,7 +440,7 @@ begin
                   n.state := s_txsop;           -- next: echo it
                 when c_eop =>                 -- if eop (unexpected)
                   n.nakeop := '1';              -- send nak,eop
-                  n.state  := s_txnak;          -- next: send nak
+                  n.state   := s_txnak;         -- next: send nak
                 when c_attn =>                -- if attn
                   n.state := s_txito;           -- next: send ito byte
                 when others => null;          -- other commas: silently ignore
@@ -415,29 +456,38 @@ begin
           
       when s_txito =>                   -- s_txito: send timeout symbol ------
         if has_attn = '1' then              
-          ido := c_rri_dat_attn;          -- if attn pending: send attn symbol
+          ido := c_rlink_dat_attn;        -- if attn pending: send attn symbol
           n.andone := '1';
         else
-          ido := c_rri_dat_idle;          -- otherwise: send idle symbol
+          ido := c_rlink_dat_idle;        -- otherwise: send idle symbol
         end if;
         ival := '1';
-        if CP_HOLD = '0' then             -- wait for accept
-          n.state := s_idle;              -- next: wait for sop
+        if RL_HOLD = '0' then             -- wait for accept
+          n.monattn := has_attn;            -- signal on rl_moni
+          n.state := s_idle;                -- next: wait for sop
         end if;
 
       when s_txsop =>                   -- s_txsop: send sop -----------------
-        ido := c_rri_dat_sop;             -- send sop character
+        ido := c_rlink_dat_sop;           -- send sop character
         ival := '1';
-        if CP_HOLD = '0' then             -- wait for accept
+        if RL_HOLD = '0' then             -- wait for accept
           n.state := s_rxcmd;             -- next: read first command
         end if;
         
       when s_txnak =>                   -- s_txnak: send nak -----------------
-        ido := c_rri_dat_nak;             -- send nak character
+        ido := c_rlink_dat_nak;           -- send nak character
         ival := '1';
-        if CP_HOLD = '0' then             -- wait for accept
-          n.nakeop := '0';
-          if r.nakeop = '1' then            -- if eop after nak requested
+        if RL_HOLD = '0' then             -- wait for accept
+          n.nakeop  := '0';               -- clear all 'do on nak' state flags
+          n.nakcerr := '0';
+          n.nakderr := '0';
+          if r.nakcerr = '1' then         -- if setting cerr requested
+            n.cerr := '1';                  -- do it
+          end if;
+          if r.nakderr = '1' then         -- if settung derr requested
+            n.derr := '1';                  -- do it
+          end if;
+          if r.nakeop = '1' then           -- if eop after nak requested
             n.state := s_txeop;             -- next: send eop
           else
             n.state := s_error;             -- next: error state, wait for eop
@@ -445,16 +495,16 @@ begin
         end if;
         
       when s_txeop =>                   -- s_txeop: send eop -----------------
-        ido := c_rri_dat_eop;             -- send eop character
+        ido := c_rlink_dat_eop;           -- send eop character
         ival := '1';
-        if CP_HOLD = '0' then             -- wait for accept
-          n.flush := '1';                   -- send flush pulse 
+        if RL_HOLD = '0' then             -- wait for accept
+          n.moneop := '1';                  -- signal on rl_moni
           n.state := s_idle;                -- next: idle state, wait for sop
         end if;
         
       when s_error =>                   -- s_error: wait for eop -------------
         ibusy := '0';                     -- accept input
-        if CP_ENA = '1' then
+        if RL_ENA = '1' then
           if is_comma = '1' then          -- if comma
             case comma_typ is
               when c_sop =>                 -- if sop (unexpected)
@@ -472,7 +522,7 @@ begin
 
       when s_rxcmd =>                   -- s_rxcmd: wait for cmd -------------
         ibusy := '0';                     -- accept input
-        if CP_ENA = '1' then
+        if RL_ENA = '1' then
           if is_comma = '1' then          -- if comma
             case comma_typ is
               when c_sop =>                 -- if sop (unexpected)
@@ -483,44 +533,52 @@ begin
                 n.state  := s_txnak;          -- next: echo nak
               when others => null;          --other commas: silently ignore
             end case;
-          else
-            icrcena  := '1';              -- update input crc
-            n.rcmd := idi8;               -- latch read command code
-            case CP_DI(c_rri_cmd_rbf_code) is
-              when c_rri_cmd_rreg | c_rri_cmd_rblk |
-                   c_rri_cmd_wreg | c_rri_cmd_wblk |
-                   c_rri_cmd_init =>      -- for commands needing addr(data)
-                n.state := s_rxaddr;      -- next: read address
-              when c_rri_cmd_stat | c_rri_cmd_attn => -- stat and attn commands
-                n.state := s_rxccrc;      -- next: read command crc
+          else                            -- if not comma
+            icrcena   := '1';               -- update input crc
+            n.rcmd    := idi8;              -- latch received command code
+                                            -- unless the command is stat
+            if RL_DI(c_rlink_cmd_rbf_code) /= c_rlink_cmd_stat then 
+              n.nakcerr := '1';               -- set cerr on eop/nak abort
+            end if;
+            case RL_DI(c_rlink_cmd_rbf_code) is
+              when c_rlink_cmd_rreg |
+                   c_rlink_cmd_rblk |
+                   c_rlink_cmd_wreg |
+                   c_rlink_cmd_wblk |
+                   c_rlink_cmd_init =>      -- for commands needing addr(data)
+                n.state := s_rxaddr;          -- next: read address
+              when c_rlink_cmd_stat |
+                   c_rlink_cmd_attn =>      -- stat and attn commands
+                n.state := s_rxccrc;          -- next: read command crc
               when others =>
-                n.state := s_idle;        -- if bad command abort here
+                n.state := s_txnak;           -- next: send nak
             end case;                     -- rcmd,ccmd always hold good cmd 
           end if;
         end if;
         
       when s_rxaddr =>                  -- s_rxaddr: wait for addr -----------
         ibusy := '0';                     -- accept input
-        if CP_ENA = '1' then
+        if RL_ENA = '1' then
           if is_comma = '1' then          -- if comma
             do_comma_abort(n.state, n.nakeop, comma_typ);
           else
             icrcena  := '1';              -- update input crc
             n.addr := idi8;               -- latch read address
-            case r.rcmd(c_rri_cmd_rbf_code) is
-              when c_rri_cmd_rreg =>      -- for rreg command
-                n.state := s_rxccrc;      -- next: read command crc
-              when c_rri_cmd_wreg | c_rri_cmd_init => -- for wreg, init command
-                n.state := s_rxdatl;      -- next: read data lsb
-              when others =>              -- for rblk or wblk
-                n.state := s_rxcnt;       -- next: read count
+            case r.rcmd(c_rlink_cmd_rbf_code) is
+              when c_rlink_cmd_rreg =>      -- for rreg command
+                n.state := s_rxccrc;          -- next: read command crc
+              when c_rlink_cmd_wreg |
+                   c_rlink_cmd_init =>      -- for wreg, init command
+                n.state := s_rxdatl;          -- next: read data lsb
+              when others =>                -- for rblk or wblk
+                n.state := s_rxcnt;           -- next: read count
             end case;
           end if;
         end if;
         
       when s_rxdatl =>                  -- s_rxdatl: wait for data low -------
         ibusy := '0';                     -- accept input
-        if CP_ENA = '1' then
+        if RL_ENA = '1' then
           if is_comma = '1' then          -- if comma 
             do_comma_abort(n.state, n.nakeop, comma_typ);
          else
@@ -532,16 +590,15 @@ begin
         
       when s_rxdath =>                  -- s_rxdath: wait for data high ------
         ibusy := '0';                     -- accept input
-        if CP_ENA = '1' then
+        if RL_ENA = '1' then
           if is_comma = '1' then          -- if comma
             do_comma_abort(n.state, n.nakeop, comma_typ);
           else
             icrcena  := '1';              -- update input crc
             n.dih := idi8;                -- latch data msb part
-            if r.rcmd(c_rri_cmd_rbf_code) = c_rri_cmd_wblk then  -- if wblk
-              n.rbreq := '1';
-              n.rbwe  := '1';
-              n.state := s_wreg;            -- next: write reg
+            if r.rcmd(c_rlink_cmd_rbf_code) = c_rlink_cmd_wblk then  -- if wblk
+              n.rbaval := '1';              -- prepare rbus cycle
+              n.state  := s_wstart;         -- next: start write reg
            else                           -- otherwise
              n.state := s_rxccrc;         -- next: read command crc
            end if;
@@ -550,7 +607,7 @@ begin
         
       when s_rxcnt =>                   -- s_rxcnt: wait for count -----------
         ibusy := '0';                     -- accept input
-        if CP_ENA = '1' then
+        if RL_ENA = '1' then
           if is_comma = '1' then            -- if comma
             do_comma_abort(n.state, n.nakeop, comma_typ);
           else
@@ -562,12 +619,15 @@ begin
 
       when s_rxccrc =>                  -- s_rxccrc: wait for command crc ----
         ibusy := '0';                     -- accept input
-        if CP_ENA = '1' then
+        if RL_ENA = '1' then
           if is_comma = '1' then            -- if comma
             do_comma_abort(n.state, n.nakeop, comma_typ);
           else
             if idi8 /= ICRC_OUT then        -- if crc error
-              n.ccrc := '1';                  -- set command crc error flag
+                                              -- unless the command is stat
+              if r.rcmd(c_rlink_cmd_rbf_code) /= c_rlink_cmd_stat then
+                n.cerr := '1';                   -- set command error flag
+              end if;
               n.state  := s_txnak;            -- next: send nak
             else                            -- if crc ok
               n.state := s_txcmd;             -- next: echo command
@@ -578,39 +638,41 @@ begin
       when s_txcmd =>                   -- s_txcmd: send cmd -----------------
         ido := '0' & r.rcmd;              -- send read command
         ival := '1';
-        if CP_HOLD = '0' then             -- wait for accept
+        if RL_HOLD = '0' then             -- wait for accept
           ocrcena  := '1';                  -- update output crc
-          if r.rcmd(c_rri_cmd_rbf_code) /= c_rri_cmd_stat then -- unless stat
-            n.ccmd := r.rcmd;                 -- latch read command in ccmd
-            n.stat := RB_STAT;                -- latch external status bits
-            n.ccrc := '0';
-            n.dcrc := '0';
-            n.ioto := '0';
-            n.ioerr := '0';
+          if r.rcmd(c_rlink_cmd_rbf_code) /= c_rlink_cmd_stat then --unless stat
+            n.ccmd  := r.rcmd;                -- latch current command in ccmd
+            n.stat  := RB_STAT;               -- latch external status bits
+            n.cerr  := '0';
+            n.derr  := '0';
+            n.rbnak := '0';
+            n.rberr := '0';
           end if;
-          case r.rcmd(c_rri_cmd_rbf_code) is -- main command dispatcher
-            when c_rri_cmd_rreg  =>           -- rreg ----------------
-              n.rbreq := '1';
-              n.state := s_rreg; 
-            when c_rri_cmd_rblk =>            -- rblk ----------------
+          n.nakcerr := '0';                 -- all command rx done up to here
+
+          case r.rcmd(c_rlink_cmd_rbf_code) is -- main command dispatcher
+            when c_rlink_cmd_rreg  =>          -- rreg ----------------
+              n.rbaval := '1';                   -- prepare rbus cycle
+              n.state := s_rstart;               -- next: start read reg
+            when c_rlink_cmd_rblk =>           -- rblk ----------------
               n.state := s_txcnt; 
-            when c_rri_cmd_wreg =>            -- wreg ----------------
-              n.rbreq := '1';
-              n.rbwe  := '1';
-              n.state := s_wreg;
-            when c_rri_cmd_wblk =>            -- wblk ----------------
+            when c_rlink_cmd_wreg =>           -- wreg ----------------
+              n.rbaval := '1';                   -- prepare rbus cycle
+              n.state := s_wstart;               -- next: start write reg
+            when c_rlink_cmd_wblk =>           -- wblk ----------------
+              n.nakderr := '1';                  -- set derr on eop/nak abort
               n.state := s_rxdatl;
-            when c_rri_cmd_stat =>            -- stat ----------------
+            when c_rlink_cmd_stat =>           -- stat ----------------
               n.state := s_txccmd;
-            when c_rri_cmd_attn =>            -- attn ----------------
+            when c_rlink_cmd_attn =>           -- attn ----------------
               n.state := s_attn;
               
-            when c_rri_cmd_init =>            -- init ----------------
+            when c_rlink_cmd_init =>           -- init ----------------
               n.rbinit := '1';                   -- send init pulse
               if r.addr(7 downto 3) = "11111" then   -- is internal init
                 if r.addr(2 downto 0) = "111" then     -- is rri init 
-                  n.anena  := r.dih(c_rri_iint_rbf_anena  - 8);
-                  n.itoena := r.dih(c_rri_iint_rbf_itoena - 8);
+                  n.anena  := r.dih(c_rlink_iint_rbf_anena  - 8);
+                  n.itoena := r.dih(c_rlink_iint_rbf_itoena - 8);
                   n.itoval := r.dil(ITOWIDTH-1 downto 0);
                                             -- note: itocnt will load in next
                                             -- cycle because ito_go=0, so no
@@ -630,37 +692,42 @@ begin
       when s_txcnt =>                   -- s_txcnt: send cnt -----------------
         ido := '0' & r.cnt;               -- send cnt
         ival := '1';
-        if CP_HOLD = '0' then             -- wait for accept
-          ocrcena := '1';                 -- update output crc
-          n.rbreq := '1';
-          n.state := s_rreg;              -- next: first read reg
+        if RL_HOLD = '0' then             -- wait for accept
+          ocrcena  := '1';                  -- update output crc
+          n.rbaval := '1';                  -- prepare rbus cycle
+          n.state  := s_rstart;             -- next: start first read reg
         end if;
 
-      when s_rreg =>                    -- s_rreg: reg or blk read -----------
-        -- this state handles all rbus reads. Expects that previous state
-        -- sets n.rbreq := '1' to start an rbus read cycle
+      when s_rstart =>                  -- s_rstart: start reg or blk read ---
+        n.rbaval := '1';                  -- start actual read cycle
+        n.rbre   := '1';
+        n.state  := s_rreg;               -- next: reg read 
+
+      when s_rreg =>                    -- s_rreg: do reg or blk read --------
+        -- this state handles all rbus reads
         ato_go := '1';                    -- activate timeout counter
-        if RB_SRES.err = '1' then         -- latch error flag
-          n.ioerr := '1';
+        if RB_SRES.err = '1' then         -- latch rbus error flag
+          n.rberr := '1';
         end if;
         n.doh := RB_SRES.dout(15 downto 8); -- latch data
         n.dol := RB_SRES.dout( 7 downto 0);
         n.stat := RB_STAT;                -- latch external status bits
         if RB_SRES.busy='0' or ato_end='1' then -- wait for non-busy or timeout
           if RB_SRES.busy='1' and ato_end='1' then -- if timeout and still busy
-            n.ioto := '1';                    -- set timeout flag
+            n.rbnak := '1';                   -- set rbus nak flag
           elsif RB_SRES.ack = '0' then      -- if non-busy and no ack
-            n.ioto := '1';                    -- set timeout flag            
+            n.rbnak := '1';                    -- set rbus nak flag            
           end if;
           n.state := s_txdatl;              -- next: send data lsb
         else                              -- otherwise rbus read continues
-          n.rbreq := '1';                   -- extend req
+          n.rbaval := '1';                  -- extend cycle
+          n.rbre   := '1';
         end if;
-
+    
       when s_txdatl =>                  -- s_txdatl: send data low -----------
         ido := '0' & r.dol;               -- send data
         ival := '1';
-        if CP_HOLD = '0' then             -- wait for accept
+        if RL_HOLD = '0' then             -- wait for accept
           ocrcena  := '1';                -- update output crc
           n.state := s_txdath;            -- next: send data msb
         end if;
@@ -668,65 +735,69 @@ begin
       when s_txdath =>                  -- s_txdath: send data high
         ido := '0' & r.doh;               -- send data
         ival := '1';
-        if CP_HOLD = '0' then             -- wait for accept
+        if RL_HOLD = '0' then             -- wait for accept
           ocrcena  := '1';                -- update output crc
-          if r.rcmd(c_rri_cmd_rbf_code) = c_rri_cmd_rblk then -- if rblk
+          if r.rcmd(c_rlink_cmd_rbf_code) = c_rlink_cmd_rblk then -- if rblk
             n.state := s_blk;             -- next: block count handling
           else                            -- otherwise
             n.state := s_txstat;          -- next: send stat
           end if;
         end if;
         
-      when s_wreg =>                    -- s_wreg: reg or blk write ----------
-        -- this state handles all rbus writes. Expects that previous state
-        -- sets n.rbreq := '1' and n.rbwe := '1' to start an rbus write cycle
+      when s_wstart =>                  -- s_wstart: start reg or blk write --
+        n.rbaval := '1';                  -- start actual write cycle
+        n.rbwe   := '1';
+        n.state  := s_wreg;               -- next: reg write 
+        
+      when s_wreg =>                    -- s_wreg: do reg or blk write -------
+        -- this state handles all rbus writes
         ato_go := '1';                    -- activate timeout counter
-        if RB_SRES.err = '1' then         -- latch error flag
-          n.ioerr := '1';
+        if RB_SRES.err = '1' then         -- latch rbus error flag
+          n.rberr := '1';
         end if;
         n.stat := RB_STAT;                -- latch external status bits
         if RB_SRES.busy='0' or ato_end='1' then -- wait for non-busy or timeout
           if RB_SRES.busy='1' and ato_end='1' then -- if timeout and still busy
-            n.ioto := '1';                    -- set timeout flag
+            n.rbnak := '1';                    -- set rbus nak flag
           elsif RB_SRES.ack='0' then        -- if non-busy and no ack
-            n.ioto := '1';                    -- set timeout flag            
+            n.rbnak := '1';                    -- set rbus nak flag            
           end if;
-          if r.rcmd(c_rri_cmd_rbf_code) = c_rri_cmd_wblk then   -- if wblk
+          if r.rcmd(c_rlink_cmd_rbf_code) = c_rlink_cmd_wblk then   -- if wblk
             n.state := s_blk;               -- next: block count handling
           else                              -- otherwise
             n.state := s_txstat;            -- next: send stat
           end if;
         else                              -- otherwise rbus write continues
-          n.rbreq := '1';                   -- extend req
-          n.rbwe  := '1';                   -- extend we
+          n.rbaval := '1';                  -- extend cycle
+          n.rbwe   := '1';
         end if;
           
       when s_blk =>                     -- s_blk: block count handling -------
         n.cnt := unsigned(r.cnt) - 1;     -- decrement transfer count
         if unsigned(r.cnt) = 0 then       -- if last transfer 
-          if r.rcmd(c_rri_cmd_rbf_code) = c_rri_cmd_rblk then -- if rblk
+          if r.rcmd(c_rlink_cmd_rbf_code) = c_rlink_cmd_rblk then -- if rblk
             n.state := s_txstat;          -- next: send stat
           else                            -- otherwise
             n.state := s_rxdcrc;          -- next: read data crc
           end if;
 
         else                              -- otherwise more to transfer
-          if r.rcmd(c_rri_cmd_rbf_code) = c_rri_cmd_rblk then   -- if rblk
-            n.rbreq := '1';
-            n.state := s_rreg;            -- next: read blk
+          if r.rcmd(c_rlink_cmd_rbf_code) = c_rlink_cmd_rblk then   -- if rblk
+            n.rbaval := '1';                -- prepare rbus cycle
+            n.state := s_rstart;            -- next: start read blk
           else                            -- otherwise
-            n.state := s_rxdatl;          -- next: read data
+            n.state := s_rxdatl;            -- next: read data
           end if;
         end if;
         
       when s_rxdcrc =>                  -- s_rxdcrc: wait for data crc -------
         ibusy := '0';                     -- accept input
-        if CP_ENA = '1' then
+        if RL_ENA = '1' then
           if is_comma = '1' then            -- if comma
             do_comma_abort(n.state, n.nakeop, comma_typ);
           else
             if idi8 /= ICRC_OUT then        -- if crc error
-              n.dcrc := '1';                  -- set data crc error flag
+              n.derr := '1';                  -- set data error flag
             end if;
             n.state := s_txstat;          -- next: echo command
           end if;
@@ -742,21 +813,21 @@ begin
       when s_txccmd =>                  -- s_txccmd: send last command
         ido := '0' & r.ccmd;              -- send last accepted command
         ival := '1';
-        if CP_HOLD = '0' then             -- wait for accept
+        if RL_HOLD = '0' then             -- wait for accept
           ocrcena  := '1';                -- update output crc
           n.state := s_txdatl;            -- next: send last data lsb
         end if;
         
       when s_txstat =>                  -- s_txstat: send status -------------
         ido := (others=>'0');
-        ido(c_rri_stat_rbf_stat)  := r.stat;
-        ido(c_rri_stat_rbf_attn)  := has_attn;
-        ido(c_rri_stat_rbf_ccrc)  := r.ccrc;
-        ido(c_rri_stat_rbf_dcrc)  := r.dcrc;
-        ido(c_rri_stat_rbf_ioto)  := r.ioto;
-        ido(c_rri_stat_rbf_ioerr) := r.ioerr;
+        ido(c_rlink_stat_rbf_stat)  := r.stat;
+        ido(c_rlink_stat_rbf_attn)  := has_attn;
+        ido(c_rlink_stat_rbf_cerr)  := r.cerr;
+        ido(c_rlink_stat_rbf_derr)  := r.derr;
+        ido(c_rlink_stat_rbf_rbnak) := r.rbnak;
+        ido(c_rlink_stat_rbf_rberr) := r.rberr;
         ival := '1';
-        if CP_HOLD  ='0' then             -- wait for accept
+        if RL_HOLD  ='0' then             -- wait for accept
           ocrcena  := '1';                -- update output crc
           n.state := s_txcrc;             -- next: send crc
         end if;
@@ -764,8 +835,15 @@ begin
       when s_txcrc =>                   -- s_txcrc: send crc -----------------
         ido := "0" & OCRC_OUT;            -- send crc code
         ival := '1';
-        if CP_HOLD = '0' then             -- wait for accept
-          n.state := s_rxcmd;                -- next: read command or eop
+        if RL_HOLD = '0' then             -- wait for accept
+                                            -- if dcrc seen in wblk
+          if r.rcmd(c_rlink_cmd_rbf_code)=c_rlink_cmd_wblk and r.derr='1' then
+            n.state := s_txnak;             -- next: send nak
+          else                            -- otherwise
+            n.nakcerr := '0';               -- clear 'set on nak' requests
+            n.nakderr := '0';
+            n.state := s_rxcmd;             -- next: read command or eop
+          end if;
         end if;
         
       when others => null;              -- <> --------------------------------
@@ -787,13 +865,17 @@ begin
     
     N_REGS <= n;
 
-    CP_BUSY  <= ibusy;
-    CP_DO    <= ido;
-    CP_VAL   <= ival;
-    CP_FLUSH <= r.flush;
+    RL_BUSY  <= ibusy;
+    RL_DO    <= ido;
+    RL_VAL   <= ival;
+
+    RL_MONI.eop  <= r.moneop;
+    RL_MONI.attn <= r.monattn;
+    RL_MONI.lamp <= r.monlamp;
     
     RB_MREQ      <= rb_mreq_init;
-    RB_MREQ.req  <= r.rbreq;
+    RB_MREQ.aval <= r.rbaval;
+    RB_MREQ.re   <= r.rbre;
     RB_MREQ.we   <= r.rbwe;
     RB_MREQ.init <= r.rbinit;
     RB_MREQ.addr <= r.addr;
diff --git a/rtl/vlib/rlink/rlink_mon.vbom b/rtl/vlib/rlink/rlink_mon.vbom
new file mode 100644
index 00000000..5d7c87c2
--- /dev/null
+++ b/rtl/vlib/rlink/rlink_mon.vbom
@@ -0,0 +1,7 @@
+# libs
+../slvtypes.vhd
+../simlib/simlib.vhd
+rlinklib.vbom
+# components
+# design
+rlink_mon.vhd
diff --git a/rtl/vlib/rri/tb/rritb_cpmon.vhd b/rtl/vlib/rlink/rlink_mon.vhd
similarity index 69%
rename from rtl/vlib/rri/tb/rritb_cpmon.vhd
rename to rtl/vlib/rlink/rlink_mon.vhd
index 138782a3..a994c70f 100644
--- a/rtl/vlib/rri/tb/rritb_cpmon.vhd
+++ b/rtl/vlib/rlink/rlink_mon.vhd
@@ -1,4 +1,4 @@
--- $Id: rritb_cpmon.vhd 314 2010-07-09 17:38:41Z mueller $
+-- $Id: rlink_mon.vhd 348 2010-12-26 15:23:44Z mueller $
 --
 -- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -12,14 +12,17 @@
 -- for complete details.
 --
 ------------------------------------------------------------------------------
--- Module Name:    rritb_cpmon - sim
--- Description:    rritb: rri comm port monitor
+-- Module Name:    rlink_mon - sim
+-- Description:    rlink monitor (for tb's)
 --
 -- Dependencies:   -
 -- Test bench:     -
--- Tool versions:  xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+-- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
+--
 -- Revision History: 
 -- Date         Rev Version  Comment
+-- 2010-12-24   347   3.0.1  rename: CP_*->RL->*
+-- 2010-12-22   346   3.0    renamed rritb_cpmon -> rlink_mon
 -- 2010-06-11   303   2.5.1  fix data9 assignment, always proper width now
 -- 2010-06-07   302   2.5    use sop/eop framing instead of soc+chaining
 -- 2008-03-24   129   1.0.1  CLK_CYCLE now 31 bits
@@ -34,33 +37,33 @@ use std.textio.all;
 
 use work.slvtypes.all;
 use work.simlib.all;
-use work.rrilib.all;
+use work.rlinklib.all;
 
-entity rritb_cpmon is                   -- rritb, rri comm port monitor
+entity rlink_mon is                     -- rlink monitor
   generic (
     DWIDTH : positive :=  9);           -- data port width (8 or 9)
   port (
     CLK  : in slbit;                    -- clock
     CLK_CYCLE : in slv31 := (others=>'0');  -- clock cycle number
     ENA  : in slbit := '1';             -- enable monitor output
-    CP_DI : in slv(DWIDTH-1 downto 0);  -- comm port: data in
-    CP_ENA : in slbit;                  -- comm port: data enable
-    CP_BUSY : in slbit;                 -- comm port: data busy
-    CP_DO : in slv(DWIDTH-1 downto 0);  -- comm port: data out
-    CP_VAL : in slbit;                  -- comm port: data valid
-    CP_HOLD : in slbit                  -- comm port: data hold
+    RL_DI : in slv(DWIDTH-1 downto 0);  -- rlink: data in
+    RL_ENA : in slbit;                  -- rlink: data enable
+    RL_BUSY : in slbit;                 -- rlink: data busy
+    RL_DO : in slv(DWIDTH-1 downto 0);  -- rlink: data out
+    RL_VAL : in slbit;                  -- rlink: data valid
+    RL_HOLD : in slbit                  -- rlink: data hold
   );
-end rritb_cpmon;
+end rlink_mon;
 
 
-architecture sim of rritb_cpmon is
+architecture sim of rlink_mon is
 
 begin
 
   assert DWIDTH=8 or DWIDTH=9
     report "assert(DWIDTH=8 or DWIDTH=9)" severity failure;
   
-  proc_cpmoni: process
+  proc_moni: process
     variable oline : line;
     variable nbusy : integer := 0;
     variable nhold : integer := 0;
@@ -94,11 +97,11 @@ begin
         data9(data'range) := data;
         write(L, string'("  comma"));
         case data9 is
-          when c_rri_dat_idle => write(L, string'(" idle"));
-          when c_rri_dat_sop  => write(L, string'(" sop"));
-          when c_rri_dat_eop  => write(L, string'(" eop"));
-          when c_rri_dat_nak  => write(L, string'(" nak"));
-          when c_rri_dat_attn => write(L, string'(" attn"));
+          when c_rlink_dat_idle => write(L, string'(" idle"));
+          when c_rlink_dat_sop  => write(L, string'(" sop"));
+          when c_rlink_dat_eop  => write(L, string'(" eop"));
+          when c_rlink_dat_nak  => write(L, string'(" nak"));
+          when c_rlink_dat_attn => write(L, string'(" attn"));
           when others => null;
         end case;
       end if;
@@ -116,22 +119,22 @@ begin
 
       wait until CLK'event and CLK='1'; -- check at end of clock cycle
 
-      if CP_ENA = '1' then
-        if CP_BUSY = '1' then
+      if RL_ENA = '1' then
+        if RL_BUSY = '1' then
           nbusy := nbusy + 1;
         else
-          write_val(oline, CP_DI, nbusy, ": cprx  ", "  nbusy=");
+          write_val(oline, RL_DI, nbusy, ": rlrx  ", "  nbusy=");
           nbusy := 0;
         end if;
       else
         nbusy := 0;
       end if;
         
-      if CP_VAL = '1' then
-        if CP_HOLD = '1' then
+      if RL_VAL = '1' then
+        if RL_HOLD = '1' then
           nhold := nhold + 1;
         else
-          write_val(oline, CP_DO, nhold, ": cptx  ", "  nhold=");
+          write_val(oline, RL_DO, nhold, ": rltx  ", "  nhold=");
           nhold := 0;
         end if;
       else
@@ -139,6 +142,6 @@ begin
       end if;
       
     end loop;
-  end process proc_cpmoni;
+  end process proc_moni;
   
 end sim;
diff --git a/rtl/vlib/rlink/rlink_mon_sb.vbom b/rtl/vlib/rlink/rlink_mon_sb.vbom
new file mode 100644
index 00000000..057508a0
--- /dev/null
+++ b/rtl/vlib/rlink/rlink_mon_sb.vbom
@@ -0,0 +1,9 @@
+# libs
+../slvtypes.vhd
+../simlib/simlib.vhd
+../simlib/simbus.vhd
+rlinklib.vbom
+# components
+rlink_mon.vbom
+# design
+rlink_mon_sb.vhd
diff --git a/rtl/vlib/rri/tb/rritb_cpmon_sb.vhd b/rtl/vlib/rlink/rlink_mon_sb.vhd
similarity index 58%
rename from rtl/vlib/rri/tb/rritb_cpmon_sb.vhd
rename to rtl/vlib/rlink/rlink_mon_sb.vhd
index dc9c1ddd..53f083fb 100644
--- a/rtl/vlib/rri/tb/rritb_cpmon_sb.vhd
+++ b/rtl/vlib/rlink/rlink_mon_sb.vhd
@@ -1,4 +1,4 @@
--- $Id: rritb_cpmon_sb.vhd 314 2010-07-09 17:38:41Z mueller $
+-- $Id: rlink_mon_sb.vhd 347 2010-12-24 12:10:42Z mueller $
 --
 -- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -12,14 +12,17 @@
 -- for complete details.
 --
 ------------------------------------------------------------------------------
--- Module Name:    rritb_cpmon_sb - sim
--- Description:    rritb: rri comm port monitor; simbus wrapper
+-- Module Name:    rlink_mon_sb - sim
+-- Description:    simbus wrapper for rlink monitor
 --
 -- Dependencies:   simbus
 -- Test bench:     -
--- Tool versions:  xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+-- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
+--
 -- Revision History: 
 -- Date         Rev Version  Comment
+-- 2010-12-24   347   3.0.1  rename: CP_*->RL->*
+-- 2010-12-22   346   3.0    renamed rritb_cpmon_sb -> rlink_mon_sb
 -- 2010-05-02   287   1.0.1  use sbcntl_sbf_cpmon def
 -- 2007-08-25    75   1.0    Initial version 
 ------------------------------------------------------------------------------
@@ -30,25 +33,25 @@ use ieee.std_logic_1164.all;
 use work.slvtypes.all;
 use work.simlib.all;
 use work.simbus.all;
-use work.rritblib.all;
+use work.rlinklib.all;
 
-entity rritb_cpmon_sb is                -- simbus wrap rri comm port monitor
+entity rlink_mon_sb is                  -- simbus wrap for rlink monitor
   generic (
     DWIDTH : positive :=  9;            -- data port width (8 or 9)
-    ENAPIN : integer := sbcntl_sbf_cpmon); -- SB_CNTL signal to use for enable
+    ENAPIN : integer := sbcntl_sbf_rlmon); -- SB_CNTL signal to use for enable
   port (
     CLK  : in slbit;                    -- clock
-    CP_DI : in slv(DWIDTH-1 downto 0);  -- comm port: data in
-    CP_ENA : in slbit;                  -- comm port: data enable
-    CP_BUSY : in slbit;                 -- comm port: data busy
-    CP_DO : in slv(DWIDTH-1 downto 0);  -- comm port: data out
-    CP_VAL : in slbit;                  -- comm port: data valid
-    CP_HOLD : in slbit                  -- comm port: data hold
+    RL_DI : in slv(DWIDTH-1 downto 0);  -- rlink: data in
+    RL_ENA : in slbit;                  -- rlink: data enable
+    RL_BUSY : in slbit;                 -- rlink: data busy
+    RL_DO : in slv(DWIDTH-1 downto 0);  -- rlink: data out
+    RL_VAL : in slbit;                  -- rlink: data valid
+    RL_HOLD : in slbit                  -- rlink: data hold
   );
-end rritb_cpmon_sb;
+end rlink_mon_sb;
 
 
-architecture sim of rritb_cpmon_sb is
+architecture sim of rlink_mon_sb is
 
   signal ENA : slbit := '0';
   
@@ -59,19 +62,19 @@ begin
 
   ENA <= to_x01(SB_CNTL(ENAPIN));
   
-  CPMON : rritb_cpmon
+  CPMON : rlink_mon
     generic map (
       DWIDTH => DWIDTH)
     port map (
       CLK       => CLK,
       CLK_CYCLE => SB_CLKCYCLE,
       ENA       => ENA,
-      CP_DI     => CP_DI,
-      CP_ENA    => CP_ENA,
-      CP_BUSY   => CP_BUSY,
-      CP_DO     => CP_DO,
-      CP_VAL    => CP_VAL,
-      CP_HOLD   => CP_HOLD
+      RL_DI     => RL_DI,
+      RL_ENA    => RL_ENA,
+      RL_BUSY   => RL_BUSY,
+      RL_DO     => RL_DO,
+      RL_VAL    => RL_VAL,
+      RL_HOLD   => RL_HOLD
     );
   
 end sim;
diff --git a/rtl/vlib/rri/rri_serport.vbom b/rtl/vlib/rlink/rlink_rlb2rl.vbom
similarity index 60%
rename from rtl/vlib/rri/rri_serport.vbom
rename to rtl/vlib/rlink/rlink_rlb2rl.vbom
index 5189108d..cf5f73ec 100644
--- a/rtl/vlib/rri/rri_serport.vbom
+++ b/rtl/vlib/rlink/rlink_rlb2rl.vbom
@@ -1,14 +1,11 @@
 # libs
 ../slvtypes.vhd
-../genlib/genlib.vhd
-../memlib/memlib.vhd
 ../comlib/comlib.vhd
-../serport/serport.vhd
-rrilib.vhd
+../memlib/memlib.vhd
+rlinklib.vbom
 # components
-../serport/serport_uart_rxtx_ab.vbom
 ../comlib/byte2cdata.vbom
 ../comlib/cdata2byte.vbom
 ../memlib/fifo_1c_dram.vbom
 # design
-rri_serport.vhd
+rlink_rlb2rl.vhd
diff --git a/rtl/vlib/rlink/rlink_rlb2rl.vhd b/rtl/vlib/rlink/rlink_rlb2rl.vhd
new file mode 100644
index 00000000..b589243a
--- /dev/null
+++ b/rtl/vlib/rlink/rlink_rlb2rl.vhd
@@ -0,0 +1,209 @@
+-- $Id: rlink_rlb2rl.vhd 350 2010-12-28 16:40:11Z mueller $
+--
+-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for complete details.
+-- 
+------------------------------------------------------------------------------
+-- Module Name:    rlink_rlb2rl - syn
+-- Description:    rlink 8 bit(rlb) to 9 bit(rl) adapter
+--
+-- Dependencies:   comlib/byte2cdata
+--                 comlib/cdata2byte
+--                 memlib/fifo_1c_dram
+--
+-- Test bench:     tb/rb_rlink_serport
+--
+-- Target Devices: generic
+-- Tool versions:  xst 12.1; ghdl 0.29
+--
+-- Synthesized (xst):
+-- Date         Rev  ise         Target      flop lutl lutm slic t peri ifa ofa
+-- 2010-12-25   348 12.1    M53d xc3s1000-4    61  121   72  114 s  8.3   5   5
+-- 2010-12-25   348 12.1    M53d xc3s1000-4    41   84   36   73 s  8.3   5   0
+-- 2010-12-25   348 12.1    M53d xc3s1000-4    22   50    -   30 s  4.5   0   0
+--
+-- Revision History: 
+-- Date         Rev Version  Comment
+-- 2010-12-24   348   1.0    Initial version 
+------------------------------------------------------------------------------
+--
+--                  byte2cdata         fifo_1c_dram
+--                +--------------+    +--------------+
+--                |              |    |              |
+--   RLB_DI     ->| DI        DO |--->| DI        DO |-> RL_DI
+--                |              |    |              |
+--   RLB_ENA    ->| ENA      VAL |--->| ENA      VAL |-> RL_ENA
+--                |              |    |              |
+--   RLB_BUSY   <-| BUSY    HOLD |<---| BUSY    HOLD |<- RL_BUSY
+--                |              |    |              |
+--                +--------------+    |              |
+--                                    |              |
+--                           +---+    |              |
+--   IFIFO_FILL <------------|map|<---| SIZE         |
+--                           +---+    +--------------+
+-- 
+-- 
+--                  cdata2byte         fifo_1c_dram
+--                +--------------+    +--------------+
+--                |              |    |              |
+--   RLB_DO     <-| DO        DI |<---| DO        DI |<- RL_DO
+--                |              |    |              |
+--   RLB_VAL    <-| VAL      ENA |<---| VAL      ENA |<- RL_VAL
+--                |              |    |              |
+--   RLB_HOLD   ->| HOLD    BUSY |--->| HOLD    BUSY |-> RL_HOLD
+--                |              |    |              |
+--                +--------------+    |              |
+--                                    |              |
+--                           +---+    |              |
+--   OFIFO_FILL <------------|map|<---| SIZE         |
+--                           +---+    +--------------+
+-- 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+use work.slvtypes.all;
+use work.comlib.all;
+use work.memlib.all;
+use work.rlinklib.all;
+
+entity rlink_rlb2rl is                  -- rlink 8 bit(rlb) to 9 bit(rl) adapter
+  generic (
+    CPREF : slv4 :=  "1000";            -- comma prefix
+    IFAWIDTH : natural :=  5;           -- input fifo address width  (0=none)
+    OFAWIDTH : natural :=  5);          -- output fifo address width (0=none)
+  port (
+    CLK  : in slbit;                    -- clock
+    RESET : in slbit;                   -- reset
+    RLB_DI : in slv8;                   -- rlink 8bit: data in
+    RLB_ENA : in slbit;                 -- rlink 8bit: data enable
+    RLB_BUSY : out slbit;               -- rlink 8bit: data busy
+    RLB_DO : out slv8;                  -- rlink 8bit: data out
+    RLB_VAL : out slbit;                -- rlink 8bit: data valid
+    RLB_HOLD : in slbit;                -- rlink 8bit: data hold
+    IFIFO_SIZE : out slv4;              --  input fifo size (4 msb's)
+    OFIFO_SIZE : out slv4;              -- output fifo fill (4 msb's)
+    RL_DI : out slv9;                   -- rlink 9bit: data in
+    RL_ENA : out slbit;                 -- rlink 9bit: data enable
+    RL_BUSY : in slbit;                 -- rlink 9bit: data busy
+    RL_DO : in slv9;                    -- rlink 9bit: data out
+    RL_VAL : in slbit;                  -- rlink 9bit: data valid
+    RL_HOLD : out slbit                 -- rlink 9bit: data hold
+  );
+end rlink_rlb2rl;
+
+architecture syn of rlink_rlb2rl is
+
+  signal RLB_BUSY_L : slbit := '0';
+  signal IFIFO_DI : slv9 := (others=>'0');
+  signal IFIFO_ENA : slbit := '0';
+  signal IFIFO_BUSY : slbit := '0';
+  signal OFIFO_DO : slv9 := (others=>'0');
+  signal OFIFO_VAL : slbit := '0';
+  signal OFIFO_HOLD : slbit := '0';
+
+begin
+
+-- RLB -> RL converter (DI handling) -------------
+  
+  B2CD : byte2cdata                     -- byte stream -> 9bit comma,data
+  generic map (
+    CPREF => CPREF,
+    NCOMM => c_rlink_ncomm)
+  port map (
+    CLK   => CLK,
+    RESET => RESET,
+    DI    => RLB_DI,
+    ENA   => RLB_ENA,
+    BUSY  => RLB_BUSY_L,
+    DO    => IFIFO_DI,
+    VAL   => IFIFO_ENA,
+    HOLD  => IFIFO_BUSY
+  );
+
+  DOIFIFO: if IFAWIDTH > 0 generate
+    signal SIZE: slv(IFAWIDTH downto 0) := (others=>'0');
+  begin
+    IFIFO : fifo_1c_dram                -- input fifo, 1 clock, dram based
+    generic map (
+      AWIDTH => IFAWIDTH,
+      DWIDTH => 9)
+    port map (
+      CLK   => CLK,
+      RESET => RESET,
+      DI    => IFIFO_DI,
+      ENA   => IFIFO_ENA,
+      BUSY  => IFIFO_BUSY,
+      DO    => RL_DI,
+      VAL   => RL_ENA,
+      HOLD  => RL_BUSY,
+      SIZE  => SIZE
+    );
+    IFIFO_SIZE <= SIZE(IFAWIDTH downto IFAWIDTH-3);
+  end generate DOIFIFO;
+
+  NOIFIFO: if IFAWIDTH = 0 generate
+    RL_DI      <= IFIFO_DI;
+    RL_ENA     <= IFIFO_ENA;
+    IFIFO_BUSY <= RL_BUSY;
+    IFIFO_SIZE <= RLB_BUSY_L & "000";
+  end generate NOIFIFO;
+
+  RLB_BUSY <= RLB_BUSY_L;
+  
+-- RL -> RLB converter (DO handling) -------------
+
+  CD2B : cdata2byte                     -- 9bit comma,data -> byte stream
+  generic map (
+    CPREF => CPREF,
+    NCOMM => c_rlink_ncomm)
+  port map (
+    CLK   => CLK,
+    RESET => RESET,
+    DI    => OFIFO_DO,
+    ENA   => OFIFO_VAL,
+    BUSY  => OFIFO_HOLD,
+    DO    => RLB_DO,
+    VAL   => RLB_VAL,
+    HOLD  => RLB_HOLD
+  );
+
+  DOOFIFO: if OFAWIDTH > 0 generate
+    signal SIZE : slv(OFAWIDTH downto 0) := (others=>'0');
+  begin
+    OFIFO : fifo_1c_dram                -- input fifo, 1 clock, dram based
+    generic map (
+      AWIDTH => OFAWIDTH,
+      DWIDTH => 9)
+    port map (
+      CLK   => CLK,
+      RESET => RESET,
+      DI    => RL_DO,
+      ENA   => RL_VAL,
+      BUSY  => RL_HOLD,
+      DO    => OFIFO_DO,
+      VAL   => OFIFO_VAL,
+      HOLD  => OFIFO_HOLD,
+      SIZE  => SIZE
+    );
+    OFIFO_SIZE <= SIZE(OFAWIDTH downto OFAWIDTH-3);
+  end generate DOOFIFO;
+
+  NOOFIFO: if OFAWIDTH = 0 generate
+    OFIFO_DO   <= RL_DO;
+    OFIFO_VAL  <= RL_VAL;
+    RL_HOLD    <= OFIFO_HOLD;
+    OFIFO_SIZE <= OFIFO_HOLD & "000";
+  end generate NOOFIFO;
+  
+end syn;
diff --git a/rtl/vlib/rlink/rlink_serport.vbom b/rtl/vlib/rlink/rlink_serport.vbom
new file mode 100644
index 00000000..82bc9c63
--- /dev/null
+++ b/rtl/vlib/rlink/rlink_serport.vbom
@@ -0,0 +1,9 @@
+# libs
+../slvtypes.vhd
+../serport/serport.vhd
+../rbus/rblib.vhd
+rlinklib.vbom
+# components
+../serport/serport_uart_rxtx_ab.vbom
+# design
+rlink_serport.vhd
diff --git a/rtl/vlib/rlink/rlink_serport.vhd b/rtl/vlib/rlink/rlink_serport.vhd
new file mode 100644
index 00000000..c3edccf3
--- /dev/null
+++ b/rtl/vlib/rlink/rlink_serport.vhd
@@ -0,0 +1,235 @@
+-- $Id: rlink_serport.vhd 350 2010-12-28 16:40:11Z mueller $
+--
+-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for complete details.
+-- 
+------------------------------------------------------------------------------
+-- Module Name:    rlink_serport - syn
+-- Description:    rlink: serport adapter (serial to rlink_base)
+--
+-- Dependencies:   serport/serport_uart_rxtx_ab
+--
+-- Test bench:     tb/tb_rlink_serport
+--
+-- Target Devices: generic
+-- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
+--
+-- Synthesized (xst):
+-- Date         Rev  ise         Target      flop lutl lutm slic t peri
+-- 2010-12-26   348 12.1    M53d xc3s1000-4   122  227    -  152 s  9.8
+--
+-- Revision History: 
+-- Date         Rev Version  Comment
+-- 2010-12-25   348   3.1    re-written, is now a serial to rlink_base adapter
+-- 2010-12-24   347   3.0.1  rename: CP_*->RL->*
+-- 2010-12-04   343   3.0    renamed rri_ -> rlink_
+-- 2010-06-06   301   2.3    use NCOMM=4 (new eop,nak commas)
+-- 2010-06-03   300   2.2.1  use FAWIDTH=5 
+-- 2010-05-02   287   2.2    drop RTSFLUSH generic
+-- 2010-04-18   279   2.1    rewrite flow control, drop RTSFBUF generic
+-- 2010-04-03   274   2.0    flow control interfaces: RTSFLUSH, CTS_N, RTS_N
+-- 2007-06-24    60   1.0    Initial version 
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+use work.slvtypes.all;
+use work.serport.all;
+use work.rblib.all;
+use work.rlinklib.all;
+
+entity rlink_serport is                 -- rlink serport adapter
+  generic (
+    RB_ADDR : slv8 := conv_std_logic_vector(2#11111110#,8);
+    CDWIDTH : positive := 13;           -- clk divider width
+    CDINIT : natural   := 15);          -- clk divider initial/reset setting
+  port (
+    CLK  : in slbit;                    -- clock
+    CE_USEC : in slbit;                 -- 1 usec clock enable
+    CE_MSEC : in slbit;                 -- 1 msec clock enable
+    RESET  : in slbit;                  -- reset
+    RXSD : in slbit;                    -- receive serial data      (board view)
+    TXSD : out slbit;                   -- transmit serial data     (board view)
+    CTS_N : in slbit := '0';            -- clear to send   (act.low, board view)
+    RTS_N : out slbit;                  -- request to send (act.low, board view)
+    RLB_DI : out slv8;                  -- rlink 8b: data in
+    RLB_ENA : out slbit;                -- rlink 8b: data enable
+    RLB_BUSY : in slbit;                -- rlink 8b: data busy
+    RLB_DO : in slv8;                   -- rlink 8b: data out
+    RLB_VAL : in slbit;                 -- rlink 8b: data valid
+    RLB_HOLD : out slbit;               -- rlink 8b: data hold
+    RB_MREQ : in rb_mreq_type;          -- rbus: request (for inits only)
+    IFIFO_SIZE : in slv4;               -- rlink_rlb2rb: input fifo size
+    RL_MONI : in rl_moni_type;          -- rlink_core: monitor port
+    RL_SER_MONI : out rl_ser_moni_type  -- rlink_serport: monitor port
+  );
+end rlink_serport;
+
+
+architecture syn of rlink_serport is
+
+  type regs_type is record
+    flpend  : slbit;                    -- flush pending
+    fldbusy : slbit;                    -- flush delay busy
+    fldcnt  : slv3;                     -- flush delay counter
+    flpbusy : slbit;                    -- flush pulse busy
+    flpcnt  : slv3;                     -- flush pulse counter
+    ffblock : slbit;                    -- fifo block
+    fena    : slbit;                    -- flush enable
+    fwidth  : slv3;                     -- flush pulse width
+    fdelay  : slv3;                     -- flush pulse delay
+    rtsoff  : slv3;                     -- rts off level (fifo high water)
+    rtson   : slv3;                     -- rts on  level (fifo low water)
+  end record regs_type;
+
+  constant regs_init : regs_type := (
+    '0','0',"000",                      -- flpend,fldbusy,fldcnt
+    '0',"000",                          -- flpbusy,flpcnt
+    '0',                                -- ffblock
+    '0',                                -- fena
+    "000","000",                        -- fwidth,fdelay
+    "111","110"                         -- rtsoff,rtson
+  );
+
+  signal R_REGS : regs_type := regs_init;  -- state registers
+  signal N_REGS : regs_type := regs_init;  -- next value state regs
+
+  signal RXVAL : slbit := '0';
+  signal RXERR : slbit := '0';
+  signal RXACT : slbit := '0';
+  signal TXBUSY : slbit := '0';
+  signal ABACT : slbit := '0';
+  signal ABDONE : slbit := '0';
+  signal ABCLKDIV : slv16 := (others=>'0');
+
+begin
+
+  assert CDWIDTH<=16
+    report "assert(CDWIDTH<=16): max width of UART clock divider"
+    severity failure;
+
+  UART : serport_uart_rxtx_ab           -- uart, rx+tx+autobauder combo
+  generic map (
+    CDWIDTH => CDWIDTH,
+    CDINIT  => CDINIT)
+  port map (
+    CLK      => CLK,
+    CE_MSEC  => CE_MSEC,
+    RESET    => RESET,
+    RXSD     => RXSD,
+    RXDATA   => RLB_DI,
+    RXVAL    => RXVAL,
+    RXERR    => RXERR,
+    RXACT    => RXACT,
+    TXSD     => TXSD,
+    TXDATA   => RLB_DO,
+    TXENA    => RLB_VAL,
+    TXBUSY   => TXBUSY,
+    ABACT    => ABACT,
+    ABDONE   => ABDONE,
+    ABCLKDIV => ABCLKDIV(CDWIDTH-1 downto 0)
+  );
+  
+  proc_regs: process (CLK)
+  begin
+
+    if CLK'event and CLK='1' then
+      if RESET = '1' then
+        R_REGS <= regs_init;
+      else
+        R_REGS <= N_REGS;
+      end if;
+    end if;
+
+  end process proc_regs;
+
+  proc_next: process (R_REGS, RB_MREQ, IFIFO_SIZE, RL_MONI, TXBUSY, CE_USEC)
+
+    variable r : regs_type := regs_init;
+    variable n : regs_type := regs_init;
+
+  begin
+
+    r := R_REGS;
+    n := R_REGS;
+
+    -- handle init
+    if RB_MREQ.init='1' and RB_MREQ.we='0' and RB_MREQ.addr=RB_ADDR then
+      n.fena   := RB_MREQ.din(c_rlink_serport_rbf_fena);
+      n.fwidth := RB_MREQ.din(c_rlink_serport_rbf_fwidth);
+      n.fdelay := RB_MREQ.din(c_rlink_serport_rbf_fdelay);
+      n.rtsoff := RB_MREQ.din(c_rlink_serport_rbf_rtsoff);
+      n.rtson  := RB_MREQ.din(c_rlink_serport_rbf_rtson);
+    end if;
+
+    -- fifo back preasure
+    if IFIFO_SIZE(3)='1' or
+       unsigned(IFIFO_SIZE(2 downto 0))>unsigned(r.rtsoff) then
+      n.ffblock := '1';
+    elsif unsigned(IFIFO_SIZE(2 downto 0)) <= unsigned(r.rtson) then
+      n.ffblock := '0';
+    end if;
+
+    -- send flush pulse if
+    --   eop send unless a pending attn
+    --   or an attn was send
+    
+    if (RL_MONI.eop='1' and RL_MONI.lamp='0') or RL_MONI.attn='1' then
+      n.flpend := r.fena;
+    end if;
+
+    -- flush pulse logic
+    --   start delay when flpend is set
+    --   re-start delay when TXBUSY=1
+    --   when timer expires, clear flpend, start pulse
+    
+    if r.flpend='1' and (r.fldbusy='0' or TXBUSY='1') then
+      n.fldbusy := '1';
+      n.fldcnt  := r.fdelay;
+    elsif CE_USEC='1' and r.fldbusy='1' then
+      if unsigned(r.fldcnt) = 0 then
+        n.flpend  := '0';
+        n.fldbusy := '0';
+        n.flpbusy := '1';
+        n.flpcnt  := r.fwidth;
+      else
+        n.fldcnt := unsigned(r.fldcnt) - 1;
+      end if;
+    end if;
+
+    if CE_USEC='1' and r.flpbusy='1' then
+      if unsigned(r.flpcnt) = 0 then
+        n.flpbusy := '0';
+      else
+        n.flpcnt := unsigned(r.flpcnt) - 1;
+      end if;
+    end if;
+    
+    N_REGS <= n;
+
+  end process proc_next;
+    
+  RTS_N    <= R_REGS.ffblock or R_REGS.flpbusy;
+
+  RLB_ENA  <= RXVAL;
+  RLB_HOLD <= TXBUSY or CTS_N;
+  
+  RL_SER_MONI.rxerr  <= RXERR;
+  RL_SER_MONI.rxdrop <= RXVAL and RLB_BUSY;
+  RL_SER_MONI.rxact  <= RXACT;
+  RL_SER_MONI.txact  <= TXBUSY;
+  RL_SER_MONI.abact  <= ABACT;
+  RL_SER_MONI.abdone <= ABDONE;
+  RL_SER_MONI.clkdiv <= ABCLKDIV;
+
+end syn;
diff --git a/rtl/vlib/rlink/rlinklib.vbom b/rtl/vlib/rlink/rlinklib.vbom
new file mode 100644
index 00000000..6d929d6d
--- /dev/null
+++ b/rtl/vlib/rlink/rlinklib.vbom
@@ -0,0 +1,4 @@
+# libs
+../slvtypes.vhd
+../rbus/rblib.vhd
+rlinklib.vhd
diff --git a/rtl/vlib/rlink/rlinklib.vhd b/rtl/vlib/rlink/rlinklib.vhd
new file mode 100644
index 00000000..af52a792
--- /dev/null
+++ b/rtl/vlib/rlink/rlinklib.vhd
@@ -0,0 +1,308 @@
+-- $Id: rlinklib.vhd 348 2010-12-26 15:23:44Z mueller $
+--
+-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name:   rlinklib
+-- Description:    Definitions for rlink interface and bus entities
+--
+-- Dependencies:   -
+-- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
+--
+-- Revision History: 
+-- Date         Rev Version  Comment
+-- 2010-12-25   348   3.1.2  drop RL_FLUSH support, add RL_MONI for rlink_core;
+--                           new rlink_serport interface;
+--                           rename rlink_core_serport->rlink_base_serport
+-- 2010-12-24   347   3.1.1  rename: CP_*->RL->*
+-- 2010-12-22   346   3.1    rename: [cd]crc->[cd]err, ioto->rbnak, ioerr->rberr
+-- 2010-12-04   343   3.0    move rbus components to rbus/rblib; renames
+--                           rri_ -> rlink and c_rri -> c_rlink;
+-- 2010-06-18   306   2.5.1  rename rbus data fields to _rbf_
+-- 2010-06-06   302   2.5    use sop/eop framing instead of soc+chaining
+-- 2010-06-03   300   2.1.5  use FAWIDTH=5 for rri_serport
+-- 2010-05-02   287   2.1.4  ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
+--                           drop RP_IINT from interfaces; drop RTSFLUSH generic
+-- 2010-05-01   285   2.1.3  remove rri_rb_rpcompat, now obsolete
+-- 2010-04-18   279   2.1.2  rri_core_serport: drop RTSFBUF generic
+-- 2010-04-10   275   2.1.1  add rri_core_serport
+-- 2010-04-03   274   2.1    add CP_FLUSH for rri_core, rri_serport;
+--                           CE_USEC, RTSFLUSH, CTS_N, RTS_N  for rri_serport
+-- 2008-08-24   162   2.0    all with new rb_mreq/rb_sres interface
+-- 2008-08-22   161   1.3    renamed rri_rbres_ -> rb_sres_; drop rri_[24]rp
+-- 2008-02-16   116   1.2.1  added rri_wreg(rw|w|r)_3
+-- 2008-01-20   113   1.2    added rb_[mreq|sres]; _rbres_or_*; _rb_rpcompat
+-- 2007-11-24    98   1.1    added RP_IINT for rri_core.
+-- 2007-09-09    81   1.0    Initial version 
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+use work.slvtypes.all;
+use work.rblib.all;
+
+package rlinklib is
+
+constant c_rlink_cpref : slv4 := "1000";  -- default comma prefix
+constant c_rlink_ncomm : positive := 4;   -- number commas (sop,eop,nak,attn)
+
+constant c_rlink_dat_idle : slv9 := "100000000";
+constant c_rlink_dat_sop  : slv9 := "100000001";
+constant c_rlink_dat_eop  : slv9 := "100000010";
+constant c_rlink_dat_nak  : slv9 := "100000011";
+constant c_rlink_dat_attn : slv9 := "100000100";
+
+constant c_rlink_cmd_rreg : slv3 := "000";
+constant c_rlink_cmd_rblk : slv3 := "001";
+constant c_rlink_cmd_wreg : slv3 := "010";
+constant c_rlink_cmd_wblk : slv3 := "011";
+constant c_rlink_cmd_stat : slv3 := "100";
+constant c_rlink_cmd_attn : slv3 := "101";
+constant c_rlink_cmd_init : slv3 := "110";
+
+constant c_rlink_iint_rbf_anena:    integer := 15;         -- anena flag
+constant c_rlink_iint_rbf_itoena:   integer := 14;         -- itoena flag
+subtype  c_rlink_iint_rbf_itoval is integer range 7 downto 0; -- command code
+
+subtype  c_rlink_cmd_rbf_seq is  integer range 7 downto 3; -- sequence number
+subtype  c_rlink_cmd_rbf_code is integer range 2 downto 0; -- command code
+
+subtype  c_rlink_stat_rbf_stat is integer range 7 downto 5;  -- ext status bits
+constant c_rlink_stat_rbf_attn:   integer := 4;  -- attention flags set
+constant c_rlink_stat_rbf_cerr:   integer := 3;  -- command error
+constant c_rlink_stat_rbf_derr:   integer := 2;  -- data error
+constant c_rlink_stat_rbf_rbnak:  integer := 1;  -- rbus no ack or timeout
+constant c_rlink_stat_rbf_rberr:  integer := 0;  -- rbus err bit set
+
+type rl_moni_type is record             -- rlink_core monitor port
+  eop  : slbit;                         -- eop send in last cycle
+  attn : slbit;                         -- attn send in last cycle
+  lamp : slbit;                         -- attn (lam) pending
+end record rl_moni_type;
+
+constant rl_moni_init : rl_moni_type :=
+  ('0','0','0');                        -- eop,attn,lamp
+
+component rlink_core is                 -- rlink core with 9bit iface
+  generic (
+    ATOWIDTH : positive :=  5;          -- access timeout counter width
+    ITOWIDTH : positive :=  6);         -- idle timeout counter width
+  port (
+    CLK  : in slbit;                    -- clock
+    CE_INT : in slbit := '0';           -- rlink ito time unit clock enable
+    RESET  : in slbit;                  -- reset
+    RL_DI : in slv9;                    -- rlink 9b: data in
+    RL_ENA : in slbit;                  -- rlink 9b: data enable
+    RL_BUSY : out slbit;                -- rlink 9b: data busy
+    RL_DO : out slv9;                   -- rlink 9b: data out
+    RL_VAL : out slbit;                 -- rlink 9b: data valid
+    RL_HOLD : in slbit;                 -- rlink 9b: data hold
+    RL_MONI : out rl_moni_type;         -- rlink: monitor port
+    RB_MREQ : out rb_mreq_type;         -- rbus: request
+    RB_SRES : in rb_sres_type;          -- rbus: response
+    RB_LAM : in slv16;                  -- rbus: look at me
+    RB_STAT : in slv3                   -- rbus: status flags
+  );
+end component;
+
+component rlink_aif is                  -- rlink, abstract interface
+  port (
+    CLK  : in slbit;                    -- clock
+    CE_INT : in slbit := '0';           -- rlink ito time unit clock enable
+    RESET  : in slbit :='0';            -- reset
+    RL_DI : in slv9;                    -- rlink 9b: data in
+    RL_ENA : in slbit;                  -- rlink 9b: data enable
+    RL_BUSY : out slbit;                -- rlink 9b: data busy
+    RL_DO : out slv9;                   -- rlink 9b: data out
+    RL_VAL : out slbit;                 -- rlink 9b: data valid
+    RL_HOLD : in slbit := '0'           -- rlink 9b: data hold
+  );
+end component;
+
+component rlink_rlb2rl is               -- rlink 8 bit(rlb) to 9 bit(rl) adapter
+  generic (
+    CPREF : slv4 := c_rlink_cpref;      -- comma prefix
+    IFAWIDTH : natural :=  5;           -- input fifo address width  (0=none)
+    OFAWIDTH : natural :=  5);          -- output fifo address width (0=none)
+  port (
+    CLK  : in slbit;                    -- clock
+    RESET : in slbit;                   -- reset
+    RLB_DI : in slv8;                   -- rlink 8b: data in
+    RLB_ENA : in slbit;                 -- rlink 8b: data enable
+    RLB_BUSY : out slbit;               -- rlink 8b: data busy
+    RLB_DO : out slv8;                  -- rlink 8b: data out
+    RLB_VAL : out slbit;                -- rlink 8b: data valid
+    RLB_HOLD : in slbit;                -- rlink 8b: data hold
+    IFIFO_SIZE : out slv4;              --  input fifo size (4 msb's)
+    OFIFO_SIZE : out slv4;              -- output fifo fill (4 msb's)
+    RL_DI : out slv9;                   -- rlink 9b: data in
+    RL_ENA : out slbit;                 -- rlink 9b: data enable
+    RL_BUSY : in slbit;                 -- rlink 9b: data busy
+    RL_DO : in slv9;                    -- rlink 9b: data out
+    RL_VAL : in slbit;                  -- rlink 9b: data valid
+    RL_HOLD : out slbit                 -- rlink 9b: data hold
+  );
+end component;
+
+-- this definition logically belongs into the 'for test benches' section'
+-- must be here because it is needed as generic default in rlink_base
+-- simbus sb_cntl field usage for rlink
+  constant sbcntl_sbf_rlmon : integer := 15;
+
+component rlink_base is                 -- rlink base: core+rl2rlb+rlmon+rbmon
+                                        -- with buffered 8bit interface
+  generic (
+    ATOWIDTH : positive :=  5;          -- access timeout counter width
+    ITOWIDTH : positive :=  6;          -- idle timeout counter width
+    CPREF : slv4 := c_rlink_cpref;      -- comma prefix
+    IFAWIDTH : natural :=  5;           -- input fifo address width  (0=none)
+    OFAWIDTH : natural :=  5;           -- output fifo address width (0=none)
+    ENAPIN_RLMON : integer := sbcntl_sbf_rlmon;  -- SB_CNTL for rlmon (-1=none)
+    ENAPIN_RBMON : integer := sbcntl_sbf_rbmon); -- SB_CNTL for rbmon (-1=none)
+  port (
+    CLK  : in slbit;                    -- clock
+    CE_INT : in slbit := '0';           -- rlink ito time unit clock enable
+    RESET  : in slbit;                  -- reset
+    RLB_DI : in slv8;                   -- rlink 8b: data in
+    RLB_ENA : in slbit;                 -- rlink 8b: data enable
+    RLB_BUSY : out slbit;               -- rlink 8b: data busy
+    RLB_DO : out slv8;                  -- rlink 8b: data out
+    RLB_VAL : out slbit;                -- rlink 8b: data valid
+    RLB_HOLD : in slbit;                -- rlink 8b: data hold
+    IFIFO_SIZE : out slv4;              --  input fifo size (4 msb's)
+    OFIFO_SIZE : out slv4;              -- output fifo fill (4 msb's)
+    RL_MONI : out rl_moni_type;         -- rlink: monitor port
+    RB_MREQ : out rb_mreq_type;         -- rbus: request
+    RB_SRES : in rb_sres_type;          -- rbus: response
+    RB_LAM : in slv16;                  -- rbus: look at me
+    RB_STAT : in slv3                   -- rbus: status flags
+  );
+end component;
+
+type rl_ser_moni_type is record         -- rlink_serport monitor port
+  rxerr : slbit;                        -- rx err
+  rxdrop : slbit;                       -- rx drop
+  rxact : slbit;                        -- rx active
+  txact : slbit;                        -- tx active
+  abact : slbit;                        -- ab active
+  abdone : slbit;                       -- ab done
+  clkdiv : slv16;                       -- clock divider
+end record rl_ser_moni_type;
+
+constant rl_ser_moni_init : rl_ser_moni_type :=
+  ('0','0',                             -- rxerr,rxdrop
+   '0','0',                             -- rxact,txact
+   '0','0',                             -- abact,abdone
+   (others=>'0'));                      -- clkdiv
+
+constant c_rlink_serport_rbf_fena:     integer := 12;             -- 
+subtype  c_rlink_serport_rbf_fwidth is integer range 11 downto 9; -- 
+subtype  c_rlink_serport_rbf_fdelay is integer range  8 downto 6; -- 
+subtype  c_rlink_serport_rbf_rtsoff is integer range  5 downto 3; -- 
+subtype  c_rlink_serport_rbf_rtson  is integer range  2 downto 0; -- 
+
+component rlink_serport is              -- rlink serport adapter
+  generic (
+    RB_ADDR : slv8 := conv_std_logic_vector(2#11111110#,8);
+    CDWIDTH : positive := 13;           -- clk divider width
+    CDINIT : natural   := 15);          -- clk divider initial/reset setting
+  port (
+    CLK  : in slbit;                    -- clock
+    CE_USEC : in slbit;                 -- 1 usec clock enable
+    CE_MSEC : in slbit;                 -- 1 msec clock enable
+    RESET  : in slbit;                  -- reset
+    RXSD : in slbit;                    -- receive serial data      (board view)
+    TXSD : out slbit;                   -- transmit serial data     (board view)
+    CTS_N : in slbit := '0';            -- clear to send   (act.low, board view)
+    RTS_N : out slbit;                  -- request to send (act.low, board view)
+    RLB_DI : out slv8;                  -- rlink 8b: data in
+    RLB_ENA : out slbit;                -- rlink 8b: data enable
+    RLB_BUSY : in slbit;                -- rlink 8b: data busy
+    RLB_DO : in slv8;                   -- rlink 8b: data out
+    RLB_VAL : in slbit;                 -- rlink 8b: data valid
+    RLB_HOLD : out slbit;               -- rlink 8b: data hold
+    RB_MREQ : in rb_mreq_type;          -- rbus: request (for inits only)
+    IFIFO_SIZE : in slv4;               -- rlink_rlb2rb: input fifo size
+    RL_MONI : in rl_moni_type;          -- rlink_core: monitor port
+    RL_SER_MONI : out rl_ser_moni_type  -- rlink_serport: monitor port
+  );
+end component;
+
+component rlink_base_serport is         -- rlink base+serport combo
+  generic (
+    ATOWIDTH : positive :=  5;          -- access timeout counter width
+    ITOWIDTH : positive :=  6;          -- idle timeout counter width
+    CPREF : slv4 := c_rlink_cpref;      -- comma prefix
+    IFAWIDTH : natural :=  5;           -- input fifo address width  (0=none)
+    OFAWIDTH : natural :=  5;           -- output fifo address width (0=none)
+    ENAPIN_RLMON : integer := sbcntl_sbf_rlmon;  -- SB_CNTL for rlmon (-1=none)
+    ENAPIN_RBMON : integer := sbcntl_sbf_rbmon;  -- SB_CNTL for rbmon (-1=none)
+    RB_ADDR : slv8 := conv_std_logic_vector(2#11111110#,8);
+    CDWIDTH : positive := 13;           -- clk divider width
+    CDINIT : natural   := 15);          -- clk divider initial/reset setting
+  port (
+    CLK  : in slbit;                    -- clock
+    CE_USEC : in slbit;                 -- 1 usec clock enable
+    CE_MSEC : in slbit;                 -- 1 msec clock enable
+    CE_INT : in slbit := '0';           -- rri ito time unit clock enable
+    RESET  : in slbit;                  -- reset
+    RXSD : in slbit;                    -- receive serial data      (board view)
+    TXSD : out slbit;                   -- transmit serial data     (board view)
+    CTS_N : in slbit := '0';            -- clear to send   (act.low, board view)
+    RTS_N : out slbit;                  -- request to send (act.low, board view)
+    RB_MREQ : out rb_mreq_type;         -- rbus: request
+    RB_SRES : in rb_sres_type;          -- rbus: response
+    RB_LAM : in slv16;                  -- rbus: look at me
+    RB_STAT : in slv3;                  -- rbus: status flags
+    RL_MONI : out rl_moni_type;         -- rlink_core: monitor port
+    RL_SER_MONI : out rl_ser_moni_type  -- rlink_serport: monitor port
+  );
+end component;
+
+--
+-- components for use in test benches (not synthesizable)
+--
+
+component rlink_mon is                  -- rlink monitor
+  generic (
+    DWIDTH : positive :=  9);           -- data port width (8 or 9)
+  port (
+    CLK  : in slbit;                    -- clock
+    CLK_CYCLE : in slv31 := (others=>'0');  -- clock cycle number
+    ENA  : in slbit := '1';             -- enable monitor output
+    RL_DI : in slv(DWIDTH-1 downto 0);  -- rlink: data in
+    RL_ENA : in slbit;                  -- rlink: data enable
+    RL_BUSY : in slbit;                 -- rlink: data busy
+    RL_DO : in slv(DWIDTH-1 downto 0);  -- rlink: data out
+    RL_VAL : in slbit;                  -- rlink: data valid
+    RL_HOLD : in slbit                  -- rlink: data hold
+  );
+end component;
+
+component rlink_mon_sb is              -- simbus wrap for rlink monitor
+  generic (
+    DWIDTH : positive :=  9;            -- data port width (8 or 9)
+    ENAPIN : integer := sbcntl_sbf_rlmon); -- SB_CNTL signal to use for enable
+  port (
+    CLK  : in slbit;                    -- clock
+    RL_DI : in slv(DWIDTH-1 downto 0);  -- rlink: data in
+    RL_ENA : in slbit;                  -- rlink: data enable
+    RL_BUSY : in slbit;                 -- rlink: data busy
+    RL_DO : in slv(DWIDTH-1 downto 0);  -- rlink: data out
+    RL_VAL : in slbit;                  -- rlink: data valid
+    RL_HOLD : in slbit                  -- rlink: data hold
+  );
+end component;
+
+end rlinklib;
diff --git a/rtl/vlib/rlink/tb/.cvsignore b/rtl/vlib/rlink/tb/.cvsignore
new file mode 100644
index 00000000..883b6dd5
--- /dev/null
+++ b/rtl/vlib/rlink/tb/.cvsignore
@@ -0,0 +1,18 @@
+tb_rlink_stim
+tb_rlink_direct
+tb_rlink_direct_[sft]sim
+tb_rlink_direct_ISim
+tb_rlink_direct_ISim_[sft]sim
+tb_rlink_serport
+tb_rlink_serport_[sft]sim
+tb_rlink_serport_ISim
+tb_rlink_serport_ISim_[sft]sim
+tb_rlink_tba_stim
+tb_rlink_tba_ttcombo
+tb_rlink_tba_ttcombo_[sft]sim
+tb_rlink_tba_ttcombo_ISim
+tb_rlink_tba_ttcombo_ISim_[sft]sim
+tb_rlink_tba_eyemon
+tb_rlink_tba_eyemon_[sft]sim
+tb_rlink_tba_eyemon_ISim
+tb_rlink_tba_eyemon_ISim_[sft]sim
diff --git a/rtl/vlib/rri/tb/Makefile b/rtl/vlib/rlink/tb/Makefile
similarity index 76%
rename from rtl/vlib/rri/tb/Makefile
rename to rtl/vlib/rlink/tb/Makefile
index ea191432..13671146 100644
--- a/rtl/vlib/rri/tb/Makefile
+++ b/rtl/vlib/rlink/tb/Makefile
@@ -1,15 +1,17 @@
-# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $
+# $Id: Makefile 349 2010-12-28 14:02:13Z mueller $
 #
 #  Revision History: 
 # Date         Rev Version  Comment
+# 2010-12-28   349   1.3.1  add tb_rlink_tba_eyemon
+# 2010-12-05   343   1.3    rri->rlink renames
 # 2009-11-21   252   1.2    add ISim support
 # 2007-11-03    95   1.1.2  use .log rather .dat output in check_dsim
 # 2007-09-16    83   1.1.1  add include *.o.dep_ghdl
 # 2007-06-29    61   1.1    add clean and all
 # 2007-06-10    51   1.0    Initial version
 #
-EXE_all = tb_rri_core tb_rri_serport \
-	tb_rritba_ttcombo tb_rriext_ttcombo
+EXE_all = tb_rlink_direct tb_rlink_serport \
+            tb_rlink_tba_ttcombo tb_rlink_tba_eyemon
 #
 #
 .phony : all all_ssim all_tsim clean
diff --git a/rtl/vlib/rri/tb/cext_rriext.c b/rtl/vlib/rlink/tb/rlink_cext.c
similarity index 74%
rename from rtl/vlib/rri/tb/cext_rriext.c
rename to rtl/vlib/rlink/tb/rlink_cext.c
index 714a58ca..fe75a781 100644
--- a/rtl/vlib/rri/tb/cext_rriext.c
+++ b/rtl/vlib/rlink/tb/rlink_cext.c
@@ -1,6 +1,6 @@
-/* $Id: cext_rriext.c 314 2010-07-09 17:38:41Z mueller $
+/* $Id: rlink_cext.c 351 2010-12-30 21:50:54Z mueller $
  *
- * Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+ * Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
  *
  * This program is free software; you may redistribute and/or modify it under
  * the terms of the GNU General Public License as published by the Free
@@ -13,6 +13,9 @@
  *
  *  Revision History: 
  * Date         Rev  Vers    Comment
+ * 2010-12-29   351   1.3    rename cext_rriext -> rlink_cext; rename functions
+ *                           cext_* -> rlink_cext_* and fifo file names
+ *                           tb_cext_* -> rlink_cext_*
  * 2007-11-18    96   1.2    add 'read before write' logic to avoid deadlocks
  *                           under cygwin broken fifo (size=1 !) implementation
  * 2007-10-19    90   1.1    add trace option, controlled by setting an
@@ -58,11 +61,11 @@ static int  qr_err = EAGAIN;
    0 if EGAIN or 
  */
 
-static void cext_dotrace(const char *text, int dat)
+static void rlink_cext_dotrace(const char *text, int dat)
 {
   int i;
   int mask = 0x80;
-  printf("cext_rriext-I: %s   ", text);
+  printf("rlink_cext-I: %s   ", text);
   for (i=0; i<8; i++) {
     printf("%c", (dat&mask)?'1':'0' );
     mask >>= 1;
@@ -70,7 +73,7 @@ static void cext_dotrace(const char *text, int dat)
   printf("\n");
 }
 
-static void cext_doread()
+static void rlink_cext_doread()
 {
   char buf[1];
   ssize_t nbyte;
@@ -83,7 +86,7 @@ static void cext_doread()
   } else {
     qr_err = EAGAIN;
     if (qr_nb < QRBUFSIZE) {
-      if (io_trace) cext_dotrace("rcv8", (unsigned char) buf[0]);
+      if (io_trace) rlink_cext_dotrace("rcv8", (unsigned char) buf[0]);
       qr_buf[qr_pw++] = buf[0];
       if (qr_pw >= QRBUFSIZE) qr_pw = 0;
       qr_nb += 1;
@@ -93,7 +96,7 @@ static void cext_doread()
   }
 }
 
-int cext_getbyte(int clk)
+int rlink_cext_getbyte(int clk)
 {
   char buf[1];
   ssize_t nbyte;
@@ -107,36 +110,36 @@ int cext_getbyte(int clk)
   static int nside = -1;
 
   if (fd_rx < 0) {		/* fifo's not yet opened */
-    fd_rx = open("tb_rriext_fifo_rx", O_RDONLY|O_NONBLOCK);
+    fd_rx = open("rlink_cext_fifo_rx", O_RDONLY|O_NONBLOCK);
     if (fd_rx <= 0) {
-      perror("cext_rriext-E: failed to open tb_rriext_fifo_rx");
+      perror("rlink_cext-E: failed to open rlink_cext_fifo_rx");
       return -2;
     }
-    printf("cext_rriext-I: connected to tb_rriext_fifo_rx\n");
-    fd_tx = open("tb_rriext_fifo_tx", O_WRONLY);
+    printf("rlink_cext-I: connected to rlink_cext_fifo_rx\n");
+    fd_tx = open("rlink_cext_fifo_tx", O_WRONLY);
     if (fd_tx <= 0) {
-      perror("cext_rriext-E: failed to open tb_rriext_fifo_tx");
+      perror("rlink_cext-E: failed to open rlink_cext_fifo_tx");
       return -2;
     }
-    printf("cext_rriext-I: connected to tb_rriext_fifo_tx\n");
+    printf("rlink_cext-I: connected to rlink_cext_fifo_tx\n");
     nidle = 0;
     ncesc = 0;
     nside = -1;
 
     io_trace = 0;
-    env_val = getenv("CEXT_RRIEXT_TRACE");
+    env_val = getenv("RLINK_CEXT_TRACE");
     if (env_val && strcmp(env_val, "1") == 0) {
       io_trace = 1;
     }
     
   }
 
-  cext_doread();
+  rlink_cext_doread();
 
   if (qr_nb == 0) {		            /* no character to be processed */
     if (qr_eof != 0) {		            /* EOF seen */
       if (ncesc >= 2) {			    /*  two+ CESC seen  ? */
-	printf("cext_rriext-I: seen EOF, wait for reconnect\n");
+	printf("rlink_cext-I: seen EOF, wait for reconnect\n");
 	close(fd_rx);
 	close(fd_tx);
 	fd_rx = -1;
@@ -145,18 +148,18 @@ int cext_getbyte(int clk)
 	return 0x100;			    /* return idle, will reconnect */
       }
     
-      printf("cext_rriext-I: seen EOF, schedule clock stop and exit\n");
+      printf("rlink_cext-I: seen EOF, schedule clock stop and exit\n");
       return -1;			    /* signal EOF seen */
     } else if (qr_err == EAGAIN) {          /* nothing read, return idle */
       if (nidle < 8 || (nidle%1024)==0) {
 	irc = sched_yield();
-	if (irc < 0) perror("cext_rriext-W: sched_yield failed");
+	if (irc < 0) perror("rlink_cext-W: sched_yield failed");
       }
       nidle += 1;
       return 0x100;
     } else {			            /* must be a read error */
       errno = qr_err;
-      perror("cext_rriext-E: read error on tb_rriext_fifo_rx");
+      perror("rlink_cext-E: read error on rlink_cext_fifo_rx");
       return -3;
     }
   }
@@ -194,20 +197,20 @@ int cext_getbyte(int clk)
   }  
 }
 
-int cext_putbyte(int dat) 
+int rlink_cext_putbyte(int dat) 
 {
   char buf[1];
   ssize_t nbyte;
 
-  cext_doread();
+  rlink_cext_doread();
 
-  if (io_trace) cext_dotrace("snd8", dat);
+  if (io_trace) rlink_cext_dotrace("snd8", dat);
 
   buf[0] = (unsigned char) dat;
   nbyte = write(fd_tx, buf, 1);
 
   if (nbyte < 0) {
-    perror("cext_rriext-E: write error on tb_rriext_fifo_tx");
+    perror("rlink_cext-E: write error on rlink_cext_fifo_tx");
     return -3;
   }
 
diff --git a/rtl/vlib/rri/tb/vhpi_rriext.vhd b/rtl/vlib/rlink/tb/rlink_cext_vhpi.vhd
similarity index 55%
rename from rtl/vlib/rri/tb/vhpi_rriext.vhd
rename to rtl/vlib/rlink/tb/rlink_cext_vhpi.vhd
index 22f48955..d687544b 100644
--- a/rtl/vlib/rri/tb/vhpi_rriext.vhd
+++ b/rtl/vlib/rlink/tb/rlink_cext_vhpi.vhd
@@ -1,6 +1,6 @@
--- $Id: vhpi_rriext.vhd 314 2010-07-09 17:38:41Z mueller $
+-- $Id: rlink_cext_vhpi.vhd 351 2010-12-30 21:50:54Z mueller $
 --
--- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
 -- This program is free software; you may redistribute and/or modify it under
 -- the terms of the GNU General Public License as published by the Free
@@ -12,44 +12,47 @@
 -- for complete details.
 -- 
 ------------------------------------------------------------------------------
--- Package Name:   vhpi_rriext
+-- Package Name:   rlink_cext_vhpi
 -- Description:    VHDL procedural interface: VHDL declaration side
 --
 -- Dependencies:   -
--- Tool versions:  xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+-- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
 -- Revision History: 
 -- Date         Rev Version  Comment
+-- 2010-12-29   351   1.1    rename vhpi_rriext->rlink_cext_vhpi; new rbv3 names
 -- 2007-08-26    76   1.0    Initial version 
 ------------------------------------------------------------------------------
 
-package vhpi_rriext is
+package rlink_cext_vhpi is
 
-  impure function cext_getbyte (
+  impure function rlink_cext_getbyte (
     clk : integer)                      -- clock cycle
     return integer;
-  attribute foreign of cext_getbyte : function is "VHPIDIRECT cext_getbyte";
+  attribute foreign of rlink_cext_getbyte :
+    function is "VHPIDIRECT rlink_cext_getbyte";
   
-  impure function cext_putbyte (
+  impure function rlink_cext_putbyte (
     dat : integer)                      -- data byte
     return integer;
-  attribute foreign of cext_putbyte : function is "VHPIDIRECT cext_putbyte";
+  attribute foreign of rlink_cext_putbyte :
+    function is "VHPIDIRECT rlink_cext_putbyte";
 
-end vhpi_rriext;
+end rlink_cext_vhpi;
 
-package body vhpi_rriext is
+package body rlink_cext_vhpi is
 
-  impure function cext_getbyte (
+  impure function rlink_cext_getbyte (
     clk : integer)                      -- clock cycle
     return integer is
   begin
-    report "cext_getbyte not vhpi'ed" severity failure;
-  end cext_getbyte;
+    report "rlink_cext_getbyte not vhpi'ed" severity failure;
+  end rlink_cext_getbyte;
 
-  impure function cext_putbyte (
+  impure function rlink_cext_putbyte (
     dat : integer)                      -- data byte
     return integer is
   begin
-    report "cext_getbyte not vhpi'ed" severity failure;
-  end cext_putbyte;
+    report "rlink_cext_getbyte not vhpi'ed" severity failure;
+  end rlink_cext_putbyte;
 
-end vhpi_rriext;
+end rlink_cext_vhpi;
diff --git a/rtl/vlib/rlink/tb/rlinktblib.vhd b/rtl/vlib/rlink/tb/rlinktblib.vhd
new file mode 100644
index 00000000..b6b529ee
--- /dev/null
+++ b/rtl/vlib/rlink/tb/rlinktblib.vhd
@@ -0,0 +1,177 @@
+-- $Id: rlinktblib.vhd 351 2010-12-30 21:50:54Z mueller $
+--
+-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name:   rlinktblib
+-- Description:    rlink test environment components
+--
+-- Dependencies:   -
+-- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
+-- Revision History: 
+-- Date         Rev Version  Comment
+-- 2010-12-29   351   3.0.1  add rbtba_aif;
+-- 2010-12-24   347   3.0    rename rritblib->rlinktblib, CP_*->RL_*;
+--                           many rri->rlink renames; drop rbus parts;
+-- 2010-11-13   338   2.5.2  add rritb_core_dcm
+-- 2010-06-26   309   2.5.1  add rritb_sres_or_mon
+-- 2010-06-06   302   2.5    use sop/eop framing instead of soc+chaining
+-- 2010-06-05   301   2.1.2  renamed _rpmon -> _rbmon
+-- 2010-05-02   287   2.1.1  rename CE_XSEC->CE_INT,RP_STAT->RB_STAT
+--                           drop RP_IINT signal from interfaces
+--                           add sbcntl_sbf_(cp|rp)mon defs
+-- 2010-04-24   282   2.1    add rritb_core
+-- 2008-08-24   162   2.0    all with new rb_mreq/rb_sres interface
+-- 2008-03-24   129   1.1.5  CLK_CYCLE now 31 bits
+-- 2007-12-23   105   1.1.4  add AP_LAM  for rritb_rpmon(_sb)
+-- 2007-11-24    98   1.1.3  add RP_IINT for rritb_rpmon(_sb)
+-- 2007-09-01    78   1.1.2  add rricp_rp
+-- 2007-08-25    75   1.1.1  add rritb_cpmon_sb, rritb_rpmon_sb
+-- 2007-08-16    74   1.1    remove rritb_tt* component; some interface changes
+-- 2007-08-03    71   1.0.2  use rrirp_acif; change generics for rritb_[cr]pmon
+-- 2007-07-22    68   1.0.1  add rritb_cpmon rritb_rpmon monitors
+-- 2007-07-15    66   1.0    Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+use work.rlinklib.all;
+
+package rlinktblib is
+
+type rlink_tba_cntl_type is record      -- rlink_tba control
+  cmd : slv3;                           -- command code
+  ena : slbit;                          -- command enable
+  addr : slv8;                          -- address
+  cnt : slv8;                           -- block size
+  eop : slbit;                          -- end packet after current command
+end record rlink_tba_cntl_type;
+
+constant rlink_tba_cntl_init : rlink_tba_cntl_type := (
+           (others=>'0'),               -- cmd
+           '0',                         -- ena
+           (others=>'0'),               -- addr
+           (others=>'0'),               -- cnt
+           '0');                        -- eop
+           
+type rlink_tba_stat_type is record      -- rlink_tba status
+  busy : slbit;                         -- command busy
+  ack : slbit;                          -- command acknowledge
+  err : slbit;                          -- command error flag
+  stat : slv8;                          -- status flags
+  braddr : slv8;                        -- block read address  (for wblk)
+  bre : slbit;                          -- block read enable   (for wblk)
+  bwaddr : slv8;                        -- block write address (for rblk)
+  bwe : slbit;                          -- block write enable  (for rblk)
+  attnpend : slbit;                     -- attn pending
+  attnint : slbit;                      -- attn interrupt
+end record rlink_tba_stat_type;
+
+constant rlink_tba_stat_init : rlink_tba_stat_type := (
+           '0','0','0',                 -- busy, ack, err
+           (others=>'0'),               -- stat
+           (others=>'0'),               -- braddr
+           '0',                         -- bre
+           (others=>'0'),               -- bwaddr
+           '0',                         -- bwe
+           '0','0');                    -- attnpend, attnint
+
+component rlink_tba is                  -- rlink test bench adapter
+  port (
+    CLK  : in slbit;                    -- clock
+    RESET  : in slbit;                  -- reset
+    CNTL : in rlink_tba_cntl_type;      -- control port
+    DI : in slv16;                      -- input data
+    STAT : out rlink_tba_stat_type;     -- status port
+    DO : out slv16;                     -- output data
+    RL_DI : out slv9;                   -- rlink: data in
+    RL_ENA : out slbit;                 -- rlink: data enable
+    RL_BUSY : in slbit;                 -- rlink: data busy
+    RL_DO : in slv9;                    -- rlink: data out
+    RL_VAL : in slbit;                  -- rlink: data valid
+    RL_HOLD : out slbit                 -- rlink: data hold
+  );
+end component;
+
+component rbtba_aif is                  -- rbus tba, abstract interface
+                                        -- no generics, no records
+  port (
+    CLK  : in slbit;                    -- clock
+    RESET  : in slbit := '0';           -- reset
+    RB_MREQ_aval : in slbit;            -- rbus: request - aval
+    RB_MREQ_re : in slbit;              -- rbus: request - re
+    RB_MREQ_we : in slbit;              -- rbus: request - we
+    RB_MREQ_initt : in slbit;           -- rbus: request - init; avoid name coll
+    RB_MREQ_addr : in slv8;             -- rbus: request - addr
+    RB_MREQ_din : in slv16;             -- rbus: request - din
+    RB_SRES_ack : out slbit;            -- rbus: response - ack
+    RB_SRES_busy : out slbit;           -- rbus: response - busy
+    RB_SRES_err : out slbit;            -- rbus: response - err
+    RB_SRES_dout : out slv16;           -- rbus: response - dout
+    RB_LAM : out slv16;                 -- rbus: look at me
+    RB_STAT : out slv3                  -- rbus: status flags
+  );
+end component;
+
+component tbcore_rlink is               -- core of vhpi_cext based test bench
+  generic (
+    CLK_PERIOD : time :=  20 ns;        -- clock period
+    CLK_OFFSET : time := 200 ns;        -- clock offset (time to start clock)
+    SETUP_TIME : time :=   5 ns;        -- setup time
+    C2OUT_TIME : time :=  10 ns);       -- clock to output time
+  port (
+    CLK : out slbit;                    -- main clock
+    RX_DATA : out slv8;                 -- read data         (data ext->tb)
+    RX_VAL : out slbit;                 -- read data valid   (data ext->tb)
+    RX_HOLD : in slbit;                 -- read data hold    (data ext->tb)
+    TX_DATA : in slv8;                  -- write data        (data tb->ext)
+    TX_ENA : in slbit                   -- write data enable (data tb->ext)
+  );
+end component;
+
+component tbcore_rlink_dcm is           -- dcm aware core of vhpi_cext based tb
+  generic (
+    CLKOSC_PERIOD : time :=  20 ns;     -- clock osc period
+    CLKOSC_OFFSET : time := 200 ns;     -- clock osc offset (time to start clk)
+    SETUP_TIME : time :=   5 ns;        -- setup time
+    C2OUT_TIME : time :=  10 ns);       -- clock to output time
+  port (
+    CLKOSC : out slbit;                 -- clock osc
+    CLKSYS : in slbit;                  -- DCM derived system clock
+    RX_DATA : out slv8;                 -- read data         (data ext->tb)
+    RX_VAL : out slbit;                 -- read data valid   (data ext->tb)
+    RX_HOLD : in slbit;                 -- read data hold    (data ext->tb)
+    TX_DATA : in slv8;                  -- write data        (data tb->ext)
+    TX_ENA : in slbit                   -- write data enable (data tb->ext)
+  );
+end component;
+
+-- FIXME after this point !!
+
+component rricp_rp is                   -- rri comm->reg port aif forwarder
+                                        -- implements rricp_aif, uses rrirp_aif
+  port (
+    CLK  : in slbit;                    -- clock
+    CE_INT : in slbit := '0';           -- rri ito time unit clock enable
+    RESET  : in slbit :='0';            -- reset
+    RL_DI : in slv9;                    -- rlink: data in
+    RL_ENA : in slbit;                  -- rlink: data enable
+    RL_BUSY : out slbit;                -- rlink: data busy
+    RL_DO : out slv9;                   -- rlink: data out
+    RL_VAL : out slbit;                 -- rlink: data valid
+    RL_HOLD : in slbit := '0'           -- rlink: data hold
+  );
+end component;
+
+end rlinktblib;
diff --git a/rtl/vlib/rlink/tb/tb_rlink.vbom b/rtl/vlib/rlink/tb/tb_rlink.vbom
new file mode 100644
index 00000000..7be48ebc
--- /dev/null
+++ b/rtl/vlib/rlink/tb/tb_rlink.vbom
@@ -0,0 +1,23 @@
+# Not meant for direct top level usage. Used with 
+# tb_rlink_(direct|serport|...)[_ssim].vbom and config
+# lines to generate the different cases.
+#
+# libs
+../../slvtypes.vhd
+../../genlib/genlib.vhd
+../../comlib/comlib.vhd
+../../rbus/rblib.vhd
+../../rbus/rbdlib.vhd
+../rlinklib.vbom
+../../simlib/simlib.vhd
+../../simlib/simbus.vhd
+# components
+../../simlib/simclk.vbom
+../../genlib/clkdivce.vbom
+../../rbus/rbd_tester.vbom
+../../rbus/rb_mon.vbom
+../rlink_mon.vbom
+tbd_rlink_gen : tbd_rlink_direct.vbom
+# design
+tb_rlink.vhd
+@top:tb_rlink
diff --git a/rtl/vlib/rri/tb/tb_rri.vhd b/rtl/vlib/rlink/tb/tb_rlink.vhd
similarity index 54%
rename from rtl/vlib/rri/tb/tb_rri.vhd
rename to rtl/vlib/rlink/tb/tb_rlink.vhd
index b232779c..c3da5fc7 100644
--- a/rtl/vlib/rri/tb/tb_rri.vhd
+++ b/rtl/vlib/rlink/tb/tb_rlink.vhd
@@ -1,4 +1,4 @@
--- $Id: tb_rri.vhd 314 2010-07-09 17:38:41Z mueller $
+-- $Id: tb_rlink.vhd 351 2010-12-30 21:50:54Z mueller $
 --
 -- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -12,20 +12,34 @@
 -- for complete details.
 --
 ------------------------------------------------------------------------------
--- Module Name:    tb_rri - sim
--- Description:    Test bench for rri_core
+-- Module Name:    tb_rlink - sim
+-- Description:    Test bench for rlink_core
 --
 -- Dependencies:   simlib/simclk
 --                 genlib/clkdivce
---                 tbd_rri_gen [UUT]
+--                 rbus/tbd_tester
+--                 rbus/rb_mon
+--                 rlink/rlink_mon
+--                 tbd_rlink_gen [UUT]
 --
--- To test:        rri_core
---                 rri_serport
+-- To test:        rlink_core     (via tbd_rlink_direct)
+--                 rlink_base     (via tbd_rlink_serport)
+--                 rlink_serport  (via tbd_rlink_serport)
 --
 -- Target Devices: generic
--- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
+-- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
+--
 -- Revision History: 
 -- Date         Rev Version  Comment
+-- 2010-12-29   351   3.0.6  use new rbd_tester addr 111100xx (from 111101xx)
+-- 2010-12-26   348   3.0.5  use simbus to export clkcycle (for tbd_..serport)
+-- 2010-12-23   347   3.0.4  use rb_mon, rlink_mon directly; rename CP_*->RL_*
+-- 2010-12-22   346   3.0.3  add .rlmon and .rbmon commands
+-- 2010-12-21   345   3.0.2  rename commands .[rt]x... to [rt]x...;
+--                           add .[rt]x(idle|attn) cmds; remove 'bbbbbbbb' cmd
+-- 2010-12-12   344   3.0.1  add .attn again; add .txbad, .txoof; ren oob->oof
+-- 2010-12-05   343   3.0    rri->rlink renames; port to rbus V3 protocol;
+--                           use rbd_tester instead of sim target;
 -- 2010-06-06   302   2.5    use sop/eop framing instead of soc+chaining
 -- 2010-06-03   299   2.2.2  new init encoding (WE=0/1 int/ext);use sv_ prefix
 --                           for shared variables 
@@ -42,6 +56,41 @@
 -- 2007-10-12    88   1.0.1  avoid ieee.std_logic_unsigned, use cast to unsigned
 -- 2007-09-09    81   1.0    Initial version 
 ------------------------------------------------------------------------------
+-- command set:
+--   .reset                               assert RESET for 1 clk
+--   .rlmon ien                           enable rlink monitor
+--   .rbmon ien                           enable rbus monitor
+--   .wait n                              wait n clks
+--   .iowt n                              wait n clks for rlink i/o; auto-extend
+--   .attn dat(16)                        pulse attn lines with dat
+--   txsop                                send <sop>
+--   txeop                                send <eop>
+--   txnak                                send <nak>
+--   txidle                               send <idle>
+--   txattn                               send <attn>
+--   tx8   dat(8)                         send  8 bit value
+--   tx16  dat(16)                        send 16 bit value
+--   txcrc                                send crc
+--   txbad                                send bad (inverted) crc
+--   txc   cmd(8)                         send cmd - crc
+--   txca  cmd(8) addr(8)                 send cmd - addr - crc
+--   txcad cmd(8) addr(8) dat(16)         send cmd - addr - dl dh - crc
+--   txcac cmd(8) addr(8) cnt(8)          send cmd - addr - cnt - crc
+--   txoof dat(9)                         send out-of-frame symbol
+--   rxsop                                reset rx list; expect sop
+--   rxeop                                expect <eop>
+--   rxnak                                expect <nak>
+--   rxidle                               expect <idle>
+--   rxattn                               expect <attn>
+--   rx8   dat(8)                         expect  8 bit value
+--   rx16  dat(16)                        expect 16 bit value
+--   rxcrc                                expect crc
+--   rxcs  cmd(8) stat(8)                 expect cmd - stat - crc
+--   rxcds cmd(8) dat(16) stat(8)         expect cmd - dl dh - stat - crc
+--   rxccd cmd(8) ccmd(8) dat(16) stat(8) expect cmd - ccmd - dl dh - stat - crc
+--   rxoof dat(9)                         expect out-of-frame symbol
+--
+------------------------------------------------------------------------------
 
 library ieee;
 use ieee.std_logic_1164.all;
@@ -52,25 +101,29 @@ use std.textio.all;
 use work.slvtypes.all;
 use work.genlib.all;
 use work.comlib.all;
-use work.rrilib.all;
+use work.rblib.all;
+use work.rbdlib.all;
+use work.rlinklib.all;
 use work.simlib.all;
+use work.simbus.all;
 
-entity tb_rri is
-end tb_rri;
+entity tb_rlink is
+end tb_rlink;
 
-architecture sim of tb_rri is
+architecture sim of tb_rlink is
   
   signal CLK : slbit := '0';
   signal CE_USEC : slbit := '0';
   signal CE_MSEC : slbit := '0';
   signal RESET : slbit := '0';
-  signal CP_DI : slv9 := (others=>'0');
-  signal CP_ENA : slbit := '0';
-  signal CP_BUSY : slbit := '0';
-  signal CP_DO : slv9 := (others=>'0');
-  signal CP_VAL : slbit := '0';
-  signal CP_HOLD : slbit := '0';
-  signal RB_MREQ_req : slbit := '0';
+  signal RL_DI : slv9 := (others=>'0');
+  signal RL_ENA : slbit := '0';
+  signal RL_BUSY : slbit := '0';
+  signal RL_DO : slv9 := (others=>'0');
+  signal RL_VAL : slbit := '0';
+  signal RL_HOLD : slbit := '0';
+  signal RB_MREQ_aval : slbit := '0';
+  signal RB_MREQ_re : slbit := '0';
   signal RB_MREQ_we : slbit := '0';
   signal RB_MREQ_initt: slbit := '0';
   signal RB_MREQ_addr : slv8 := (others=>'0');
@@ -79,12 +132,19 @@ architecture sim of tb_rri is
   signal RB_SRES_busy : slbit := '0';
   signal RB_SRES_err : slbit := '0';
   signal RB_SRES_dout : slv16 := (others=>'0');
+  signal RB_LAM_TBENCH : slv16 := (others=>'0');
+  signal RB_LAM_TESTER : slv16 := (others=>'0');
   signal RB_LAM : slv16 := (others=>'0');
   signal RB_STAT : slv3 := (others=>'0');
   signal TXRXACT : slbit := '0';
+
+  signal RLMON_EN : slbit := '0';
+  signal RBMON_EN : slbit := '0';
+
+  signal RB_MREQ : rb_mreq_type := rb_mreq_init;
+  signal RB_SRES : rb_sres_type := rb_sres_init;
   
   signal CLK_STOP : slbit := '0';
-  signal CLK_CYCLE : slv31 := (others=>'0');
 
   constant slv9_zero  : slv9  := (others=>'0');
   constant slv16_zero : slv16 := (others=>'0');
@@ -101,19 +161,20 @@ architecture sim of tb_rri is
   constant setup_time : time :=  5 ns;
   constant c2out_time : time := 10 ns;
 
-component tbd_rri_gen is                -- rri, generic tb design interface
+component tbd_rlink_gen is              -- rlink, generic tb design interface
   port (
     CLK  : in slbit;                    -- clock
-    CE_INT : in slbit;                  -- rri ito time unit clock enable
+    CE_INT : in slbit;                  -- rlink ito time unit clock enable
     CE_USEC : in slbit;                 -- 1 usec clock enable
     RESET  : in slbit;                  -- reset
-    CP_DI : in slv9;                    -- comm port: data in
-    CP_ENA : in slbit;                  -- comm port: data enable
-    CP_BUSY : out slbit;                -- comm port: data busy
-    CP_DO : out slv9;                   -- comm port: data out
-    CP_VAL : out slbit;                 -- comm port: data valid
-    CP_HOLD : in slbit;                 -- comm port: data hold
-    RB_MREQ_req : out slbit;            -- rbus: request - req
+    RL_DI : in slv9;                    -- rlink: data in
+    RL_ENA : in slbit;                  -- rlink: data enable
+    RL_BUSY : out slbit;                -- rlink: data busy
+    RL_DO : out slv9;                   -- rlink: data out
+    RL_VAL : out slbit;                 -- rlink: data valid
+    RL_HOLD : in slbit;                 -- rlink: data hold
+    RB_MREQ_aval : out slbit;           -- rbus: request - aval
+    RB_MREQ_re : out slbit;             -- rbus: request - re
     RB_MREQ_we : out slbit;             -- rbus: request - we
     RB_MREQ_initt: out slbit;           -- rbus: request - init; avoid name coll
     RB_MREQ_addr : out slv8;            -- rbus: request - addr
@@ -136,7 +197,7 @@ begin
       OFFSET => clock_offset)
     port map (
       CLK       => CLK,
-      CLK_CYCLE => CLK_CYCLE,
+      CLK_CYCLE => SB_CLKCYCLE,
       CLK_STOP  => CLK_STOP
     );
 
@@ -152,19 +213,74 @@ begin
       CE_MSEC => CE_MSEC
     );
 
-  UUT : tbd_rri_gen
+  RB_MREQ.aval <= RB_MREQ_aval;
+  RB_MREQ.re   <= RB_MREQ_re;
+  RB_MREQ.we   <= RB_MREQ_we;
+  RB_MREQ.init <= RB_MREQ_initt;
+  RB_MREQ.addr <= RB_MREQ_addr;
+  RB_MREQ.din  <= RB_MREQ_din;
+
+  RB_SRES_ack   <= RB_SRES.ack;
+  RB_SRES_busy  <= RB_SRES.busy;
+  RB_SRES_err   <= RB_SRES.err;
+  RB_SRES_dout  <= RB_SRES.dout;
+
+  RBTEST : rbd_tester
+    generic map (
+      RB_ADDR => conv_std_logic_vector(2#11110000#,8))
+    port map (
+      CLK      => CLK,
+      RESET    => '0',
+      RB_MREQ  => RB_MREQ,
+      RB_SRES  => RB_SRES,
+      RB_LAM   => RB_LAM_TESTER,
+      RB_STAT  => RB_STAT
+    );
+
+  RB_LAM <= RB_LAM_TESTER or RB_LAM_TBENCH;
+    
+  RLMON : rlink_mon
+    generic map (
+      DWIDTH => RL_DI'length)
+    port map (
+      CLK       => CLK,
+      CLK_CYCLE => SB_CLKCYCLE,
+      ENA       => RLMON_EN,
+      RL_DI     => RL_DI,
+      RL_ENA    => RL_ENA,
+      RL_BUSY   => RL_BUSY,
+      RL_DO     => RL_DO,
+      RL_VAL    => RL_VAL,
+      RL_HOLD   => RL_HOLD
+    );
+
+  RBMON : rb_mon
+    generic map (
+      DBASE  => 2)
+    port map (
+      CLK       => CLK,
+      CLK_CYCLE => SB_CLKCYCLE,
+      ENA       => RBMON_EN,
+      RB_MREQ   => RB_MREQ,
+      RB_SRES   => RB_SRES,
+      RB_LAM    => RB_LAM,
+      RB_STAT   => RB_STAT
+    );
+
+  UUT : tbd_rlink_gen
     port map (
       CLK          => CLK,
       CE_INT       => CE_MSEC,
       CE_USEC      => CE_USEC,
       RESET        => RESET,
-      CP_DI        => CP_DI,
-      CP_ENA       => CP_ENA,
-      CP_BUSY      => CP_BUSY,
-      CP_DO        => CP_DO,
-      CP_VAL       => CP_VAL,
-      CP_HOLD      => CP_HOLD,
-      RB_MREQ_req  => RB_MREQ_req,
+      RL_DI        => RL_DI,
+      RL_ENA       => RL_ENA,
+      RL_BUSY      => RL_BUSY,
+      RL_DO        => RL_DO,
+      RL_VAL       => RL_VAL,
+      RL_HOLD      => RL_HOLD,
+      RB_MREQ_aval => RB_MREQ_aval,
+      RB_MREQ_re   => RB_MREQ_re,
       RB_MREQ_we   => RB_MREQ_we,
       RB_MREQ_initt=> RB_MREQ_initt,
       RB_MREQ_addr => RB_MREQ_addr,
@@ -178,18 +294,18 @@ begin
       TXRXACT      => TXRXACT
     );
 
-
   proc_stim: process
-    file fstim : text open read_mode is "tb_rri_stim";
+    file fstim : text open read_mode is "tb_rlink_stim";
     variable iline : line;
     variable oline : line;
+    variable ien   : slbit := '0';
     variable icmd  : slv8 := (others=>'0');
     variable iaddr : slv8 := (others=>'0');
     variable icnt  : slv8 := (others=>'0');
     variable istat : slv3 := (others=>'0');
-    variable iattn : slv8 := (others=>'0');
+    variable iattn : slv16 := (others=>'0');
     variable idata : slv16 := (others=>'0');
-    variable ioob  : slv9 := (others=>'0');
+    variable ioof  : slv9 := (others=>'0');
     variable ok : boolean;
     variable dname : string(1 to 6) := (others=>' ');
     variable idelta : integer := 0;
@@ -228,7 +344,7 @@ begin
     begin
       if sv_rxind < sv_nrxlist then
         for i in sv_rxind to sv_nrxlist-1 loop
-          writetimestamp(oline, CLK_CYCLE, ": moni ");
+          writetimestamp(oline, SB_CLKCYCLE, ": moni ");
           write(oline, string'("  FAIL MISSING DATA="));
           write(oline, sv_rxlist(i)(8));
           write(oline, string'(" "));
@@ -250,7 +366,8 @@ begin
       readcomment(iline, ok);
       next file_loop when ok;
 
-      readcommand(iline, dname, ok);
+      readword(iline, dname, ok);
+      
       if ok then
         case dname is
           when ".reset" =>              -- .reset 
@@ -261,6 +378,16 @@ begin
             RESET <= '0';
             wait for 9*clock_period;
 
+          when ".rlmon" =>              -- .rlmon
+            read_ea(iline, ien);
+            RLMON_EN <= ien;
+            wait for 2*clock_period;      -- wait for monitor to start
+
+          when ".rbmon" =>              -- .rbmon
+            read_ea(iline, ien);
+            RBMON_EN <= ien;
+            wait for 2*clock_period;      -- wait for monitor to start
+
           when ".wait " =>              -- .wait
             read_ea(iline, idelta);
             wait for idelta*clock_period;
@@ -277,49 +404,58 @@ begin
               wait for clock_period;
             end loop;
 
-          when ".stat " =>              -- .stat
-            read_ea(iline, istat);
-            RB_STAT <= istat;             -- set ext. status lines
-            wait for clock_period;        -- ensure some setling
-
           when ".attn " =>              -- .attn
             read_ea(iline, iattn);
-            RB_LAM(7 downto 0) <= iattn;  -- pulse lsb attn lines
-            wait for clock_period;                     -- for 1 clock
-            RB_LAM(7 downto 0) <= (others=>'0');
+            RB_LAM_TBENCH <= iattn;       -- pulse attn lines
+            wait for clock_period;        -- for 1 clock
+            RB_LAM_TBENCH <= (others=>'0');
 
-          when ".txsop" =>              -- .txsop  send sop
-            txlist(0) := c_rri_dat_sop;
+          when "txsop " =>              -- txsop   send sop
+            txlist(0) := c_rlink_dat_sop;
             ntxlist := 1;
             txcrc := (others=>'0');
-          when ".txeop" =>              -- .txeop  send eop
-            txlist(0) := c_rri_dat_eop;
+          when "txeop " =>              -- txeop   send eop
+            txlist(0) := c_rlink_dat_eop;
             ntxlist := 1;
             txcrc := (others=>'0');
-          when ".txnak" =>              -- .txnak  send nak
-            txlist(0) := c_rri_dat_nak;
+
+          when "txnak " =>              -- txnak   send nak
+            txlist(0) := c_rlink_dat_nak;
             ntxlist := 1;
             txcrc := (others=>'0');
-          when ".tx8  " =>              -- .tx8    send 8 bit value
+
+          when "txidle" =>              -- txidle  send idle
+            txlist(0) := c_rlink_dat_idle;
+            ntxlist := 1;
+          when "txattn" =>              -- txattn  send attn
+            txlist(0) := c_rlink_dat_attn;
+            ntxlist := 1;
+
+          when "tx8   " =>              -- tx8     send 8 bit value
             read_ea(iline, iaddr);
             ntxlist := 0;
             do_tx8(iaddr);
-          when ".tx16 " =>              -- .tx16   send 16 bit value
+          when "tx16  " =>              -- tx16    send 16 bit value
             read_ea(iline, idata);
             ntxlist := 0;
             do_tx16(idata);
-          when ".txcrc" =>              -- .txcrc  send crc  
+
+          when "txcrc " =>              -- txcrc   send crc  
             txlist(0) := '0' & txcrc;
             ntxlist := 1;
 
-          when ".txc  " =>              -- .txc    send: cmd crc
+          when "txbad " =>              -- txbad   send bad crc  
+            txlist(0) := '0' & (not txcrc);
+            ntxlist := 1;
+
+          when "txc   " =>              -- txc     send: cmd crc
             read_ea(iline, icmd);
             ntxlist := 0;
             do_tx8(icmd);
             txlist(ntxlist) := '0' & txcrc;
             ntxlist := ntxlist + 1;
 
-          when ".txca " =>              -- .txc    send: cmd addr crc
+          when "txca  " =>              -- txc     send: cmd addr crc
             read_ea(iline, icmd);
             read_ea(iline, iaddr);
             ntxlist := 0;
@@ -328,7 +464,7 @@ begin
             txlist(ntxlist) := '0' & txcrc;
             ntxlist := ntxlist + 1;
 
-          when ".txcad" =>              -- .txc    send: cmd addr data crc
+          when "txcad " =>              -- txc     send: cmd addr data crc
             read_ea(iline, icmd);
             read_ea(iline, iaddr);
             read_ea(iline, idata);
@@ -339,7 +475,7 @@ begin
             txlist(ntxlist) := '0' & txcrc;
             ntxlist := ntxlist + 1;
 
-          when ".txcac" =>              -- .txc    send: cmd addr cnt crc
+          when "txcac " =>              -- txc     send: cmd addr cnt crc
             read_ea(iline, icmd);
             read_ea(iline, iaddr);
             read_ea(iline, icnt);
@@ -350,29 +486,42 @@ begin
             txlist(ntxlist) := '0' & txcrc;
             ntxlist := ntxlist + 1;
 
-          when ".rxsop" =>              -- .rxsop  expect sop
+          when "txoof " =>              -- txoof   send out-of-frame symbol
+            read_ea(iline, txlist(0));
+            ntxlist := 1;
+            
+          when "rxsop " =>              -- rxsop   expect sop
             checkmiss_rx;
-            sv_rxlist(0) := c_rri_dat_sop;
+            sv_rxlist(0) := c_rlink_dat_sop;
             sv_nrxlist := 1;
             sv_rxind := 0;
             rxcrc := (others=>'0');
-          when ".rxeop" =>              -- .rxeop  expect eop
-            sv_rxlist(sv_nrxlist) := c_rri_dat_eop;
+          when "rxeop " =>              -- rxeop   expect eop
+            sv_rxlist(sv_nrxlist) := c_rlink_dat_eop;
             sv_nrxlist := sv_nrxlist + 1;
-          when ".rxnak" =>              -- .rxnak  expect nak
-            sv_rxlist(sv_nrxlist) := c_rri_dat_nak;
+
+          when "rxnak " =>              -- rxnak   expect nak
+            sv_rxlist(sv_nrxlist) := c_rlink_dat_nak;
             sv_nrxlist := sv_nrxlist + 1;
-          when ".rx8  " =>              -- .rx8    expect 8 bit value
+          when "rxidle" =>              -- rxidle  expect idle
+            sv_rxlist(sv_nrxlist) := c_rlink_dat_idle;
+            sv_nrxlist := sv_nrxlist + 1;
+          when "rxattn" =>              -- rxattn  expect attn
+            sv_rxlist(sv_nrxlist) := c_rlink_dat_attn;
+            sv_nrxlist := sv_nrxlist + 1;
+
+          when "rx8   " =>              -- rx8     expect 8 bit value
             read_ea(iline, iaddr);
             do_rx8(iaddr);
-          when ".rx16 " =>              -- .rx16   expect 16 bit value
+          when "rx16  " =>              -- rx16    expect 16 bit value
             read_ea(iline, idata);
             do_rx16(idata);
-          when ".rxcrc" =>              -- .rxcrc  expect crc
+
+          when "rxcrc " =>              -- rxcrc   expect crc
             sv_rxlist(sv_nrxlist) := '0' & rxcrc;
             sv_nrxlist := sv_nrxlist+1;
 
-          when ".rxcs " =>              -- .rxcs   expect: cmd stat crc
+          when "rxcs  " =>              -- rxcs    expect: cmd stat crc
             read_ea(iline, icmd);
             read_ea(iline, iaddr);
             do_rx8(icmd);
@@ -380,7 +529,7 @@ begin
             sv_rxlist(sv_nrxlist) := '0' & rxcrc;
             sv_nrxlist := sv_nrxlist + 1;
 
-          when ".rxcds" =>              -- .rxcsd  expect: cmd data stat crc
+          when "rxcds " =>              -- rxcsd   expect: cmd data stat crc
             read_ea(iline, icmd);
             read_ea(iline, idata); 
             read_ea(iline, iaddr);
@@ -390,7 +539,7 @@ begin
             sv_rxlist(sv_nrxlist) := '0' & rxcrc;
             sv_nrxlist := sv_nrxlist + 1;
 
-          when ".rxccd" =>              -- .rxccd  expect: cmd ccmd dat stat crc
+          when "rxccd " =>              -- rxccd   expect: cmd ccmd dat stat crc
             read_ea(iline, icmd);
             read_ea(iline, icnt);
             read_ea(iline, idata); 
@@ -402,45 +551,43 @@ begin
             sv_rxlist(sv_nrxlist) := '0' & rxcrc;
             sv_nrxlist := sv_nrxlist + 1;
 
-          when ".rxoob" =>              -- .rxoob  expect: out-of-band symbol
-            read_ea(iline, ioob);
-            sv_rxlist(sv_nrxlist) := ioob;
+          when "rxoof " =>              -- rxoof   expect: out-of-frame symbol
+            read_ea(iline, ioof);
+            sv_rxlist(sv_nrxlist) := ioof;
             sv_nrxlist := sv_nrxlist + 1;
 
-          when others =>                -- bad directive
-            write(oline, string'("?? unknown directive: "));
+          when others =>                -- bad command
+            write(oline, string'("?? unknown command: "));
             write(oline, dname);
             writeline(output, oline);
             report "aborting" severity failure;
         end case;
 
       else
-        read_ea(iline, txlist(0));
-        ntxlist := 1;
-
+        report "failed to find command" severity failure;
       end if;
 
       next file_loop when ntxlist=0;
       
       for i in 0 to ntxlist-1 loop
         
-        CP_DI <= txlist(i);
-        CP_ENA <= '1';
+        RL_DI <= txlist(i);
+        RL_ENA <= '1';
 
-        writetimestamp(oline, CLK_CYCLE, ": stim ");
+        writetimestamp(oline, SB_CLKCYCLE, ": stim");
         write(oline, txlist(i)(8), right, 3);
         write(oline, txlist(i)(7 downto 0), right, 9);
         if txlist(i)(8) = '1' then
           case txlist(i) is
-            when c_rri_dat_idle =>
+            when c_rlink_dat_idle =>
               write(oline, string'(" (idle)"));
-            when c_rri_dat_sop =>
+            when c_rlink_dat_sop =>
               write(oline, string'(" (sop) "));
-            when c_rri_dat_eop =>
+            when c_rlink_dat_eop =>
               write(oline, string'(" (eop) "));
-            when c_rri_dat_nak =>
+            when c_rlink_dat_nak =>
               write(oline, string'(" (nak) "));
-            when c_rri_dat_attn =>
+            when c_rlink_dat_attn =>
               write(oline, string'(" (attn)"));
             when others => 
               write(oline, string'(" (????)"));
@@ -449,10 +596,10 @@ begin
         writeline(output, oline);
       
         wait for clock_period;
-        while CP_BUSY = '1' loop
+        while RL_BUSY = '1' loop
           wait for clock_period;
         end loop;
-        CP_ENA <= '0';
+        RL_ENA <= '0';
       
       end loop;  -- i
 
@@ -463,7 +610,7 @@ begin
     wait for 50*clock_period;
 
     checkmiss_rx;
-    writetimestamp(oline, CLK_CYCLE, ": DONE ");
+    writetimestamp(oline, SB_CLKCYCLE, ": DONE ");
     writeline(output, oline);
 
     CLK_STOP <= '1';
@@ -482,21 +629,21 @@ begin
       wait until CLK'event and CLK='1';
       wait for c2out_time;
 
-      if CP_VAL = '1' then
-        writetimestamp(oline, CLK_CYCLE, ": moni ");
-        write(oline, CP_DO(8), right, 3);
-        write(oline, CP_DO(7 downto 0), right, 9);
-        if CP_DO(8) = '1' then
-          case CP_DO is
-            when c_rri_dat_idle =>
+      if RL_VAL = '1' then
+        writetimestamp(oline, SB_CLKCYCLE, ": moni");
+        write(oline, RL_DO(8), right, 3);
+        write(oline, RL_DO(7 downto 0), right, 9);
+        if RL_DO(8) = '1' then
+          case RL_DO is
+            when c_rlink_dat_idle =>
               write(oline, string'(" (idle)"));
-            when c_rri_dat_sop =>
+            when c_rlink_dat_sop =>
               write(oline, string'(" (sop) "));
-            when c_rri_dat_eop =>
+            when c_rlink_dat_eop =>
               write(oline, string'(" (eop) "));
-            when c_rri_dat_nak =>
+            when c_rlink_dat_nak =>
               write(oline, string'(" (nak) "));
-            when c_rri_dat_attn =>
+            when c_rlink_dat_attn =>
               write(oline, string'(" (attn)"));
             when others => 
               write(oline, string'(" (????)"));
@@ -505,7 +652,7 @@ begin
         if sv_nrxlist > 0 then
           write(oline, string'("  CHECK"));
           if sv_rxind < sv_nrxlist then
-            if CP_DO = sv_rxlist(sv_rxind) then
+            if RL_DO = sv_rxlist(sv_rxind) then
               write(oline, string'(" OK"));
             else
               write(oline, string'(" FAIL, exp="));
@@ -524,197 +671,4 @@ begin
     
   end process proc_moni;
 
-
--- simulated target:
---    00000000 ... 00111111:  64 registers, no wait states
---    00010000             :  (16) pointer register for mem 0
---    00010001             :  (17) pointer register for mem 1
---    00010010             :  (18) counter for init's
---    01000000 ... 01111111:  64 registers, addr(5 downto 0)+1 wait states
---    10000000             :  256 word memory, addressed by reg(00010000)
---    10000001             :  256 word memory, addressed by reg(00010001)
---    10000010             :  ping RB_LAM(15 downto 8) on WE access
---    11000000             :  signal err, write noop, read 10101010
---    others               :  no ack
--- 
-
-  proc_targ: process
-    variable reg0 : slv16_array_type := (others=>slv16_zero);
-    variable reg1 : slv16_array_type := (others=>slv16_zero);
-    variable mem0 : slv16_array_type := (others=>slv16_zero);
-    variable mem1 : slv16_array_type := (others=>slv16_zero);
-    variable iack : slbit := '0';
-    variable ierr : slbit := '0';
-    variable nhold : integer := 0;
-    variable addr  : slv8 := (others=>'0');
-    variable idout : slv16 := (others=>'0');
-    variable ind   : integer := 0;
-    variable oline : line;
-
-    constant c2out_setup : time := clock_period-c2out_time-setup_time;
-
-    type acc_type is (acc_reg0, acc_reg1, acc_mem0, acc_mem1, acc_lam,
-                      acc_err, acc_bad);
-    variable acc : acc_type := acc_bad;
-
-    procedure write_data (pref : in string;
-                          data : in slv16;
-                          iack : in slbit;
-                          ierr : in slbit;
-                          nhold : in integer)  is
-      variable oline : line;
-    begin
-      writetimestamp(oline, CLK_CYCLE, pref);
-      write(oline, RB_MREQ_addr, right, 10);
-      write(oline, data, right, 18);
-      if nhold > 0 then
-        write(oline, string'("  nhold="));
-        write(oline, nhold, right, 2);        
-      end if;
-      if iack = '0' then
-        write(oline, string'("  ACK=0"));
-      end if;
-      if ierr = '1' then
-        write(oline, string'("  ERR=1"));
-      end if;
-      writeline(output, oline);     
-   end procedure write_data;
-
-  begin
-
---    assert c2out_setup>0 report "assert(x>0)" severity FAILURE;
-    
-    wait until CLK'event and CLK='1';
-    wait for c2out_time;
-
-    RB_SRES_ack  <= '0';
-    RB_SRES_busy <= '0';
-    RB_SRES_err  <= '0';
-    RB_SRES_dout <= (others=>'1');
-
-    addr  := RB_MREQ_addr;
-    idout := (others=>'0');
-    nhold := 0;
-
-    acc := acc_bad;
-    if unsigned(addr) <= 2#00111111# then
-      acc := acc_reg0;
-    elsif unsigned(addr) <= 2#01111111# then
-      acc := acc_reg1;
-      nhold := conv_integer(unsigned(addr and "00111111")) + 1;
-    elsif unsigned(addr) = 2#10000000# then
-      acc := acc_mem0;
-    elsif unsigned(addr) = 2#10000001# then
-      acc := acc_mem1;
-    elsif unsigned(addr) = 2#10000010# then
-      acc := acc_lam;
-    elsif unsigned(addr) = 2#11000000# then
-      acc := acc_err;
-    end if;
-
-    iack := '1';
-    ierr := '0';
-    
-    if acc = acc_bad then               -- if bad address
-      iack := '0';                        -- don't acknowledge
-    end if;
-
-    RB_SRES_ack  <= iack;
-
-    RB_LAM(15 downto 8) <= (others=>'0');
-    
-    if RB_MREQ_req = '1' then
-      
-      -- handle WE transactions
-      if RB_MREQ_we  ='1' then
-        case acc is
-          when acc_reg0 =>
-            reg0(conv_integer(unsigned(addr))) := RB_MREQ_din;
-          when acc_reg1 =>
-            reg1(conv_integer(unsigned(addr))) := RB_MREQ_din;
-          when acc_mem0 =>
-            ind := conv_integer(unsigned(reg0(16) and X"00ff"));
-            mem0(ind) := RB_MREQ_din;
-            reg0(16) := unsigned(reg0(16)) + 1;
-          when acc_mem1 =>
-            ind := conv_integer(unsigned(reg0(17) and X"00ff"));
-            mem1(ind) := RB_MREQ_din;
-            reg0(17) := unsigned(reg0(17)) + 1;
-          when acc_lam =>
-            RB_LAM(15 downto 8) <= RB_MREQ_din(15 downto 8);
-            writetimestamp(oline, CLK_CYCLE,
-                         ": targ w ap_lam(15 downto 8) pinged");
-            writeline(output, oline);     
-          when acc_err =>
-            ierr := '1';
-          when others => null;
-        end case;
-      
-        write_data(": targ w ", RB_MREQ_din, iack, ierr, nhold);
-
-        while nhold>0 and RB_MREQ_req='1' loop
-          RB_SRES_busy <= '1';
-          wait for clock_period;
-          nhold := nhold - 1;
-        end loop;
-        RB_SRES_ack  <= iack;
-        RB_SRES_err  <= ierr;
-        RB_SRES_busy <= '0';
-
-      -- handle RE transactions
-      else
-        case acc is
-          when acc_reg0 =>
-            idout := reg0(conv_integer(unsigned(addr)));
-          when acc_reg1 =>
-            idout := reg1(conv_integer(unsigned(addr)));
-          when acc_mem0 =>
-            ind := conv_integer(unsigned(reg0(16) and X"00ff"));
-            idout := mem0(ind);
-            reg0(16) := unsigned(reg0(16)) + 1;
-          when acc_mem1 =>
-            ind := conv_integer(unsigned(reg0(17) and X"00ff"));
-            idout := mem1(ind);
-            reg0(17) := unsigned(reg0(17)) + 1;
-          when acc_err =>
-            ierr := '1';
-            idout := "1010101010101010";
-          when acc_bad =>
-            idout := "1010101010101010";
-          when others => null;
-        end case;
-      
-        write_data(": targ r ", idout, iack, ierr, nhold);
-
-        RB_SRES_dout <= "0101010101010101";
-        wait for c2out_setup;
-
-        while nhold>0 and RB_MREQ_req='1' loop
-          RB_SRES_busy <= '1';
-          wait for clock_period;
-          nhold := nhold - 1;
-        end loop;
-        RB_SRES_ack  <= iack;
-        RB_SRES_err  <= ierr;
-        RB_SRES_busy <= '0';
-
-        RB_SRES_dout <= idout;
-      
-      end if;
-    end if;
-
-    -- handle INIT transactions (ext and int) (just for monitoring...)
-    
-    if RB_MREQ_initt = '1' then
-      if RB_MREQ_we = '1' then          -- ext init
-        write_data(": targ i ", RB_MREQ_din, '1', '0', 0);
-        reg0(18) := unsigned(reg0(18)) + 1;
-      else                              -- int init
-        write_data(": iint   ", RB_MREQ_din, '1', '0', 0);
-      end if;
-    end if;
-
-  end process proc_targ;
-
-
 end sim;
diff --git a/rtl/vlib/rlink/tb/tb_rlink_direct.vbom b/rtl/vlib/rlink/tb/tb_rlink_direct.vbom
new file mode 100644
index 00000000..76587270
--- /dev/null
+++ b/rtl/vlib/rlink/tb/tb_rlink_direct.vbom
@@ -0,0 +1,6 @@
+# configure tb_rlink with tbd_rlink_direct wrapper
+# use vhdl configure file (tb_rlink_direct.vhd) at allow 
+# that all configurations will co-exist in work library
+tbd_rlink_gen = tbd_rlink_direct.vbom
+tb_rlink.vbom
+tb_rlink_direct.vhd
diff --git a/rtl/vlib/rri/tb/tb_rri_core.vhd b/rtl/vlib/rlink/tb/tb_rlink_direct.vhd
similarity index 71%
rename from rtl/vlib/rri/tb/tb_rri_core.vhd
rename to rtl/vlib/rlink/tb/tb_rlink_direct.vhd
index 4cee273d..6144da2d 100644
--- a/rtl/vlib/rri/tb/tb_rri_core.vhd
+++ b/rtl/vlib/rlink/tb/tb_rlink_direct.vhd
@@ -1,6 +1,6 @@
--- $Id: tb_rri_core.vhd 314 2010-07-09 17:38:41Z mueller $
+-- $Id: tb_rlink_direct.vhd 343 2010-12-05 21:24:38Z mueller $
 --
--- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
 -- This program is free software; you may redistribute and/or modify it under
 -- the terms of the GNU General Public License as published by the Free
@@ -12,16 +12,16 @@
 -- for complete details.
 --
 ------------------------------------------------------------------------------
--- Module Name:    tb_rri_core
--- Description:    Configuration for tb_rri_core for tb_rri.
+-- Module Name:    tb_rlink_direct
+-- Description:    Configuration for tb_rlink_direct for tb_rlink.
 --
--- Dependencies:   tbd_rri_gen
+-- Dependencies:   tbd_rlink_gen
 --
--- To test:        rri_core
+-- To test:        rlink_core
 --
 -- Target Devices: generic
 --
--- Verified (with tb_rri_stim.dat):
+-- Verified (with tb_rlink_stim.dat):
 -- Date         Rev  Code  ghdl  ise          Target     Comment
 -- 2007-11-02    93  _tsim 0.26  8.2.03 I34   xc3s1000   d:ok
 -- 2007-10-12    88  _ssim 0.26  8.1.03 I27   xc3s1000   c:ok
@@ -33,12 +33,12 @@
 -- 2007-07-08    65   1.0    Initial version 
 ------------------------------------------------------------------------------
 
-configuration tb_rri_core of tb_rri is
+configuration tb_rlink_direct of tb_rlink is
 
   for sim
-    for all : tbd_rri_gen
-      use entity work.tbd_rri_core;
+    for all : tbd_rlink_gen
+      use entity work.tbd_rlink_direct;
     end for;
   end for;
 
-end tb_rri_core;
+end tb_rlink_direct;
diff --git a/rtl/vlib/rlink/tb/tb_rlink_direct_ssim.vbom b/rtl/vlib/rlink/tb/tb_rlink_direct_ssim.vbom
new file mode 100644
index 00000000..e21b443f
--- /dev/null
+++ b/rtl/vlib/rlink/tb/tb_rlink_direct_ssim.vbom
@@ -0,0 +1,4 @@
+# configure tb_rlink with tbd_rlink_direct wrapper; _*sim case
+tbd_rlink_gen = tbd_rlink_direct_ssim.vhd
+tb_rlink_direct.vbom
+@top : tb_rlink_direct
diff --git a/rtl/vlib/rlink/tb/tb_rlink_serport.vbom b/rtl/vlib/rlink/tb/tb_rlink_serport.vbom
new file mode 100644
index 00000000..1a080d36
--- /dev/null
+++ b/rtl/vlib/rlink/tb/tb_rlink_serport.vbom
@@ -0,0 +1,6 @@
+# configure tb_rlink with tbd_rlink_serport wrapper;
+# use vhdl configure file (tb_rlink_serport.vhd) to allow 
+# that all configurations will co-exist in work library
+tbd_rlink_gen = tbd_rlink_serport.vbom
+tb_rlink.vbom
+tb_rlink_serport.vhd
diff --git a/rtl/vlib/rri/tb/tb_rri_serport.vhd b/rtl/vlib/rlink/tb/tb_rlink_serport.vhd
similarity index 67%
rename from rtl/vlib/rri/tb/tb_rri_serport.vhd
rename to rtl/vlib/rlink/tb/tb_rlink_serport.vhd
index 90932802..9d66b81f 100644
--- a/rtl/vlib/rri/tb/tb_rri_serport.vhd
+++ b/rtl/vlib/rlink/tb/tb_rlink_serport.vhd
@@ -1,6 +1,6 @@
--- $Id: tb_rri_serport.vhd 314 2010-07-09 17:38:41Z mueller $
+-- $Id: tb_rlink_serport.vhd 343 2010-12-05 21:24:38Z mueller $
 --
--- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
 -- This program is free software; you may redistribute and/or modify it under
 -- the terms of the GNU General Public License as published by the Free
@@ -12,33 +12,34 @@
 -- for complete details.
 --
 ------------------------------------------------------------------------------
--- Module Name:    tb_rri_serport
--- Description:    Configuration for tb_rri_serport for tb_rri.
+-- Module Name:    tb_rlink_serport
+-- Description:    Configuration for tb_rlink_serport for tb_rlink.
 --
--- Dependencies:   tbd_rri_gen
+-- Dependencies:   tbd_rlink_gen
 --
--- To test:        rri_serport
---                 rri_core
+-- To test:        rlink_serport
+--                 rlink_core
 --
 -- Target Devices: generic
 --
--- Verified (with tb_rri_stim.dat):
+-- Verified (with tb_rlink_stim.dat):
 -- Date         Rev  Code  ghdl  ise          Target     Comment
 -- 2007-10-12    88  _ssim 0.26  8.1.03 I27   xc3s1000   c:ok (Test 15 fails)
 -- 2007-10-12    88  -     0.26  -            -          c:ok (Test 15 fails)
 -- 
 -- Revision History: 
 -- Date         Rev Version  Comment
+-- 2010-12-05   343   3.0    rri->rlink renames
 -- 2007-11-25    98   1.0.1  use entity rather arch name to switch core/serport
 -- 2007-07-08    65   1.0    Initial version 
 ------------------------------------------------------------------------------
 
-configuration tb_rri_serport of tb_rri is
+configuration tb_rlink_serport of tb_rlink is
 
   for sim
-    for all : tbd_rri_gen
-      use entity work.tbd_rri_serport;
+    for all : tbd_rlink_gen
+      use entity work.tbd_rlink_serport;
     end for;
   end for;
 
-end tb_rri_serport;
+end tb_rlink_serport;
diff --git a/rtl/vlib/rlink/tb/tb_rlink_serport_ssim.vbom b/rtl/vlib/rlink/tb/tb_rlink_serport_ssim.vbom
new file mode 100644
index 00000000..2d87c13a
--- /dev/null
+++ b/rtl/vlib/rlink/tb/tb_rlink_serport_ssim.vbom
@@ -0,0 +1,5 @@
+# configure tb_rlink with tbd_rlink_serport wrapper; _*sim case
+tbd_rlink_gen = tbd_rlink_serport.vbom
+tbu_rlink_serport = tbu_rlink_serport_ssim.vhd
+tb_rlink_serport.vbom
+@top:tb_rlink_serport
diff --git a/rtl/vlib/rlink/tb/tb_rlink_serport_stim.dat b/rtl/vlib/rlink/tb/tb_rlink_serport_stim.dat
new file mode 100644
index 00000000..40dbacda
--- /dev/null
+++ b/rtl/vlib/rlink/tb/tb_rlink_serport_stim.dat
@@ -0,0 +1,312 @@
+# $Id: tb_rlink_serport_stim.dat 351 2010-12-30 21:50:54Z mueller $
+#
+#  Revision History: 
+# Date         Rev Version  Comment
+# 2010-12-29   351   1.0.1  use new rbd_tester addr 111100xx (from 111101xx)
+# 2010-12-26   348   1.0    Initial version (Test 3 from tb_rlink_stim.dat)
+#
+#---------------------------------------
+# rbus address mapping
+#   11110000   rbd_tester cntl
+#   11110001   rbd_tester data
+#   11110010   rbd_tester fifo
+#   11110011   rbd_tester attn
+#
+.rlmon 0
+.rbmon 1
+#
+C -----------------------------------------------------------------------------
+C Test 1: wreg(data)
+C   data := 0011001111001100
+C   ==> shows that rlink can write a register
+C
+C wreg: tx: sop - cmd(00001,010) addr(0001) dl dh ccrc - eop
+C       rx: sop - cmd(010) stat crc - eop
+#
+rxsop 
+rxcs   00001010 00000000
+rxeop 
+#
+txsop 
+txcad  00001010 11110001 0011001111001100
+txeop 
+#
+.iowt 10
+#
+C -----------------------------------------------------------------------------
+C Test 2: rreg(data)
+C   data -> 0011001111001100
+C   ==> shows that rlink can read back a register
+C
+C rreg: tx: sop - cmd(00001,000) addr(0001) ccrc - eop
+C       rx: sop - cmd(000) dl dh stat crc - eop
+#
+rxsop 
+rxcds  00001000          0011001111001100 00000000
+rxeop 
+#
+txsop 
+txca   00001000 11110001
+txeop 
+#
+.iowt 10
+#
+C -----------------------------------------------------------------------------
+C Test 3: Test comma escapes
+C         Assumes CPREF=1000, covers 11111111:10000111 and 10001101:10010000
+C
+C   data := 1000000011111111      <idle>,...
+C   data -> 1000000011111111
+C   data := 1000001010000001      <eop> ,<sop>
+C   data -> 1000001010000001
+C   data := 1000010010000011      <attn>,<nak>
+C   data -> 1000010010000011
+C   data := 1000011010000101      6,5
+C   data -> 1000011010000101
+C   data := 1000100010000111      8,7
+C   data -> 1000100010000111
+C   data := 1000111010001101      14,13
+C   data -> 1000111010001101
+C   data := 1001000010001111      ..,<esc>
+C   data -> 1001000010001111
+C
+C wreg: tx: sop - cmd(00001,010) addr(0001) dl dh ccrc
+C rreg: tx:     - cmd(00010,000) addr(0001) ccrc
+C wreg: tx:     - cmd(00011,010) addr(0001) dl dh ccrc
+C rreg: tx:     - cmd(00100,000) addr(0001) ccrc
+C wreg: tx:     - cmd(00101,010) addr(0001) dl dh ccrc
+C rreg: tx:     - cmd(00110,000) addr(0001) ccrc
+C wreg: tx:     - cmd(00111,010) addr(0001) dl dh ccrc
+C rreg: tx:     - cmd(01000,000) addr(0001) ccrc
+C wreg: tx:     - cmd(01001,010) addr(0001) dl dh ccrc
+C rreg: tx:     - cmd(01010,000) addr(0001) ccrc
+C wreg: tx:     - cmd(01011,010) addr(0001) dl dh ccrc
+C rreg: tx:     - cmd(01100,000) addr(0001) ccrc
+C wreg: tx:     - cmd(01101,010) addr(0001) dl dh ccrc
+C rreg: tx:     - cmd(01110,000) addr(0001) ccrc
+C       tx:     - eop
+C       rx: sop - cmd(010) stat crc
+C       rx:     - cmd(000) dl dh stat crc
+C       rx:     - cmd(010) stat crc
+C       rx:     - cmd(000) dl dh stat crc
+C       rx:     - cmd(010) stat crc
+C       rx:     - cmd(000) dl dh stat crc
+C       rx:     - cmd(010) stat crc
+C       rx:     - cmd(000) dl dh stat crc
+C       rx:     - cmd(010) stat crc
+C       rx:     - cmd(000) dl dh stat crc
+C       rx:     - cmd(010) stat crc
+C       rx:     - cmd(000) dl dh stat crc
+C       rx:     - cmd(010) stat crc
+C       rx:     - cmd(000) dl dh stat crc
+C       rx:     - eop
+#
+rxsop 
+rxcs   00001010 00000000
+rxcds  00010000          1000000011111111 00000000
+rxcs   00011010 00000000
+rxcds  00100000          1000001010000001 00000000
+rxcs   00101010 00000000
+rxcds  00110000          1000010010000011 00000000
+rxcs   00111010 00000000
+rxcds  01000000          1000011010000101 00000000
+rxcs   01001010 00000000
+rxcds  01010000          1000100010000111 00000000
+rxcs   01011010 00000000
+rxcds  01100000          1000111010001101 00000000
+rxcs   01101010 00000000
+rxcds  01110000          1001000010001111 00000000
+rxeop 
+#
+txsop 
+txcad  00001010 11110001 1000000011111111
+txca   00010000 11110001 
+txcad  00011010 11110001 1000001010000001
+txca   00100000 11110001 
+txcad  00101010 11110001 1000010010000011
+txca   00110000 11110001 
+txcad  00111010 11110001 1000011010000101
+txca   01000000 11110001 
+txcad  01001010 11110001 1000100010000111
+txca   01010000 11110001 
+txcad  01011010 11110001 1000111010001101
+txca   01100000 11110001 
+txcad  01101010 11110001 1001000010001111
+txca   01110000 11110001 
+txeop 
+#
+.iowt 10
+#
+C -----------------------------------------------------------------------------
+C Test 4: Test RTS throttling via wreg/rreg
+C         Note: RTS_N response is *not* selfchecking, look into log and check
+C               for 'RTS_N' lines.
+C
+C   init (11111110:0000000000001000)  fena(0),fwth(0),fdly(0),rtsoff(1),rtson(0)
+C   fifo := 1000000010000000
+C   fifo := 1000000010000001
+C   fifo := 1000000010000010
+C   fifo := 1000000010000011
+C   fifo := 1000000110000000
+C   fifo := 1000000110000001
+C   fifo := 1000000110000010
+C   fifo := 1000000110000011
+C   fifo -> 8 read (will produce escapes for dl and dh, thus slow down a bit)
+C
+C init: tx: sop - cmd(11110,110) addr(----) dl dh ccrc
+C wreg: tx:     - cmd(00001,010) addr(0010) dl dh ccrc
+C wreg:           ....
+C wreg: tx:     - cmd(01000,010) addr(0010) dl dh ccrc
+C rreg: tx:     - cmd(10001,000) addr(0010) ccrc
+C                 ....
+C rreg: tx:     - cmd(11000,000) addr(0010) ccrc
+C       tx:     - eop
+C       rx: sop - cmd(110) stat crc
+C       rx:     - cmd(010) stat crc
+C                 ...
+C       rx:     - cmd(010) stat crc
+C       rx:     - cmd(000) dl dh stat crc
+C                 ...
+C       rx:     - cmd(000) dl dh stat crc
+C       rx:     - eop
+C
+#
+rxsop 
+rxcs   11110110 00000000
+rxcs   00001010 00000000
+rxcs   00010010 00000000
+rxcs   00011010 00000000
+rxcs   00100010 00000000
+rxcs   00101010 00000000
+rxcs   00110010 00000000
+rxcs   00111010 00000000
+rxcs   01000010 00000000
+rxcds  10001000          1000000010000000 00000000
+rxcds  10010000          1000000010000001 00000000
+rxcds  10011000          1000000010000010 00000000
+rxcds  10100000          1000000010000011 00000000
+rxcds  10101000          1000000110000000 00000000
+rxcds  10110000          1000000110000001 00000000
+rxcds  10111000          1000000110000010 00000000
+rxcds  11000000          1000000110000011 00000000
+rxeop 
+#
+txsop 
+txcad  11110110 11111110 0000000000001000
+txcad  00001010 11110010 1000000010000000
+txcad  00010010 11110010 1000000010000001
+txcad  00011010 11110010 1000000010000010
+txcad  00100010 11110010 1000000010000011
+txcad  00101010 11110010 1000000110000000
+txcad  00110010 11110010 1000000110000001
+txcad  00111010 11110010 1000000110000010
+txcad  01000010 11110010 1000000110000011
+txca   10001000 11110010 
+txca   10010000 11110010 
+txca   10011000 11110010 
+txca   10100000 11110010 
+txca   10101000 11110010 
+txca   10110000 11110010 
+txca   10111000 11110010 
+txca   11000000 11110010 
+txeop 
+#
+.iowt 10
+#
+C -----------------------------------------------------------------------------
+C Test 5: Test RTS flush pulse
+C         Note: RTS_N response is *not* selfchecking, look into log and check
+C               for 'RTS_N' lines.
+C
+C 1a. setup width=1, delay=1
+C
+C   init (11111110:0001001001111110)  fena(1),fwth(1),fdly(1),rtsoff(7),rtson(6)
+C init: tx: sop - cmd(11110,110) addr(----) dl dh ccrc - eop
+#
+rxsop 
+rxcs   11110110 00000000
+rxeop 
+txsop 
+txcad  11110110 11111110 0001001001111110
+txeop 
+.iowt 10
+.wait 50
+C
+C 1b. test with wreg sequence
+C   data := 0000000000000001
+C wreg: tx: sop - cmd(00001,010) addr(0001) dl dh ccrc - eop
+C       rx: sop - cmd(010) stat crc - eop
+C
+#
+rxsop 
+rxcs   00001010 00000000
+rxeop 
+txsop 
+txcad  00001010 11110001 0000000000000001
+txeop 
+.iowt 10
+.wait 50
+C
+C 2a. setup width=3, delay=1
+C
+C   init (11111110:0001011001111110)  fena(1),fwth(3),fdly(1),rtsoff(7),rtson(6)
+C init: tx: sop - cmd(11110,110) addr(----) dl dh ccrc - eop
+#
+rxsop 
+rxcs   11110110 00000000
+rxeop 
+txsop 
+txcad  11110110 11111110 0001011001111110
+txeop 
+.iowt 10
+.wait 50
+C
+C 2b. test with wreg sequence
+C   data := 0000000000000001
+C wreg: tx: sop - cmd(00001,010) addr(0001) dl dh ccrc - eop
+C       rx: sop - cmd(010) stat crc - eop
+#
+rxsop 
+rxcs   00001010 00000000
+rxeop 
+txsop 
+txcad  00001010 11110001 0000000000000001
+txeop 
+.iowt 10
+.wait 50
+#
+C
+C 3a. setup width=7, delay=7
+C
+C   init (11111110:0001111111111110)  fena(1),fwth(7),fdly(7),rtsoff(7),rtson(6)
+C init: tx: sop - cmd(11110,110) addr(----) dl dh ccrc - eop
+#
+rxsop 
+rxcs   11110110 00000000
+rxeop 
+txsop 
+txcad  11110110 11111110 0001111111111110
+txeop 
+.iowt 10
+.wait 50
+C
+C 3b. test with wreg sequence
+C   data := 0000000000000001
+C wreg: tx: sop - cmd(00001,010) addr(0001) dl dh ccrc - eop
+C       rx: sop - cmd(010) stat crc - eop
+#
+rxsop 
+rxcs   00001010 00000000
+rxeop 
+txsop 
+txcad  00001010 11110001 0000000000000001
+txeop 
+.iowt 10
+.wait 50
+#
+#==============================================================================
+#
+C -----------------------------------------------------------------------------
+C Run down and Finish
+.iowt 10
+.wait 100
diff --git a/rtl/vlib/rlink/tb/tb_rlink_stim.dat b/rtl/vlib/rlink/tb/tb_rlink_stim.dat
new file mode 100644
index 00000000..55fe96df
--- /dev/null
+++ b/rtl/vlib/rlink/tb/tb_rlink_stim.dat
@@ -0,0 +1,3110 @@
+# $Id: tb_rlink_stim.dat 351 2010-12-30 21:50:54Z mueller $
+#
+#  Revision History: 
+# Date         Rev Version  Comment
+# 2010-12-29   351   3.0.6  use new rbd_tester addr 111100xx (from 111101xx)
+# 2010-12-28   350   3.3.2  adapt for cdinit=0 in tbd/tbu(some .iowt 10->20)
+# 2010-12-25   348   3.3.1  Test 3b moved to tb_rlink_serport_stim.dat
+# 2010-12-22   346   3.3    Test 7: check dcrc sends nak and ends in s_error
+#                           Test 20: check that '111' ends in s_error
+#                           Test 21*: now covers eop aborts of all commands
+# 2010-12-21   345   3.2    rename .[rt]x... -> [rt]x...; use .[rt]x(idle|attn)
+# 2010-12-12   344   3.1    now almost complete test coverage
+# 2010-12-05   343   3.0    re-write for usage with tbd_tester
+# 2010-06-06   302   2.0    use sop/eop framing instead of soc+chaining
+# 2007-11-24    98   1.2    adapt to new internal init handling
+# 2007-11-04    95   1.1    add .iowt's in Test 15 to get serport timing right
+# 2007-06-17    58   1.0    Initial version
+#
+#---------------------------------------
+# test coverage table
+#   rlink_core
+#     command function and attribute matrix
+#        cmd  function  rberr  rbnak- rbnak- rbnak- busy  cerr  derr  idle  eop 
+#                              nak    dnak   time
+#       rreg  2,3a      4a     8a     12a    10     10    6a    n/a   18a   21b
+#       wreg  1,3a      4b     8a     12a    10     10    6b    n/a   18a   21a
+#       rblk  4a        4b,7   8b     12b    11     11    6c    n/a   18b   21d
+#       wblk  4a        4b     8b     12b    11     11    6c    7     18b   21c
+#       stat  5,6*,7    n/a    n/a    n/a    n/a    n/a   6c    n/a   18c   21e
+#       attn  13*       n/a    n/a    n/a    n/a    n/a   16    n/a   18c   21f
+#       init  9,15a     n/a    n/a    n/a    n/a    n/a   16    n/a   18c   21g
+#
+#     cmd rreg
+#     cmd wreg
+#     cmd rblk
+#     cmd wblk
+#     cmd stat
+#       returns last command status     -> 5
+#       returns cerr error flag         -> 6a,6b
+#       returns derr error flag         -> 7
+#     cmd attn
+#     cmd init
+#       generates external init         -> 9
+#       generates internal init         -> 15a
+#     drop cmd after ccrc               -> 6b
+#     attn poll                         -> 14
+#     attn notification                 -> 15a,15b
+#     idle timeout                      -> 17
+#     idle insertion at any state       -> 18a,18b,18c
+#     sop-eop framing                   -> 19
+#     unused command code 111 gives nak -> 20
+#     eop aborts (all commands)         -> 21*
+#     nak aborts (only wreg)            -> 21
+#     
+#   tbd_tester
+#     reg cntl
+#       nofifo: read/write, disable fifo-> 8a,8b
+#       nofifo: clear fifo on 1->0      -> 8a
+#       stat: write and RB_STAT connect -> 3
+#       stat: read                      -> 3
+#       nbusy: controls # of busy cycles-> 10
+#       cleared by init (..001)         -> 9
+#     reg data
+#       write                           -> 1,3,5
+#       read                            -> 2,3,5
+#       cleared by init (..010)         -> 9
+#     reg fifo
+#       write/read normal               -> 4a
+#       read: rberr on EMPTY            -> 4a,4b,8a
+#       write: rberr on FULL            -> 4b
+#       cleared by nofifo 1->0          -> 8a
+#       cleared by init (..100)         -> 9
+#     reg attn
+#       returns cycle length on read    -> 10
+#       write tickles RB_LAM            -> 13b
+#
+#---------------------------------------
+# rbus address mapping
+#   11110000   rbd_tester cntl
+#   11110001   rbd_tester data
+#   11110010   rbd_tester fifo
+#   11110011   rbd_tester attn
+#
+.rlmon 0
+.rbmon 0
+#
+.wait 5
+C some non frame data first
+tx8   00000000
+.wait 5
+tx8   00000001
+.wait 5
+tx8   00000010
+#
+.iowt 10
+#
+C -----------------------------------------------------------------------------
+C Test 1: wreg(data)
+C   data := 0011001111001100
+C   ==> shows that rlink can write a register
+C
+C wreg: tx: sop - cmd(00001,010) addr(0001) dl dh ccrc - eop
+C       rx: sop - cmd(010) stat crc - eop
+#
+rxsop 
+rxcs   00001010 00000000
+rxeop 
+#
+txsop 
+txcad  00001010 11110001 0011001111001100
+txeop 
+#
+.iowt 10
+#
+C -----------------------------------------------------------------------------
+C Test 2: rreg(data)
+C   data -> 0011001111001100
+C   ==> shows that rlink can read back a register
+C
+C rreg: tx: sop - cmd(00001,000) addr(0001) ccrc - eop
+C       rx: sop - cmd(000) dl dh stat crc - eop
+#
+rxsop 
+rxcds  00001000          0011001111001100 00000000
+rxeop 
+#
+txsop 
+txca   00001000 11110001
+txeop 
+#
+.iowt 10
+#
+C -----------------------------------------------------------------------------
+C Test 3: chained wreg(cntl) - wreg(data) - rreg(cntl) - rreg(data)
+C   cntl := 0111000000000000  (nf=0,stat=111,nbusy=0)
+C   data := 1100110000110011                            --> stat=111 !
+C   cntl -> 0111000000000000                            --> stat=111 !
+C   data -> 1100110000110011                            --> stat=111 !
+C   ==> shows that rlink can properly address two registers
+C   ==> shows that tbd_tester cntl can set RB_STAT
+C
+C wreg: tx: sop - cmd(00001,010) addr(0000) dl dh ccrc
+C wreg: tx:     - cmd(00010,010) addr(0001) dl dh ccrc
+C rreg: tx:     - cmd(00011,000) addr(0000) ccrc
+C rreg: tx:     - cmd(00100,000) addr(0001) ccrc
+C       tx:     - eop
+C       rx: sop - cmd(010) stat crc
+C       rx:     - cmd(010) stat crc
+C       rx:     - cmd(000) dl dh stat crc
+C       rx:     - cmd(000) dl dh stat crc
+C       rx:     - eop
+#
+rxsop 
+rxcs   00001010 00000000
+rxcs   00010010 11100000
+rxcds  00011000          0111000000000000 11100000
+rxcds  00100000          1100110000110011 11100000
+rxeop 
+#
+txsop 
+txcad  00001010 11110000 0111000000000000
+txcad  00010010 11110001 1100110000110011
+txca   00011000 11110000
+txca   00100000 11110001 
+txeop 
+#
+.iowt 10
+#
+C -----------------------------------------------------------------------------
+C Test 4a: wblk - rblk (normal)
+C   write 8 words to fifo with wblk
+C   read back 8 words from fifo with rblk
+C   read back 9'th word from fifo with rreg (fails with err)
+C   ==> shows that block write/read work
+C   ==> shows that RB_SRES.err works with rreg
+C
+C wblk: tx: sop - cmd(10110,011) addr(0010) cnt(8->111) ccrc dl dh .. dcrc
+C       tx:     - eop
+C       rx: sop - cmd(011) stat crc
+C       rx:     - eop
+#
+rxsop 
+rxcs   10110011 11100000
+rxeop 
+#
+txsop 
+txcac  10110011 11110010 00000111
+tx16   0000000001000000
+tx16   0000000001000001
+tx16   0000000001000010
+tx16   0000000001000011
+tx16   0000000001000100
+tx16   0000000001000101
+tx16   0000000001000110
+tx16   0000000001000111
+txcrc 
+txeop 
+#
+.iowt 10
+#
+C rblk: tx: sop - cmd(10111,001) addr(0010) cnt(8->111) ccrc - eop
+C       rx: sop - cmd(001) cnt dl dh ... stat crc - eop
+#
+rxsop 
+rx8    10111001
+rx8    00000111
+rx16   0000000001000000
+rx16   0000000001000001
+rx16   0000000001000010
+rx16   0000000001000011
+rx16   0000000001000100
+rx16   0000000001000101
+rx16   0000000001000110
+rx16   0000000001000111
+rx8    11100000
+rxcrc 
+rxeop 
+#
+txsop 
+txcac  10111001 11110010 00000111
+txeop 
+#
+.iowt 10
+#
+C rreg: tx: sop - cmd(11000,000) addr(0010) ccrc - eop
+C       rx: sop - cmd(000) dl dh stat crc - eop
+C
+C     stat: stat(111),attn(0),cerr(0),derr(0),rbnak(0),rberr(1) -> 11100001
+C     Note: returns 0101... empty pattern
+#
+rxsop 
+rxcds  11000000          0101010101010101 11100001
+rxeop 
+#
+txsop 
+txca   11000000 11110010
+txeop 
+#
+.iowt 10
+#
+C -----------------------------------------------------------------------------
+C Test 4b: wblk - rblk (rberr response)
+C   write 17 words to fifo with wblk
+C   write 18'th word to fifo with wreg
+C   read back 17 words from fifo with rblk
+C   ==> shows that RB_SRES.err works with wblk,wreg,rblk
+C
+C wblk: tx: sop - cmd(00001,011) addr(0010) cnt(17->10000) ccrc dl dh .. dcrc
+C wreg: tx:     - cmd(00010,010) addr(0010) dl dh ccrc
+C rblk: tx:     - cmd(00011,001) addr(0010) cnt(18->10001) ccrc
+C       tx:     - eop
+C       rx: sop - cmd(011) stat crc
+C       rx:     - cmd(010) stat crc
+C       rx:     - cmd(001) cnt dl dh ... stat crc
+C       rx:     - eop
+C
+C     stat: stat(111),attn(0),cerr(0),derr(0),rbnak(0),rberr(1) -> 11100001
+#
+rxsop 
+rxcs   00001011 11100001
+rxcs   00010010 11100001
+rx8    00011001
+rx8    00010001
+rx16   0000001111000000
+rx16   0000001111000001
+rx16   0000001111000010
+rx16   0000001111000011
+rx16   0000001111000100
+rx16   0000001111000101
+rx16   0000001111000110
+rx16   0000001111000111
+rx16   0000001111001000
+rx16   0000001111001001
+rx16   0000001111001010
+rx16   0000001111001011
+rx16   0000001111001100
+rx16   0000001111001101
+rx16   0000001111001110
+rx16   0000001111001111
+rx16   0101010101010101
+rx16   0101010101010101
+rx8    11100001
+rxcrc 
+rxeop 
+#
+txsop 
+txcac  00001011 11110010 00010000
+tx16   0000001111000000
+tx16   0000001111000001
+tx16   0000001111000010
+tx16   0000001111000011
+tx16   0000001111000100
+tx16   0000001111000101
+tx16   0000001111000110
+tx16   0000001111000111
+tx16   0000001111001000
+tx16   0000001111001001
+tx16   0000001111001010
+tx16   0000001111001011
+tx16   0000001111001100
+tx16   0000001111001101
+tx16   0000001111001110
+tx16   0000001111001111
+tx16   0000001111010000
+txcrc 
+txcad  00010010 11110010 0000001111010001
+txcac  00011001 11110010 00010001
+txeop 
+#
+.iowt 10
+#
+C -----------------------------------------------------------------------------
+C Test 5: stat (in non-error case) re-read last cmd twice, shouldn't change
+C   cntl := 0000000000000000  (nf=0,stat=000,nbusy=0)   --> stat=111
+C   data := 1010101010101010                            --> stat=000
+C   cntl -> 0000000000000000                            --> stat=000
+C   data -> 1010101010101010                            --> stat=000
+C   use 'stat' twice, should give cmd and data of last 'read data'
+C   ==> shows that stat command works properly
+C
+C wreg: tx: sop - cmd(00001,010) addr(0000) dl dh ccrc
+C wreg: tx:     - cmd(00010,010) addr(0001) dl dh ccrc
+C rreg: tx:     - cmd(00011,000) addr(0000) ccrc
+C rreg: tx:     - cmd(00100,000) addr(0001) ccrc
+C stat: tx:     - cmd(00101,100) ccrc
+C stat: tx:     - cmd(00110,100) ccrc
+C       tx:     - eop
+C       rx: sop - cmd(010) stat crc
+C       rx:     - cmd(010) stat crc
+C       rx:     - cmd(000) dl dh stat crc
+C       rx:     - cmd(000) dl dh stat crc
+C       rx:     - cmd(100) ccmd(000) dl dh stat crc
+C       rx:     - cmd(100) ccmd(000) dl dh stat crc
+C       rx:     - eop
+#
+rxsop 
+rxcs   00001010 11100000
+rxcs   00010010 00000000
+rxcds  00011000          0000000000000000 00000000
+rxcds  00100000          1010101010101010 00000000
+rxccd  00101100 00100000 1010101010101010 00000000
+rxccd  00110100 00100000 1010101010101010 00000000
+rxeop 
+#
+txsop 
+txcad  00001010 11110000 0000000000000000
+txcad  00010010 11110001 1010101010101010 
+txca   00011000 11110000
+txca   00100000 11110001
+txc    00101100
+txc    00110100
+txeop 
+#
+.iowt 10
+#
+C -----------------------------------------------------------------------------
+C Test 6a: ccrc error abort for rreg, last command in packet fails
+C   cntl := 0101000000000000  (nf=0,stat=101,nbusy=0)   --> stat=000
+C   data := 1100110011001100                            --> stat=101
+C   cntl -> 0101000000000000                            --> stat=101
+C   data -> 1100110011001100   *send with bad CCRC*, will fail
+C   ==> shows command ccrc check works properly
+C
+C wreg: tx: sop - cmd(00001,010) addr(0000) dl dh ccrc
+C wreg: tx:     - cmd(00010,010) addr(0001) dl dh ccrc
+C rreg: tx:     - cmd(00011,000) addr(0000) ccrc
+C rreg: tx:     - cmd(00100,000) addr(0001) *BAD CCRC*
+C       tx:     - eop
+C       rx: sop - cmd(010) stat crc
+C       rx:     - cmd(010) stat crc
+C       rx:     - cmd(000) dl dh stat crc
+C       rx:     - nak  *ABORT*
+C       rx:     - eop
+#
+rxsop 
+rxcs   00001010 00000000
+rxcs   00010010 10100000
+rxcds  00011000          0101000000000000 10100000
+rxnak 
+rxeop 
+#
+txsop 
+txcad  00001010 11110000 0101000000000000
+txcad  00010010 11110001 1100110011001100
+txca   00011000 11110000
+tx8    00100000 
+tx8    11110001
+txbad 
+txeop 
+#
+.iowt 10
+#
+C
+C now check that stat reflects last successfull rreg; re-read cerr=1 sticks !
+C   ==> shows command stat allows to deterine last successful (non-stat) command
+C
+C stat: tx: sop - cmd(00101,100) ccrc
+C stat: tx:     - cmd(00110,100) ccrc
+C       tx:     - eop
+C       rx:     - cmd(100) ccmd(000) dl dh stat crc
+C       rx:     - cmd(100) ccmd(000) dl dh stat crc
+C       rx:     - eop
+C
+C     stat: stat(101),attn(0),cerr(1),derr(0),rbnak(0),rberr(0) -> 10101000
+rxsop 
+rxccd  00101100 00011000 0101000000000000 10101000
+rxccd  00110100 00011000 0101000000000000 10101000
+rxeop 
+#
+txsop 
+txc    00101100
+txc    00110100
+txeop 
+#
+.iowt 10
+#
+C -----------------------------------------------------------------------------
+C Test 6b: ccrc error abort for wreg, failure inside packet
+C   cntl := 0000000000000000  (nf=0,stat=000,nbusy=0)
+C   cntl := 0111000000000000  (nf=0,stat=111,nbusy=0) *send with bad CCRC*
+C   data := 0011001100110011                          *will be ignored*  
+C   ==> shows commands after a ccrc fail are ignored
+C
+C wreg: tx: sop - cmd(00001,010) addr(0000) dl dh ccrc
+C wreg: tx:     - cmd(00010,010) addr(0000) dl dh *BAD CCRC*
+C wreg: tx:     - cmd(00011,010) addr(0001) dl dh ccrc
+C       tx:     - eop
+C       rx: sop - cmd(010) stat crc
+C       rx:     - nak  *ABORT*
+C       rx:     - eop
+C
+rxsop 
+rxcs   00001010 10100000
+rxnak 
+rxeop 
+#
+txsop 
+txcad  00001010 11110000 0000000000000000
+tx8    00010010 
+tx8    11110000
+tx8    00000000
+tx8    01110000
+txbad 
+txcad  00011010 11110001 0011001100110011
+txeop 
+#
+.iowt 10
+#
+C
+C now check that stat reflects first successfull wreg; re-read cerr=1 sticks !
+C   ==> shows command stat allows to deterine last successful (non-stat) command
+C
+C stat: tx: sop - cmd(00101,100) ccrc
+C stat: tx:     - cmd(00110,100) ccrc
+C       tx:     - eop
+C       rx:     - cmd(100) ccmd (000) dl dh stat crc
+C       rx:     - cmd(100) ccmd (000) dl dh stat crc
+C       rx:     - eop
+C
+C     stat: stat(101),attn(0),cerr(1),derr(0),rbnak(0),rberr(0) -> 10101000
+rxsop 
+rxccd  00101100 00001010 0101000000000000 10101000
+rxccd  00110100 00001010 0101000000000000 10101000
+rxeop 
+#
+txsop 
+txc    00101100
+txc    00110100
+txeop 
+#
+.iowt 10
+#
+C
+C finally check that cntl register was really written by first wreg
+C   cntl -> 0000000000000000
+C
+C rreg: tx: sop - cmd(01000,000) addr(0000) ccrc - eop
+C       rx: sop - cmd(000) dl dh stat crc - eop
+#
+rxsop 
+rxcds  01000000          0000000000000000 00000000
+rxeop 
+#
+txsop 
+txca   01000000 11110000
+txeop 
+#
+.iowt 10
+#
+C -----------------------------------------------------------------------------
+C Test 6c: ccrc error abort for wblk,rblk and stat
+C   write 2 words to fifo with bad CCRC   -> nak
+C   read 2 words from fifo with bad CCRC  -> nak
+C   cmd stat with bad CCRC                -> nak
+C   finally stat, will return last successfull read from Test 6b
+C
+C wblk: tx: sop - cmd(00001,011) addr(0010) cnt(2->001) *BAD CCRC* dl dh .. dcrc
+C               - eop
+C       rx: sop - nak - eop
+C
+rxsop 
+rxnak 
+rxeop 
+#
+txsop 
+tx8    00001011 
+tx8    11110010 
+tx8    00000001
+txbad  
+tx16   1010101010101010
+tx16   0101010101010101
+txcrc  
+txeop 
+#
+.iowt 10
+#
+C
+C rblk: tx: sop - cmd(00010,001) addr(0010) cnt(2->001) *BAD CCRC* - eop
+C       rx: sop - nak - eop
+C
+rxsop 
+rxnak 
+rxeop 
+#
+txsop 
+tx8    00010001 
+tx8    11110010 
+tx8    00000001
+txbad  
+txeop 
+#
+.iowt 10
+#
+C
+C stat: tx: sop - cmd(00011,100) *BAD CCRC* - eop
+C       rx: sop - nak - eop
+C
+rxsop 
+rxnak 
+rxeop 
+#
+txsop 
+tx8    00011100 
+txbad  
+txeop 
+#
+.iowt 10
+#
+C
+C stat: tx: sop - cmd(00100,100) ccrc - eop
+C       rx: sop - cmd(100) ccmd (000) dl dh stat crc - eop
+C
+C     stat: stat(000),attn(0),cerr(1),derr(0),rbnak(0),rberr(0) -> 00001000
+C
+rxsop 
+rxccd  00100100 01000000 0000000000000000 00001000
+rxeop 
+#
+txsop 
+txc    00100100
+txeop 
+#
+.iowt 10
+#
+C -----------------------------------------------------------------------------
+C Test 7: dcrc error condition in wblk
+C   write 4 words to fifo with wblk and bad DCRC, will cause a dcrc fail
+C   ==> shows that data dcrc works in wblk, aborts with <nak>
+C   ==> shows that commands after a dcrc failed wblk are discarded
+C
+C wblk: tx: sop - cmd(00001,011) addr(0010) cnt(4->011) ccrc dl dh .. 
+C                 *BAD DCRC* 
+C                 cmd(00010,000) addr(0001) ccrc
+C               - eop
+C       rx: sop - cmd(011) stat crc
+C       rx:     - nak eop
+C
+C     stat: stat(000),attn(0),cerr(0),derr(1),rbnak(0),rberr(0) -> 00000100
+#
+rxsop 
+rxcs   00001011 00000100
+rxnak
+rxeop 
+#
+txsop 
+txcac  00001011 11110010 00000011
+tx16   0001000001000000
+tx16   0001000001000001
+tx16   0001000001000010
+tx16   0001000001000011
+txbad 
+txca   00010000 11110001
+txeop 
+#
+.iowt 10
+#
+C
+C now check that stat reflects bad dcrc: re-read derr=1 sticks !
+C stat: tx: sop - cmd(00011,100) ccrc
+C stat: tx:     - cmd(00100,100) ccrc
+C       tx:     - eop
+C       rx:     - cmd(100) ccmd (000) dl dh stat crc
+C       rx:     - cmd(100) ccmd (000) dl dh stat crc
+C       rx:     - eop
+C
+C     stat: stat(000),attn(0),cerr(0),derr(1),rbnak(0),rberr(0) -> 00000100
+C     Note: dl,dh still the last read of Test 6 !!
+rxsop 
+rxccd  00011100 00001011 0000000000000000 00000100
+rxccd  00100100 00001011 0000000000000000 00000100
+rxeop 
+#
+txsop 
+txc    00011100
+txc    00100100
+txeop 
+#
+.iowt 10
+#
+C
+C now read 6 words from fifo: first 4 previous data, 2 empty reads and err=1
+C rblk: tx: sop - cmd(00101,001) addr(0010) cnt(6->101) ccrc - eop
+C       rx: sop - cmd(001) cnt dl dh ... stat crc - eop
+C
+C     stat: stat(000),attn(0),cerr(0),derr(0),rbnak(0),rberr(1) -> 00000001
+#
+rxsop 
+rx8   00101001
+rx8   00000101
+rx16  0001000001000000
+rx16  0001000001000001
+rx16  0001000001000010
+rx16  0001000001000011
+rx16  0101010101010101
+rx16  0101010101010101
+rx8   00000001
+rxcrc 
+rxeop 
+#
+txsop 
+txcac  00101001 11110010 00000101
+txeop 
+#
+.iowt 10
+#
+C -----------------------------------------------------------------------------
+C Test 8a: rbnak(no ack) condition (rreg/wreg)
+C   fifo := 1111111100000000     -> rbnak=0
+C   cntl := 1000000000000000  (nf=1,stat=000,nbusy=0) --> disable fifo
+C   fifo := 1111111100001111     -> rbnak=1
+C   fifo -> 0101010101010101     -> rbnak=1            
+C   cntl := 0000000000000000  (nf=0,stat=000,nbusy=0) --> enable and clear fifo
+C   fifo := 0000000001010101     -> rbnak=0
+C   fifo -> 0000000001010101     -> rbnak=0
+C   fifo -> 0101010101010101     -> rberr=1 (first fifo write data cleared...)
+C   ==> shows that missing ack is handled properly and rbnak flag set
+C
+C wreg: tx: sop - cmd(00001,010) addr(0010) dl dh ccrc
+C wreg: tx:     - cmd(00010,010) addr(0000) dl dh ccrc
+C wreg: tx:     - cmd(00011,010) addr(0010) dl dh ccrc
+C rreg: tx:     - cmd(00100,000) addr(0010) ccrc
+C wreg: tx:     - cmd(00101,010) addr(0000) dl dh ccrc
+C wreg: tx:     - cmd(00110,010) addr(0010) dl dh ccrc
+C rreg: tx:     - cmd(00111,000) addr(0010) ccrc
+C rreg: tx:     - cmd(01000,000) addr(0010) ccrc
+C       tx:     - eop
+C       rx: sop - cmd(010) stat crc
+C       rx:     - cmd(010) stat crc
+C       rx:     - cmd(010) stat crc
+C       rx:     - cmd(000) dl dh stat crc
+C       rx:     - cmd(010) stat crc
+C       rx:     - cmd(010) stat crc
+C       rx:     - cmd(000) dl dh stat crc
+C       rx:     - cmd(000) dl dh stat crc
+C       rx:     - eop
+C
+C   stat-3: stat(000),attn(0),cerr(0),derr(0),rbnak(1),rberr(0) -> 00000010
+C   stat-8: stat(000),attn(0),cerr(0),derr(0),rbnak(0),rberr(1) -> 00000001
+C     Note: fifo will nak when nofifo flag set in cntl
+C     Note: tb returns 0000000000000000 for access to bad addresses
+#
+rxsop 
+rxcs   00001010 00000000
+rxcs   00010010 00000000
+rxcs   00011010 00000010
+rxcds  00100000          0000000000000000 00000010
+rxcs   00101010 00000000
+rxcs   00110010 00000000
+rxcds  00111000          0000000010101010 00000000
+rxcds  01000000          0101010101010101 00000001
+rxeop 
+#
+txsop 
+txcad  00001010 11110010 1111111100000000
+txcad  00010010 11110000 1000000000000000
+txcad  00011010 11110010 1111111100001111
+txca   00100000 11110010
+txcad  00101010 11110000 0000000000000000
+txcad  00110010 11110010 0000000010101010
+txca   00111000 11110010
+txca   01000000 11110010
+txeop 
+#
+.iowt 10
+#
+C -----------------------------------------------------------------------------
+C Test 8b: rbnak(no ack) condition (rblk/wblk)
+C   cntl := 1000000000000000  (nf=1,stat=000,nbusy=0) --> disable fifo
+C   write 2 words to fifo    -> rbnak=1
+C   read 2 words from fifo   -> rbnak=1
+C   cntl := 0000000000000000  (nf=0,stat=000,nbusy=0) --> enable and clear fifo
+C   ==> shows that missing ack is handled properly and rbnak flag set
+C
+C wreg: tx: sop - cmd(00001,010) addr(0000) dl dh ccrc
+C wblk: tx:     - cmd(00010,011) addr(0010) cnt(2->001) ccrc dl dh .. dcrc
+C rblk: tx:     - cmd(00011,001) addr(0010) cnt(2->001) ccrc
+C wreg: tx:     - cmd(00100,010) addr(0000) dl dh ccrc
+C       tx:     - eop
+C       rx: sop - cmd(010) stat crc
+C       rx:     - cmd(011) stat crc
+C       rx:     - cmd(001) cnt dl dh ... stat crc - eop
+C       rx:     - cmd(010) stat crc
+C       rx:     - eop
+C
+C     stat: stat(000),attn(0),cerr(0),derr(0),rbnak(1),rberr(0) -> 00000010
+C     Note: fifo will nak when nofifo flag set in cntl
+C     Note: tb returns 0000000000000000 for access to bad addresses
+#
+rxsop 
+rxcs   00001010 00000000
+rxcs   00010011 00000010
+rx8    00011001
+rx8    00000001
+rx16   0000000000000000
+rx16   0000000000000000
+rx8    00000010
+rxcrc 
+rxcs   00100010 00000000
+rxeop 
+#
+txsop 
+txcad  00001010 11110000 1000000000000000
+txcac  00010011 11110010 00000001
+tx16   0011110000000000
+tx16   0011110000000001
+txcrc 
+txcac  00011001 11110010 00000001
+txcad  00100010 11110000 0000000000000000
+txeop 
+#
+.iowt 10
+#
+C -----------------------------------------------------------------------------
+C Test 9: init 
+C   cntl := 0010000000000000  (nf=0,stat=010,nbusy=0)
+C   data := 1100110000000000
+C   fifo := 1100110011000000
+C   fifo := 1100110011000001
+C   fifo := 1100110011000010
+C   fifo := 1100110011000011
+C   init (11110000:0000000000000000)  noop
+C   cntl -> 0010000000000000  
+C   data -> 1100110000000000
+C   fifo -> 1100110011000000
+C   init (11110000:0000000000000001)  clear cntl
+C   cntl -> 0000000000000000  
+C   data -> 1100110000000000
+C   fifo -> 1100110011000001
+C   init (11110000:0000000000000010)  clear data
+C   data -> 0000000000000000
+C   fifo -> 1100110011000010
+C   init (11110000:0000000000000100)  clear fifo
+C   fifo -> 0101010101010101 ierr=1
+C   ==> shows that init is issued and properly decoded
+C
+C wreg: tx: sop - cmd(00001,010) addr(0000) dl dh ccrc
+C wreg: tx:     - cmd(00010,010) addr(0001) dl dh ccrc
+C wreg: tx:     - cmd(00011,010) addr(0010) dl dh ccrc
+C wreg: tx:     - cmd(00100,010) addr(0010) dl dh ccrc
+C wreg: tx:     - cmd(00101,010) addr(0010) dl dh ccrc
+C wreg: tx:     - cmd(00110,010) addr(0010) dl dh ccrc
+C init: tx:     - cmd(00111,110) addr(0000) dl dh ccrc
+C rreg: tx:     - cmd(01000,000) addr(0000) ccrc
+C rreg: tx:     - cmd(01001,000) addr(0001) ccrc
+C rreg: tx:     - cmd(01010,000) addr(0010) ccrc
+C init: tx:     - cmd(01011,110) addr(0000) dl dh ccrc
+C rreg: tx:     - cmd(01100,000) addr(0000) ccrc
+C rreg: tx:     - cmd(01101,000) addr(0001) ccrc
+C rreg: tx:     - cmd(01110,000) addr(0010) ccrc
+C init: tx:     - cmd(01111,110) addr(0000) dl dh ccrc
+C rreg: tx:     - cmd(10000,000) addr(0001) ccrc
+C rreg: tx:     - cmd(10001,000) addr(0010) ccrc
+C init: tx:     - cmd(10010,110) addr(0000) dl dh ccrc
+C rreg: tx:     - cmd(10011,000) addr(0010) ccrc
+C       tx:     - eop
+C       rx: sop - cmd(010) stat crc
+C       rx:     - cmd(010) stat crc
+C       rx:     - cmd(010) stat crc
+C       rx:     - cmd(010) stat crc
+C       rx:     - cmd(010) stat crc
+C       rx:     - cmd(010) stat crc
+C       rx:     - cmd(110) stat crc
+C       rx:     - cmd(000) dl dh stat crc
+C       rx:     - cmd(000) dl dh stat crc
+C       rx:     - cmd(000) dl dh stat crc
+C       rx:     - cmd(110) stat crc
+C       rx:     - cmd(000) dl dh stat crc
+C       rx:     - cmd(000) dl dh stat crc
+C       rx:     - cmd(000) dl dh stat crc
+C       rx:     - cmd(110) stat crc
+C       rx:     - cmd(000) dl dh stat crc
+C       rx:     - cmd(000) dl dh stat crc
+C       rx:     - cmd(110) stat crc
+C       rx:     - cmd(000) dl dh stat crc
+C       rx:     - eop
+C
+#
+rxsop 
+rxcs   00001010 00000000
+rxcs   00010010 01000000
+rxcs   00011010 01000000
+rxcs   00100010 01000000
+rxcs   00101010 01000000
+rxcs   00110010 01000000
+rxcs   00111110 01000000
+rxcds  01000000          0010000000000000 01000000
+rxcds  01001000          1100110000000000 01000000
+rxcds  01010000          1100110011000000 01000000
+rxcs   01011110 01000000
+rxcds  01100000          0000000000000000 00000000
+rxcds  01101000          1100110000000000 00000000
+rxcds  01110000          1100110011000001 00000000
+rxcs   01111110 00000000
+rxcds  10000000          0000000000000000 00000000
+rxcds  10001000          1100110011000010 00000000
+rxcs   10010110 00000000
+rxcds  10011000          0101010101010101 00000001
+rxeop 
+#
+txsop 
+txcad  00001010 11110000 0010000000000000
+txcad  00010010 11110001 1100110000000000
+txcad  00011010 11110010 1100110011000000
+txcad  00100010 11110010 1100110011000001
+txcad  00101010 11110010 1100110011000010
+txcad  00110010 11110010 1100110011000011
+txcad  00111110 11110000 0000000000000000
+txca   01000000 11110000
+txca   01001000 11110001
+txca   01010000 11110010
+txcad  01011110 11110000 0000000000000001
+txca   01100000 11110000
+txca   01101000 11110001
+txca   01110000 11110010
+txcad  01111110 11110000 0000000000000010
+txca   10000000 11110001
+txca   10001000 11110010
+txcad  10010110 11110000 0000000000000100
+txca   10011000 11110010
+txeop 
+#
+.iowt 10
+#
+C
+C   cntl := 1111001111111111  (nf=1,stat=111,nbusy=1023)
+C   cntl -> 1111001111111111  
+C   init (11110000:0000000000000001)  clear cntl
+C   cntl -> 0000000000000000  
+C   ==> shows that init completely clears cntl
+C
+C wreg: tx: sop - cmd(00001,010) addr(0000) dl dh ccrc
+C rreg: tx:     - cmd(00010,000) addr(0000) ccrc
+C init: tx:     - cmd(00011,110) addr(0000) dl dh ccrc
+C rreg: tx:     - cmd(00100,000) addr(0000) ccrc
+C       tx:     - eop
+C       rx: sop - cmd(010) stat crc
+C       rx:     - cmd(000) dl dh stat crc
+C       rx:     - cmd(110) stat crc
+C       rx:     - cmd(000) dl dh stat crc
+C       rx:     - eop
+#
+rxsop 
+rxcs   00001010 00000000
+rxcds  00010000          1111001111111111 11100000
+rxcs   00011110 11100000
+rxcds  00100000          0000000000000000 00000000
+rxeop 
+#
+txsop 
+txcad  00001010 11110000 1111001111111111
+txca   00010000 11110000
+txcad  00011110 11110000 0000000000000001
+txca   00100000 11110000
+txeop 
+#
+.iowt 10
+#
+C -----------------------------------------------------------------------------
+C Test 10: rbus busy handling (wreg/rreg via data)
+C   cntl := 0000000000000000  (nf=0,stat=000,nbusy=0)
+C   cntl -> 0000000000000000
+C   data := 0011001100000000  -> ncyc=1
+C   attn -> 0000000000000001
+C   data -> 0011001100000000  -> ncyc=1
+C   attn -> 0000000000000001
+C   ==> shows that reading register attn returns proper ncyc if no busy
+C
+C wreg: tx: sop - cmd(00001,010) addr(0000) dl dh ccrc
+C rreg: tx:     - cmd(00010,000) addr(0000) ccrc
+C wreg: tx:     - cmd(00011,010) addr(0001) dl dh ccrc
+C rreg: tx:     - cmd(00100,000) addr(0011) ccrc
+C rreg: tx:     - cmd(00101,000) addr(0001) ccrc
+C rreg: tx:     - cmd(00110,000) addr(0011) ccrc
+C       tx:     - eop
+C       rx: sop - cmd(010) stat crc
+C       rx:     - cmd(000) dl dh stat crc
+C       rx:     - cmd(010) stat crc
+C       rx:     - cmd(000) dl dh stat crc
+C       rx:     - cmd(000) dl dh stat crc
+C       rx:     - cmd(000) dl dh stat crc
+C       rx:     - eop
+C
+#
+rxsop 
+rxcs   00001010 00000000
+rxcds  00010000          0000000000000000 00000000
+rxcs   00011010 00000000
+rxcds  00100000          0000000000000001 00000000
+rxcds  00101000          0011001100000000 00000000
+rxcds  00110000          0000000000000001 00000000
+rxeop 
+#
+txsop 
+txcad  00001010 11110000 0000000000000000
+txca   00010000 11110000
+txcad  00011010 11110001 0011001100000000
+txca   00100000 11110011
+txca   00101000 11110001
+txca   00110000 11110011
+txeop 
+#
+.iowt 10
+#
+C
+C - now with nbusy=1
+C   cntl := 0000000000000001  (nf=0,stat=000,nbusy=1)
+C   cntl -> 0000000000000001
+C   data := 0011001100000001  -> ncyc=2
+C   attn -> 0000000000000010
+C   data -> 0011001100000001  -> ncyc=2
+C   attn -> 0000000000000010
+C   ==> shows that wreg/rreg strech cycle; attn returns proper ncyc
+C
+#
+rxsop 
+rxcs   00001010 00000000
+rxcds  00010000          0000000000000001 00000000
+rxcs   00011010 00000000
+rxcds  00100000          0000000000000010 00000000
+rxcds  00101000          0011001100000001 00000000
+rxcds  00110000          0000000000000010 00000000
+rxeop 
+#
+txsop 
+txcad  00001010 11110000 0000000000000001
+txca   00010000 11110000
+txcad  00011010 11110001 0011001100000001
+txca   00100000 11110011
+txca   00101000 11110001
+txca   00110000 11110011
+txeop 
+#
+.iowt 10
+#
+C
+C - now with nbusy=2
+C   cntl := 0000000000000010  (nf=0,stat=000,nbusy=2)
+C   cntl -> 0000000000000010
+C   data := 0011001100000010  -> ncyc=3
+C   attn -> 0000000000000011
+C   data -> 0011001100000010  -> ncyc=3
+C   attn -> 0000000000000011
+C
+#
+rxsop 
+rxcs   00001010 00000000
+rxcds  00010000          0000000000000010 00000000
+rxcs   00011010 00000000
+rxcds  00100000          0000000000000011 00000000
+rxcds  00101000          0011001100000010 00000000
+rxcds  00110000          0000000000000011 00000000
+rxeop 
+#
+txsop 
+txcad  00001010 11110000 0000000000000010
+txca   00010000 11110000
+txcad  00011010 11110001 0011001100000010
+txca   00100000 11110011
+txca   00101000 11110001
+txca   00110000 11110011
+txeop 
+#
+.iowt 10
+#
+C
+C - now with nbusy=31 (still succeeds)
+C   cntl := 0000000000011111  (nf=0,stat=000,nbusy=31)
+C   cntl -> 0000000000011111
+C   data := 0011001100011111  -> ncyc=32
+C   attn -> 0000000000100000
+C   data -> 0011001100011111  -> ncyc=32
+C   attn -> 0000000000100000
+C
+#
+rxsop 
+rxcs   00001010 00000000
+rxcds  00010000          0000000000011111 00000000
+rxcs   00011010 00000000
+rxcds  00100000          0000000000100000 00000000
+rxcds  00101000          0011001100011111 00000000
+rxcds  00110000          0000000000100000 00000000
+rxeop 
+#
+txsop 
+txcad  00001010 11110000 0000000000011111
+txca   00010000 11110000
+txcad  00011010 11110001 0011001100011111
+txca   00100000 11110011
+txca   00101000 11110001
+txca   00110000 11110011
+txeop 
+#
+.iowt 20
+#
+C
+C - now with nbusy=32  (fails with rbnak=1)
+C   cntl := 0000000000100000  (nf=0,stat=000,nbusy=32)
+C   cntl -> 0000000000100000
+C   data := 0011001100100000  -> ncyc=32, rbnak=1
+C   attn -> 0000000000100000
+C   data -> 0011001100100000  -> ncyc=32, rbnak=1
+C   attn -> 0000000000100000
+C
+C     stat: stat(000),attn(0),cerr(0),derr(0),rbnak(1),rberr(0) -> 00000010
+C   ==> shows that timeout abort works
+C
+#
+rxsop 
+rxcs   00001010 00000000
+rxcds  00010000          0000000000100000 00000000
+rxcs   00011010 00000010
+rxcds  00100000          0000000000100000 00000000
+rxcds  00101000          0101010101010101 00000010
+rxcds  00110000          0000000000100000 00000000
+rxeop 
+#
+txsop 
+txcad  00001010 11110000 0000000000100000
+txca   00010000 11110000
+txcad  00011010 11110001 0011001100100000
+txca   00100000 11110011
+txca   00101000 11110001
+txca   00110000 11110011
+txeop 
+#
+.iowt 20
+#
+C
+C - now with nbusy=1023
+C   cntl := 0000001111111111  (nf=0,stat=000,nbusy=1023)
+C   cntl -> 0000001111111111
+C   data := 0011001111111111  -> ncyc=32,rbnak=1
+C   attn -> 0000000000100000
+C   data -> 0101010101010101  -> ncyc=32,rbnak=1
+C   attn -> 0000000000100000
+C
+C     stat: stat(000),attn(0),cerr(0),derr(0),rbnak(1),rberr(0) -> 00000010
+C
+#
+rxsop 
+rxcs   00001010 00000000
+rxcds  00010000          0000001111111111 00000000
+rxcs   00011010 00000010
+rxcds  00100000          0000000000100000 00000000
+rxcds  00101000          0101010101010101 00000010
+rxcds  00110000          0000000000100000 00000000
+rxeop 
+#
+txsop 
+txcad  00001010 11110000 0000001111111111
+txca   00010000 11110000
+txcad  00011010 11110001 0011001111111111
+txca   00100000 11110011
+txca   00101000 11110001
+txca   00110000 11110011
+txeop 
+#
+.iowt 20
+#
+C -----------------------------------------------------------------------------
+C Test 11: rbus busy handling (wblk/rblk via fifo)
+C   cntl := 0000000000000000  (nf=0,stat=000,nbusy=0)
+C   cntl -> 0000000000000000
+C   write 2 words to fifo     -> ncyc=1
+C   attn -> 0000000000000001
+C   read  2 words from fifo   -> ncyc=1
+C   attn -> 0000000000000001
+C
+C wreg: tx: sop - cmd(00001,010) addr(0000) dl dh ccrc
+C rreg: tx:     - cmd(00010,000) addr(0000) ccrc
+C wblk: tx:     - cmd(00011,011) addr(0010) cnt(2->001) ccrc dl dh .. dcrc
+C rreg: tx:     - cmd(00100,000) addr(0011) ccrc
+C rblk: tx:     - cmd(00101,001) addr(0010) cnt(2->001) ccrc
+C rreg: tx:     - cmd(00110,000) addr(0011) ccrc
+C       tx:     - eop
+C       rx: sop - cmd(010) stat crc
+C       rx:     - cmd(000) dl dh stat crc
+C       rx:     - cmd(011) stat crc
+C       rx:     - cmd(000) dl dh stat crc
+C       rx:     - cmd(001) cnt dl dh ... stat crc
+C       rx:     - cmd(000) dl dh stat crc
+C       rx:     - eop
+C
+rxsop 
+rxcs   00001010 00000000
+rxcds  00010000          0000000000000000 00000000
+rxcs   00011011 00000000
+rxcds  00100000          0000000000000001 00000000
+rx8    00101001
+rx8    00000001
+rx16   0011001100000000
+rx16   0011001100000001
+rx8    00000000
+rxcrc 
+rxcds  00110000          0000000000000001 00000000
+rxeop 
+#
+txsop 
+txcad  00001010 11110000 0000000000000000
+txca   00010000 11110000
+txcac  00011011 11110010 00000001
+tx16   0011001100000000
+tx16   0011001100000001
+txcrc 
+txca   00100000 11110011
+txcac  00101001 11110010 00000001
+txca   00110000 11110011
+txeop 
+#
+.iowt 10
+#
+C
+C - now with nbusy=1
+C   cntl := 0000000000000001  (nf=0,stat=000,nbusy=1)
+C   cntl -> 0000000000000001
+C   write 2 words to fifo     -> ncyc=2
+C   attn -> 0000000000000010
+C   read  2 words from fifo   -> ncyc=2
+C   attn -> 0000000000000010
+C
+rxsop 
+rxcs   00001010 00000000
+rxcds  00010000          0000000000000001 00000000
+rxcs   00011011 00000000
+rxcds  00100000          0000000000000010 00000000
+rx8    00101001
+rx8    00000001
+rx16   0011001100000000
+rx16   0011001100000001
+rx8    00000000
+rxcrc 
+rxcds  00110000          0000000000000010 00000000
+rxeop 
+#
+txsop 
+txcad  00001010 11110000 0000000000000001
+txca   00010000 11110000
+txcac  00011011 11110010 00000001
+tx16   0011001100000000
+tx16   0011001100000001
+txcrc 
+txca   00100000 11110011
+txcac  00101001 11110010 00000001
+txca   00110000 11110011
+txeop 
+#
+.iowt 10
+#
+C
+C - now with nbusy=31 (still succeeds)
+C   cntl := 0000000000011111  (nf=0,stat=000,nbusy=31)
+C   cntl -> 0000000000011111
+C   write 2 words to fifo     -> ncyc=32
+C   attn -> 0000000000100000
+C   read  2 words from fifo   -> ncyc=32
+C   attn -> 0000000000100000
+C
+rxsop 
+rxcs   00001010 00000000
+rxcds  00010000          0000000000011111 00000000
+rxcs   00011011 00000000
+rxcds  00100000          0000000000100000 00000000
+rx8    00101001
+rx8    00000001
+rx16   0011001100000000
+rx16   0011001100000001
+rx8    00000000
+rxcrc 
+rxcds  00110000          0000000000100000 00000000
+rxeop 
+#
+txsop 
+txcad  00001010 11110000 0000000000011111
+txca   00010000 11110000
+txcac  00011011 11110010 00000001
+tx16   0011001100000000
+tx16   0011001100000001
+txcrc 
+txca   00100000 11110011
+txcac  00101001 11110010 00000001
+txca   00110000 11110011
+txeop 
+#
+.iowt 20
+#
+C
+C - now with nbusy=32  (fails with rbnak=1)
+C   cntl := 0000000000100000  (nf=0,stat=000,nbusy=32)
+C   cntl -> 0000000000100000
+C   write 2 words to fifo     -> ncyc=32,rbnak=1
+C   attn -> 0000000000100000
+C   read  2 words from fifo   -> ncyc=32,rbnak=1
+C   attn -> 0000000000100000
+C
+C     stat: stat(000),attn(0),cerr(0),derr(0),rbnak(1),rberr(0) -> 00000010
+C
+rxsop 
+rxcs   00001010 00000000
+rxcds  00010000          0000000000100000 00000000
+rxcs   00011011 00000010
+rxcds  00100000          0000000000100000 00000000
+rx8    00101001
+rx8    00000001
+rx16   0101010101010101
+rx16   0101010101010101
+rx8    00000010
+rxcrc 
+rxcds  00110000          0000000000100000 00000000
+rxeop 
+#
+txsop 
+txcad  00001010 11110000 0000000000100000
+txca   00010000 11110000
+txcac  00011011 11110010 00000001
+tx16   0011001100000000
+tx16   0011001100000001
+txcrc 
+txca   00100000 11110011
+txcac  00101001 11110010 00000001
+txca   00110000 11110011
+txeop 
+#
+.iowt 20
+#
+C -----------------------------------------------------------------------------
+C Test 12a: rbus delay non-ack handling (wreg/rreg via disabled fifo)
+C   cntl := 1000000000000011  (nf=1,stat=000,nbusy=3)
+C   cntl -> 1000000000000011
+C   data := 1111000000000011  -> ncyc=4,rbnak=1
+C   attn -> 0000000000000100
+C   data -> 0000000000000000  -> ncyc=4,rbnak=1
+C   attn -> 0000000000000100
+C   init (11110000:0000000000000111)   clear all  
+C
+C     stat: stat(000),attn(0),cerr(0),derr(0),rbnak(1),rberr(0) -> 00000010
+C   ==> shows that cycle can be first stretched and than aborted
+C
+C wreg: tx: sop - cmd(00001,010) addr(0000) dl dh ccrc
+C rreg: tx:     - cmd(00010,000) addr(0000) ccrc
+C wreg: tx:     - cmd(00011,010) addr(0010) dl dh ccrc
+C rreg: tx:     - cmd(00100,000) addr(0011) ccrc
+C rreg: tx:     - cmd(00101,000) addr(0010) ccrc
+C rreg: tx:     - cmd(00110,000) addr(0011) ccrc
+C init: tx:     - cmd(00111,110) addr(0000) dl dh ccrc
+C       tx:     - eop
+C       rx: sop - cmd(010) stat crc
+C       rx:     - cmd(000) dl dh stat crc
+C       rx:     - cmd(010) stat crc
+C       rx:     - cmd(000) dl dh stat crc
+C       rx:     - cmd(000) dl dh stat crc
+C       rx:     - cmd(000) dl dh stat crc
+C       rx:     - cmd(110) stat crc
+C       rx:     - eop
+C
+#
+rxsop 
+rxcs   00001010 00000000
+rxcds  00010000          1000000000000011 00000000
+rxcs   00011010 00000010
+rxcds  00100000          0000000000000100 00000000
+rxcds  00101000          0000000000000000 00000010
+rxcds  00110000          0000000000000100 00000000
+rxcs   00111110 00000000
+rxeop 
+#
+txsop 
+txcad  00001010 11110000 1000000000000011
+txca   00010000 11110000
+txcad  00011010 11110010 1111000000000011
+txca   00100000 11110011
+txca   00101000 11110010
+txca   00110000 11110011
+txcad  00111110 11110000 0000000000000111
+txeop 
+#
+.iowt 10
+#
+C -----------------------------------------------------------------------------
+C Test 12b: rbus delay non-ack handling (wbk/rblk via disabled fifo)
+C   cntl := 1000000000000011  (nf=1,stat=000,nbusy=3)
+C   cntl -> 1000000000000011
+C   write 2 words to fifo     -> ncyc=3,rbnak=1
+C   attn -> 0000000000000100
+C   read  2 words from fifo   -> ncyc=3,rbnak=1
+C   attn -> 0000000000000100
+C   init (11110000:0000000000000111)   clear all  
+C
+C wreg: tx: sop - cmd(00001,010) addr(0000) dl dh ccrc
+C rreg: tx:     - cmd(00010,000) addr(0000) ccrc
+C wblk: tx:     - cmd(00011,011) addr(0010) cnt(2->001) ccrc dl dh .. dcrc
+C rreg: tx:     - cmd(00100,000) addr(0011) ccrc
+C rblk: tx:     - cmd(00101,001) addr(0010) cnt(2->001) ccrc
+C rreg: tx:     - cmd(00110,000) addr(0011) ccrc
+C init: tx:     - cmd(00111,110) addr(0000) dl dh ccrc
+C       tx:     - eop
+C       rx: sop - cmd(010) stat crc
+C       rx:     - cmd(000) dl dh stat crc
+C       rx:     - cmd(011) stat crc
+C       rx:     - cmd(000) dl dh stat crc
+C       rx:     - cmd(001) cnt dl dh ... stat crc
+C       rx:     - cmd(000) dl dh stat crc
+C       rx:     - cmd(110) stat crc
+C       rx:     - eop
+C
+rxsop 
+rxcs   00001010 00000000
+rxcds  00010000          1000000000000011 00000000
+rxcs   00011011 00000010
+rxcds  00100000          0000000000000100 00000000
+rx8    00101001
+rx8    00000001
+rx16   0000000000000000
+rx16   0000000000000000
+rx8    00000010
+rxcrc 
+rxcds  00110000          0000000000000100 00000000
+rxcs   00111110 00000000
+rxeop 
+#
+txsop 
+txcad  00001010 11110000 1000000000000011
+txca   00010000 11110000
+txcac  00011011 11110010 00000001
+tx16   1111000000000000
+tx16   1111000000000001
+txcrc 
+txca   00100000 11110011
+txcac  00101001 11110010 00000001
+txca   00110000 11110011
+txcad  00111110 11110000 0000000000000111
+txeop 
+#
+.iowt 10
+#
+C -----------------------------------------------------------------------------
+C Test 13a: attention logic (via asynchronous LAM from test bench)
+C   .attn   0000000000000000          
+C   cmd attn returns 0000000000000000, stat=00000000
+C   .attn   1000000000000000
+C   cmd attn returns 1000000000000000, stat=00000000
+C   cmd attn returns 0000000000000000, stat=00000000
+C   .attn   0100000000000000
+C   .attn   0010000000000000
+C   cmd attn returns 0110000000000000, stat=00000000
+C   cmd attn returns 0000000000000000, stat=00000000
+C
+C   ==> shows that attn command works properly
+C
+C       .attn 0000000000000000
+C attn: tx: sop - cmd(00001,101) ccrc - eop
+C       rx: sop - cmd(101) dl dh stat crc - eop
+#
+.attn  0000000000000000
+rxsop 
+rxcds  00001101          0000000000000000 00000000
+rxeop 
+txsop 
+txc    00001101
+txeop 
+.iowt  10
+C
+C       .attn 1000000000000000
+C attn: tx: sop - cmd(00010,101) ccrc
+C attn: tx:     - cmd(00011,101) ccrc - eop
+C       rx: sop - cmd(101) dl dh stat crc
+C       rx:     - cmd(101) dl dh stat crc - eop
+#
+.attn  1000000000000000
+rxsop 
+rxcds  00010101          1000000000000000 00000000
+rxcds  00011101          0000000000000000 00000000
+rxeop 
+txsop 
+txc    00010101
+txc    00011101
+txeop 
+.iowt  10
+C
+C       .attn 0100000000000000
+C       .attn 0110000000000000
+C attn: tx: sop - cmd(00100,101) ccrc
+C attn: tx:     - cmd(00101,101) ccrc - eop
+C       rx: sop - cmd(101) dl dh stat crc
+C       rx:     - cmd(101) dl dh stat crc - eop
+C
+#
+.attn  0100000000000000
+.attn  0010000000000000
+rxsop 
+rxcds  00100101          0110000000000000 00000000
+rxcds  00101101          0000000000000000 00000000
+rxeop 
+txsop 
+txc    00100101
+txc    00101101
+txeop 
+.iowt 10
+#
+C -----------------------------------------------------------------------------
+C Test 13b: attention logic (via synchronous LAM from rbd_tester)
+C   attn := 0000000000000000           stat=00000000
+C   cmd attn returns 0000000000000000, stat=00000000
+C   attn := 0000000000000001           stat=00010000
+C   cmd attn returns 0000000000000001, stat=00000000
+C   cmd attn returns 0000000000000000, stat=00000000
+C   attn := 0000000000000010           stat=00010000
+C   attn := 0000000000000100           stat=00010000
+C   cmd attn returns 0000000000000110, stat=00000000
+C   cmd attn returns 0000000000000000, stat=00000000
+C
+C     stat: stat(000),attn(1),cerr(0),derr(0),rbnak(0),rberr(0) -> 00010000
+C   ==> shows that attn command works properly
+C   ==> shows that attn register in tb_rlink triggers RB_LAM
+C
+C wreg: tx: sop - cmd(00001,010) addr(0011) dl dh ccrc
+C attn: tx:     - cmd(00010,101) ccrc
+C wreg: tx:     - cmd(00011,010) addr(0011) dl dh ccrc
+C attn: tx:     - cmd(00100,101) ccrc
+C attn: tx:     - cmd(00101,101) ccrc
+C wreg: tx:     - cmd(00110,010) addr(0011) dl dh ccrc
+C wreg: tx:     - cmd(00111,010) addr(0011) dl dh ccrc
+C attn: tx:     - cmd(01000,101) ccrc
+C attn: tx:     - cmd(01001,101) ccrc
+C       tx:     - eop
+C       rx: sop - cmd(010) stat crc
+C       rx:     - cmd(101) dl dh stat crc
+C       rx:     - cmd(010) stat crc
+C       rx:     - cmd(101) dl dh stat crc
+C       rx:     - cmd(101) dl dh stat crc
+C       rx:     - cmd(010) stat crc
+C       rx:     - cmd(010) stat crc
+C       rx:     - cmd(101) dl dh stat crc
+C       rx:     - cmd(101) dl dh stat crc
+C       rx:     - eop
+C
+#
+rxsop 
+rxcs   00001010 00000000
+rxcds  00010101          0000000000000000 00000000
+rxcs   00011010 00010000
+rxcds  00100101          0000000000000001 00000000
+rxcds  00101101          0000000000000000 00000000
+rxcs   00110010 00010000
+rxcs   00111010 00010000
+rxcds  01000101          0000000000000110 00000000
+rxcds  01001101          0000000000000000 00000000
+rxeop 
+#
+txsop 
+txcad  00001010 11110011 0000000000000000
+txc    00010101
+txcad  00011010 11110011 0000000000000001
+txc    00100101
+txc    00101101
+txcad  00110010 11110011 0000000000000010
+txcad  00111010 11110011 0000000000000100
+txc    01000101
+txc    01001101
+txeop 
+#
+.iowt 10
+#
+C -----------------------------------------------------------------------------
+C Test 14: attn poll
+C   send 2 attn commas, get 2 idle chars
+C   attn := 0000000000001000           stat=00010000
+C   send 2 attn commas, get 2 attn chars
+C   cmd attn returns 0000000000001000, stat=00010000
+C   send 2 attn commas, get 2 idle chars
+C
+C send 2 <attn>, expect two <idle> back
+C
+C oof:  tx: attn - attn
+C       rx: idle - idle
+C
+rxidle
+rxidle
+txattn
+txattn
+.iowt 10
+C
+C write attn register, set attn bit and flag
+C
+C wreg: tx: sop  - cmd(00001,010) addr(0011) dl dh ccrc - eop
+C       rx: sop  - cmd(010) stat crc - eop
+C
+rxsop 
+rxcs   00001010 00010000
+rxeop 
+txsop 
+txcad  00001010 11110011 0000000000001000
+txeop 
+.iowt 10
+C
+C send 2 <attn>, expect two <attn> back
+C
+C oof:  tx: attn - attn
+C       rx: attn - attn
+C
+rxattn
+rxattn
+txattn
+txattn
+.iowt 10
+C
+C send attn cmd, read and clear attn bits and flag
+C
+C attn: tx:      - cmd(00010,101) ccrc  - eop
+C       rx:      - cmd(101) dl dh stat crc - eop
+C
+rxsop 
+rxcds  00010101          0000000000001000 00000000
+rxeop 
+txsop 
+txc    00010101
+txeop 
+.iowt 10
+C
+C send 2 <attn>, expect two <idle> back
+C
+C oof:  tx: attn - attn
+C       rx: idle - idle
+C
+rxidle
+rxidle
+txattn
+txattn
+.iowt 10
+#
+C -----------------------------------------------------------------------------
+C Test 15a: enable and test asynchronous attn notification (when idle)
+C   init (11111111:1000000000000000)  noop
+C      anena(1), itoena(0), ito(0)   -> 11111111,1000000000000000
+C   .attn   0001000000000000
+C      --> <attn> will be send
+C   cmd attn returns 0001000000000000, stat=00000000
+C
+C   ==> shows that internal init works
+C   ==> shows asynchronous attn notification works
+C
+C init: tx: sob - cmd(00001,110) addr(11111111) dl dh ccrc - eop
+C       rx: sob - cmd(110) stat crc - eop
+C
+rxsop 
+rxcs   00001110 00000000
+rxeop 
+txsop 
+txcad  00001110 11111111 1000000000000000
+txeop 
+.iowt 10
+C
+C now ping an attention line, expect out-of-frame attn symbol
+C       .attn 0001000000000000
+C       rx: attn
+C
+.wait 20
+rxattn
+.attn  0001000000000000
+.wait 20
+.iowt 10
+C
+C attn: tx:     - cmd(00010,101) ccrc  - eop
+C       rx:     - cmd(101) dl dh stat crc - eop
+C
+rxsop 
+rxcds  00010101          0001000000000000 00000000
+rxeop 
+txsop 
+txc    00010101
+txeop 
+.iowt 10
+#
+C -----------------------------------------------------------------------------
+C Test 15b: enable and test asynchronous attn notification (when in packet)
+C   attn := 0000000000010000           stat=00010000
+C      --> <attn> will be send after eop
+C   cmd attn returns 0000000000010000, stat=00000000
+C   
+C   ==> shows asynchronous attn notification comes after eop
+C
+C write attn register, set attn bit and flag, expect <attn> comma after <eop>
+C
+C wreg: tx: sop - cmd(00001,010) addr(0011) dl dh ccrc - eop
+C       rx: sop - cmd(010) stat crc - eop
+C       rx: attn
+C
+rxsop 
+rxcs   00001010 00010000
+rxeop 
+rxattn
+txsop 
+txcad  00001010 11110011 0000000000010000
+txeop 
+.iowt 10
+C
+C send attn cmd, read and clear attn bits and flag
+C
+C attn: tx:     - cmd(00010,101) ccrc  - eop
+C       rx:     - cmd(101) dl dh stat crc - eop
+C
+rxsop 
+rxcds  00010101          0000000000010000 00000000
+rxeop 
+txsop 
+txc    00010101
+txeop 
+.iowt 10
+#
+C -----------------------------------------------------------------------------
+C Test 16: ccrc error abort for attn,init
+C
+C attn: tx: sop - cmd(00001,101) *BAD CRC - eop
+C       rx: sop - nak - eop
+C
+rxsop 
+rxnak 
+rxeop 
+#
+txsop 
+tx8    00001101 
+txbad  
+txeop 
+#
+.iowt 10
+#
+C
+C init: tx:     - cmd(00010,110) addr(0000) dl dh ccrc
+C       rx: sop - nak - eop
+C
+rxsop 
+rxnak 
+rxeop 
+#
+txsop 
+tx8    00010110 
+tx8    11110000
+tx8    00000000
+tx8    00000000
+txbad 
+txeop 
+#
+.iowt 10
+#
+C -----------------------------------------------------------------------------
+C Test 17: enable and test idle timeout
+C   init (11111111:1100000000001001)
+C      anena(1), itoena(1), ito(9)   -> 11111111,1100000000001001
+C      ito=9 --> divider=10; ce_xsec div is 1:20 --> total every 200 cycles
+C   --> send <idle> every 200 cycles
+C   .attn   0000100000000000
+C   --> send <attn> every 200 cycles
+C   cmd attn returns 0000100000000000, stat=00000000
+C   --> send <idle> every 200 cycles
+C   init (11111111:0000000000000000)
+C
+C first init (11111111:1100000000001001) -> enable idle timeout
+C
+C init: tx: sob - cmd(00001,110) addr(00000011) dl dh ccrc - eop
+C       rx: sob - cmd(110) stat crc - eop
+C       rx: idle (every 200 cycles)
+C       .attn 0000100000000000
+C       rx: attn (every 200 cycles)
+C
+rxsop 
+rxcs   00001110 00000000
+rxeop 
+rxidle
+rxidle
+txsop 
+txcad  00001110 11111111 1100000000001001
+txeop 
+.iowt 10
+.wait 500
+C
+C set attn bits, now <attn> send (1 prompt, 2 more every 200 cycles) 
+C
+rxattn
+rxattn
+rxattn
+.attn  0000100000000000
+.wait 500
+C
+C send attn cmd, read and clear attn bits and flag
+C
+C attn: tx:     - cmd(00010,101) ccrc  - eop
+C       rx:     - cmd(101) dl dh stat crc - eop
+C       rx: idle (every 200 cycles)
+C
+rxsop 
+rxcds  00010101          0000100000000000 00000000
+rxeop 
+rxidle
+rxidle
+txsop 
+txc    00010101
+txeop 
+.iowt 10
+.wait 500
+C
+C second init (11111111:0000000000000000) -> disable idle timeout
+C
+C init: tx: sob - cmd(00011,110) addr(00000011) dl dh ccrc - eop
+C       rx: sob - cmd(110) stat crc - eop
+C
+rxsop 
+rxcs   00001110 00000000
+rxeop 
+txsop 
+txcad  00001110 11111111 0000000000000000
+txeop 
+.iowt 10
+C
+C wait to be sure there are no more <idle> or <attn> comming
+C
+.wait 300
+#
+C -----------------------------------------------------------------------------
+C Test 18a: verify that <idle> commas are tolerated at any state: wreg/rreg
+C          do wreg+rreg, with <idle> between all command bytes send
+C          use as data 1000000 and 10000001 to force escaping here
+C
+C wreg: tx: sop - cmd(00001,010) addr(0001) dl dh ccrc
+C rreg: tx:     - cmd(00010,000) addr(0001) ccrc
+C       tx:     - eop
+C       rx: sop - cmd(010) stat crc
+C       rx:     - cmd(000) dl dh stat crc
+C       rx:     - eop
+#
+rxsop 
+rxcs   00001010 00000000
+rxcds  00010000          1000000010000001 00000000
+rxeop 
+#
+txidle
+txsop 
+txidle
+tx8    00001010 
+txidle
+tx8    11110001 
+txidle
+tx8    10000001
+txidle
+txidle
+tx8    10000000
+txidle
+txcrc 
+txidle
+tx8    00010000 
+txidle
+txidle
+txidle
+tx8    11110001
+txidle
+txcrc 
+txeop 
+#
+.iowt 10
+#
+C -----------------------------------------------------------------------------
+C Test 18b: verify that <idle> commas are tolerated at any state: wblk/rblk
+C          do wblk+rblk, with <idle> between all command bytes send
+C          use as data 1000000 to 10000011 to force escaping here
+C
+C wblk: tx: sop - cmd(00001,011) addr(0010) cnt(2->001) ccrc dl dh .. dcrc
+C rblk: tx:     - cmd(00010,001) addr(0010) cnt(2->001) ccrc
+C       tx:     - eop
+C       rx: sop - cmd(011) stat crc
+C       rx:     - cmd(001) cnt dl dh ... stat crc
+C       rx:     - eop
+#
+rxsop 
+rxcs   00001011 00000000
+rx8    00010001
+rx8    00000001
+rx16   1000000010000001
+rx16   1000001010000011
+rx8    00000000
+rxcrc 
+rxeop 
+#
+# wblk
+txidle
+txsop 
+txidle
+tx8    00001011
+txidle
+tx8    11110010
+txidle
+tx8    00000001
+txidle
+txcrc 
+txidle
+tx8    10000001
+txidle
+tx8    10000000
+txidle
+tx8    10000011
+txidle
+tx8    10000010
+txidle
+txcrc 
+# rblk
+txidle
+tx8    00010001
+txidle
+tx8    11110010
+txidle
+tx8    00000001
+txidle
+txcrc 
+txidle
+txeop 
+txidle
+#
+.iowt 10
+#
+C -----------------------------------------------------------------------------
+C Test 18c: verify that <idle> commas are tolerated at any state: stat,attn,init
+C   cntl := 0000000000001111
+C   cntl -> 0000000000001111
+C   cmd stat
+C   cmd attn
+C   cmd init (11110000:0000000000000001)  clear cntl
+C   cntl -> 0000000000000000
+C   
+C wreg: tx: sop - cmd(00001,010) addr(0000) dl dh ccrc
+C rreg: tx:     - cmd(00010,000) addr(0000) ccrc
+C stat: tx:     - cmd(00011,100) ccrc
+C attn: tx:     - cmd(00100,101) ccrc
+C init: tx:     - cmd(00101,110) addr(0000) dl dh ccrc
+C rreg: tx:     - cmd(00110,000) addr(0000) ccrc
+C       tx:     - eop
+C       rx: sop - cmd(010) stat crc
+C       rx:     - cmd(000) dl dh stat crc
+C       rx:     - cmd(100) ccmd(010) dl dh stat crc
+C       rx:     - cmd(101) dl dh stat crc
+C       rx:     - cmd(110) stat crc
+C       rx:     - cmd(000) dl dh stat crc
+C       rx:     - eop
+C
+#
+rxsop 
+rxcs   00001010 00000000                          
+rxcds  00010000          0000000000001111 00000000
+rxccd  00011100 00010000 0000000000001111 00000000
+rxcds  00100101          0000000000000000 00000000
+rxcs   00101110 00000000                          
+rxcds  00110000          0000000000000000 00000000
+rxeop 
+#
+txsop 
+# wreg
+txidle
+txcad  00001010 11110000 0000000000001111
+# rreg
+txidle
+txca   00010000 11110000 
+txidle
+# stat
+tx8    00011100 
+txidle
+txcrc 
+# attn
+txidle
+tx8    00100101 
+txidle
+txcrc 
+# init
+txidle
+tx8    00101110 
+txidle
+tx8    11110000 
+txidle
+tx8    00000001 
+txidle
+tx8    00000000 
+txidle
+txcrc 
+# rreg
+txidle
+txca   00110000 11110000 
+txidle
+txeop 
+#
+.iowt 10
+#
+C -----------------------------------------------------------------------------
+C Test 19: sop - eop framing
+C   test all sequences of sop and eop and nak
+C
+C 1. sop-eop  ==> sop-eop  (empty packet)
+C       tx: sop - eop
+C       rx: sop - eop
+C
+rxsop 
+rxeop 
+#
+txsop 
+txeop 
+.iowt 10
+C
+C 2. eop  ==> nak-eop  (out-of-order eop, gives nak)
+C       tx: eop
+C       rx: nak - eop
+C       tx: sop - eop
+C       rx: sop - eop
+C
+rxnak 
+rxeop 
+txeop 
+#
+.iowt 10
+rxsop 
+rxeop 
+txsop 
+txeop 
+.iowt 10
+C
+C 3. sop - sop - eop  ==> sop-nak-eop  (out-of-order sop, gives nak)
+C       tx: sop - sop - eop
+C       rx: sop - nak - eop
+C
+rxsop 
+rxnak 
+rxeop 
+# (use txoof for 2nd sop to avoid the side effects of txsop ) 
+txsop 
+txoof  100000001
+txeop 
+.iowt 10
+C
+C 4. sop - nak - eop  ==> sop-nak-eop  (nak is echoed)
+C       tx: sop - nak - eop
+C       rx: sop - nak - eop
+C
+rxsop 
+rxnak 
+rxeop 
+# 
+txsop 
+txoof  100000011
+txeop 
+.iowt 10
+C
+C 5. nak  ==> {ignored}  (out-of-order nak is ignored)
+C       tx: nak
+C       tx: sop - eop
+C       rx: sop - eop
+C
+rxsop 
+rxeop 
+# 
+txoof  100000011
+txsop 
+txeop 
+.iowt 10
+#
+C -----------------------------------------------------------------------------
+C Test 20: unused command code '111' gives a nak and transits to error state
+C   1. do '111' command (will abort with nak)
+C   2. do rreg command  (will be ignored)
+C
+C 111:  tx: sop - '111' 
+C rreg: tx:     - cmd(00010,000) addr(0001) ccrc
+C       tx:     - eop
+C       rx: sop - nak 
+C       rx:     - eop
+C
+rxsop 
+rxnak 
+rxeop 
+#
+txsop 
+tx8    00000111
+txca   00010000 11110001 
+txeop 
+.iowt 10
+#
+C -----------------------------------------------------------------------------
+C Test 21a: eop aborts of wreg
+C
+C 0. write all-1s to data register and read back to initialize context
+C wreg: tx: sop - cmd(11110,010) addr(0001) dl dh ccrc
+C rreg: tx:     - cmd(11111,000) addr(0001) ccrc 
+C       tx:     - eop
+C       rx: sop - cmd(010) stat crc
+C       rx: sop - cmd(000) dl dh stat crc
+C       rx:     - eop
+#
+rxsop 
+rxcs   11110010 00000000
+rxcds  11111000          1111111111111111 00000000
+rxeop 
+#
+txsop 
+txcad  11110010 11110001 1111111111111111
+txca   11111000 11110001
+txeop 
+#
+.iowt 10
+#
+C
+C 1a. abort after cmd
+C wreg: tx: sop - cmd(00001,010) [[addr(0001) dl dh ccrc]] - eop
+C       rx: sop - nak - eop
+C
+#
+rxsop 
+rxnak 
+rxeop 
+#
+txsop 
+tx8    00100010 
+txeop 
+.iowt 10
+C 
+C 1b. check stat
+C     stat: stat(000),attn(0),cerr(1),derr(0),rbnak(0),rberr(0) -> 00001000
+C stat: tx: sop - cmd(00110,100) ccrc - eop
+C       rx: sop - cmd(100) ccmd(000) dl dh stat crc - eop
+C
+#
+rxsop 
+rxccd  00110100 11111000 1111111111111111 00001000
+rxeop 
+txsop 
+txc    00110100
+txeop 
+.iowt 10
+C
+C 2a. abort after addr
+C wreg: tx: sop - cmd(00001,010) addr(0001) [[dl dh ccrc]] - eop
+C       rx: sop - nak - eop
+C
+#
+rxsop 
+rxnak 
+rxeop 
+#
+txsop 
+tx8    00001010 
+tx8    11110001 
+txeop 
+.iowt 10
+C 
+C 2b. check stat (stat as for 1a.)
+C
+#
+rxsop 
+rxccd  00110100 11111000 1111111111111111 00001000
+rxeop 
+txsop 
+txc    00110100
+txeop 
+.iowt 10
+C
+C 3a. abort after dl
+C wreg: tx: sop - cmd(00001,010) addr(0001) dl [[dh ccrc]] - eop
+C       rx: sop - nak - eop
+C
+#
+rxsop 
+rxnak 
+rxeop 
+#
+txsop 
+tx8    00001010 
+tx8    11110001 
+tx8    00000011 
+txeop 
+.iowt 10
+C 
+C 3b. check stat (stat as for 1a.)
+C
+#
+rxsop 
+rxccd  00110100 11111000 1111111111111111 00001000
+rxeop 
+txsop 
+txc    00110100
+txeop 
+.iowt 10
+C
+C 4a. abort after dh
+C wreg: tx: sop - cmd(00001,010) addr(0001) dl dh [[ccrc]] - eop
+C       rx: sop - nak - eop
+C
+#
+rxsop 
+rxnak 
+rxeop 
+#
+txsop 
+tx8    00001010 
+tx8    11110001 
+tx8    00000011 
+tx8    11000000 
+txeop 
+.iowt 10
+C 
+C 4b. check stat (stat as for 1a.)
+C
+#
+rxsop 
+rxccd  00110100 11111000 1111111111111111 00001000
+rxeop 
+txsop 
+txc    00110100
+txeop 
+.iowt 10
+C
+C 5a. finally just normal wreg to data register
+C wreg: tx: sop - cmd(00001,010) addr(0001) dl dh ccrc - eop
+C       rx: sop - cmd(010) stat crc - eop
+C
+#
+rxsop 
+rxcs   00001010 00000000
+rxeop 
+#
+txsop 
+tx8    00001010 
+tx8    11110001 
+tx8    00000011 
+tx8    11000000 
+txcrc 
+txeop 
+.iowt 10
+C 
+C 5b. check stat (now cerr=0 again)
+C
+#
+rxsop 
+rxccd  00110100 00001010 1111111111111111 00000000
+rxeop 
+txsop 
+txc    00110100
+txeop 
+.iowt 10
+#
+C -----------------------------------------------------------------------------
+C Test 21b: eop aborts of rreg
+C
+C 1a. abort after cmd
+C rreg: tx: sop - cmd(00001,000) [[addr(0001) ccrc]] - eop
+C       rx: sop - nak - eop
+C
+#
+rxsop 
+rxnak 
+rxeop 
+#
+txsop 
+tx8    00001000 
+txeop 
+.iowt 10
+C 
+C 1b. check stat (cerr=1, last successfull command in Test 21a/5a)
+C
+#
+rxsop 
+rxccd  00110100 00001010 1111111111111111 00001000
+rxeop 
+txsop 
+txc    00110100
+txeop 
+.iowt 10
+#
+C
+C 2a. abort after addr
+C rreg: tx: sop - cmd(00001,000) addr(0001) [[ccrc]] - eop
+C       rx: sop - nak - eop
+C
+#
+rxsop 
+rxnak 
+rxeop 
+#
+txsop 
+tx8    00001000 
+tx8    11110001
+txeop 
+.iowt 10
+C 
+C 2b. check stat (cerr=1)
+C
+#
+rxsop 
+rxccd  00110100 00001010 1111111111111111 00001000
+rxeop 
+txsop 
+txc    00110100
+txeop 
+.iowt 10
+C
+C 3a. finally just normal rreg from data register
+C rreg: tx: sop - cmd(00001,000) addr(0001) ccrc - eop
+C       rx: sop - cmd(000) dl dh stat crc - eop
+C
+#
+rxsop 
+rxcds  00001000          1100000000000011 00000000
+rxeop 
+#
+txsop 
+tx8    00001000 
+tx8    11110001
+txcrc 
+txeop 
+.iowt 10
+C 
+C 3b. check stat (cerr=0 again)
+C
+#
+rxsop 
+rxccd  00110100 00001000 1100000000000011 00000000
+rxeop 
+txsop 
+txc    00110100
+txeop 
+.iowt 10
+#
+C -----------------------------------------------------------------------------
+C Test 21c: eop aborts of wblk (with cnt=2)
+C
+C 1a. abort after cmd
+C wreg: tx: sop - cmd(00001,011) [[addr cnt(2->001) ccrc dl dh dl dh dcrc]] -eop
+C       rx: sop - nak - eop
+C
+#
+rxsop 
+rxnak 
+rxeop 
+#
+txsop 
+tx8    00001011 
+txeop 
+.iowt 10
+C 
+C 1b. check stat (cerr=1)
+C     stat: stat(000),attn(0),cerr(1),derr(0),rbnak(0),rberr(0) -> 00001000
+C
+#
+rxsop 
+rxccd  00110100 00001000 1100000000000011 00001000
+rxeop 
+txsop 
+txc    00110100
+txeop 
+.iowt 10
+C
+C 2a. abort after addr
+C wreg: tx: sop - cmd(00001,011) addr [[cnt(2->001) ccrc dl dh dl dh dcrc]] -eop
+C       rx: sop - nak - eop
+C
+#
+rxsop 
+rxnak 
+rxeop 
+#
+txsop 
+tx8    00001011 
+tx8    11110010
+txeop 
+.iowt 10
+C 
+C 2b. check stat (cerr=1)
+C
+#
+rxsop 
+rxccd  11110100 00001000 1100000000000011 00001000
+rxeop 
+txsop 
+txc    11110100
+txeop 
+.iowt 10
+C
+C 3a. abort after cnt
+C wreg: tx: sop - cmd(00001,011) addr cnt(2->001) [[ccrc dl dh dl dh dcrc]] -eop
+C       rx: sop - nak - eop
+C
+#
+rxsop 
+rxnak 
+rxeop 
+#
+txsop 
+tx8    00001011 
+tx8    11110010
+tx8    00000001
+txeop 
+.iowt 10
+C 
+C 3b. check stat (cerr=1)
+C
+#
+rxsop 
+rxccd  11110100 00001000 1100000000000011 00001000
+rxeop 
+txsop 
+txc    11110100
+txeop 
+.iowt 10
+C
+C 4a. abort after ccrc
+C wreg: tx: sop - cmd(00001,011) addr cnt(2->001) ccrc [[dl dh dl dh dcrc]] -eop
+C       rx: sop - cmd(011) - nak - eop
+C
+#
+rxsop 
+rx8    00001011 
+rxnak 
+rxeop 
+#
+txsop 
+tx8    00001011 
+tx8    11110010
+tx8    00000001
+txcrc
+txeop 
+.iowt 10
+C 
+C 4b. check stat (ccmd is wblk now; cerr=0,derr=1)
+C     stat: stat(000),attn(0),cerr(0),derr(1),rbnak(0),rberr(0) -> 00000100
+C
+#
+rxsop 
+rxccd  11110100 00001011 1100000000000011 00000100
+rxeop 
+txsop 
+txc    11110100
+txeop 
+.iowt 10
+C
+C 5a. abort after 1st dl
+C wreg: tx: sop - cmd(00010,011) addr cnt(2->001) ccrc dl [[dh dl dh dcrc]] -eop
+C       rx: sop - cmd(011) - nak - eop
+C
+#
+rxsop 
+rx8    00010011 
+rxnak 
+rxeop 
+#
+txsop 
+tx8    00010011 
+tx8    11110010
+tx8    00000001
+txcrc
+tx8    00000001
+txeop 
+.iowt 10
+C 
+C 5b. check stat (ccmd is wblk now; cerr=0,derr=1)
+C
+#
+rxsop 
+rxccd  11110100 00010011 1100000000000011 00000100
+rxeop 
+txsop 
+txc    11110100
+txeop 
+.iowt 10
+C
+C 6a. abort after 1st dh
+C wreg: tx: sop - cmd(00011,011) addr cnt(2->001) ccrc dl dh [[dl dh dcrc]] -eop
+C       rx: sop - cmd(011) - nak - eop
+C
+#
+rxsop 
+rx8    00011011 
+rxnak 
+rxeop 
+#
+txsop 
+tx8    00011011 
+tx8    11110010
+tx8    00000001
+txcrc
+tx8    00000001
+tx8    00011011
+txeop 
+.iowt 10
+C 
+C 6b. check stat (ccmd is wblk now; cerr=0,derr=1)
+C
+#
+rxsop 
+rxccd  11110100 00011011 1100000000000011 00000100
+rxeop 
+txsop 
+txc    11110100
+txeop 
+.iowt 10
+C
+C 7a. abort after 2nd dl
+C wreg: tx: sop - cmd(00100,011) addr cnt(2->001) ccrc dl dh dl [[dh dcrc]] -eop
+C       rx: sop - cmd(011) - nak - eop
+C
+#
+rxsop 
+rx8    00100011 
+rxnak 
+rxeop 
+#
+txsop 
+tx8    00100011 
+tx8    11110010
+tx8    00000001
+txcrc
+tx8    00000001
+tx8    00100011
+tx8    00000010
+txeop 
+.iowt 10
+C 
+C 7b. check stat (ccmd is wblk now; cerr=0,derr=1)
+C
+#
+rxsop 
+rxccd  11110100 00100011 1100000000000011 00000100
+rxeop 
+txsop 
+txc    11110100
+txeop 
+.iowt 10
+C
+C 8a. abort after 2nd dh
+C wreg: tx: sop - cmd(00101,011) addr cnt(2->001) ccrc dl dh dl dh [[dcrc]] -eop
+C       rx: sop - cmd(011) - nak - eop
+C
+#
+rxsop 
+rx8    00101011 
+rxnak 
+rxeop 
+#
+txsop 
+tx8    00101011 
+tx8    11110010
+tx8    00000001
+txcrc
+tx8    00000001
+tx8    00101011
+tx8    00000010
+tx8    00101011 
+txeop 
+.iowt 10
+C 
+C 8b. check stat (ccmd is wblk now; cerr=0,derr=1)
+C
+#
+rxsop 
+rxccd  11110100 00101011 1100000000000011 00000100
+rxeop 
+txsop 
+txc    11110100
+txeop 
+.iowt 10
+C
+C 9a. finally complete wblk without about, for a change
+C wreg: tx: sop - cmd(00110,011) addr cnt(2->001) ccrc dl dh dl dh dcrc - eop
+C       rx: sop - cmd(011) stat crc - eop
+C
+#
+rxsop 
+rx8    00101011 
+rx8    00000000 
+rxcrc
+rxeop 
+#
+txsop 
+tx8    00101011 
+tx8    11110010
+tx8    00000001
+txcrc
+tx8    00000001
+tx8    00110011
+tx8    00000010
+tx8    00110011 
+txcrc
+txeop 
+.iowt 10
+C
+C 10. now read back fifo, it will contain data from partially done wblk's
+C       6a:  00011011 00000001
+C       7a:  00100011 00000001
+C       8a:  00101011 00000001
+C            00101011 00000010
+C       9a:  00110011 00000001
+C            00110011 00000010
+C      --> read back 7 words, gives the above 6 plus '0101...' and a rberr=1
+C
+C rblk: tx: sop - cmd(00111,001) addr(0010) cnt(7->110) ccrc - eop
+C       rx: sop - cmd(001) cnt dl dh ... stat crc - eop
+C
+C     stat: stat(000),attn(0),cerr(0),derr(0),rbnak(0),rberr(1) -> 00000001
+C
+rxsop 
+rx8    00111001
+rx8    00000110
+rx16   0001101100000001
+rx16   0010001100000001
+rx16   0010101100000001
+rx16   0010101100000010
+rx16   0011001100000001
+rx16   0011001100000010
+rx16   0101010101010101
+rx8    00000001
+rxcrc 
+rxeop 
+#
+txsop 
+txcac  00111001 11110010 00000110
+txeop 
+#
+.iowt 10
+#
+C -----------------------------------------------------------------------------
+C Test 21d: eop aborts of rblk (with cnt=2)
+C
+C 1. to prepare write 2 words into fifo
+C wreg: tx: sop - cmd(00001,011) addr cnt(2->001) ccrc dl dh dl dh dcrc - eop
+C       rx: sop - cmd(011) stat crc - eop
+C
+#
+rxsop 
+rxcs   00001011 00000000
+rxeop 
+#
+txsop 
+txcac  00001011 11110010 00000001
+tx16   1111111100000000
+tx16   1111111100000001
+txcrc 
+txeop 
+.iowt 10
+#
+C
+C 2a. abort after cmd
+C rblk: tx: sop - cmd(00010,001) [[addr(0010) cnt(2->001) ccrc]] - eop
+C       rx: sop - nak - eop
+C
+rxsop
+rxnak
+rxeop
+#
+txsop
+tx8    00010001
+txeop
+.iowt 10
+#
+C 
+C 2b. check stat (cerr=1)
+C
+#
+rxsop 
+rxccd  11110100 00001011 0101010101010101 00001000
+rxeop 
+txsop 
+txc    11110100
+txeop 
+.iowt 10
+#
+C
+C 3a. abort after addr
+C rblk: tx: sop - cmd(00011,001) addr(0010) [[cnt(2->001) ccrc]] - eop
+C       rx: sop - nak - eop
+C
+rxsop
+rxnak
+rxeop
+#
+txsop
+tx8    00011001
+tx8    11110010
+txeop
+.iowt 10
+#
+C 
+C 3b. check stat (cerr=1)
+C
+#
+rxsop 
+rxccd  11110100 00001011 0101010101010101 00001000
+rxeop 
+txsop 
+txc    11110100
+txeop 
+.iowt 10
+C
+C 4a. abort after cnt
+C rblk: tx: sop - cmd(00100,001) addr(0010) cnt(2->001) [[ccrc]] - eop
+C       rx: sop - nak - eop
+C
+rxsop
+rxnak
+rxeop
+#
+txsop
+tx8    00100001
+tx8    11110010
+tx8    00000001
+txeop
+.iowt 10
+#
+C 
+C 4b. check stat (cerr=1)
+C
+#
+rxsop 
+rxccd  11110100 00001011 0101010101010101 00001000
+rxeop 
+txsop 
+txc    11110100
+txeop 
+.iowt 10
+#
+C
+C 5a. finally do successful rblk
+C rblk: tx: sop - cmd(00101,001) addr(0010) cnt(2->001) ccrc - eop
+C       rx: sop - cmd(001) cnt dl dh ... stat crc - eop
+C
+rxsop
+rx8    00101001
+rx8    00000001
+rx16   1111111100000000
+rx16   1111111100000001
+rx8    00000000
+rxcrc
+rxeop
+#
+txsop
+tx8    00101001
+tx8    11110010
+tx8    00000001
+txcrc
+txeop
+.iowt 10
+#
+C 
+C 5b. check stat (cerr=0)
+C
+#
+rxsop 
+rxccd  11110100 00101001 1111111100000001 00000000
+rxeop 
+txsop 
+txc    11110100
+txeop 
+.iowt 10
+#
+C -----------------------------------------------------------------------------
+C Test 21e: eop aborts of stat
+C
+C 1. abort after cmd
+C rblk: tx: sop - cmd(00001,100) [[ccrc]] - eop
+C       rx: sop - nak - eop
+C
+rxsop
+rxnak
+rxeop
+#
+txsop
+tx8    00001100
+txeop
+.iowt 10
+#
+C
+C 2. normal stat, finally
+C rblk: tx: sop - cmd(00010,100) [[ccrc]] - eop
+C       rx: sop - cmd(100) ccmd(001) dl dh stat crc
+C
+C     stat: stat(000),attn(0),cerr(0),derr(0),rbnak(0),rberr(0) -> 00000000
+C           --> Note: stat commands don't the status
+C           -->       no cerr bit set here, despite the failed stat above !!
+C
+rxsop
+rx8    00010100
+rx8    00101001
+rx16   1111111100000001
+rx8    00000000
+rxcrc  
+rxeop
+#
+txsop
+tx8    00010100
+txcrc
+txeop
+.iowt 10
+#
+C -----------------------------------------------------------------------------
+C Test 21f: eop aborts of attn
+C
+C 0. prepare, set 1 attn flag
+C
+.attn  0000000100000000
+C
+C 1a. abort after cmd
+C rblk: tx: sop - cmd(00001,101) [[ccrc]] - eop
+C       rx: sop - nak - eop
+C
+rxsop
+rxnak
+rxeop
+#
+txsop
+tx8    00001101
+txeop
+.iowt 10
+C 
+C 1b. check stat
+C     stat: stat(000),attn(1),cerr(1),derr(0),rbnak(0),rberr(0) -> 00011000
+C
+#
+rxsop 
+rxccd  11110100 00101001 1111111100000001 00011000
+rxeop 
+txsop 
+txc    11110100
+txeop 
+.iowt 10
+#
+C
+C 2. normal attn, finally
+C rblk: tx: sop - cmd(00001,101) ccrc - eop
+C       rx: sop - cmd(101) dl dh stat crc - eop
+C
+rxsop
+rx8    00001101
+rx16   0000000100000000
+rx8    00000000
+rxcrc
+rxeop
+#
+txsop
+tx8    00001101
+txcrc
+txeop
+.iowt 10
+#
+C -----------------------------------------------------------------------------
+C Test 21g: eop aborts of init
+C
+C 0. prepare, set data register
+C   data := 0000000000000001
+C
+rxsop 
+rxcs   00001010 00000000
+rxeop 
+txsop 
+txcad  00001010 11110001 0000000000000001
+txeop 
+.iowt 10
+#
+C
+C 1a. abort after cmd
+C rblk: tx: sop - cmd(00010,110) [[addr(0000) dl dh ccrc]] - eop
+C       rx: sop - nak - eop
+C
+rxsop
+rxnak
+rxeop
+#
+txsop
+tx8    00010110
+txeop
+.iowt 10
+C 
+C 1b. check stat
+C     stat: stat(000),attn(0),cerr(1),derr(0),rbnak(0),rberr(0) -> 00001000
+C
+#
+rxsop 
+rxccd  11110100 00001010 0000000100000000 00001000
+rxeop 
+txsop 
+txc    11110100
+txeop 
+.iowt 10
+C
+C 2a. abort after addr
+C rblk: tx: sop - cmd(00010,110) addr(0000) [[dl dh ccrc]] - eop
+C       rx: sop - nak - eop
+C
+rxsop
+rxnak
+rxeop
+#
+txsop
+tx8    00010110
+tx8    11110000
+txeop
+.iowt 10
+C 
+C 2b. check stat
+C
+#
+rxsop 
+rxccd  11110100 00001010 0000000100000000 00001000
+rxeop 
+txsop 
+txc    11110100
+txeop 
+.iowt 10
+C
+C 3a. abort after dl
+C rblk: tx: sop - cmd(00010,110) addr(0000) dl [[dh ccrc]] - eop
+C       rx: sop - nak - eop
+C
+rxsop
+rxnak
+rxeop
+#
+txsop
+tx8    00010110
+tx8    11110000
+tx8    00000010
+txeop
+.iowt 10
+C 
+C 3b. check stat
+C
+#
+rxsop 
+rxccd  11110100 00001010 0000000100000000 00001000
+rxeop 
+txsop 
+txc    11110100
+txeop 
+.iowt 10
+C
+C 4a. abort after dh
+C rblk: tx: sop - cmd(00010,110) addr(0000) dl dh [[ccrc]] - eop
+C       rx: sop - nak - eop
+C
+rxsop
+rxnak
+rxeop
+#
+txsop
+tx8    00010110
+tx8    11110000
+tx8    00000010
+tx8    00000000
+txeop
+.iowt 10
+C 
+C 4b. check stat
+C
+#
+rxsop 
+rxccd  11110100 00001010 0000000100000000 00001000
+rxeop 
+txsop 
+txc    11110100
+txeop 
+.iowt 10
+#
+C
+C 5a. normal init, finally
+C rblk: tx: sop - cmd(00010,110) addr(0000) dl dh ccrc - eop
+C       rx: sop - cmd(110) stat crc - eop
+C
+rxsop
+rx8    00010110
+rx8    00000000
+rxcrc
+rxeop
+#
+txsop
+tx8    00010110
+tx8    11110000
+tx8    00000010
+tx8    00000000
+txcrc
+txeop
+.iowt 10
+C
+C 5b. check that data register cleared
+C   data -> 0000000000000000
+C
+C rreg: tx: sop - cmd(00001,000) addr(0001) ccrc - eop
+C       rx: sop - cmd(000) dl dh stat crc - eop
+#
+rxsop 
+rxcds  00001000          0000000000000000 00000000
+rxeop 
+#
+txsop 
+txca   00001000 11110001
+txeop 
+#
+.iowt 10
+#
+C -----------------------------------------------------------------------------
+C Test 22: nak aborts of wreg
+C   Note: nak aborts only tested for wreg !
+C         sufficient because implementation is internally common for eop and
+C         nak aborts and all eop aborts are tested above in Test 21*.
+C
+C 0. write all-1s to data register and read back to initialize context
+C wreg: tx: sop - cmd(11110,010) addr(0001) dl dh ccrc
+C rreg: tx:     - cmd(11111,000) addr(0001) ccrc 
+C       tx:     - eop
+C       rx: sop - cmd(010) stat crc
+C       rx: sop - cmd(000) dl dh stat crc
+C       rx:     - eop
+#
+rxsop 
+rxcs   11110010 00000000
+rxcds  11111000          1111111111111111 00000000
+rxeop 
+#
+txsop 
+txcad  11110010 11110001 1111111111111111
+txca   11111000 11110001
+txeop 
+#
+.iowt 10
+#
+C
+C 1a. abort after cmd
+C wreg: tx: sop - cmd(00001,010) nak - eop
+C       rx: sop - nak - eop
+C
+#
+rxsop 
+rxnak 
+rxeop 
+#
+txsop 
+tx8    00100010 
+txnak
+txeop 
+.iowt 10
+C 
+C 1b. check stat
+C     stat: stat(000),attn(0),cerr(1),derr(0),rbnak(0),rberr(0) -> 00001000
+C stat: tx: sop - cmd(00110,100) ccrc - eop
+C       rx: sop - cmd(100) ccmd(000) dl dh stat crc - eop
+C
+#
+rxsop 
+rxccd  00110100 11111000 1111111111111111 00001000
+rxeop 
+txsop 
+txc    00110100
+txeop 
+.iowt 10
+C
+C 2a. abort after addr
+C wreg: tx: sop - cmd(00001,010) addr(0001) nak - eop
+C       rx: sop - nak - eop
+C
+#
+rxsop 
+rxnak 
+rxeop 
+#
+txsop 
+tx8    00001010 
+tx8    11110001
+txnak 
+txeop 
+.iowt 10
+C 
+C 2b. check stat (stat as for 1a.)
+C
+#
+rxsop 
+rxccd  00110100 11111000 1111111111111111 00001000
+rxeop 
+txsop 
+txc    00110100
+txeop 
+.iowt 10
+C
+C 3a. abort after dl
+C wreg: tx: sop - cmd(00001,010) addr(0001) dl nak - eop
+C       rx: sop - nak - eop
+C
+#
+rxsop 
+rxnak 
+rxeop 
+#
+txsop 
+tx8    00001010 
+tx8    11110001 
+tx8    00000011 
+txnak
+txeop 
+.iowt 10
+C 
+C 3b. check stat (stat as for 1a.)
+C
+#
+rxsop 
+rxccd  00110100 11111000 1111111111111111 00001000
+rxeop 
+txsop 
+txc    00110100
+txeop 
+.iowt 10
+C
+C 4a. abort after dh
+C wreg: tx: sop - cmd(00001,010) addr(0001) dl dh nak - eop
+C       rx: sop - nak - eop
+C
+#
+rxsop 
+rxnak 
+rxeop 
+#
+txsop 
+tx8    00001010 
+tx8    11110001 
+tx8    00000011 
+tx8    11000000 
+txnak
+txeop 
+.iowt 10
+C 
+C 4b. check stat (stat as for 1a.)
+C
+#
+rxsop 
+rxccd  00110100 11111000 1111111111111111 00001000
+rxeop 
+txsop 
+txc    00110100
+txeop 
+.iowt 10
+C
+C 5a. finally just normal wreg to data register
+C wreg: tx: sop - cmd(00001,010) addr(0001) dl dh ccrc - eop
+C       rx: sop - cmd(010) stat crc - eop
+C
+#
+rxsop 
+rxcs   00001010 00000000
+rxeop 
+#
+txsop 
+tx8    00001010 
+tx8    11110001 
+tx8    00000011 
+tx8    11000000 
+txcrc 
+txeop 
+.iowt 10
+C 
+C 5b. check stat (now cerr=0 again)
+C
+#
+rxsop 
+rxccd  00110100 00001010 1111111111111111 00000000
+rxeop 
+txsop 
+txc    00110100
+txeop 
+.iowt 10
+#
+#==============================================================================
+#
+C -----------------------------------------------------------------------------
+C Run down and Finish
+.iowt 10
+.wait 10
diff --git a/rtl/vlib/rri/tb/rritb_core.vbom b/rtl/vlib/rlink/tb/tbcore_rlink.vbom
similarity index 55%
rename from rtl/vlib/rri/tb/rritb_core.vbom
rename to rtl/vlib/rlink/tb/tbcore_rlink.vbom
index 7962d3d5..975e7ae3 100644
--- a/rtl/vlib/rri/tb/rritb_core.vbom
+++ b/rtl/vlib/rlink/tb/tbcore_rlink.vbom
@@ -2,11 +2,13 @@
 ../../slvtypes.vhd
 ../../simlib/simlib.vhd
 ../../simlib/simbus.vhd
-rritblib.vhd
-vhpi_rriext.vhd
+../../rbus/rblib.vhd
+../rlinklib.vbom
+rlinktblib.vhd
+rlink_cext_vhpi.vhd
 # components
 ../../simlib/simclk.vbom
 # vhpi
-cext_rriext.c
+rlink_cext.c
 # design
-rritb_core.vhd
+tbcore_rlink.vhd
diff --git a/rtl/vlib/rri/tb/rritb_core.vhd b/rtl/vlib/rlink/tb/tbcore_rlink.vhd
similarity index 88%
rename from rtl/vlib/rri/tb/rritb_core.vhd
rename to rtl/vlib/rlink/tb/tbcore_rlink.vhd
index 6b1a1e74..32195a77 100644
--- a/rtl/vlib/rri/tb/rritb_core.vhd
+++ b/rtl/vlib/rlink/tb/tbcore_rlink.vhd
@@ -1,4 +1,4 @@
--- $Id: rritb_core.vhd 314 2010-07-09 17:38:41Z mueller $
+-- $Id: tbcore_rlink.vhd 351 2010-12-30 21:50:54Z mueller $
 --
 -- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -12,18 +12,19 @@
 -- for complete details.
 -- 
 ------------------------------------------------------------------------------
--- Module Name:    rritb_core - sim
--- Description:    Core for a rri and cext based test bench
+-- Module Name:    tbcore_rlink - sim
+-- Description:    Core for a rlink_cext based test bench
 --
 -- Dependencies:   simlib/simclk
 --
--- To test:        generic, any rri/cext based target
+-- To test:        generic, any rlink_cext based target
 --
 -- Target Devices: generic
 -- Tool versions:  xst 11.4; ghdl 0.26
 -- Revision History: 
 -- Date         Rev Version  Comment
--- 2010-06-05   301   1.1.2  renamed .rpmon -> .rbmon
+-- 2010-12-29   351   3.0    rename rritb_core->tbcore_rlink; use rbv3 naming
+-- 2010-06-05   301   1.1.2  rename .rpmon -> .rbmon
 -- 2010-05-02   287   1.1.1  rename config command .sdata -> .sinit;
 --                           use sbcntl_sbf_(cp|rp)mon defs, use rritblib;
 -- 2010-04-25   283   1.1    new clk handling in proc_stim, wait period-setup
@@ -39,10 +40,12 @@ use std.textio.all;
 use work.slvtypes.all;
 use work.simlib.all;
 use work.simbus.all;
-use work.rritblib.all;
-use work.vhpi_rriext.all;
+use work.rblib.all;
+use work.rlinklib.all;
+use work.rlinktblib.all;
+use work.rlink_cext_vhpi.all;
 
-entity rritb_core is                    -- core of rri/cext based test bench
+entity tbcore_rlink is                  -- core of rlink_cext based test bench
   generic (
     CLK_PERIOD : time :=  20 ns;        -- clock period
     CLK_OFFSET : time := 200 ns;        -- clock offset (time to start clock)
@@ -56,9 +59,9 @@ entity rritb_core is                    -- core of rri/cext based test bench
     TX_DATA : in slv8;                  -- write data        (data tb->ext)
     TX_ENA : in slbit                   -- write data enable (data tb->ext)
   );
-end rritb_core;
+end tbcore_rlink;
 
-architecture sim of rritb_core is
+architecture sim of tbcore_rlink is
 
   signal CLK_L : slbit := '0';
   signal CLK_STOP : slbit := '0';
@@ -78,7 +81,7 @@ begin
   CLK <= CLK_L;
   
   proc_conf: process
-    file fconf : text open read_mode is "tb_rriext_conf";
+    file fconf : text open read_mode is "rlink_cext_conf";
     variable iline : line;
     variable oline : line;
     variable ok : boolean;
@@ -116,12 +119,12 @@ begin
               SB_CNTL(ibit) <= 'L';
             end if;
 
-          when ".cpmon" =>              -- .cpmon
+          when ".rlmon" =>              -- .rlmon
             read_ea(iline, ien);
             if ien = '1' then
-              SB_CNTL(sbcntl_sbf_cpmon) <= 'H';
+              SB_CNTL(sbcntl_sbf_rlmon) <= 'H';
             else
-              SB_CNTL(sbcntl_sbf_cpmon) <= 'L';
+              SB_CNTL(sbcntl_sbf_rlmon) <= 'L';
             end if;
 
           when ".rbmon" =>              -- .rbmon
@@ -188,7 +191,7 @@ begin
       RX_VAL <= '0';
 
       if RX_HOLD = '0'  then
-        irxint := cext_getbyte(icycle);
+        irxint := rlink_cext_getbyte(icycle);
         if irxint >= 0 then
           if irxint <= 16#ff# then      -- normal data byte
             RX_DATA <= conv_std_logic_vector(irxint, 8);
@@ -220,7 +223,7 @@ begin
         elsif irxint = -1 then           -- end-of-file seen
           exit stim_loop;
         else
-          report "cext_getbyte error: " & integer'image(-irxint)
+          report "rlink_cext_getbyte error: " & integer'image(-irxint)
             severity failure;
         end if;
       end if;
@@ -251,9 +254,9 @@ begin
       wait for C2OUT_TIME;
       if TX_ENA = '1' then
         itxdata := conv_integer(unsigned(TX_DATA));
-        itxrc := cext_putbyte(itxdata);
+        itxrc := rlink_cext_putbyte(itxdata);
         assert itxrc=0
-          report "cext_putbyte error: "  & integer'image(itxrc)
+          report "rlink_cext_putbyte error: "  & integer'image(itxrc)
           severity failure;
       end if;
 
diff --git a/rtl/vlib/rri/tb/rritb_core_dcm.vbom b/rtl/vlib/rlink/tb/tbcore_rlink_dcm.vbom
similarity index 59%
rename from rtl/vlib/rri/tb/rritb_core_dcm.vbom
rename to rtl/vlib/rlink/tb/tbcore_rlink_dcm.vbom
index ccb016c0..7c59d941 100644
--- a/rtl/vlib/rri/tb/rritb_core_dcm.vbom
+++ b/rtl/vlib/rlink/tb/tbcore_rlink_dcm.vbom
@@ -2,12 +2,14 @@
 ../../slvtypes.vhd
 ../../simlib/simlib.vhd
 ../../simlib/simbus.vhd
-rritblib.vhd
-vhpi_rriext.vhd
+../../rbus/rblib.vhd
+../rlinklib.vbom
+rlinktblib.vhd
+rlink_cext_vhpi.vhd
 # components
 ../../simlib/simclk.vbom
 ../../simlib/simclkcnt.vbom
 # vhpi
-cext_rriext.c
+rlink_cext.c
 # design
-rritb_core_dcm.vhd
+tbcore_rlink_dcm.vhd
diff --git a/rtl/vlib/rri/tb/rritb_core_dcm.vhd b/rtl/vlib/rlink/tb/tbcore_rlink_dcm.vhd
similarity index 89%
rename from rtl/vlib/rri/tb/rritb_core_dcm.vhd
rename to rtl/vlib/rlink/tb/tbcore_rlink_dcm.vhd
index 4f5e69a3..fb40ad86 100644
--- a/rtl/vlib/rri/tb/rritb_core_dcm.vhd
+++ b/rtl/vlib/rlink/tb/tbcore_rlink_dcm.vhd
@@ -1,4 +1,4 @@
--- $Id: rritb_core_dcm.vhd 339 2010-11-22 21:20:51Z mueller $
+-- $Id: tbcore_rlink_dcm.vhd 351 2010-12-30 21:50:54Z mueller $
 --
 -- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -12,19 +12,20 @@
 -- for complete details.
 -- 
 ------------------------------------------------------------------------------
--- Module Name:    rritb_core_dcm - sim
--- Description:    DCM aware core for a rri and cext based test bench
+-- Module Name:    tbcore_rlink_dcm - sim
+-- Description:    DCM aware core for a rlink_cext based test bench
 --
 -- Dependencies:   simlib/simclk
 --                 simlib/simclkcnt
 --
--- To test:        generic, any rri/cext based target
+-- To test:        generic, any rlink_cext based target
 --
 -- Target Devices: generic
 -- Tool versions:  11.4-12.1; ghdl 0.26-0.29
 --
 -- Revision History: 
 -- Date         Rev Version  Comment
+-- 2010-12-29   351   3.0    rename rritb_core_dcm->tbcore_rlink_dcm; rbv3 names
 -- 2010-11-13   338   1.1    First DCM aware version, cloned from rritb_core
 -- 2010-06-05   301   1.1.2  renamed .rpmon -> .rbmon
 -- 2010-05-02   287   1.1.1  rename config command .sdata -> .sinit;
@@ -42,10 +43,12 @@ use std.textio.all;
 use work.slvtypes.all;
 use work.simlib.all;
 use work.simbus.all;
-use work.rritblib.all;
-use work.vhpi_rriext.all;
+use work.rblib.all;
+use work.rlinklib.all;
+use work.rlinktblib.all;
+use work.rlink_cext_vhpi.all;
 
-entity rritb_core_dcm is                -- dcm aware core of rri/cext based tb's
+entity tbcore_rlink_dcm is              -- dcm aware core of rlink_cext based tb
   generic (
     CLKOSC_PERIOD : time :=  20 ns;     -- clock osc period
     CLKOSC_OFFSET : time := 200 ns;     -- clock osc offset (time to start clk)
@@ -60,9 +63,9 @@ entity rritb_core_dcm is                -- dcm aware core of rri/cext based tb's
     TX_DATA : in slv8;                  -- write data        (data tb->ext)
     TX_ENA : in slbit                   -- write data enable (data tb->ext)
   );
-end rritb_core_dcm;
+end tbcore_rlink_dcm;
 
-architecture sim of rritb_core_dcm is
+architecture sim of tbcore_rlink_dcm is
 
   signal CLK_STOP : slbit := '0';
   
@@ -85,7 +88,7 @@ begin
     );
   
   proc_conf: process
-    file fconf : text open read_mode is "tb_rriext_conf";
+    file fconf : text open read_mode is "rlink_cext_conf";
     variable iline : line;
     variable oline : line;
     variable ok : boolean;
@@ -123,12 +126,12 @@ begin
               SB_CNTL(ibit) <= 'L';
             end if;
 
-          when ".cpmon" =>              -- .cpmon
+          when ".rlmon" =>              -- .rlmon
             read_ea(iline, ien);
             if ien = '1' then
-              SB_CNTL(sbcntl_sbf_cpmon) <= 'H';
+              SB_CNTL(sbcntl_sbf_rlmon) <= 'H';
             else
-              SB_CNTL(sbcntl_sbf_cpmon) <= 'L';
+              SB_CNTL(sbcntl_sbf_rlmon) <= 'L';
             end if;
 
           when ".rbmon" =>              -- .rbmon
@@ -204,7 +207,7 @@ begin
       RX_VAL <= '0';
 
       if RX_HOLD = '0'  then
-        irxint := cext_getbyte(icycle);
+        irxint := rlink_cext_getbyte(icycle);
         if irxint >= 0 then
           if irxint <= 16#ff# then      -- normal data byte
             RX_DATA <= conv_std_logic_vector(irxint, 8);
@@ -236,7 +239,7 @@ begin
         elsif irxint = -1 then           -- end-of-file seen
           exit stim_loop;
         else
-          report "cext_getbyte error: " & integer'image(-irxint)
+          report "rlink_cext_getbyte error: " & integer'image(-irxint)
             severity failure;
         end if;
       end if;
@@ -270,9 +273,9 @@ begin
       wait for C2OUT_TIME;
       if TX_ENA = '1' then
         itxdata := conv_integer(unsigned(TX_DATA));
-        itxrc := cext_putbyte(itxdata);
+        itxrc := rlink_cext_putbyte(itxdata);
         assert itxrc=0
-          report "cext_putbyte error: "  & integer'image(itxrc)
+          report "rlink_cext_putbyte error: "  & integer'image(itxrc)
           severity failure;
       end if;
 
diff --git a/rtl/vlib/rlink/tb/tbd_rlink_direct.vbom b/rtl/vlib/rlink/tb/tbd_rlink_direct.vbom
new file mode 100644
index 00000000..b35ffad0
--- /dev/null
+++ b/rtl/vlib/rlink/tb/tbd_rlink_direct.vbom
@@ -0,0 +1,8 @@
+# libs
+../../slvtypes.vhd
+../../rbus/rblib.vhd
+../rlinklib.vbom
+# components
+../rlink_core.vbom
+# design
+tbd_rlink_direct.vhd
diff --git a/rtl/vlib/rri/tb/tbd_rri_core.vhd b/rtl/vlib/rlink/tb/tbd_rlink_direct.vhd
similarity index 69%
rename from rtl/vlib/rri/tb/tbd_rri_core.vhd
rename to rtl/vlib/rlink/tb/tbd_rlink_direct.vhd
index abb20432..114e40fd 100644
--- a/rtl/vlib/rri/tb/tbd_rri_core.vhd
+++ b/rtl/vlib/rlink/tb/tbd_rlink_direct.vhd
@@ -1,4 +1,4 @@
--- $Id: tbd_rri_core.vhd 314 2010-07-09 17:38:41Z mueller $
+-- $Id: tbd_rlink_direct.vhd 348 2010-12-26 15:23:44Z mueller $
 --
 -- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -12,14 +12,14 @@
 -- for complete details.
 --
 ------------------------------------------------------------------------------
--- Module Name:    tbd_rri_core - syn
--- Description:    Wrapper for rri_core to avoid records. It has a port
+-- Module Name:    tbd_rlink_direct - syn
+-- Description:    Wrapper for rlink_core to avoid records. It has a port
 --                 interface which will not be modified by xst synthesis
 --                 (no records, no generic port).
 --
--- Dependencies:   rri_core
+-- Dependencies:   rlink_core
 --
--- To test:        rri_core
+-- To test:        rlink_core
 --
 -- Target Devices: generic
 --
@@ -31,9 +31,13 @@
 -- 2007-10-27    92  8.2.03 I34  xc3s1000-4   153  302    0  162 s 7.65
 -- 2007-10-27    92  8.1.03 I27  xc3s1000-4   138  306    0    - s 7.64
 --
--- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
+-- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
+--
 -- Revision History: 
 -- Date         Rev Version  Comment
+-- 2010-12-25   348   3.0.2  drop RL_FLUSH, add RL_MONI for rlink_core
+-- 2010-12-24   347   3.0.1  rename: CP_*->RL->*
+-- 2010-12-05   343   3.0    rri->rlink renames; port to rbus V3 protocol;
 -- 2010-05-02   287   2.2.1  ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
 --                           drop RP_IINT signal from interfaces
 -- 2010-04-03   274   2.2    add CP_FLUSH for rri_core, add CE_USEC
@@ -49,23 +53,25 @@ use ieee.std_logic_1164.all;
 use ieee.std_logic_arith.all;
 
 use work.slvtypes.all;
-use work.rrilib.all;
+use work.rblib.all;
+use work.rlinklib.all;
 
-entity tbd_rri_core is                  -- rri_core tb design
+entity tbd_rlink_direct is              -- rlink_core only tb design
                                         -- generic: ATOWIDTH=5; ITOWIDTH=6
-                                        -- implements tbd_rri_gen
+                                        -- implements tbd_rlink_gen
   port (
     CLK  : in slbit;                    -- clock
-    CE_INT : in slbit;                  -- rri ito time unit clock enable
+    CE_INT : in slbit;                  -- rlink ito time unit clock enable
     CE_USEC : in slbit;                 -- 1 usec clock enable
     RESET  : in slbit;                  -- reset
-    CP_DI : in slv9;                    -- comm port: data in
-    CP_ENA : in slbit;                  -- comm port: data enable
-    CP_BUSY : out slbit;                -- comm port: data busy
-    CP_DO : out slv9;                   -- comm port: data out
-    CP_VAL : out slbit;                 -- comm port: data valid
-    CP_HOLD : in slbit;                 -- comm port: data hold
-    RB_MREQ_req : out slbit;            -- rbus: request - req
+    RL_DI : in slv9;                    -- rlink: data in
+    RL_ENA : in slbit;                  -- rlink: data enable
+    RL_BUSY : out slbit;                -- rlink: data busy
+    RL_DO : out slv9;                   -- rlink: data out
+    RL_VAL : out slbit;                 -- rlink: data valid
+    RL_HOLD : in slbit;                 -- rlink: data hold
+    RB_MREQ_aval : out slbit;           -- rbus: request - aval
+    RB_MREQ_re : out slbit;             -- rbus: request - re
     RB_MREQ_we : out slbit;             -- rbus: request - we
     RB_MREQ_initt : out slbit;          -- rbus: request - init; avoid name coll
     RB_MREQ_addr : out slv8;            -- rbus: request - addr
@@ -78,18 +84,19 @@ entity tbd_rri_core is                  -- rri_core tb design
     RB_STAT : in slv3;                  -- rbus: status flags
     TXRXACT : out slbit                 -- txrx active flag
   );
-end entity tbd_rri_core;
+end entity tbd_rlink_direct;
 
 
-architecture syn of tbd_rri_core is
+architecture syn of tbd_rlink_direct is
 
-  signal CP_FLUSH : slbit := '0';
+  signal RL_MONI : rl_moni_type := rl_moni_init;
   signal RB_MREQ : rb_mreq_type := rb_mreq_init;
   signal RB_SRES : rb_sres_type := rb_sres_init;
 
 begin
 
-  RB_MREQ_req  <= RB_MREQ.req;
+  RB_MREQ_aval <= RB_MREQ.aval;
+  RB_MREQ_re   <= RB_MREQ.re;
   RB_MREQ_we   <= RB_MREQ.we;
   RB_MREQ_initt<= RB_MREQ.init;
   RB_MREQ_addr <= RB_MREQ.addr;
@@ -100,7 +107,7 @@ begin
   RB_SRES.err  <= RB_SRES_err;
   RB_SRES.dout <= RB_SRES_dout;
   
-  UUT : rri_core
+  UUT : rlink_core
     generic map (
       ATOWIDTH => 5,
       ITOWIDTH => 6)
@@ -108,13 +115,13 @@ begin
       CLK      => CLK,
       CE_INT   => CE_INT,
       RESET    => RESET,
-      CP_DI    => CP_DI,
-      CP_ENA   => CP_ENA,
-      CP_BUSY  => CP_BUSY,
-      CP_DO    => CP_DO,
-      CP_VAL   => CP_VAL,
-      CP_HOLD  => CP_HOLD,
-      CP_FLUSH => CP_FLUSH,
+      RL_DI    => RL_DI,
+      RL_ENA   => RL_ENA,
+      RL_BUSY  => RL_BUSY,
+      RL_DO    => RL_DO,
+      RL_VAL   => RL_VAL,
+      RL_HOLD  => RL_HOLD,
+      RL_MONI  => RL_MONI,
       RB_MREQ  => RB_MREQ,
       RB_SRES  => RB_SRES,
       RB_LAM   => RB_LAM,
diff --git a/rtl/vlib/rri/tb/tbd_rri_serport.vbom b/rtl/vlib/rlink/tb/tbd_rlink_serport.vbom
similarity index 59%
rename from rtl/vlib/rri/tb/tbd_rri_serport.vbom
rename to rtl/vlib/rlink/tb/tbd_rlink_serport.vbom
index 151f2685..2fc46ca5 100644
--- a/rtl/vlib/rri/tb/tbd_rri_serport.vbom
+++ b/rtl/vlib/rlink/tb/tbd_rlink_serport.vbom
@@ -2,12 +2,15 @@
 ../../slvtypes.vhd
 ../../comlib/comlib.vhd
 ../../serport/serport.vhd
-../rrilib.vhd
+../../rbus/rblib.vhd
+../rlinklib.vbom
+../../simlib/simlib.vhd
+../../simlib/simbus.vhd
 # components
-tbu_rri_serport : tbu_rri_serport.vbom
+tbu_rlink_serport : tbu_rlink_serport.vbom
 ../../serport/serport_uart_tx.vbom
 ../../serport/serport_uart_rx.vbom
 ../../comlib/byte2cdata.vbom
 ../../comlib/cdata2byte.vbom
 # design
-tbd_rri_serport.vhd
+tbd_rlink_serport.vhd
diff --git a/rtl/vlib/rri/tb/tbd_rri_serport.vhd b/rtl/vlib/rlink/tb/tbd_rlink_serport.vhd
similarity index 63%
rename from rtl/vlib/rri/tb/tbd_rri_serport.vhd
rename to rtl/vlib/rlink/tb/tbd_rlink_serport.vhd
index 4e9f202f..86898bc2 100644
--- a/rtl/vlib/rri/tb/tbd_rri_serport.vhd
+++ b/rtl/vlib/rlink/tb/tbd_rlink_serport.vhd
@@ -1,4 +1,4 @@
--- $Id: tbd_rri_serport.vhd 314 2010-07-09 17:38:41Z mueller $
+-- $Id: tbd_rlink_serport.vhd 350 2010-12-28 16:40:11Z mueller $
 --
 -- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -12,24 +12,30 @@
 -- for complete details.
 -- 
 ------------------------------------------------------------------------------
--- Module Name:    tbd_rri_serport - syn
--- Description:    Wrapper for rri_core plus rri_serport with an interface
---                 compatible to the rri_core only module.
+-- Module Name:    tbd_rlink_serport - syn
+-- Description:    Wrapper for rlink_core plus rlink_serport with an interface
+--                 compatible to the rlink_core only module.
 --                 NOTE: this implementation is a hack, should be redone
 --                 using configurations.
 --
--- Dependencies:   tbu_rri_serport [UUT]
+-- Dependencies:   tbu_rlink_serport [UUT]
 --                 serport_uart_tx
 --                 serport_uart_rx
 --                 byte2cdata
 --                 cdata2byte
 --
--- To test:        rri_serport
+-- To test:        rlink_serport
 --
 -- Target Devices: generic
--- Tool versions:  xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+-- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
+--
 -- Revision History: 
 -- Date         Rev Version  Comment
+-- 2010-12-28   350   3.0.4  use CLKDIV/CDINIT=0;
+-- 2010-12-26   348   3.0.3  add RTS/CTS ports for tbu_;
+-- 2010-12-24   347   3.0.2  rename: CP_*->RL->*
+-- 2010-12-22   346   3.0.1  removed proc_moni, use .rlmon cmd in test bench
+-- 2010-12-05   343   3.0    rri->rlink renames; port to rbus V3 protocol;
 -- 2010-06-06   301   2.3    use NCOMM=4 (new eop,nak commas)
 -- 2010-05-02   287   2.2.2  ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
 --                           drop RP_IINT signal from interfaces
@@ -47,30 +53,31 @@
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.std_logic_arith.all;
--- synthesis translate_off
 use ieee.std_logic_textio.all;
 use std.textio.all;
--- synthesis translate_on
 
 use work.slvtypes.all;
-use work.rrilib.all;
+use work.rlinklib.all;
 use work.comlib.all;
 use work.serport.all;
+use work.simlib.all;
+use work.simbus.all;
 
-entity tbd_rri_serport is               -- rri_core+rri_serport tb design
-                                        -- implements tbd_rri_gen
+entity tbd_rlink_serport is             -- rlink_core+rlink_serport tb design
+                                        -- implements tbd_rlink_gen
   port (
     CLK  : in slbit;                    -- clock
-    CE_INT : in slbit;                  -- rri ito time unit clock enable
+    CE_INT : in slbit;                  -- rlink ito time unit clock enable
     CE_USEC : in slbit;                 -- 1 usec clock enable
     RESET  : in slbit;                  -- reset
-    CP_DI : in slv9;                    -- comm port: data in
-    CP_ENA : in slbit;                  -- comm port: data enable
-    CP_BUSY : out slbit;                -- comm port: data busy
-    CP_DO : out slv9;                   -- comm port: data out
-    CP_VAL : out slbit;                 -- comm port: data valid
-    CP_HOLD : in slbit;                 -- comm port: data hold
-    RB_MREQ_req : out slbit;            -- rbus: request - req
+    RL_DI : in slv9;                    -- rlink: data in
+    RL_ENA : in slbit;                  -- rlink: data enable
+    RL_BUSY : out slbit;                -- rlink: data busy
+    RL_DO : out slv9;                   -- rlink: data out
+    RL_VAL : out slbit;                 -- rlink: data valid
+    RL_HOLD : in slbit;                 -- rlink: data hold
+    RB_MREQ_aval : out slbit;           -- rbus: request - aval
+    RB_MREQ_re : out slbit;             -- rbus: request - re
     RB_MREQ_we : out slbit;             -- rbus: request - we
     RB_MREQ_initt : out slbit;          -- rbus: request - init; avoid name coll
     RB_MREQ_addr : out slv8;            -- rbus: request - addr
@@ -83,32 +90,38 @@ entity tbd_rri_serport is               -- rri_core+rri_serport tb design
     RB_STAT : in slv3;                  -- rbus: status flags
     TXRXACT : out slbit                 -- txrx active flag
   );
-end entity tbd_rri_serport;
+end entity tbd_rlink_serport;
 
 
-architecture syn of tbd_rri_serport is
+architecture syn of tbd_rlink_serport is
+  
+  constant CDWIDTH : positive := 13;
+  constant c_cdinit : natural := 0;   -- NOTE: change in tbu_rlink_serport !!
 
   signal RRI_RXSD : slbit := '0';
   signal RRI_TXSD : slbit := '0';
+  signal RTS_N : slbit := '0';
   signal RXDATA : slv8 := (others=>'0');
   signal RXVAL : slbit := '0';
   signal RXACT : slbit := '0';
   signal TXDATA : slv8 := (others=>'0');
   signal TXENA : slbit := '0';
   signal TXBUSY : slbit := '0';
-  signal CLKDIV : slv13 := conv_std_logic_vector(1,13);
-                           -- NOTE: change also CDINIT in tbu_rri_serport !!
+  signal CLKDIV : slv13 := conv_std_logic_vector(c_cdinit,CDWIDTH);
   
-component tbu_rri_serport is            -- rri core+serport combo
+component tbu_rlink_serport is            -- rlink core+serport combo
   port (
     CLK  : in slbit;                    -- clock
-    CE_INT : in slbit;                  -- rri ito time unit clock enable
+    CE_INT : in slbit;                  -- rlink ito time unit clock enable
     CE_USEC : in slbit;                 -- 1 usec clock enable
     CE_MSEC : in slbit;                 -- 1 msec clock enable
     RESET  : in slbit;                  -- reset
-    RXSD : in slbit;                    -- receive serial data (uart view)
-    TXSD : out slbit;                   -- transmit serial data (uart view)
-    RB_MREQ_req : out slbit;            -- rbus: request - req
+    RXSD : in slbit;                    -- receive serial data      (board view)
+    TXSD : out slbit;                   -- transmit serial data     (board view)
+    CTS_N : in slbit;                   -- clear to send   (act.low, board view)
+    RTS_N : out slbit;                  -- request to send (act.low, board view)
+    RB_MREQ_aval : out slbit;           -- rbus: request - aval
+    RB_MREQ_re : out slbit;             -- rbus: request - re
     RB_MREQ_we : out slbit;             -- rbus: request - we
     RB_MREQ_initt : out slbit;          -- rbus: request - init; avoid name coll
     RB_MREQ_addr : out slv8;            -- rbus: request - addr
@@ -122,12 +135,9 @@ component tbu_rri_serport is            -- rri core+serport combo
   );
 end component;
 
-  constant CPREF : slv4 := "1000";
-  constant NCOMM : positive := 4;
-
 begin
 
-  UUT : tbu_rri_serport
+  UUT : tbu_rlink_serport
     port map (
       CLK          => CLK,
       CE_INT       => CE_INT,
@@ -136,7 +146,10 @@ begin
       RESET        => RESET,
       RXSD         => RRI_RXSD,
       TXSD         => RRI_TXSD,
-      RB_MREQ_req  => RB_MREQ_req,
+      CTS_N        => '0',
+      RTS_N        => RTS_N,
+      RB_MREQ_aval => RB_MREQ_aval,
+      RB_MREQ_re   => RB_MREQ_re,
       RB_MREQ_we   => RB_MREQ_we,
       RB_MREQ_initt=> RB_MREQ_initt,
       RB_MREQ_addr => RB_MREQ_addr,
@@ -151,7 +164,7 @@ begin
 
   UARTRX : serport_uart_rx
     generic map (
-      CDWIDTH => 13)
+      CDWIDTH => CDWIDTH)
     port map (
       CLK    => CLK,
       RESET  => RESET,
@@ -165,7 +178,7 @@ begin
 
   UARTTX : serport_uart_tx
     generic map (
-      CDWIDTH => 13)
+      CDWIDTH => CDWIDTH)
     port map (
       CLK    => CLK,
       RESET  => RESET,
@@ -180,67 +193,56 @@ begin
   
   B2CD : byte2cdata                     -- byte stream -> 9bit comma,data
     generic map (
-      CPREF => CPREF,
-      NCOMM => NCOMM)
+      CPREF => c_rlink_cpref,
+      NCOMM => c_rlink_ncomm)
     port map (
       CLK   => CLK,
       RESET => RESET,
       DI    => RXDATA,
       ENA   => RXVAL,
       BUSY  => open,
-      DO    => CP_DO,
-      VAL   => CP_VAL,
-      HOLD  => CP_HOLD
+      DO    => RL_DO,
+      VAL   => RL_VAL,
+      HOLD  => RL_HOLD
     );
 
   CD2B : cdata2byte                     -- 9bit comma,data -> byte stream
     generic map (
-      CPREF => CPREF,
-      NCOMM => NCOMM)
+      CPREF => c_rlink_cpref,
+      NCOMM => c_rlink_ncomm)
     port map (
       CLK   => CLK,
       RESET => RESET,
-      DI    => CP_DI,
-      ENA   => CP_ENA,
-      BUSY  => CP_BUSY,
+      DI    => RL_DI,
+      ENA   => RL_ENA,
+      BUSY  => RL_BUSY,
       DO    => TXDATA,
       VAL   => TXENA,
       HOLD  => TXBUSY
     );
-
--- synthesis translate_off
+  
   proc_moni: process
     variable oline : line;
-    constant c2out_time : time := 10 ns;  -- FIXME - this isn't modular !!!
-
+    variable rts_last : slbit := '0';
+    variable ncycle : integer := 0;
   begin
-
-    loop 
-      wait until CLK'event and CLK='1';
-      wait for c2out_time;
-
-      if TXENA='1' and TXBUSY='0' then
-        write(oline, now, right, 12);
-        write(oline, string'("       "));
-        write(oline, string'(":   tx  "));
-        write(oline, string'("  "));
-        write(oline, TXDATA, right, 9);
+    loop
+      wait until CLK'event and CLK='1'; -- check at end of clock cycle
+      if RTS_N /= rts_last then
+        writetimestamp(oline, SB_CLKCYCLE, ": rts  ");
+        write(oline, string'(" RTS_N "));
+        write(oline, rts_last, right, 1);
+        write(oline, string'(" -> "));
+        write(oline, RTS_N, right, 1);
+        write(oline, string'(" after "));
+        write(oline, ncycle, right, 5);
+        write(oline, string'(" cycles"));
         writeline(output, oline);
+        rts_last := RTS_N;
+        ncycle   := 0;
       end if;
-      
-      if RXVAL = '1' then
-        write(oline, now, right, 12);
-        write(oline, string'("       "));
-        write(oline, string'(":   rx  "));
-        write(oline, string'("  "));
-        write(oline, RXDATA, right, 9);
-        writeline(output, oline);
-      end if;
-      
+      ncycle := ncycle + 1;
     end loop;
-
   end process proc_moni;
--- synthesis translate_on
 
-  
 end syn;
diff --git a/rtl/vlib/rlink/tb/tbu_rlink_serport.vbom b/rtl/vlib/rlink/tb/tbu_rlink_serport.vbom
new file mode 100644
index 00000000..76373a6a
--- /dev/null
+++ b/rtl/vlib/rlink/tb/tbu_rlink_serport.vbom
@@ -0,0 +1,9 @@
+# libs
+../../slvtypes.vhd
+../../rbus/rblib.vhd
+../rlinklib.vbom
+# components
+../rlink_base.vbom
+../rlink_serport.vbom
+# design
+tbu_rlink_serport.vhd
diff --git a/rtl/vlib/rri/tb/tbu_rri_serport.vhd b/rtl/vlib/rlink/tb/tbu_rlink_serport.vhd
similarity index 51%
rename from rtl/vlib/rri/tb/tbu_rri_serport.vhd
rename to rtl/vlib/rlink/tb/tbu_rlink_serport.vhd
index 42f31401..2867e381 100644
--- a/rtl/vlib/rri/tb/tbu_rri_serport.vhd
+++ b/rtl/vlib/rlink/tb/tbu_rlink_serport.vhd
@@ -1,4 +1,4 @@
--- $Id: tbu_rri_serport.vhd 314 2010-07-09 17:38:41Z mueller $
+-- $Id: tbu_rlink_serport.vhd 350 2010-12-28 16:40:11Z mueller $
 --
 -- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -12,15 +12,15 @@
 -- for complete details.
 --
 ------------------------------------------------------------------------------
--- Module Name:    tbu_rri_serport - syn
--- Description:    Wrapper for rri_core plus rri_serport to avoid records. It
---                 has a port interface which will not be modified by xst
+-- Module Name:    tbu_rlink_serport - syn
+-- Description:    Wrapper for rlink_base plus rlink_serport to avoid records.
+--                 It has a port interface which will not be modified by xst
 --                 synthesis (no records, no generic port).
 --
--- Dependencies:   rri_core
---                 rri_serport
+-- Dependencies:   rlink_base
+--                 rlink_serport
 --
--- To test:        rri_serport
+-- To test:        rlink_serport
 --
 -- Target Devices: generic
 --
@@ -32,9 +32,14 @@
 -- 2007-10-27    92  8.2.03 I34  xc3s1000-4   283  594   18  323 s 10.3
 -- 2007-10-27    92  8.1.03 I27  xc3s1000-4   285  596   18    - s 9.32
 --
--- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
+-- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
+--
 -- Revision History: 
 -- Date         Rev Version  Comment
+-- 2010-12-28   350   3.1.1  use CLKDIV/CDINIT=0;
+-- 2010-12-26   348   3.1    use rlink_base now; add RTS/CTS ports
+-- 2010-12-24   347   3.0.1  rename: CP_*->RL->*
+-- 2010-12-05   343   3.0    rri->rlink renames; port to rbus V3 protocol;
 -- 2010-06-03   300   2.2.3  use default FAWIDTH for rri_core_serport
 -- 2010-05-02   287   2.2.2  ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
 --                           drop RP_IINT from interfaces; drop RTSFLUSH generic
@@ -51,18 +56,22 @@ use ieee.std_logic_1164.all;
 use ieee.std_logic_arith.all;
 
 use work.slvtypes.all;
-use work.rrilib.all;
+use work.rblib.all;
+use work.rlinklib.all;
 
-entity tbu_rri_serport is               -- rri core+serport combo
+entity tbu_rlink_serport is             -- rlink core+serport combo
   port (
     CLK  : in slbit;                    -- clock
-    CE_INT : in slbit;                  -- rri ito time unit clock enable
+    CE_INT : in slbit;                  -- rlink ito time unit clock enable
     CE_USEC : in slbit;                 -- 1 usec clock enable
     CE_MSEC : in slbit;                 -- 1 msec clock enable
     RESET  : in slbit;                  -- reset
-    RXSD : in slbit;                    -- receive serial data (board view)
-    TXSD : out slbit;                   -- transmit serial data (board view)
-    RB_MREQ_req : out slbit;            -- rbus: request - req
+    RXSD : in slbit;                    -- receive serial data      (board view)
+    TXSD : out slbit;                   -- transmit serial data     (board view)
+    CTS_N : in slbit;                   -- clear to send   (act.low, board view)
+    RTS_N : out slbit;                  -- request to send (act.low, board view)
+    RB_MREQ_aval : out slbit;           -- rbus: request - aval
+    RB_MREQ_re : out slbit;             -- rbus: request - re
     RB_MREQ_we : out slbit;             -- rbus: request - we
     RB_MREQ_initt: out slbit;           -- rbus: request - init; avoid name coll
     RB_MREQ_addr : out slv8;            -- rbus: request - addr
@@ -74,28 +83,30 @@ entity tbu_rri_serport is               -- rri core+serport combo
     RB_LAM : in slv16;                  -- rbus: look at me
     RB_STAT : in slv3                   -- rbus: status flags
   );
-end entity tbu_rri_serport;
+end entity tbu_rlink_serport;
 
 
-architecture syn of tbu_rri_serport is
+architecture syn of tbu_rlink_serport is
+
+  constant CDWIDTH : positive := 13;
+  constant c_cdinit : natural := 0;   -- NOTE: change in tbd_rlink_serport !!
 
   signal RB_MREQ : rb_mreq_type := rb_mreq_init;
   signal RB_SRES : rb_sres_type := rb_sres_init;
 
-  signal CTS_N : slbit := '0';
-  signal RTS_N : slbit := '0';
-
-  signal CP_DI : slv9 := (others=>'0');
-  signal CP_ENA : slbit := '0';
-  signal CP_BUSY : slbit := '0';
-  signal CP_DO : slv9 := (others=>'0');
-  signal CP_VAL : slbit := '0';
-  signal CP_HOLD : slbit := '0';
-  signal CP_FLUSH : slbit := '0';
+  signal RLB_DI : slv8 := (others=>'0');
+  signal RLB_ENA : slbit := '0';
+  signal RLB_BUSY : slbit := '0';
+  signal RLB_DO : slv8 := (others=>'0');
+  signal RLB_VAL : slbit := '0';
+  signal RLB_HOLD : slbit := '0';
+  signal IFIFO_SIZE : slv4 := (others=>'0');
+  signal RL_MONI : rl_moni_type := rl_moni_init;
   
 begin
 
-  RB_MREQ_req  <= RB_MREQ.req;
+  RB_MREQ_aval <= RB_MREQ.aval;
+  RB_MREQ_re   <= RB_MREQ.re;
   RB_MREQ_we   <= RB_MREQ.we;
   RB_MREQ_initt<= RB_MREQ.init;
   RB_MREQ_addr <= RB_MREQ.addr;
@@ -105,46 +116,59 @@ begin
   RB_SRES.busy <= RB_SRES_busy;
   RB_SRES.err  <= RB_SRES_err;
   RB_SRES.dout <= RB_SRES_dout;
-  
-  CORE : rri_core
+
+  BASE : rlink_base
+    generic map (
+      ATOWIDTH     =>  5,
+      ITOWIDTH     =>  6,
+      CPREF        =>  c_rlink_cpref,
+      IFAWIDTH     =>  5,
+      OFAWIDTH     =>  0,               -- no output fifo
+      ENAPIN_RLMON => -1,               -- no monitors (both are instantiated in
+      ENAPIN_RBMON => -1)               --   tbd_rlink_serport for ssim avail.)
     port map (
-      CLK      => CLK,
-      CE_INT   => CE_INT,
-      RESET    => RESET,
-      CP_DI    => CP_DI,
-      CP_ENA   => CP_ENA,
-      CP_BUSY  => CP_BUSY,
-      CP_DO    => CP_DO,
-      CP_VAL   => CP_VAL,
-      CP_HOLD  => CP_HOLD,
-      CP_FLUSH => CP_FLUSH,
-      RB_MREQ  => RB_MREQ,
-      RB_SRES  => RB_SRES,
-      RB_LAM   => RB_LAM,
-      RB_STAT  => RB_STAT
+      CLK        => CLK,
+      CE_INT     => CE_INT,
+      RESET      => RESET,
+      RLB_DI     => RLB_DI,
+      RLB_ENA    => RLB_ENA,
+      RLB_BUSY   => RLB_BUSY,
+      RLB_DO     => RLB_DO,
+      RLB_VAL    => RLB_VAL,
+      RLB_HOLD   => RLB_HOLD,
+      IFIFO_SIZE => IFIFO_SIZE,
+      OFIFO_SIZE => open,
+      RL_MONI    => RL_MONI,
+      RB_MREQ    => RB_MREQ,
+      RB_SRES    => RB_SRES,
+      RB_LAM     => RB_LAM,
+      RB_STAT    => RB_STAT
     );
 
-  SERPORT : rri_serport
+  SERPORT : rlink_serport
     generic map (
-      CPREF    => "1000",
-      CDWIDTH  => 13,
-      CDINIT   =>  1)        -- NOTE: change also CLKDIV in tbd_rri_serport !!
+      RB_ADDR  => conv_std_logic_vector(2#11111110#,8),
+      CDWIDTH  => CDWIDTH,
+      CDINIT   => c_cdinit)
     port map (
-      CLK      => CLK,
-      CE_USEC  => CE_USEC,
-      CE_MSEC  => CE_MSEC,
-      RESET    => RESET,
-      RXSD     => RXSD,
-      TXSD     => TXSD,
-      CTS_N    => CTS_N,
-      RTS_N    => RTS_N,
-      CP_DI    => CP_DI,
-      CP_ENA   => CP_ENA,
-      CP_BUSY  => CP_BUSY,
-      CP_DO    => CP_DO,
-      CP_VAL   => CP_VAL,
-      CP_HOLD  => CP_HOLD,
-      CP_FLUSH => CP_FLUSH
+      CLK        => CLK,
+      CE_USEC    => CE_USEC,
+      CE_MSEC    => CE_MSEC,
+      RESET      => RESET,
+      RXSD       => RXSD,
+      TXSD       => TXSD,
+      CTS_N      => CTS_N,
+      RTS_N      => RTS_N,
+      RLB_DI     => RLB_DI,
+      RLB_ENA    => RLB_ENA,
+      RLB_BUSY   => RLB_BUSY,
+      RLB_DO     => RLB_DO,
+      RLB_VAL    => RLB_VAL,
+      RLB_HOLD   => RLB_HOLD,
+      RB_MREQ    => RB_MREQ,
+      IFIFO_SIZE => IFIFO_SIZE,
+      RL_MONI    => RL_MONI,
+      RL_SER_MONI=> open
     );
   
 end syn;
diff --git a/rtl/vlib/rlink/tb/tbw.dat b/rtl/vlib/rlink/tb/tbw.dat
new file mode 100644
index 00000000..e7d83938
--- /dev/null
+++ b/rtl/vlib/rlink/tb/tbw.dat
@@ -0,0 +1,10 @@
+# $Id: tbw.dat 349 2010-12-28 14:02:13Z mueller $
+#
+[tb_rlink_direct]
+tb_rlink_stim = tb_rlink_stim.dat
+[tb_rlink_serport]
+tb_rlink_stim = tb_rlink_stim.dat
+[tb_rlink_tba_ttcombo]
+tb_rlink_tba_stim = tb_rlink_tba_ttcombo_stim.dat
+[tb_rlink_tba_eyemon]
+tb_rlink_tba_stim = tb_rlink_tba_eyemon_stim.dat
diff --git a/rtl/vlib/rri/rb_sres_or_2.vbom b/rtl/vlib/rri/rb_sres_or_2.vbom
deleted file mode 100644
index e74f2182..00000000
--- a/rtl/vlib/rri/rb_sres_or_2.vbom
+++ /dev/null
@@ -1,8 +0,0 @@
-# libs
-../slvtypes.vhd
-rrilib.vhd
-[ghdl,isim]tb/rritblib.vhd
-# components
-[ghdl,isim]tb/rritb_sres_or_mon.vbom
-# design
-rb_sres_or_2.vhd
diff --git a/rtl/vlib/rri/rb_sres_or_3.vbom b/rtl/vlib/rri/rb_sres_or_3.vbom
deleted file mode 100644
index cfba7cd3..00000000
--- a/rtl/vlib/rri/rb_sres_or_3.vbom
+++ /dev/null
@@ -1,8 +0,0 @@
-# libs
-../slvtypes.vhd
-rrilib.vhd
-[ghdl,isim]tb/rritblib.vhd
-# components
-[ghdl,isim]tb/rritb_sres_or_mon.vbom
-# design
-rb_sres_or_3.vhd
diff --git a/rtl/vlib/rri/rri_core_serport.vbom b/rtl/vlib/rri/rri_core_serport.vbom
deleted file mode 100644
index 9b91c0f0..00000000
--- a/rtl/vlib/rri/rri_core_serport.vbom
+++ /dev/null
@@ -1,11 +0,0 @@
-# libs
-../slvtypes.vhd
-rrilib.vhd
-[ghdl,isim]tb/rritblib.vhd
-# components
-rri_serport.vbom
-rri_core.vbom
-[ghdl,isim]tb/rritb_cpmon_sb.vbom
-[ghdl,isim]tb/rritb_rbmon_sb.vbom
-# design
-rri_core_serport.vhd
diff --git a/rtl/vlib/rri/rri_core_serport.vhd b/rtl/vlib/rri/rri_core_serport.vhd
deleted file mode 100644
index 51d14750..00000000
--- a/rtl/vlib/rri/rri_core_serport.vhd
+++ /dev/null
@@ -1,170 +0,0 @@
--- $Id: rri_core_serport.vhd 314 2010-07-09 17:38:41Z mueller $
---
--- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
---
--- This program is free software; you may redistribute and/or modify it under
--- the terms of the GNU General Public License as published by the Free
--- Software Foundation, either version 2, or at your option any later version.
---
--- This program is distributed in the hope that it will be useful, but
--- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
--- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
--- for complete details.
--- 
-------------------------------------------------------------------------------
--- Module Name:    rri_core_serport - syn
--- Description:    rri: core + serport combo, with cpmon and rbmon
---
--- Dependencies:   rri_serport
---                 rri_core
---                 rritb_cpmon_sb  [sim only]
---                 rritb_rbmon_sb  [sim only]
---
--- Test bench:     -
---
--- Target Devices: generic
--- Tool versions:  xst 11.4; ghdl 0.26
---
--- Synthesized (xst):
--- Date         Rev  ise         Target      flop lutl lutm slic t peri
--- 2010-04-03   275  11.4    L68 xc3s1000-4   280  600   18  375 s  9.8
---
--- Revision History: 
--- Date         Rev Version  Comment
--- 2010-06-05   301   1.2.2  renamed _rpmon -> _rbmon
--- 2010-06-03   300   1.2.1  use FAWIDTH=5 
--- 2010-05-02   287   1.2    ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
---                           drop RP_IINT from interfaces; drop RTSFLUSH generic
--- 2010-04-18   279   1.1    drop RTSFBUF generic
--- 2010-04-10   275   1.0    Initial version 
-------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-
-use work.slvtypes.all;
-use work.rrilib.all;
--- synthesis translate_off
-use work.rritblib.all;
--- synthesis translate_on
-
-entity rri_core_serport is              -- rri, core+serport with cpmon+rbmon
-  generic (
-    ATOWIDTH : positive :=  5;          -- access timeout counter width
-    ITOWIDTH : positive :=  6;          -- idle timeout counter width
-    FAWIDTH : positive :=  5;           -- rx fifo address port width
-    CDWIDTH : positive := 13;           -- clk divider width
-    CDINIT : natural   := 15);          -- clk divider initial/reset setting
-  port (
-    CLK  : in slbit;                    -- clock
-    CE_USEC : in slbit;                 -- 1 usec clock enable
-    CE_MSEC : in slbit;                 -- 1 msec clock enable
-    CE_INT : in slbit := '0';           -- rri ito time unit clock enable
-    RESET  : in slbit;                  -- reset
-    RXSD : in slbit;                    -- receive serial data      (board view)
-    TXSD : out slbit;                   -- transmit serial data     (board view)
-    CTS_N : in slbit := '0';            -- clear to send   (act.low, board view)
-    RTS_N : out slbit;                  -- request to send (act.low, board view)
-    RB_MREQ : out rb_mreq_type;         -- rbus: request
-    RB_SRES : in rb_sres_type;          -- rbus: response
-    RB_LAM : in slv16;                  -- rbus: look at me
-    RB_STAT : in slv3                   -- rbus: status flags
-  );
-end entity rri_core_serport;
-
-
-architecture syn of rri_core_serport is
-
-  signal CP_DI : slv9 := (others=>'0');
-  signal CP_ENA : slbit := '0';
-  signal CP_BUSY : slbit := '0';
-  signal CP_DO : slv9 := (others=>'0');
-  signal CP_VAL : slbit := '0';
-  signal CP_HOLD : slbit := '0';
-  signal CP_FLUSH : slbit := '0';
-
-  signal RB_MREQ_L : rb_mreq_type := rb_mreq_init;  -- local, readable RB_MREQ
-
-begin
-  
-  SER2RRI : rri_serport
-    generic map (
-      CPREF    => "1000",
-      FAWIDTH  => FAWIDTH,
-      CDWIDTH  => CDWIDTH,
-      CDINIT   => CDINIT)
-    port map (
-      CLK      => CLK,
-      CE_USEC  => CE_USEC,
-      CE_MSEC  => CE_MSEC,
-      RESET    => RESET,
-      RXSD     => RXSD,
-      TXSD     => TXSD,
-      CTS_N    => CTS_N,
-      RTS_N    => RTS_N,
-      CP_DI    => CP_DI,
-      CP_ENA   => CP_ENA,
-      CP_BUSY  => CP_BUSY,
-      CP_DO    => CP_DO,
-      CP_VAL   => CP_VAL,
-      CP_HOLD  => CP_HOLD,
-      CP_FLUSH => CP_FLUSH
-    );
-
-  RRI : rri_core
-    generic map (
-      ATOWIDTH => ATOWIDTH,
-      ITOWIDTH => ITOWIDTH)
-    port map (
-      CLK      => CLK,
-      CE_INT   => CE_INT,
-      RESET    => RESET,
-      CP_DI    => CP_DI,
-      CP_ENA   => CP_ENA,
-      CP_BUSY  => CP_BUSY,
-      CP_DO    => CP_DO,
-      CP_VAL   => CP_VAL,
-      CP_HOLD  => CP_HOLD,
-      CP_FLUSH => CP_FLUSH,
-      RB_MREQ  => RB_MREQ_L,
-      RB_SRES  => RB_SRES,
-      RB_LAM   => RB_LAM,
-      RB_STAT  => RB_STAT
-    );
-
-  -- vhdl'93 unfortunately doesn't allow to read a signal bound to an out port
-  -- because RB_MREQ is read by the monitors, an extra internal
-  -- signal must be used. This will not be needed with vhdl'2000 anymore
-  
-  RB_MREQ <= RB_MREQ_L;
-  
--- synthesis translate_off
-  CPMON : rritb_cpmon_sb
-    generic map (
-      DWIDTH => CP_DI'length,
-      ENAPIN => 15)
-    port map (
-      CLK     => CLK,
-      CP_DI   => CP_DI,
-      CP_ENA  => CP_ENA,
-      CP_BUSY => CP_BUSY,
-      CP_DO   => CP_DO,
-      CP_VAL  => CP_VAL,
-      CP_HOLD => CP_HOLD
-    );
-
-  RBMON : rritb_rbmon_sb
-    generic map (
-      DBASE  => 8,
-      ENAPIN => 14)
-    port map (
-      CLK     => CLK,
-      RB_MREQ => RB_MREQ_L,
-      RB_SRES => RB_SRES,
-      RB_LAM  => RB_LAM,
-      RB_STAT => RB_STAT
-    );
--- synthesis translate_on
-
-end syn;
diff --git a/rtl/vlib/rri/rri_serport.vhd b/rtl/vlib/rri/rri_serport.vhd
deleted file mode 100644
index 9557f588..00000000
--- a/rtl/vlib/rri/rri_serport.vhd
+++ /dev/null
@@ -1,201 +0,0 @@
--- $Id: rri_serport.vhd 314 2010-07-09 17:38:41Z mueller $
---
--- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
---
--- This program is free software; you may redistribute and/or modify it under
--- the terms of the GNU General Public License as published by the Free
--- Software Foundation, either version 2, or at your option any later version.
---
--- This program is distributed in the hope that it will be useful, but
--- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
--- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
--- for complete details.
--- 
-------------------------------------------------------------------------------
--- Module Name:    rri_serport - syn
--- Description:    rri: serport adapter
---
--- Dependencies:   serport/serport_uart_rxtx_ab
---                 comlib/byte2cdata
---                 comlib/cdata2byte
---                 memlib/fifo_1c_dram
---
--- Test bench:     tb/tb_rri_serport
---
--- Target Devices: generic
--- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
--- Revision History: 
--- Date         Rev Version  Comment
--- 2010-06-06   301   2.3    use NCOMM=4 (new eop,nak commas)
--- 2010-06-03   300   2.2.1  use FAWIDTH=5 
--- 2010-05-02   287   2.2    drop RTSFLUSH generic
--- 2010-04-18   279   2.1    rewrite flow control, drop RTSFBUF generic
--- 2010-04-03   274   2.0    flow control interfaces: RTSFLUSH, CTS_N, RTS_N
--- 2007-06-24    60   1.0    Initial version 
-------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-
-use work.slvtypes.all;
-use work.genlib.all;
-use work.memlib.all;
-use work.comlib.all;
-use work.serport.all;
-use work.rrilib.all;
-
-entity rri_serport is                   -- rri serport adapter
-  generic (
-    CPREF : slv4 :=  "1000";            -- comma prefix
-    FAWIDTH : positive :=  5;           -- rx fifo address port width
-    CDWIDTH : positive := 13;           -- clk divider width
-    CDINIT : natural   := 15);          -- clk divider initial/reset setting
-  port (
-    CLK  : in slbit;                    -- clock
-    CE_USEC : in slbit;                 -- 1 usec clock enable
-    CE_MSEC : in slbit;                 -- 1 msec clock enable
-    RESET : in slbit;                   -- reset
-    RXSD : in slbit;                    -- receive serial data (board view)
-    TXSD : out slbit;                   -- transmit serial data (board view)
-    CTS_N : in slbit := '0';            -- clear to send   (act.low, board view)
-    RTS_N : out slbit;                  -- request to send (act.low, board view)
-    CP_DI : out slv9;                   -- comm port: data in
-    CP_ENA : out slbit;                 -- comm port: data enable
-    CP_BUSY : in slbit;                 -- comm port: data busy
-    CP_DO : in slv9;                    -- comm port: data out
-    CP_VAL : in slbit;                  -- comm port: data valid
-    CP_HOLD : out slbit;                -- comm port: data hold
-    CP_FLUSH : in slbit := '0'          -- comm port: data flush
-  );
-end rri_serport;
-
-
-architecture syn of rri_serport is
-
-  signal LRESET : slbit := '0';
-  signal RXDATA : slv8 := (others=>'0');
-  signal RXVAL : slbit := '0';
-  signal TXDATA : slv8 := (others=>'0');
-  signal TXENA : slbit := '0';
-  signal TXBUSY : slbit := '0';
-  signal ABACT : slbit := '0';
-  signal FIFO_DI : slv9 := (others=>'0');
-  signal FIFO_ENA : slbit := '0';
-  signal FIFO_BUSY : slbit := '0';
-  signal FIFO_SIZE : slv(FAWIDTH downto 0) := (others=>'0');
-  signal CD2B_HOLD : slbit := '0';
-
-  signal R_FIFOBLOCK : slbit := '0';       -- fifo block flag  
-  signal FLUSH_PULSE : slbit := '0';       -- rri flush as 2-3 usec pulse
-
-  constant NCOMM : positive := 4;
-
-begin
-
-  UART : serport_uart_rxtx_ab           -- uart, rx+tx+autobauder combo
-  generic map (
-    CDWIDTH => CDWIDTH,
-    CDINIT  => CDINIT)
-  port map (
-    CLK     => CLK,
-    CE_MSEC => CE_MSEC,
-    RESET   => RESET,
-    RXSD    => RXSD,
-    RXDATA  => RXDATA,
-    RXVAL   => RXVAL,
-    RXERR   => open,
-    RXACT   => open,
-    TXSD    => TXSD,
-    TXDATA  => TXDATA,
-    TXENA   => TXENA,
-    TXBUSY  => TXBUSY,
-    ABACT   => ABACT,
-    ABDONE  => open
-  );
-
-  LRESET <= RESET or ABACT;
-  
-  B2CD : byte2cdata                     -- byte stream -> 9bit comma,data
-  generic map (
-    CPREF => CPREF,
-    NCOMM => NCOMM)
-  port map (
-    CLK   => CLK,
-    RESET => LRESET,
-    DI    => RXDATA,
-    ENA   => RXVAL,
-    BUSY  => open,
-    DO    => FIFO_DI,
-    VAL   => FIFO_ENA,
-    HOLD  => FIFO_BUSY
-  );
-
-  CD2B : cdata2byte                     -- 9bit comma,data -> byte stream
-  generic map (
-    CPREF => CPREF,
-    NCOMM => NCOMM)
-  port map (
-    CLK   => CLK,
-    RESET => LRESET,
-    DI    => CP_DO,
-    ENA   => CP_VAL,
-    BUSY  => CP_HOLD,
-    DO    => TXDATA,
-    VAL   => TXENA,
-    HOLD  => CD2B_HOLD
-  );
-
-  FIFO : fifo_1c_dram                   -- fifo, 1 clock, dram based
-  generic map (
-    AWIDTH => FAWIDTH,
-    DWIDTH => 9)
-  port map (
-    CLK   => CLK,
-    RESET => LRESET,
-    DI    => FIFO_DI,
-    ENA   => FIFO_ENA,
-    BUSY  => FIFO_BUSY,
-    DO    => CP_DI,
-    VAL   => CP_ENA,
-    HOLD  => CP_BUSY,
-    SIZE  => FIFO_SIZE
-  );
-
--- re-write later, use RB_MREQ internal init to set parameters which
--- control the flush logic.
---
---DOFLUSH: if RTSFLUSH generate
---
---  PGEN : timer
---  generic map (
---    TWIDTH => 1,
---    RETRIG => true)
---  port map (
---    CLK   => CLK,
---    CE    => CE_USEC,
---    DELAY => "1",
---    START => CP_FLUSH,
---    STOP  => RESET,
---    BUSY  => FLUSH_PULSE
---  );
---end generate DOFLUSH;
-
-  proc_fifoblock: process (CLK)
-  begin
-
-    if CLK'event and CLK='1' then
-      if unsigned(FIFO_SIZE) >= 3*2**(FAWIDTH-2) then   -- more than 3/4 full
-        R_FIFOBLOCK <= '1';                               -- block
-      elsif unsigned(FIFO_SIZE) < 2**(FAWIDTH-1) then   -- less than 1/2 full
-        R_FIFOBLOCK <= '0';                               -- unblock
-      end if;
-    end if;
-
-  end process proc_fifoblock;
-
-  RTS_N     <= R_FIFOBLOCK or FLUSH_PULSE;
-  
-  CD2B_HOLD <= TXBUSY or CTS_N;
-  
-end syn;
diff --git a/rtl/vlib/rri/rrilib.vhd b/rtl/vlib/rri/rrilib.vhd
deleted file mode 100644
index 78fa58db..00000000
--- a/rtl/vlib/rri/rrilib.vhd
+++ /dev/null
@@ -1,259 +0,0 @@
--- $Id: rrilib.vhd 314 2010-07-09 17:38:41Z mueller $
---
--- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
---
--- This program is free software; you may redistribute and/or modify it under
--- the terms of the GNU General Public License as published by the Free
--- Software Foundation, either version 2, or at your option any later version.
---
--- This program is distributed in the hope that it will be useful, but
--- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
--- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
--- for complete details.
---
-------------------------------------------------------------------------------
--- Package Name:   rrilib
--- Description:    Remote Register Interface components
---
--- Dependencies:   -
--- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
--- Revision History: 
--- Date         Rev Version  Comment
--- 2010-06-18   306   2.5.1  rename rbus data fields to _rbf_
--- 2010-06-06   302   2.5    use sop/eop framing instead of soc+chaining
--- 2010-06-03   300   2.1.5  use FAWIDTH=5 for rri_serport
--- 2010-05-02   287   2.1.4  ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
---                           drop RP_IINT from interfaces; drop RTSFLUSH generic
--- 2010-05-01   285   2.1.3  remove rri_rb_rpcompat, now obsolete
--- 2010-04-18   279   2.1.2  rri_core_serport: drop RTSFBUF generic
--- 2010-04-10   275   2.1.1  add rri_core_serport
--- 2010-04-03   274   2.1    add CP_FLUSH for rri_core, rri_serport;
---                           CE_USEC, RTSFLUSH, CTS_N, RTS_N  for rri_serport
--- 2008-08-24   162   2.0    all with new rb_mreq/rb_sres interface
--- 2008-08-22   161   1.3    renamed rri_rbres_ -> rb_sres_; drop rri_[24]rp
--- 2008-02-16   116   1.2.1  added rri_wreg(rw|w|r)_3
--- 2008-01-20   113   1.2    added rb_[mreq|sres]; _rbres_or_*; _rb_rpcompat
--- 2007-11-24    98   1.1    added RP_IINT for rri_core.
--- 2007-09-09    81   1.0    Initial version 
-------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-use work.slvtypes.all;
-
-package rrilib is
-
-constant c_rri_dat_idle : slv9 := "100000000";
-constant c_rri_dat_sop  : slv9 := "100000001";
-constant c_rri_dat_eop  : slv9 := "100000010";
-constant c_rri_dat_nak  : slv9 := "100000011";
-constant c_rri_dat_attn : slv9 := "100000100";
-
-constant c_rri_cmd_rreg : slv3 := "000";
-constant c_rri_cmd_rblk : slv3 := "001";
-constant c_rri_cmd_wreg : slv3 := "010";
-constant c_rri_cmd_wblk : slv3 := "011";
-constant c_rri_cmd_stat : slv3 := "100";
-constant c_rri_cmd_attn : slv3 := "101";
-constant c_rri_cmd_init : slv3 := "110";
-
-constant c_rri_iint_rbf_anena:    integer := 15;         -- anena flag
-constant c_rri_iint_rbf_itoena:   integer := 14;         -- itoena flag
-subtype  c_rri_iint_rbf_itoval is integer range 7 downto 0; -- command code
-
-subtype  c_rri_cmd_rbf_seq is  integer range 7 downto 3; -- sequence number
-subtype  c_rri_cmd_rbf_code is integer range 2 downto 0; -- command code
-
-subtype  c_rri_stat_rbf_stat is integer range 7 downto 5;  -- ext status bits
-constant c_rri_stat_rbf_attn:   integer := 4;  -- attention flags set
-constant c_rri_stat_rbf_ccrc:   integer := 3;  -- command crc error
-constant c_rri_stat_rbf_dcrc:   integer := 2;  -- data crc error
-constant c_rri_stat_rbf_ioto:   integer := 1;  -- i/o time out
-constant c_rri_stat_rbf_ioerr:  integer := 0;  -- i/o error
-
-type rb_mreq_type is record             -- rribus - master request
-  req  : slbit;                         -- request
-  we   : slbit;                         -- write enable
-  init : slbit;                         -- init
-  addr : slv8;                          -- address
-  din  : slv16;                         -- data (input to slave)
-end record rb_mreq_type;
-
-constant rb_mreq_init : rb_mreq_type :=
-  ('0','0','0',                         -- req, we, init
-   (others=>'0'),                       -- addr
-   (others=>'0'));                      -- din
-
-type rb_sres_type is record             -- rribus - slave response
-  ack  : slbit;                         -- acknowledge
-  busy : slbit;                         -- busy
-  err  : slbit;                         -- error
-  dout : slv16;                         -- data (output from slave)
-end record rb_sres_type;
-
-constant rb_sres_init : rb_sres_type :=
-  ('0','0','0',                         -- ack, busy, err
-   (others=>'0'));                      -- dout
-
-component rri_core is                   -- rri, core interface
-  generic (
-    ATOWIDTH : positive :=  5;          -- access timeout counter width
-    ITOWIDTH : positive :=  6);         -- idle timeout counter width
-  port (
-    CLK  : in slbit;                    -- clock
-    CE_INT : in slbit := '0';           -- rri ito time unit clock enable
-    RESET  : in slbit;                  -- reset
-    CP_DI : in slv9;                    -- comm port: data in
-    CP_ENA : in slbit;                  -- comm port: data enable
-    CP_BUSY : out slbit;                -- comm port: data busy
-    CP_DO : out slv9;                   -- comm port: data out
-    CP_VAL : out slbit;                 -- comm port: data valid
-    CP_HOLD : in slbit;                 -- comm port: data hold
-    CP_FLUSH : out slbit;               -- comm port: data flush
-    RB_MREQ : out rb_mreq_type;         -- rbus: request
-    RB_SRES : in rb_sres_type;          -- rbus: response
-    RB_LAM : in slv16;                  -- rbus: look at me
-    RB_STAT : in slv3                   -- rbus: status flags
-  );
-end component;
-
-component rricp_aif is                  -- rri comm port, abstract interface
-  port (
-    CLK  : in slbit;                    -- clock
-    CE_INT : in slbit := '0';           -- rri ito time unit clock enable
-    RESET  : in slbit :='0';            -- reset
-    CP_DI : in slv9;                    -- comm port: data in
-    CP_ENA : in slbit;                  -- comm port: data enable
-    CP_BUSY : out slbit;                -- comm port: data busy
-    CP_DO : out slv9;                   -- comm port: data out
-    CP_VAL : out slbit;                 -- comm port: data valid
-    CP_HOLD : in slbit := '0'           -- comm port: data hold
-  );
-end component;
-
-component rrirp_aif is                  -- rri reg port, abstract interface
-  port (
-    CLK  : in slbit;                    -- clock
-    RESET  : in slbit := '0';           -- reset
-    RB_MREQ : in rb_mreq_type;          -- rbus: request
-    RB_SRES : out rb_sres_type;         -- rbus: response
-    RB_LAM : out slv16;                 -- rbus: look at me
-    RB_STAT : out slv3                  -- rbus: status flags
-  );
-end component;
-
-component rri_serport is                -- rri serport adapter
-  generic (
-    CPREF : slv4 :=  "1000";            -- comma prefix
-    FAWIDTH : positive :=  5;           -- rx fifo address port width
-    CDWIDTH : positive := 13;           -- clk divider width
-    CDINIT : natural   := 15);          -- clk divider initial/reset setting
-  port (
-    CLK  : in slbit;                    -- clock
-    CE_USEC : in slbit;                 -- 1 usec clock enable
-    CE_MSEC : in slbit;                 -- 1 msec clock enable
-    RESET  : in slbit;                  -- reset
-    RXSD : in slbit;                    -- receive serial data      (board view)
-    TXSD : out slbit;                   -- transmit serial data     (board view)
-    CTS_N : in slbit := '0';            -- clear to send   (act.low, board view)
-    RTS_N : out slbit;                  -- request to send (act.low, board view)
-    CP_DI : out slv9;                   -- comm port: data in
-    CP_ENA : out slbit;                 -- comm port: data enable
-    CP_BUSY : in slbit;                 -- comm port: data busy
-    CP_DO : in slv9;                    -- comm port: data out
-    CP_VAL : in slbit;                  -- comm port: data valid
-    CP_HOLD : out slbit;                -- comm port: data hold
-    CP_FLUSH : in slbit := '0'          -- comm port: data flush
-  );
-end component;
-
-component rri_core_serport is           -- rri, core+serport with cpmon+rbmon
-  generic (
-    ATOWIDTH : positive :=  5;          -- access timeout counter width
-    ITOWIDTH : positive :=  6;          -- idle timeout counter width
-    FAWIDTH : positive :=  5;           -- rx fifo address port width
-    CDWIDTH : positive := 13;           -- clk divider width
-    CDINIT : natural   := 15);          -- clk divider initial/reset setting
-  port (
-    CLK  : in slbit;                    -- clock
-    CE_USEC : in slbit;                 -- 1 usec clock enable
-    CE_MSEC : in slbit;                 -- 1 msec clock enable
-    CE_INT : in slbit := '0';           -- rri ito time unit clock enable
-    RESET  : in slbit;                  -- reset
-    RXSD : in slbit;                    -- receive serial data      (board view)
-    TXSD : out slbit;                   -- transmit serial data     (board view)
-    CTS_N : in slbit := '0';            -- clear to send   (act.low, board view)
-    RTS_N : out slbit;                  -- request to send (act.low, board view)
-    RB_MREQ : out rb_mreq_type;         -- rbus: request
-    RB_SRES : in rb_sres_type;          -- rbus: response
-    RB_LAM : in slv16;                  -- rbus: look at me
-    RB_STAT : in slv3                   -- rbus: status flags
-  );
-end component;
-
-component rb_sres_or_2 is               -- rribus result or, 2 input
-  port (
-    RB_SRES_1  :  in rb_sres_type;                 -- rb_sres input 1
-    RB_SRES_2  :  in rb_sres_type := rb_sres_init; -- rb_sres input 2
-    RB_SRES_OR : out rb_sres_type       -- rb_sres or'ed output
-  );
-end component;
-component rb_sres_or_3 is               -- rribus result or, 3 input
-  port (
-    RB_SRES_1  :  in rb_sres_type;                 -- rb_sres input 1
-    RB_SRES_2  :  in rb_sres_type := rb_sres_init; -- rb_sres input 2
-    RB_SRES_3  :  in rb_sres_type := rb_sres_init; -- rb_sres input 3
-    RB_SRES_OR : out rb_sres_type       -- rb_sres or'ed output
-  );
-end component;
-component rb_sres_or_4 is               -- rribus result or, 4 input
-  port (
-    RB_SRES_1  :  in rb_sres_type;                 -- rb_sres input 1
-    RB_SRES_2  :  in rb_sres_type := rb_sres_init; -- rb_sres input 2
-    RB_SRES_3  :  in rb_sres_type := rb_sres_init; -- rb_sres input 3
-    RB_SRES_4  :  in rb_sres_type := rb_sres_init; -- rb_sres input 4
-    RB_SRES_OR : out rb_sres_type       -- rb_sres or'ed output
-  );
-end component;
-
-component rri_wreg_rw_3 is              -- rri: wide register r/w 3 bit select
-  generic (
-    DWIDTH : positive := 16);
-  port (
-    CLK  : in slbit;                    -- clock
-    RESET  : in slbit;                  -- reset
-    FADDR : slv3;                       -- field address
-    SEL : slbit;                        -- select
-    DATA : out slv(DWIDTH-1 downto 0);  -- data
-    RB_MREQ :  in rb_mreq_type;         -- rribus request
-    RB_SRES : out rb_sres_type          -- rribus response
-  );
-end component;
-
-component rri_wreg_w_3 is               -- rri: wide register w-o 3 bit select
-  generic (
-    DWIDTH : positive := 16);
-  port (
-    CLK  : in slbit;                    -- clock
-    RESET  : in slbit;                  -- reset
-    FADDR : slv3;                       -- field address
-    SEL : slbit;                        -- select
-    DATA : out slv(DWIDTH-1 downto 0);  -- data
-    RB_MREQ :  in rb_mreq_type;         -- rribus request
-    RB_SRES : out rb_sres_type          -- rribus response
-  );
-end component;
-
-component rri_wreg_r_3 is               -- rri: wide register r-o 3 bit select
-  generic (
-    DWIDTH : positive := 16);
-  port (
-    FADDR : slv3;                       -- field address
-    SEL : slbit;                        -- select
-    DATA : in slv(DWIDTH-1 downto 0);   -- data
-    RB_SRES : out rb_sres_type          -- rribus response
-  );
-end component;
-
-end rrilib;
diff --git a/rtl/vlib/rri/tb/.cvsignore b/rtl/vlib/rri/tb/.cvsignore
deleted file mode 100644
index ccd22f92..00000000
--- a/rtl/vlib/rri/tb/.cvsignore
+++ /dev/null
@@ -1,19 +0,0 @@
-tb_rri_stim
-tb_rri_core
-tb_rri_core_[sft]sim
-tb_rri_core_ISim
-tb_rri_core_ISim_[sft]sim
-tb_rri_serport
-tb_rri_serport_[sft]sim
-tb_rri_serport_ISim
-tb_rri_serport_ISim_[sft]sim
-tb_rritba_stim
-tb_rritba_ttcombo
-tb_rritba_ttcombo_[sft]sim
-tb_rritba_ttcombo_ISim
-tb_rritba_ttcombo_ISim_[sft]sim
-tb_rriext_ttcombo
-tb_rriext_ttcombo_[sft]sim
-tb_rriext_fifo_rx
-tb_rriext_fifo_tx
-tb_rriext_conf
diff --git a/rtl/vlib/rri/tb/rritb_cpmon.vbom b/rtl/vlib/rri/tb/rritb_cpmon.vbom
deleted file mode 100644
index f5d41c82..00000000
--- a/rtl/vlib/rri/tb/rritb_cpmon.vbom
+++ /dev/null
@@ -1,7 +0,0 @@
-# libs
-../../slvtypes.vhd
-../../simlib/simlib.vhd
-../rrilib.vhd
-# components
-# design
-rritb_cpmon.vhd
diff --git a/rtl/vlib/rri/tb/rritb_cpmon_sb.vbom b/rtl/vlib/rri/tb/rritb_cpmon_sb.vbom
deleted file mode 100644
index 2a07a902..00000000
--- a/rtl/vlib/rri/tb/rritb_cpmon_sb.vbom
+++ /dev/null
@@ -1,9 +0,0 @@
-# libs
-../../slvtypes.vhd
-../../simlib/simlib.vhd
-../../simlib/simbus.vhd
-rritblib.vhd
-# components
-rritb_cpmon.vbom
-# design
-rritb_cpmon_sb.vhd
diff --git a/rtl/vlib/rri/tb/rritb_rbmon.vbom b/rtl/vlib/rri/tb/rritb_rbmon.vbom
deleted file mode 100644
index c31a5544..00000000
--- a/rtl/vlib/rri/tb/rritb_rbmon.vbom
+++ /dev/null
@@ -1,7 +0,0 @@
-# libs
-../../slvtypes.vhd
-../../simlib/simlib.vhd
-../rrilib.vhd
-# components
-# design
-rritb_rbmon.vhd
diff --git a/rtl/vlib/rri/tb/rritb_rbmon_sb.vbom b/rtl/vlib/rri/tb/rritb_rbmon_sb.vbom
deleted file mode 100644
index 3018c56a..00000000
--- a/rtl/vlib/rri/tb/rritb_rbmon_sb.vbom
+++ /dev/null
@@ -1,10 +0,0 @@
-# libs
-../../slvtypes.vhd
-../../simlib/simlib.vhd
-../../simlib/simbus.vhd
-../rrilib.vhd
-rritblib.vhd
-# components
-rritb_rbmon.vbom
-# design
-rritb_rbmon_sb.vhd
diff --git a/rtl/vlib/rri/tb/rritb_sres_or_mon.vbom b/rtl/vlib/rri/tb/rritb_sres_or_mon.vbom
deleted file mode 100644
index 04cfc42a..00000000
--- a/rtl/vlib/rri/tb/rritb_sres_or_mon.vbom
+++ /dev/null
@@ -1,5 +0,0 @@
-# libs
-../../slvtypes.vhd
-../rrilib.vhd
-# design
-rritb_sres_or_mon.vhd
diff --git a/rtl/vlib/rri/tb/rritblib.vhd b/rtl/vlib/rri/tb/rritblib.vhd
deleted file mode 100644
index 766985d5..00000000
--- a/rtl/vlib/rri/tb/rritblib.vhd
+++ /dev/null
@@ -1,170 +0,0 @@
--- $Id: rritblib.vhd 338 2010-11-13 22:19:25Z mueller $
---
--- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
---
--- This program is free software; you may redistribute and/or modify it under
--- the terms of the GNU General Public License as published by the Free
--- Software Foundation, either version 2, or at your option any later version.
---
--- This program is distributed in the hope that it will be useful, but
--- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
--- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
--- for complete details.
---
-------------------------------------------------------------------------------
--- Package Name:   rritblib
--- Description:    Remote Register Interface test environment components
---
--- Dependencies:   -
--- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
--- Revision History: 
--- Date         Rev Version  Comment
--- 2010-11-13   338   2.5.2  add rritb_core_dcm
--- 2010-06-26   309   2.5.1  add rritb_sres_or_mon
--- 2010-06-06   302   2.5    use sop/eop framing instead of soc+chaining
--- 2010-06-05   301   2.1.2  renamed _rpmon -> _rbmon
--- 2010-05-02   287   2.1.1  rename CE_XSEC->CE_INT,RP_STAT->RB_STAT
---                           drop RP_IINT signal from interfaces
---                           add sbcntl_sbf_(cp|rp)mon defs
--- 2010-04-24   282   2.1    add rritb_core
--- 2008-08-24   162   2.0    all with new rb_mreq/rb_sres interface
--- 2008-03-24   129   1.1.5  CLK_CYCLE now 31 bits
--- 2007-12-23   105   1.1.4  add AP_LAM  for rritb_rpmon(_sb)
--- 2007-11-24    98   1.1.3  add RP_IINT for rritb_rpmon(_sb)
--- 2007-09-01    78   1.1.2  add rricp_rp
--- 2007-08-25    75   1.1.1  add rritb_cpmon_sb, rritb_rpmon_sb
--- 2007-08-16    74   1.1    remove rritb_tt* component; some interface changes
--- 2007-08-03    71   1.0.2  use rrirp_acif; change generics for rritb_[cr]pmon
--- 2007-07-22    68   1.0.1  add rritb_cpmon rritb_rpmon monitors
--- 2007-07-15    66   1.0    Initial version
-------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-use work.slvtypes.all;
-use work.rrilib.all;
-
-package rritblib is
-
--- simbus sb_cntl field usage for rri
-  constant sbcntl_sbf_cpmon : integer := 15;
-  constant sbcntl_sbf_rbmon : integer := 14;
-
-
-component rritb_cpmon is                -- rritb, rri comm port monitor
-  generic (
-    DWIDTH : positive :=  9);           -- data port width (8 or 9)
-  port (
-    CLK  : in slbit;                    -- clock
-    CLK_CYCLE : in slv31 := (others=>'0');  -- clock cycle number
-    ENA  : in slbit := '1';             -- enable monitor output
-    CP_DI : in slv(DWIDTH-1 downto 0);  -- comm port: data in
-    CP_ENA : in slbit;                  -- comm port: data enable
-    CP_BUSY : in slbit;                 -- comm port: data busy
-    CP_DO : in slv(DWIDTH-1 downto 0);  -- comm port: data out
-    CP_VAL : in slbit;                  -- comm port: data valid
-    CP_HOLD : in slbit                  -- comm port: data hold
-  );
-end component;
-
-component rritb_cpmon_sb is             -- simbus wrap for rri comm port monitor
-  generic (
-    DWIDTH : positive :=  9;            -- data port width (8 or 9)
-    ENAPIN : integer := sbcntl_sbf_cpmon); -- SB_CNTL signal to use for enable
-  port (
-    CLK  : in slbit;                    -- clock
-    CP_DI : in slv(DWIDTH-1 downto 0);  -- comm port: data in
-    CP_ENA : in slbit;                  -- comm port: data enable
-    CP_BUSY : in slbit;                 -- comm port: data busy
-    CP_DO : in slv(DWIDTH-1 downto 0);  -- comm port: data out
-    CP_VAL : in slbit;                  -- comm port: data valid
-    CP_HOLD : in slbit                  -- comm port: data hold
-  );
-end component;
-
-component rritb_rbmon is                -- rritb, rri rbus monitor
-  generic (
-    DBASE : positive :=  2);            -- base for writing data values
-  port (
-    CLK  : in slbit;                    -- clock
-    CLK_CYCLE : in slv31 := (others=>'0');  -- clock cycle number
-    ENA  : in slbit := '1';             -- enable monitor output
-    RB_MREQ : in rb_mreq_type;          -- rbus: request
-    RB_SRES : in rb_sres_type;          -- rbus: response
-    RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me
-    RB_STAT : in slv3                   -- rbus: status flags
-  ); 
-end component;
-
-component rritb_rbmon_sb is             -- simbus wrap for rri rbus monitor
-  generic (
-    DBASE : positive :=  2;             -- base for writing data values
-    ENAPIN : integer := sbcntl_sbf_rbmon); -- SB_CNTL signal to use for enable
-  port (
-    CLK  : in slbit;                    -- clock
-    RB_MREQ : in rb_mreq_type;          -- rbus: request
-    RB_SRES : in rb_sres_type;          -- rbus: response
-    RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me
-    RB_STAT : in slv3                   -- rbus: status flags
-  );
-end component;
-
-component rritb_sres_or_mon is          -- rribus result or monitor
-  port (
-    RB_SRES_1  :  in rb_sres_type;      -- rb_sres input 1
-    RB_SRES_2  :  in rb_sres_type;      -- rb_sres input 2
-    RB_SRES_3  :  in rb_sres_type := rb_sres_init; -- rb_sres input 3
-    RB_SRES_4  :  in rb_sres_type := rb_sres_init  -- rb_sres input 4
-  );
-end component;
-
-component rritb_core is                 -- core of rri/cext based test bench
-  generic (
-    CLK_PERIOD : time :=  20 ns;        -- clock period
-    CLK_OFFSET : time := 200 ns;        -- clock offset (time to start clock)
-    SETUP_TIME : time :=   5 ns;        -- setup time
-    C2OUT_TIME : time :=  10 ns);       -- clock to output time
-  port (
-    CLK : out slbit;                    -- main clock
-    RX_DATA : out slv8;                 -- read data         (data ext->tb)
-    RX_VAL : out slbit;                 -- read data valid   (data ext->tb)
-    RX_HOLD : in slbit;                 -- read data hold    (data ext->tb)
-    TX_DATA : in slv8;                  -- write data        (data tb->ext)
-    TX_ENA : in slbit                   -- write data enable (data tb->ext)
-  );
-end component;
-
-component rritb_core_dcm is             -- dcm aware core of rri/cext based tb's
-  generic (
-    CLKOSC_PERIOD : time :=  20 ns;     -- clock osc period
-    CLKOSC_OFFSET : time := 200 ns;     -- clock osc offset (time to start clk)
-    SETUP_TIME : time :=   5 ns;        -- setup time
-    C2OUT_TIME : time :=  10 ns);       -- clock to output time
-  port (
-    CLKOSC : out slbit;                 -- clock osc
-    CLKSYS : in slbit;                  -- DCM derived system clock
-    RX_DATA : out slv8;                 -- read data         (data ext->tb)
-    RX_VAL : out slbit;                 -- read data valid   (data ext->tb)
-    RX_HOLD : in slbit;                 -- read data hold    (data ext->tb)
-    TX_DATA : in slv8;                  -- write data        (data tb->ext)
-    TX_ENA : in slbit                   -- write data enable (data tb->ext)
-  );
-end component;
-
-component rricp_rp is                   -- rri comm->reg port aif forwarder
-                                        -- implements rricp_aif, uses rrirp_aif
-  port (
-    CLK  : in slbit;                    -- clock
-    CE_INT : in slbit := '0';           -- rri ito time unit clock enable
-    RESET  : in slbit :='0';            -- reset
-    CP_DI : in slv9;                    -- comm port: data in
-    CP_ENA : in slbit;                  -- comm port: data enable
-    CP_BUSY : out slbit;                -- comm port: data busy
-    CP_DO : out slv9;                   -- comm port: data out
-    CP_VAL : out slbit;                 -- comm port: data valid
-    CP_HOLD : in slbit := '0'           -- comm port: data hold
-  );
-end component;
-
-end rritblib;
diff --git a/rtl/vlib/rri/tb/tb_rri.vbom b/rtl/vlib/rri/tb/tb_rri.vbom
deleted file mode 100644
index 0a4ff30c..00000000
--- a/rtl/vlib/rri/tb/tb_rri.vbom
+++ /dev/null
@@ -1,17 +0,0 @@
-# Not meant for direct top level usage. Used with 
-# tb_rri_(core|serport|...)[_ssim].vbom and config
-# lines to generate the different cases.
-#
-# libs
-../../slvtypes.vhd
-../../genlib/genlib.vhd
-../../comlib/comlib.vhd
-../rrilib.vhd
-../../simlib/simlib.vhd
-# components
-../../simlib/simclk.vbom
-../../genlib/clkdivce.vbom
-tbd_rri_gen : tbd_rri_core.vbom
-# design
-tb_rri.vhd
-@top:tb_rri
diff --git a/rtl/vlib/rri/tb/tb_rri_core.vbom b/rtl/vlib/rri/tb/tb_rri_core.vbom
deleted file mode 100644
index 631ec130..00000000
--- a/rtl/vlib/rri/tb/tb_rri_core.vbom
+++ /dev/null
@@ -1,6 +0,0 @@
-# configure tb_rri with tbd_rri_core wrapper
-# use vhdl configure file (tb_rri_core.vhd) at allow 
-# that all configurations will co-exist in work library
-tbd_rri_gen = tbd_rri_core.vbom
-tb_rri.vbom
-tb_rri_core.vhd
diff --git a/rtl/vlib/rri/tb/tb_rri_serport.vbom b/rtl/vlib/rri/tb/tb_rri_serport.vbom
deleted file mode 100644
index 012cf9ec..00000000
--- a/rtl/vlib/rri/tb/tb_rri_serport.vbom
+++ /dev/null
@@ -1,6 +0,0 @@
-# configure tb_rri with tbd_rri_serport wrapper;
-# use vhdl configure file (tb_rri_serport.vhd) to allow 
-# that all configurations will co-exist in work library
-tbd_rri_gen = tbd_rri_serport.vbom
-tb_rri.vbom
-tb_rri_serport.vhd
diff --git a/rtl/vlib/rri/tb/tb_rri_stim.dat b/rtl/vlib/rri/tb/tb_rri_stim.dat
deleted file mode 100644
index 89ec6dfa..00000000
--- a/rtl/vlib/rri/tb/tb_rri_stim.dat
+++ /dev/null
@@ -1,648 +0,0 @@
-# $Id: tb_rri_stim.dat 303 2010-06-12 06:12:45Z mueller $
-#
-#  Revision History: 
-# Date         Rev Version  Comment
-# 2010-06-06   302   2.0    use sop/eop framing instead of soc+chaining
-# 2007-11-24    98   1.2    adapt to new internal init handling
-# 2007-11-04    95   1.1    add .iowt's in Test 15 to get serport timing right
-# 2007-06-17    58   1.0    Initial version
-#
-.wait 5
-C some non frame data first
-.tx8  00000000
-.wait 5
-.tx8  00000001
-.wait 5
-.tx8  00000010
-#
-.iowt 10
-C -----------------------------------------------------------------------------
-C Test 1: wreg
-C wreg: tx: sop - cmd(10000,010) addr(0000) dl dh ccrc - eop
-C       rx: sop - cmd(010) stat crc - eop
-#
-.rxsop
-.rxcs  10000010 00000000
-.rxeop
-#
-.txsop
-.txcad 10000010 00000000 0011001111001100
-.txeop
-#
-.iowt 10
-C -----------------------------------------------------------------------------
-C Test 2: rreg
-C rreg: tx: sop - cmd(10010,000) addr(0000) ccrc - eop
-C       rx: sop - cmd(000) dl dh stat crc - eop
-#
-.rxsop
-.rxcds 10010000          0011001111001100 00000000
-.rxeop
-#
-.txsop
-.txca  10010000 00000000
-.txeop
-#
-.iowt 10
-C -----------------------------------------------------------------------------
-C Test 3: chained wreg - wreg - rreg
-C wreg: tx: sop - cmd(11001,010) addr(0001) dl dh ccrc
-C wreg: tx:     - cmd(11011,010) addr(0010) dl dh ccrc
-C rreg: tx:     - cmd(11100,000) addr(0001) ccrc
-C       tx:     - eop
-C       rx: sop - cmd(010) stat crc
-C       rx:     - cmd(010) stat crc
-C       rx:     - cmd(000) dl dh stat crc
-C       rx:     - eop
-#
-.rxsop
-.rxcs  11001010 00000000
-.rxcs  11001010 00000000
-.rxcds 11100000          1111111100000001 00000000
-.rxeop
-#
-.txsop
-.txcad 11001010 00000001 1111111100000001
-.txcad 11001010 00000010 1111111100000010
-.txca  11100000 00000001 
-.txeop
-#
-.iowt 10
-C -----------------------------------------------------------------------------
-C Test 4: wblk - rblk
-C wblk: rx: sop - cmd(10100,011) addr(10000000) cnt(8->111) ccrc dl dh .. dcrc
-C       rx:     - eop
-C       rx: sop - cmd(011) stat crc
-C       rx:     - eop
-#
-.rxsop
-.rxcs  10100011 00000000
-.rxeop
-#
-.txsop
-.txcac 10100011 10000000 00000111
-.tx16  0000000001000000
-.tx16  0000000001000001
-.tx16  0000000001000010
-.tx16  0000000001000011
-.tx16  0000000001000100
-.tx16  0000000001000101
-.tx16  0000000001000110
-.tx16  0000000001000111
-.txcrc
-.txeop
-#
-.iowt 10
-C
-C now check, that register 16 holds 8, clear it to prepare reread:
-C rreg: tx: sop - cmd(10011,000) addr(10000) ccrc
-C wreg: tx:     - cmd(10000,010) addr(10000) dl dh ccrc
-C       tx:     - eop
-C       rx: sop - cmd(000) dl dh stat crc
-C       rx:     - cmd(010) stat crc
-C       rx:     - eop
-#
-.rxsop
-.rxcds 10011000 0000000000001000 00000000
-.rxcs  10000010 00000000
-.rxeop
-#
-.txsop
-.txca  10011000 00010000
-.txcad 10000010 00010000 00000000000000000
-.txeop
-#
-.iowt 10
-C rblk: rx: sop - cmd(10110,001) addr(10000000) cnt(8->111) ccrc - eop
-C       rx: sop - cmd(001) cnt dl dh ... stat crc - eop
-#
-.rxsop
-.rx8  10110001
-.rx8  00000111
-.rx16 0000000001000000
-.rx16 0000000001000001
-.rx16 0000000001000010
-.rx16 0000000001000011
-.rx16 0000000001000100
-.rx16 0000000001000101
-.rx16 0000000001000110
-.rx16 0000000001000111
-.rx8  00000000
-.rxcrc
-.rxeop
-#
-.txsop
-.txcac 10110001 10000000 00000111
-.txeop
-#
-.iowt 10
-C -----------------------------------------------------------------------------
-C Test 5: stat (in non-error case) re-read last cmd twice, shouldn't change
-C wreg: tx: sop - cmd(00001,010) addr(0010) dl dh ccrc
-C wreg: tx:     - cmd(00011,010) addr(0011) dl dh ccrc
-C rreg: tx:     - cmd(00101,000) addr(0010) ccrc
-C rreg: tx:     - cmd(00111,000) addr(0011) ccrc
-C stat: tx:     - cmd(01001,100) ccrc
-C stat: tx:     - cmd(01010,100) ccrc
-C       tx:     - eop
-C       rx: sop - cmd(010) stat crc
-C       rx:     - cmd(010) stat crc
-C       rx:     - cmd(000) dl dh stat crc
-C       rx:     - cmd(000) dl dh stat crc
-C       rx:     - cmd(100) ccmd (000) dl dh stat crc
-C       rx:     - cmd(100) ccmd (000) dl dh stat crc
-C       rx:     - eop
-#
-.rxsop
-.rxcs  00001010 00000000
-.rxcs  00011010 00000000
-.rxcds 00101000          1000000000000010 00000000
-.rxcds 00111000          1000000100000011 00000000
-.rxccd 01001100 00111000 1000000100000011 00000000
-.rxccd 01010100 00111000 1000000100000011 00000000
-.rxeop
-#
-.txsop
-.txcad 00001010 00000010 1000000000000010
-.txcad 00011010 00000011 1000000100000011
-.txca  00101000 00000010
-.txca  00111000 00000011
-.txc   01001100
-.txc   01010100
-.txeop
-#
-.iowt 10
-C -----------------------------------------------------------------------------
-C Test 6: ccrc error abort
-C wreg: tx: sop - cmd(01001,010) addr(0010) dl dh ccrc
-C wreg: tx:     - cmd(01011,010) addr(0011) dl dh ccrc
-C rreg: tx:     - cmd(01101,000) addr(0010) ccrc
-C rreg: tx:     - cmd(01110,000) addr(0011) *BAD CRC*
-C       tx:     - eop
-C       rx: sop - cmd(010) stat crc
-C       rx:     - cmd(010) stat crc
-C       rx:     - cmd(000) dl dh stat crc
-C       rx:     - nak  *ABORT*
-C       rx:     - eop
-#
-.rxsop
-.rxcs  01001010 00000000
-.rxcs  01011010 00000000
-.rxcds 01101000          1000000100001010 00000000
-.rxnak
-.rxeop
-#
-.txsop
-.txcad 01001010 00000010 1000000100001010
-.txcad 01011010 00000011 1000000100001011
-.txca  01101000 00000010
-.tx8   01110000 
-.tx8   00000011
-.tx8   00000000
-.txeop
-#
-.iowt 10
-C
-C now check that stat reflects last successfull rreg; re-read ccrc=1 sticks !
-C stat: tx: sop - cmd(10001,100) ccrc
-C stat: tx:     - cmd(10010,100) ccrc
-C       tx:     - eop
-C       rx:     - cmd(100) ccmd (000) dl dh stat crc
-C       rx:     - cmd(100) ccmd (000) dl dh stat crc
-C       rx:     - eop
-C     stat: stat(000),attn(0),ccrc(1),dcrc(0),ioto(0),ioerr(0) -> 00001000
-.rxsop
-.rxccd 10001100 01101000 1000000100001010 00001000
-.rxccd 10010100 01101000 1000000100001010 00001000
-.rxeop
-#
-.txsop
-.txc   10001100
-.txc   10010100
-.txeop
-#
-.iowt 10
-C -----------------------------------------------------------------------------
-C Test 7: dcrc error condition
-C wreg: tx: sop - cmd(00001,010) addr(10000) dl dh ccrc
-C wblk: rx:     - cmd(00011,011) addr(10000000) cnt(4->011) ccrc dl dh .. 
-C                                                                   *BAD CRC*
-C       rx:     - eop
-C       rx: sop - cmd(010) stat crc
-C       rx:     - cmd(011) stat crc
-C       rx:     - eop
-C     stat: stat(000),attn(0),ccrc(0),dcrc(1),ioto(0),ioerr(0) -> 00000100
-#
-.rxsop
-.rxcs  00001010 00000000
-.rxcs  00010011 00000100
-.rxeop
-#
-.txsop
-.txcad 00001010 00010000 00000000000000000
-.txcac 00010011 10000000 00000011
-.tx16  0001000001000000
-.tx16  0001000001000001
-.tx16  0001000001000010
-.tx16  0001000001000011
-.tx8   00000000
-.txeop
-#
-.iowt 10
-C
-C now check that stat reflects bad dcrc: re-read dcrc=1 sticks !
-C stat: tx: sop - cmd(00101,100) ccrc
-C stat: tx:     - cmd(00110,100) ccrc
-C       tx:     - eop
-C       rx:     - cmd(100) ccmd (000) dl dh stat crc
-C       rx:     - cmd(100) ccmd (000) dl dh stat crc
-C       rx:     - eop
-C     stat: stat(000),attn(0),ccrc(0),dcrc(1),ioto(0),ioerr(0) -> 00000100
-C     Note: dl,dh still the last read of Test 6 !!
-.rxsop
-.rxccd 00101100 00010011 1000000100001010 00000100
-.rxccd 00110100 00010011 1000000100001010 00000100
-.rxeop
-#
-.txsop
-.txc   00101100
-.txc   00110100
-.txeop
-#
-.iowt 10
-C -----------------------------------------------------------------------------
-C Test 8: err(bad address) condition; 11000000 is an address returning err=1
-C rreg: tx: sop - cmd(00001,000) addr(00010000) ccrc
-C rreg: tx:     - cmd(00011,000) addr(11000000) ccrc
-C wreg: tx:     - cmd(00101,010) addr(00010000) dl dh ccrc
-C wreg: tx:     - cmd(00110,010) addr(11000000) dl dh ccrc
-C       tx:     - eop
-C     Note: the rreg(10000) will return 4, the prt after the last wblk !
-C     Note: tb returns 1010101010101010 for access to bad addresses
-C     stat: stat(000),attn(0),ccrc(0),dcrc(0),ioto(0),ioerr(1) -> 00000001
-#
-.rxsop
-.rxcds 00001000          0000000000000100 00000000
-.rxcds 00011000          1010101010101010 00000001
-.rxcs  00101010 00000000
-.rxcs  00110010 00000001
-.rxeop
-#
-.txsop
-.txca  00001000 00010000
-.txca  00011000 11000000
-.txcad 00101010 00010000 0000000000000000
-.txcad 00110010 11000000 1000111110001111
-.txeop
-#
-.iowt 10
-C -----------------------------------------------------------------------------
-C Test 9: to(time out) condition; 01bbbbbb addressed take n+1 hold states
-C wreg: tx: sop - cmd(00001,010) addr(01000000) dl dh ccrc  (nh=1)
-C wreg: tx:     - cmd(00011,010) addr(01001111) dl dh ccrc  (nh=16)
-C wreg: tx:     - cmd(00101,010) addr(01011101) dl dh ccrc  (nh=30)
-C wreg: tx:     - cmd(00111,010) addr(01011110) dl dh ccrc  (nh=31)
-C wreg: tx:     - cmd(01001,010) addr(01011111) dl dh ccrc  (nh=32) TO
-C wreg: tx:     - cmd(01011,010) addr(01100000) dl dh ccrc  (nh=33) TO
-C wreg: tx:     - cmd(01101,010) addr(01111111) dl dh ccrc  (nh=64) TO
-C wreg: tx:     - cmd(01110,010) addr(01000001) dl dh ccrc  (nh=2)
-C       tx:     - eop
-C     stat: stat(000),attn(0),ccrc(0),dcrc(0),ioto(1),ioerr(0) -> 00000010
-#
-.rxsop
-.rxcs  00001010 00000000
-.rxcs  00011010 00000000
-.rxcs  00101010 00000000
-.rxcs  00111010 00000000
-.rxcs  01001010 00000010
-.rxcs  01011010 00000010
-.rxcs  01101010 00000010
-.rxcs  01110010 00000000
-.rxeop
-#
-.txsop
-.txcad 00001010 01000000 0000000001000000
-.txcad 00011010 01001111 0000000001001111
-.txcad 00101010 01011101 0000000001011101
-.txcad 00111010 01011110 0000000001011110
-.txcad 01001010 01011111 0000000001011111
-.txcad 01011010 01100000 0000000001100000
-.txcad 01101010 01111110 0000000001111111
-.txcad 01110010 01000001 0000000001000001
-.txeop
-.iowt 10
-C
-C now same with rreg
-C rreg: tx: sop - cmd(00001,000) addr(01000000) ccrc  (nh=1)
-C rreg: tx:     - cmd(00011,000) addr(01001111) ccrc  (nh=16)
-C rreg: tx:     - cmd(00101,000) addr(01011101) ccrc  (nh=30)
-C rreg: tx:     - cmd(00111,000) addr(01011110) ccrc  (nh=31)
-C rreg: tx:     - cmd(01001,000) addr(01011111) ccrc  (nh=32) TO
-C rreg: tx:     - cmd(01011,000) addr(01100000) ccrc  (nh=33) TO
-C rreg: tx:     - cmd(01101,000) addr(01111111) ccrc  (nh=64) TO
-C rreg: tx:     - cmd(01110,000) addr(01000001) ccrc  (nh=2)
-C       tx:     - eop
-C     Note: tb returns 0101010101010101 for timeout
-#
-.rxsop
-.rxcds 00001000          0000000001000000 00000000
-.rxcds 00011000          0000000001001111 00000000
-.rxcds 00101000          0000000001011101 00000000
-.rxcds 00111000          0000000001011110 00000000
-.rxcds 01001000          0101010101010101 00000010
-.rxcds 01011000          0101010101010101 00000010
-.rxcds 01101000          0101010101010101 00000010
-.rxcds 01110000          0000000001000001 00000000
-.rxeop
-#
-.txsop
-.txca  00001000 01000000
-.txca  00011000 01001111
-.txca  00101000 01011101
-.txca  00111000 01011110
-.txca  01001000 01011111
-.txca  01011000 01100000
-.txca  01101000 01111110
-.txca  01110000 01000001
-.txeop
-#
-.iowt 10
-C -----------------------------------------------------------------------------
-C Test 10: external init command
-C rreg: tx: sop - cmd(00001,000) addr(00010010) ccrc 
-C init: tx:     - cmd(00011,110) addr(10000111) dl dh ccrc
-C rreg: tx:     - cmd(00100,000) addr(00010010) ccrc 
-C       tx:     - eop
-C       rx: sop - cmd(000) dl dh stat crc
-C       rx:     - cmd(110) stat crc
-C       rx:     - cmd(000) dl dh stat crc
-C       rx:     - eop
-#
-.rxsop
-.rxcds 00001000 0000000000000000 00000000
-.rxcs  00011110 00000000
-.rxcds 00100000 0000000000000001 00000000 
-.rxeop
-#
-.txsop
-.txca  00001000 00010010
-.txcad 00011110 10000111 0000111000111000
-.txca  00100000 00010010
-.txeop
-#
-.iowt 10
-C -----------------------------------------------------------------------------
-C Test 11: external status bit (RP_STAT)
-C Note: stat bits are not latched for stat command !
-C stat <= "001"
-C rreg: tx: sop - cmd(00000,000) addr(00010010) ccrc - eop
-C       rx: sop - cmd(000) dl dh stat crc - eop
-#
-.rxsop
-.rxcds 00000000          0000000000000001 00100000 
-.rxeop
-#
-.stat 001
-.txsop
-.txca  00000000 00010010
-.txeop
-#
-.iowt 10
-C stat <= "010"
-C stat: tx: sop - cmd(00011,100) ccrc
-C rreg: tx:     - cmd(00100,000) addr(00010010) ccrc 
-C       tx:     - eop
-C       rx: sop - cmd(100) ccmd (000) dl dh stat crc
-C       rx:     - cmd(000) dl dh stat crc
-C       rx:     - eop
-C Note: stat command returns old 001 status
-C       rreg command returns new 010 status
-.rxsop
-.rxccd 00011100 00000000 0000000000000001 00100000
-.rxcds 00010000          0000000000000001 01000000 
-.rxeop
-#
-.stat 010
-.txsop
-.txc   00011100
-.txca  00010000 00010010
-.txeop
-#
-C stat <= "100"
-C rreg: tx: sop - cmd(00110,000) addr(00010010) ccrc - eop
-C       rx: sop - cmd(000) dl dh stat crc - eop
-C stat <= '000'
-.iowt 10
-#
-.rxsop
-.rxcds 00110000          0000000000000001 10000000 
-.rxeop
-#
-.stat 100
-.txsop
-.txca  00110000 00010010
-.txeop
-#
-.iowt 10
-.stat 000
-C -----------------------------------------------------------------------------
-C Test 12: attention logic
-C attn <= "0000000000000100"  (async case)
-C rreg: tx: sop - cmd(01001,000) addr(00010010) ccrc
-C attn: tx:     - cmd(01011,101) ccrc
-C attn: tx:     - cmd(01101,101) ccrc
-C rreg: tx:     - cmd(01110,000) addr(00010010) ccrc
-C       tx:     - eop
-C Note: the rreg command returns attn=1
-C       the attn has attn=0, because stat is evaluated after read+clear !!
-C     stat: stat(000),attn(1),ccrc(0),dcrc(0),ioto(0),ioerr(0) -> 00010000
-#
-.rxsop
-.rxcds 01001000          0000000000000001 00010000 
-.rxcds 01011101          0000000000000100 00000000 
-.rxcds 01101101          0000000000000000 00000000 
-.rxcds 01110000          0000000000000001 00000000 
-.rxeop
-#
-.wait 5
-.attn 00000100
-.wait 5
-.txsop
-.txca  01001000 00010010
-.txc   01011101
-.txc   01101101
-.txca  01110000 00010010
-.txeop
-#
-.iowt 10
-C
-C now test sync case, the transaction causes the attention
-C a write to 10000010 causes AP_LAM(15 downto 8) be pinged with RP_DO data
-C wreg: tx: sob - cmd(10001,010) addr(10000010) dl dh ccrc
-C rreg: tx:     - cmd(10011,000) addr(00010010) ccrc
-C attn: tx:     - cmd(10101,101) ccrc
-C attn: tx:     - cmd(10111,101) ccrc
-C rreg: tx:     - cmd(11000,000) addr(00010010) ccrc
-C       tx:     - eop
-.rxsop
-.rxcs  10001010 00010000
-.rxcds 10011000          0000000000000001 00010000 
-.rxcds 10101101          0000000100000000 00000000 
-.rxcds 10111101          0000000000000000 00000000 
-.rxcds 11000000          0000000000000001 00000000 
-.rxeop
-#
-.txsop
-.txcad 10001010 10000010 0000000100000000
-.txca  10011000 00010010
-.txc   10101101
-.txc   10111101
-.txca  11000000 00010010
-.txeop
-#
-.iowt 10
-C -----------------------------------------------------------------------------
-C Test 13: verify that extra 'idle' commas are tolerated
-C          do wreg+rreg, with "100000000" between bytes
-C          use as data 1000000 and 10000001 to force escaping here
-C wreg: tx: sop - cmd(00001,010) addr(0000) dl dh ccrc
-C rreg: tx: sop - cmd(00010,000) addr(0000) ccrc
-C       tx:     - eop
-C       rx: sop - cmd(010) stat crc
-C       rx: sop - cmd(000) dl dh stat crc
-C       rx:     - eop
-#
-.rxsop
-.rxcs  00001010 00000000
-.rxcds 00010000          1000000010000001 00000000
-.rxeop
-#
-100000000
-.txsop
-100000000
-.tx8   00001010 
-100000000
-.tx8   00000000 
-100000000
-.tx8   10000001
-100000000
-100000000
-.tx8   10000000
-100000000
-.txcrc
-100000000
-.tx8   00010000 
-100000000
-100000000
-100000000
-.tx8   00000000
-100000000
-.txcrc
-.txeop
-#
-.iowt 10
-C -----------------------------------------------------------------------------
-C Test 14: enable and test asynchronous attn notification
-C init: tx: sob - cmd(00000,110) addr(00000001) dl dh ccrc - eop
-C     init: anena(1), itoena(0), ito(0)   -> 11111111,1000000000000000
-#
-.rxsop
-.rxcs  00000110 00000000
-.rxeop
-#
-.txsop
-.txcad 00000110 11111111 1000000000000000
-.txeop
-.iowt 10
-#
-C now ping an attention line, expect oob attn symbol
-.wait 50
-.rxoob 100000100
-.attn  00000001
-.iowt 10
-C finally read attn flags
-C attn: tx:     - cmd(00010,101) ccrc - eop
-.rxsop
-.rxcds 00010101          0000000000000001 00000000 
-.rxeop
-#
-.txsop
-.txc   00010101
-.txeop
-#
-.iowt 10
-C -----------------------------------------------------------------------------
-C Test 15: enable and test idle timeout
-C init: tx: sob - cmd(00100,110) addr(00000011) dl dh ccrc - eop
-C     init: anena(1), itoena(1), ito(9)   -> 11111111,1100000000001001
-C     ito=9 --> divider=10; ce_xsec div is 1:20 --> total every 200 cycles
-#
-.rxsop
-.rxcs  00100110 00000000
-.rxeop
-.rxoob 100000000
-.rxoob 100000000
-.rxoob 100000100
-.rxoob 100000100
-.rxoob 100000100
-#
-.txsop
-.txcad 00100110 11111111 1100000000001001
-.txeop
-#
-.iowt 10
-C total ito now 200 cycles; wait 500 cycles, see 2 idle symbols
-.wait 500
-C ping an attention line, expect oob attn symbol
-.attn  00000010
-.iowt 10
-C wait 500 more cycles, see 2 attn symbols
-.wait 500
-C finally read attn flags
-C attn: tx:     - cmd(00110,101) ccrc - eop
-.rxsop
-.rxcds 00110101          0000000000000010 00000000 
-.rxeop
-#
-.txsop
-.txc   00110101
-.txeop
-#
-.iowt 10
-C wait 500 more cycles, see 2 idle symbols again
-.rxoob 100000000
-.rxoob 100000000
-.wait 500
-C finally disable attn notification and idle timeout again
-C init: tx: sob - cmd(00000,110) addr(00000000) dl dh ccrc - eop
-C     init: anena(0), itoena(0), ito(0)   -> 11111111,0000000000000000
-#
-.rxsop
-.rxcs  00000110 00000000
-.rxeop
-#
-.txsop
-.txcad 00000110 11111111 0000000000000000
-.txeop
-#
-.iowt 10
-C -----------------------------------------------------------------------------
-C Test 16: attn poll
-#
-C send 2 attn, expect two idles back
-.rxoob 100000000
-.rxoob 100000000
-100000100
-100000100
-.iowt 10
-#
-C ping an attention line
-.attn  00000010
-#
-C send 2 attn, expect two attn back
-.rxoob 100000100
-.rxoob 100000100
-100000100
-100000100
-.iowt 10
-#
diff --git a/rtl/vlib/rri/tb/tbd_rri_core.vbom b/rtl/vlib/rri/tb/tbd_rri_core.vbom
deleted file mode 100644
index 4fc65d6e..00000000
--- a/rtl/vlib/rri/tb/tbd_rri_core.vbom
+++ /dev/null
@@ -1,7 +0,0 @@
-# libs
-../../slvtypes.vhd
-../rrilib.vhd
-# components
-../rri_core.vbom
-# design
-tbd_rri_core.vhd
diff --git a/rtl/vlib/rri/tb/tbu_rri_serport.vbom b/rtl/vlib/rri/tb/tbu_rri_serport.vbom
deleted file mode 100644
index e861f7d8..00000000
--- a/rtl/vlib/rri/tb/tbu_rri_serport.vbom
+++ /dev/null
@@ -1,8 +0,0 @@
-# libs
-../../slvtypes.vhd
-../rrilib.vhd
-# components
-../rri_core.vbom
-../rri_serport.vbom
-# design
-tbu_rri_serport.vhd
diff --git a/rtl/vlib/rri/tb/tbw.dat b/rtl/vlib/rri/tb/tbw.dat
deleted file mode 100644
index 5ce98375..00000000
--- a/rtl/vlib/rri/tb/tbw.dat
+++ /dev/null
@@ -1,12 +0,0 @@
-# $Id: tbw.dat 81 2007-09-09 20:50:42Z mueller $
-#
-[tb_rri_core]
-tb_rri_stim = tb_rri_stim.dat
-[tb_rri_serport]
-tb_rri_stim = tb_rri_stim.dat
-[tb_rritba_ttcombo]
-tb_rritba_stim = tb_rritba_ttcombo_stim.dat
-[tb_rriext_ttcombo]
-tb_rriext_fifo_rx = <fifo>
-tb_rriext_fifo_tx = <fifo>
-tb_rriext_conf = <null>
diff --git a/rtl/vlib/serport/serport.vhd b/rtl/vlib/serport/serport.vhd
index 47a969f5..b063c53f 100644
--- a/rtl/vlib/serport/serport.vhd
+++ b/rtl/vlib/serport/serport.vhd
@@ -1,4 +1,4 @@
--- $Id: serport.vhd 314 2010-07-09 17:38:41Z mueller $
+-- $Id: serport.vhd 348 2010-12-26 15:23:44Z mueller $
 --
 -- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -16,9 +16,11 @@
 -- Description:    serial port interface components
 --
 -- Dependencies:   -
--- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
+-- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
+--
 -- Revision History: 
 -- Date         Rev Version  Comment
+-- 2010-12-26   348   1.2.1  add ABCLKDIV to serport_uart_rxtx_ab
 -- 2010-04-10   276   1.2    add clock divider constant defs
 -- 2007-10-22    88   1.1    renames (in prev revs); remove std_logic_unsigned
 -- 2007-06-03    45   1.0    Initial version 
@@ -112,7 +114,8 @@ component serport_uart_rxtx_ab is       -- serial port uart: rx+tx+autobaud
     TXENA : in slbit;                   -- transmit data enable
     TXBUSY : out slbit;                 -- transmit busy
     ABACT : out slbit;                  -- autobaud active; if 1 clkdiv invalid
-    ABDONE : out slbit                  -- autobaud resync done
+    ABDONE : out slbit;                 -- autobaud resync done
+    ABCLKDIV : out slv(CDWIDTH-1 downto 0) -- autobaud clock divider setting
   );
 end component;
 
diff --git a/rtl/vlib/serport/serport_uart_rxtx_ab.vhd b/rtl/vlib/serport/serport_uart_rxtx_ab.vhd
index 85258193..0c8f95a0 100644
--- a/rtl/vlib/serport/serport_uart_rxtx_ab.vhd
+++ b/rtl/vlib/serport/serport_uart_rxtx_ab.vhd
@@ -1,6 +1,6 @@
--- $Id: serport_uart_rxtx_ab.vhd 314 2010-07-09 17:38:41Z mueller $
+-- $Id: serport_uart_rxtx_ab.vhd 350 2010-12-28 16:40:11Z mueller $
 --
--- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
 -- This program is free software; you may redistribute and/or modify it under
 -- the terms of the GNU General Public License as published by the Free
@@ -19,9 +19,15 @@
 --                 serport_uart_rxtx
 -- Test bench:     -
 -- Target Devices: generic
--- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
+-- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
+--
+-- Synthesized (xst):
+-- Date         Rev  ise         Target      flop lutl lutm slic t peri
+-- 2010-12-25   348 12.1    M53d xc3s1000-4    99  197    -  124 s  9.8
+--
 -- Revision History: 
 -- Date         Rev Version  Comment
+-- 2010-12-26   348   1.1    add ABCLKDIV port for clock divider setting
 -- 2007-06-24    60   1.0    Initial version 
 ------------------------------------------------------------------------------
 
@@ -50,7 +56,8 @@ entity serport_uart_rxtx_ab is          -- serial port uart: rx+tx+autobaud
     TXENA : in slbit;                   -- transmit data enable
     TXBUSY : out slbit;                 -- transmit busy
     ABACT : out slbit;                  -- autobaud active; if 1 clkdiv invalid
-    ABDONE : out slbit                  -- autobaud resync done
+    ABDONE : out slbit;                 -- autobaud resync done
+    ABCLKDIV : out slv(CDWIDTH-1 downto 0) -- autobaud clock divider setting
   );
 end serport_uart_rxtx_ab;
 
@@ -78,6 +85,7 @@ begin
 
   UART_RESET <= ABACT_L or RESET;
   ABACT      <= ABACT_L;
+  ABCLKDIV   <= CLKDIV;
   
   RXTX : serport_uart_rxtx
     generic map (
diff --git a/rtl/vlib/simlib/simlib.vhd b/rtl/vlib/simlib/simlib.vhd
index a2736693..2febf934 100644
--- a/rtl/vlib/simlib/simlib.vhd
+++ b/rtl/vlib/simlib/simlib.vhd
@@ -1,4 +1,4 @@
--- $Id: simlib.vhd 338 2010-11-13 22:19:25Z mueller $
+-- $Id: simlib.vhd 346 2010-12-22 22:59:26Z mueller $
 --
 -- Copyright 2006-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -22,6 +22,7 @@
 --
 -- Revision History: 
 -- Date         Rev Version  Comment
+-- 2010-12-22   346   1.3.7  rename readcommand -> readdotcomm
 -- 2010-11-13   338   1.3.6  add simclkcnt; xx.x ns time in writetimestamp()
 -- 2008-03-24   129   1.3.5  CLK_CYCLE now 31 bits
 -- 2008-03-02   121   1.3.4  added readempty (to discard rest of line)
@@ -76,7 +77,7 @@ procedure readcomment(
   L: inout line;
   good: out boolean);
 
-procedure readcommand(
+procedure readdotcomm(
   L: inout line;
   name: out string;
   good: out boolean);
@@ -471,7 +472,7 @@ end procedure readcomment;
 
 -- -------------------------------------
   
-procedure readcommand(
+procedure readdotcomm(
   L: inout line;
   name: out string;
   good: out boolean) is
@@ -486,7 +487,7 @@ begin
     readword(L, name, good);
   end if;
   
-end procedure readcommand;
+end procedure readdotcomm;
   
 -- -------------------------------------
   
diff --git a/rtl/w11a/pdp11.vbom b/rtl/w11a/pdp11.vbom
index 24d4a329..c4a99954 100644
--- a/rtl/w11a/pdp11.vbom
+++ b/rtl/w11a/pdp11.vbom
@@ -1,5 +1,5 @@
 # libs
 ../vlib/slvtypes.vhd
 ../ibus/iblib.vhd
-../vlib/rri/rrilib.vhd
+../vlib/rbus/rblib.vhd
 pdp11.vhd
diff --git a/rtl/w11a/pdp11.vhd b/rtl/w11a/pdp11.vhd
index 3ee890e6..93a80d86 100644
--- a/rtl/w11a/pdp11.vhd
+++ b/rtl/w11a/pdp11.vhd
@@ -1,4 +1,4 @@
--- $Id: pdp11.vhd 335 2010-10-24 22:24:23Z mueller $
+-- $Id: pdp11.vhd 351 2010-12-30 21:50:54Z mueller $
 --
 -- Copyright 2006-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -16,9 +16,10 @@
 -- Description:    Definitions for pdp11 components
 --
 -- Dependencies:   -
--- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
+-- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
 -- Revision History: 
 -- Date         Rev Version  Comment
+-- 2010-12-30   351   1.4.7  rename pdp11_core_rri->pdp11_core_rbus; use rblib
 -- 2010-10-23   335   1.4.6  rename RRI_LAM->RB_LAM;
 -- 2010-10-16   332   1.4.5  renames of pdp11_du_drv port names
 -- 2010-09-18   330   1.4.4  rename (adlm)box->(oalm)unit
@@ -84,7 +85,7 @@ use ieee.std_logic_arith.all;
 
 use work.slvtypes.all;
 use work.iblib.all;
-use work.rrilib.all;
+use work.rblib.all;
 
 package pdp11 is
 
@@ -1067,7 +1068,7 @@ component pdp11_bram is                 -- BRAM based ext. memory dummy
   );
 end component;
 
-component pdp11_core_rri is             -- core to rri reg port interface
+component pdp11_core_rbus is            -- core to rbus interface
   generic (
     RB_ADDR_CORE : slv8 := conv_std_logic_vector(2#00000000#,8);
     RB_ADDR_IBUS : slv8 := conv_std_logic_vector(2#10000000#,8));
diff --git a/rtl/w11a/pdp11_core.vhd b/rtl/w11a/pdp11_core.vhd
index db6ca8bd..cc3b8a64 100644
--- a/rtl/w11a/pdp11_core.vhd
+++ b/rtl/w11a/pdp11_core.vhd
@@ -1,4 +1,4 @@
--- $Id: pdp11_core.vhd 314 2010-07-09 17:38:41Z mueller $
+-- $Id: pdp11_core.vhd 351 2010-12-30 21:50:54Z mueller $
 --
 -- Copyright 2006-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -23,13 +23,11 @@
 --                 pdp11_sys70
 --                 ibus/ib_sres_or_4
 --
--- Test bench:     tb/tb_pdp11_core
---                 tb/tb_rritba_pdp11core
---                 tb/tb_rripdp_pdp11core
---                 tb/tb_rriext_pdp11core
+-- Test bench:     tb/tb_pdp11core
+--                 tb/tb_rlink_tba_pdp11core
 --
 -- Target Devices: generic
--- Tool versions:  xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+-- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
 -- Revision History: 
 -- Date         Rev Version  Comment
 -- 2010-06-13   305   1.3    add CP_ADDR in port; drop R_CPDIN, R_CPOUT; _vmbox
diff --git a/rtl/w11a/pdp11_core_rri.vbom b/rtl/w11a/pdp11_core_rbus.vbom
similarity index 52%
rename from rtl/w11a/pdp11_core_rri.vbom
rename to rtl/w11a/pdp11_core_rbus.vbom
index 319490be..f63ad99c 100644
--- a/rtl/w11a/pdp11_core_rri.vbom
+++ b/rtl/w11a/pdp11_core_rbus.vbom
@@ -1,6 +1,6 @@
 # libs
 ../vlib/slvtypes.vhd
-../vlib/rri/rrilib.vhd
+../vlib/rbus/rblib.vhd
 pdp11.vbom
 # design
-pdp11_core_rri.vhd
+pdp11_core_rbus.vhd
diff --git a/rtl/w11a/pdp11_core_rri.vhd b/rtl/w11a/pdp11_core_rbus.vhd
similarity index 85%
rename from rtl/w11a/pdp11_core_rri.vhd
rename to rtl/w11a/pdp11_core_rbus.vhd
index 2529696f..aca5d5e5 100644
--- a/rtl/w11a/pdp11_core_rri.vhd
+++ b/rtl/w11a/pdp11_core_rbus.vhd
@@ -1,4 +1,4 @@
--- $Id: pdp11_core_rri.vhd 335 2010-10-24 22:24:23Z mueller $
+-- $Id: pdp11_core_rbus.vhd 352 2011-01-02 13:01:37Z mueller $
 --
 -- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -12,18 +12,17 @@
 -- for complete details.
 --
 ------------------------------------------------------------------------------
--- Module Name:    pdp11_core_rri - syn
--- Description:    pdp11: core to rri register port interface
+-- Module Name:    pdp11_core_rbus - syn
+-- Description:    pdp11: core to rbus interface
 --
 -- Dependencies:   -
--- Test bench:     tb/tb_rritba_pdp11core
---                 tb/tb_rripdp_pdp11core
---                 tb/tb_rriext_pdp11core
+-- Test bench:     tb/tb_rlink_tba_pdp11core
 --
 -- Target Devices: generic
 -- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.26
 -- Revision History: -
 -- Date         Rev Version  Comment
+-- 2010-12-29   351   1.1    renamed from pdp11_core_rri; ported to rbv3
 -- 2010-10-23   335   1.2.3  rename RRI_LAM->RB_LAM;
 -- 2010-06-20   308   1.2.2  use c_ibrb_ibf_ def's
 -- 2010-06-18   306   1.2.1  rename RB_ADDR->RB_ADDR_CORE, add RB_ADDR_IBUS;
@@ -82,12 +81,12 @@ use ieee.std_logic_1164.all;
 use ieee.std_logic_arith.all;
 
 use work.slvtypes.all;
-use work.rrilib.all;
+use work.rblib.all;
 use work.pdp11.all;
 
 -- ----------------------------------------------------------------------------
 
-entity pdp11_core_rri is                -- core to rri reg port interface
+entity pdp11_core_rbus is               -- core to rbus interface
   generic (
     RB_ADDR_CORE : slv8 := conv_std_logic_vector(2#00000000#,8);
     RB_ADDR_IBUS : slv8 := conv_std_logic_vector(2#10000000#,8));
@@ -105,10 +104,10 @@ entity pdp11_core_rri is                -- core to rri reg port interface
     CP_STAT : in cp_stat_type;          -- console status port
     CP_DOUT : in slv16                  -- console data out
   );
-end pdp11_core_rri;
+end pdp11_core_rbus;
 
 
-architecture syn of pdp11_core_rri is
+architecture syn of pdp11_core_rbus is
 
   type state_type is (
     s_idle,                             -- s_idle: wait for rp access
@@ -118,6 +117,8 @@ architecture syn of pdp11_core_rri is
   
   type regs_type is record
     state : state_type;                 -- state
+    rbselc : slbit;                     -- rbus select for core
+    rbseli : slbit;                     -- rbus select for ibus
     cpreq : slbit;                      -- cp request flag
     cpfunc : slv5;                      -- cp function
     cpugo_1 : slbit;                    -- prev cycle cpugo
@@ -133,6 +134,7 @@ architecture syn of pdp11_core_rri is
 
   constant regs_init : regs_type := (
     s_idle,                             -- state
+    '0','0',                            -- rbselc,rbseli
     '0',                                -- cpreq
     (others=>'0'),                      -- cpfunc
     '0',                                -- cpugo_1
@@ -165,13 +167,12 @@ architecture syn of pdp11_core_rri is
     variable r : regs_type := regs_init;
     variable n : regs_type := regs_init;
 
-    variable irb_selc : slbit := '0';
-    variable irb_seli : slbit := '0';
     variable irb_ack  : slbit := '0';
     variable irb_busy : slbit := '0';
     variable irb_err  : slbit := '0';
     variable irb_dout : slv16 := (others=>'0');
     variable irb_lam  : slbit := '0';
+    variable irbena   : slbit := '0';
 
     variable icpreq    : slbit := '0';
     variable icpureset : slbit := '0';
@@ -182,32 +183,37 @@ architecture syn of pdp11_core_rri is
     r := R_REGS;
     n := R_REGS;
 
-    irb_selc := '0';
-    irb_seli := '0';
     irb_ack  := '0';
     irb_busy := '0';
     irb_err  := '0';
     irb_dout := (others=>'0');
     irb_lam  := '0';
-    
+
+    irbena  := RB_MREQ.re or RB_MREQ.we;
+
     icpreq    := '0';
     icpureset := '0';
 
-    if RB_MREQ.req='1' then
-      if RB_MREQ.addr(7 downto 5)=RB_ADDR_CORE(7 downto 5) then
-        irb_selc := '1';
-        irb_ack  := '1';                   -- ack all, unless reject or busy
-      end if;
-      if RB_MREQ.addr(7 downto 5)=RB_ADDR_IBUS(7 downto 5) then
-        irb_seli := '1';
-        irb_ack  := '1';                   -- ack all, unless reject or busy
-      end if;
-    end if;
-
     -- look for init's against the rbus base address, generate subsystem resets
     if RB_MREQ.init='1' and RB_MREQ.we='1' and RB_MREQ.addr=RB_ADDR_CORE then
       icpureset := RB_MREQ.din(0);
     end if;    
+
+    -- rbus address decoder
+    n.rbseli := '0';
+    n.rbselc := '0';
+    if RB_MREQ.aval='1' then
+      if RB_MREQ.addr(7 downto 5)=RB_ADDR_CORE(7 downto 5) then
+        n.rbselc := '1';
+      end if;
+      if RB_MREQ.addr(7 downto 5)=RB_ADDR_IBUS(7 downto 5) then
+        n.rbseli := '1';
+      end if;
+    end if;
+
+    if (r.rbselc='1' or r.rbseli='1') and irbena='1' then
+      irb_ack  := '1';                   -- ack all (maybe rejected later)
+    end if;
     
     case r.state is
 
@@ -216,12 +222,14 @@ architecture syn of pdp11_core_rri is
         n.doinc    := '0';
         n.waitstep := '0';
         
-        if irb_seli = '1' then
-          n.cpfunc    := c_cpfunc_rmem;
-          n.cpfunc(0) := RB_MREQ.we;
-          icpreq := '1';
+        if r.rbseli = '1' then
+          if irbena = '1' then
+            n.cpfunc    := c_cpfunc_rmem;
+            n.cpfunc(0) := RB_MREQ.we;
+            icpreq := '1';
+          end if;
 
-        elsif irb_selc = '1' then
+        elsif r.rbselc = '1' then
 
           case RB_MREQ.addr(4 downto 0) is
 
@@ -229,7 +237,9 @@ architecture syn of pdp11_core_rri is
               null;                         -- currently no action
 
             when c_rbaddr_cntl =>         -- cntl -------------------------
-              n.cpfunc := RB_MREQ.din(n.cpfunc'range);
+              if irbena = '1' then
+                n.cpfunc := RB_MREQ.din(n.cpfunc'range);
+              end if;
               if RB_MREQ.we = '1' then
                 icpreq := '1';
                 if RB_MREQ.din(3 downto 0) = c_cpfunc_step(3 downto 0) then
@@ -245,9 +255,11 @@ architecture syn of pdp11_core_rri is
               irb_dout(c_stat_rbf_cpurust) := CP_STAT.cpurust;
 
             when c_rbaddr_psw  =>         -- psw --------------------------
-              n.cpfunc    := c_cpfunc_rpsw;
-              n.cpfunc(0) := RB_MREQ.we;
-              icpreq := '1';
+              if irbena = '1' then
+                n.cpfunc    := c_cpfunc_rpsw;
+                n.cpfunc(0) := RB_MREQ.we;
+                icpreq := '1';
+              end if;
               
             when c_rbaddr_al   =>         -- al ---------------------------
               irb_dout(c_al_rbf_addr) := r.addr(c_al_rbf_addr);
@@ -269,24 +281,30 @@ architecture syn of pdp11_core_rri is
               end if;
 
             when c_rbaddr_mem  =>         -- mem -----------------
-              n.cpfunc    := c_cpfunc_rmem;
-              n.cpfunc(0) := RB_MREQ.we;
-              icpreq   := '1';
-
+              if irbena = '1' then
+                n.cpfunc    := c_cpfunc_rmem;
+                n.cpfunc(0) := RB_MREQ.we;
+                icpreq   := '1';
+              end if;
+              
             when c_rbaddr_memi  =>        -- memi ----------------
-              n.cpfunc    := c_cpfunc_rmem;
-              n.cpfunc(0) := RB_MREQ.we;
-              n.doinc  := '1';
-              icpreq   := '1';
+              if irbena = '1' then
+                n.cpfunc    := c_cpfunc_rmem;
+                n.cpfunc(0) := RB_MREQ.we;
+                n.doinc  := '1';
+                icpreq   := '1';
+              end if;
               
             when c_rbaddr_r0 | c_rbaddr_r1 |
                  c_rbaddr_r2 | c_rbaddr_r3 |
                  c_rbaddr_r4 | c_rbaddr_r5 |
                  c_rbaddr_sp | c_rbaddr_pc =>      -- r* ------------------
-              n.cpfunc    := c_cpfunc_rreg;
-              n.cpfunc(0) := RB_MREQ.we;
-              icpreq   := '1';
-
+              if irbena = '1' then
+                n.cpfunc    := c_cpfunc_rreg;
+                n.cpfunc(0) := RB_MREQ.we;
+                icpreq   := '1';
+              end if;
+              
             when c_rbaddr_ibrb  =>        -- ibrb ----------------
               irb_dout(c_ibrb_ibf_base) := r.ibrbase;
               irb_dout(c_ibrb_ibf_be)   := r.ibrberet;
@@ -316,11 +334,11 @@ architecture syn of pdp11_core_rri is
       when s_cpwait =>                  -- s_cpwait: wait for cp port ack ----
         n.cpreq := '0';                   -- cpreq only for 1 cycle
 
-        if (irb_selc or irb_seli) = '0' then    -- rbus cycle abort
+        if (r.rbselc or r.rbseli)='0' or irbena='0' then -- rbus cycle abort
           n.state := s_idle;              -- quit
         else
           irb_dout := CP_DOUT;
-          irb_err  := CP_STAT.cmderr  or CP_STAT.cmdmerr;
+          irb_err  := CP_STAT.cmderr or CP_STAT.cmdmerr;
           if CP_STAT.cmdack = '1' then       -- normal cycle end
             if r.doinc = '1' then
               n.addr := unsigned(r.addr) + 1;
@@ -337,7 +355,7 @@ architecture syn of pdp11_core_rri is
         end if;
 
       when s_cpstep =>                  -- s_cpstep: wait for cpustep done ---
-        if irb_selc = '0' then            -- rbus cycle abort
+        if r.rbselc='0' or irbena='0' then -- rbus cycle abort
           n.state := s_idle;                -- quit
         else
           if CP_STAT.cpustep = '0' then      -- cpustep done
@@ -357,7 +375,7 @@ architecture syn of pdp11_core_rri is
     icpaddr.ena_22bit := r.ena_22bit;
     icpaddr.ena_ubmap := r.ena_ubmap;
       
-    if irb_seli = '1' then
+    if r.rbseli = '1' and irbena = '1' then
       icpaddr.addr(15 downto 13)    := "111";
       icpaddr.addr(c_ibrb_ibf_base) := r.ibrbase;
       icpaddr.addr(5 downto 1)      := RB_MREQ.addr(4 downto 0);
diff --git a/rtl/w11a/pdp11_mmu_sadr.vhd b/rtl/w11a/pdp11_mmu_sadr.vhd
index 6b5ddd38..459839b2 100644
--- a/rtl/w11a/pdp11_mmu_sadr.vhd
+++ b/rtl/w11a/pdp11_mmu_sadr.vhd
@@ -1,4 +1,4 @@
--- $Id: pdp11_mmu_sadr.vhd 336 2010-11-06 18:28:27Z mueller $
+-- $Id: pdp11_mmu_sadr.vhd 351 2010-12-30 21:50:54Z mueller $
 --
 -- Copyright 2006-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -23,6 +23,7 @@
 --
 -- Revision History: 
 -- Date         Rev Version  Comment
+-- 2010-12-30   351   1.3.2  BUGFIX: fix sensitivity list of proc_eaddr
 -- 2010-10-23   335   1.3.1  change proc_eaddr logic, shorten logic path
 -- 2010-10-17   333   1.3    use ibus V2 interface
 -- 2008-08-22   161   1.2.2  rename ubf_ -> ibf_; use iblib
@@ -213,7 +214,7 @@ begin
   -- and reduce the eaddr mux to a 4-input LUT. Last resort is a 2 cycle ibus
   -- access with a state flop marking the 2nd cycle of a re/we transaction.
   
-  proc_eaddr: process (IB_MREQ, MODE, ASN)
+  proc_eaddr: process (IB_MREQ, MODE, ASN, R_IBSEL_DR, R_IBSEL_AR)
     variable eaddr : slv6 := (others=>'0');
     variable idr : slbit := '0';
     variable iar : slbit := '0';
diff --git a/rtl/w11a/tb/.cvsignore b/rtl/w11a/tb/.cvsignore
index c7ccb067..9af5fe8e 100644
--- a/rtl/w11a/tb/.cvsignore
+++ b/rtl/w11a/tb/.cvsignore
@@ -1,22 +1,12 @@
-tb_pdp11_core
-tb_pdp11_core_stim
-tb_pdp11_core_[sft]sim
-tb_pdp11_core_ISim
-tb_pdp11_core_ISim_[sft]sim
-tb_rritba_pdp11core
-tb_rritba_pdp11core_[sft]sim
-tb_rritba_pdp11core_ISim
-tb_rritba_pdp11core_ISim_[sft]sim
-tb_rritba_stim
-tb_rripdp_pdp11core
-tb_rripdp_pdp11core_[sft]sim
-tb_rripdp_pdp11core_ISim
-tb_rripdp_pdp11core_ISim_[sft]sim
-tb_rripdp_stim
-tb_rriext_pdp11core
-tb_rriext_pdp11core_[sft]sim
-tb_rriext_fifo_rx
-tb_rriext_fifo_tx
-tb_rriext_conf
-tb_pdp11_core_stim.scmd
+tb_pdp11core
+tb_pdp11core_stim
+tb_pdp11core_[sft]sim
+tb_pdp11core_ISim
+tb_pdp11core_ISim_[sft]sim
+tb_rlink_tba_pdp11core
+tb_rlink_tba_pdp11core_[sft]sim
+tb_rlink_tba_pdp11core_ISim
+tb_rlink_tba_pdp11core_ISim_[sft]sim
+tb_rlink_tba_stim
+tb_pdp11core_stim.scmd
 tmu_ofile
diff --git a/rtl/w11a/tb/Makefile b/rtl/w11a/tb/Makefile
index ba5d1cb5..fbe83962 100644
--- a/rtl/w11a/tb/Makefile
+++ b/rtl/w11a/tb/Makefile
@@ -1,14 +1,14 @@
-# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $
+# $Id: Makefile 351 2010-12-30 21:50:54Z mueller $
 #
 #  Revision History: 
 # Date         Rev Version  Comment
+# 2010-12-30   351   1.3    retire tb_rripdp_pdp11core tb_rriext_pdp11core
 # 2009-11-22   252   1.2    add ISim support
 # 2007-09-16    83   1.1.1  add include *.o.dep_ghdl
 # 2007-07-06    64   1.1    use vbom's
 # 2007-06-17    58   1.0    Initial version
 #
-EXE_all = tb_pdp11_core tb_rritba_pdp11core tb_rripdp_pdp11core \
-	tb_rriext_pdp11core
+EXE_all = tb_pdp11core tb_rlink_tba_pdp11core
 #
 #
 .phony : all all_ssim all_tsim clean
@@ -40,18 +40,18 @@ include $(wildcard *.o.dep_ghdl)
 	simdat_check $*.simh_raw_log > $*.simh_log
 	grep FAIL  $*.simh_log
 
-check_dsim: tb_pdp11_core tb_pdp11_core_stim.dat
-	time tbw tb_pdp11_core |\
-	   tee tb_pdp11_core_dsim.log |\
+check_dsim: tb_pdp11core tb_pdp11core_stim.dat
+	time tbw tb_pdp11core |\
+	   tee tb_pdp11core_dsim.log |\
 	   egrep "(FAIL|DONE)" || true
 	@ echo "# diff to reference"
-	diff tb_pdp11_core_out_ref.dat tb_pdp11_core_dsim.log
+	diff tb_pdp11core_out_ref.dat tb_pdp11core_dsim.log
 
-check_ssim: tb_pdp11_core_ssim tb_pdp11_core_stim.dat
-	time tbw tb_pdp11_core_ssim |\
-	   tee tb_pdp11_core_ssim.log |\
+check_ssim: tb_pdp11core_ssim tb_pdp11core_stim.dat
+	time tbw tb_pdp11core_ssim |\
+	   tee tb_pdp11core_ssim.log |\
 	   egrep "(FAIL|DONE)" || true
 	@ echo "# diff to reference"
-	diff tb_pdp11_core_out_ref.dat tb_pdp11_core_ssim.log
+	diff tb_pdp11core_out_ref.dat tb_pdp11core_ssim.log
 
-check_simh: tb_pdp11_core_stim.simh_log
+check_simh: tb_pdp11core_stim.simh_log
diff --git a/rtl/w11a/tb/tb_pdp11_core_ssim.vbom b/rtl/w11a/tb/tb_pdp11_core_ssim.vbom
deleted file mode 100644
index 84ccaef3..00000000
--- a/rtl/w11a/tb/tb_pdp11_core_ssim.vbom
+++ /dev/null
@@ -1,4 +0,0 @@
-# configure for _*sim case
-tbd_pdp11_core = tbd_pdp11_core_ssim.vhd
-tb_pdp11_core.vbom
-@top:tb_pdp11_core
diff --git a/rtl/w11a/tb/tb_pdp11_core.vbom b/rtl/w11a/tb/tb_pdp11core.vbom
similarity index 75%
rename from rtl/w11a/tb/tb_pdp11_core.vbom
rename to rtl/w11a/tb/tb_pdp11core.vbom
index 7c98753a..76f1105a 100644
--- a/rtl/w11a/tb/tb_pdp11_core.vbom
+++ b/rtl/w11a/tb/tb_pdp11core.vbom
@@ -6,6 +6,6 @@
 ../pdp11.vbom
 # components
 ../../vlib/simlib/simclk.vbom
-tbd_pdp11_core : tbd_pdp11_core.vbom
+tbd_pdp11core : tbd_pdp11core.vbom
 # design
-tb_pdp11_core.vhd
+tb_pdp11core.vhd
diff --git a/rtl/w11a/tb/tb_pdp11_core.vhd b/rtl/w11a/tb/tb_pdp11core.vhd
similarity index 96%
rename from rtl/w11a/tb/tb_pdp11_core.vhd
rename to rtl/w11a/tb/tb_pdp11core.vhd
index 47186020..b0477d8b 100644
--- a/rtl/w11a/tb/tb_pdp11_core.vhd
+++ b/rtl/w11a/tb/tb_pdp11core.vhd
@@ -1,6 +1,6 @@
--- $Id: tb_pdp11_core.vhd 314 2010-07-09 17:38:41Z mueller $
+-- $Id: tb_pdp11core.vhd 352 2011-01-02 13:01:37Z mueller $
 --
--- Copyright 2006-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
 -- This program is free software; you may redistribute and/or modify it under
 -- the terms of the GNU General Public License as published by the Free
@@ -12,11 +12,11 @@
 -- for complete details.
 --
 ------------------------------------------------------------------------------
--- Module Name:    tb_pdp11_core - sim
+-- Module Name:    tb_pdp11core - sim
 -- Description:    Test bench for pdp11_core
 --
 -- Dependencies:   simlib/simclk
---                 tbd_pdp11_core [UUT]
+--                 tbd_pdp11core [UUT]
 --                 pdp11_intmap
 --
 -- To test:        pdp11_core
@@ -24,8 +24,10 @@
 -- Target Devices: generic
 -- Tool versions:  ghdl 0.18-0.29; ISim 11.3
 --
--- Verified (with tb_pdp11_core_stim.dat):
+-- Verified (with tb_pdp11core_stim.dat):
 -- Date         Rev  Code  ghdl  ise          Target     Comment
+-- 2010-12-30   351  -     0.29  -            -          u:ok
+-- 2010-12-30   351  _ssim 0.29  12.1   M53d  xc3s1000   u:ok
 -- 2010-06-20   308  -     0.29  -            -          u:ok
 -- 2009-11-22   252  -     0.26  -            -          u:ok
 -- 2007-12-30   107  -     0.25  -            -          u:ok
@@ -44,6 +46,8 @@
 --
 -- Revision History: 
 -- Date         Rev Version  Comment
+-- 2011-01-02   352   1.3.1  rename .cpmon->.rlmon
+-- 2010-12-30   351   1.3    rename tb_pdp11_core -> tb_pdp11core
 -- 2010-06-20   308   1.2.2  add wibrb, ribr, wibr commands for ibr accesses
 -- 2010-06-20   307   1.2.1  add CP_ADDR_racc, CP_ADDR_be to tbd interface
 -- 2010-06-13   305   1.2    add CP_CNTL_rnum and CP_ADDR_...;  emulate old
@@ -83,10 +87,10 @@ use work.simbus.all;
 use work.pdp11_sim.all;
 use work.pdp11.all;
 
-entity tb_pdp11_core is
-end tb_pdp11_core;
+entity tb_pdp11core is
+end tb_pdp11core;
 
-architecture sim of tb_pdp11_core is
+architecture sim of tb_pdp11core is
 
   signal CLK : slbit := '0';
   signal RESET : slbit := '0';
@@ -135,7 +139,7 @@ begin
       CLK_STOP  => CLK_STOP
     );
 
-  UUT: entity work.tbd_pdp11_core
+  UUT: entity work.tbd_pdp11core
     port map (
       CLK             => CLK,
       RESET           => RESET,
@@ -160,7 +164,7 @@ begin
     );
   
   proc_stim: process
-    file ifile : text open read_mode is "tb_pdp11_core_stim";
+    file ifile : text open read_mode is "tb_pdp11core_stim";
     variable iline  : line;
     variable oline  : line;
     variable idelta : integer := 0;
@@ -299,7 +303,7 @@ begin
 
             when ".anena" =>            -- .anena (ignore it)
               readempty(iline);
-            when ".cpmon" =>            -- .cpmon (ignore it)
+            when ".rlmon" =>            -- .rlmon (ignore it)
               readempty(iline);
             when ".rbmon" =>            -- .rbmon (ignore it)
               readempty(iline);
diff --git a/rtl/w11a/tb/tb_pdp11core_ssim.vbom b/rtl/w11a/tb/tb_pdp11core_ssim.vbom
new file mode 100644
index 00000000..8e56da84
--- /dev/null
+++ b/rtl/w11a/tb/tb_pdp11core_ssim.vbom
@@ -0,0 +1,4 @@
+# configure for _*sim case
+tbd_pdp11core = tbd_pdp11core_ssim.vhd
+tb_pdp11core.vbom
+@top:tb_pdp11core
diff --git a/rtl/w11a/tb/tb_pdp11_core_stim.dat b/rtl/w11a/tb/tb_pdp11core_stim.dat
similarity index 99%
rename from rtl/w11a/tb/tb_pdp11_core_stim.dat
rename to rtl/w11a/tb/tb_pdp11core_stim.dat
index 0e7e4380..79f196e1 100644
--- a/rtl/w11a/tb/tb_pdp11_core_stim.dat
+++ b/rtl/w11a/tb/tb_pdp11core_stim.dat
@@ -1,4 +1,4 @@
-# $Id: tb_pdp11_core_stim.dat 309 2010-06-26 18:49:06Z mueller $
+# $Id: tb_pdp11core_stim.dat 351 2010-12-30 21:50:54Z mueller $
 #
 # Revision History: 
 # Date         Rev Version  Comment
@@ -31,7 +31,7 @@
 .tocmd   50
 .tostp  100
 .togo  5000
-.cpmon    0
+.rlmon    0
 .rbmon    0
 .scntl 13 0
 #
diff --git a/rtl/w11a/tb/tbd_pdp11_core.vbom b/rtl/w11a/tb/tbd_pdp11core.vbom
similarity index 93%
rename from rtl/w11a/tb/tbd_pdp11_core.vbom
rename to rtl/w11a/tb/tbd_pdp11core.vbom
index 16a58662..6e18c81c 100644
--- a/rtl/w11a/tb/tbd_pdp11_core.vbom
+++ b/rtl/w11a/tb/tbd_pdp11core.vbom
@@ -12,4 +12,4 @@ sys_conf : ../sys_conf.vhd
 ../../ibus/ibdr_minisys.vbom
 [ghdl,isim]../pdp11_tmu_sb.vbom
 # design
-tbd_pdp11_core.vhd
+tbd_pdp11core.vhd
diff --git a/rtl/w11a/tb/tbd_pdp11_core.vhd b/rtl/w11a/tb/tbd_pdp11core.vhd
similarity index 96%
rename from rtl/w11a/tb/tbd_pdp11_core.vhd
rename to rtl/w11a/tb/tbd_pdp11core.vhd
index dbee1623..1ee0ad3a 100644
--- a/rtl/w11a/tb/tbd_pdp11_core.vhd
+++ b/rtl/w11a/tb/tbd_pdp11core.vhd
@@ -1,4 +1,4 @@
--- $Id: tbd_pdp11_core.vhd 335 2010-10-24 22:24:23Z mueller $
+-- $Id: tbd_pdp11core.vhd 351 2010-12-30 21:50:54Z mueller $
 --
 -- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -12,7 +12,7 @@
 -- for complete details.
 --
 ------------------------------------------------------------------------------
--- Module Name:    tbd_pdp11_core - syn
+-- Module Name:    tbd_pdp11core - syn
 -- Description:    Wrapper for pdp11_core to avoid records. It has a port
 --                 interface which will not be modified by xst synthesis
 --                 (no records, no generic port).
@@ -41,6 +41,7 @@
 --
 -- Revision History: 
 -- Date         Rev Version  Comment
+-- 2010-12-30   351   1.5    rename tbd_pdp11_core -> tbd_pdp11core
 -- 2010-10-23   335   1.4.2  rename RRI_LAM->RB_LAM;
 -- 2010-06-20   307   1.4.1  add CP_ADDR_racc, CP_ADDR_be port
 -- 2010-06-13   305   1.4    add CP_ADDR_... in ports; add CP_CNTL_rnum in port
@@ -71,7 +72,7 @@ use work.ibdlib.all;
 use work.pdp11.all;
 use work.sys_conf.all;
 
-entity tbd_pdp11_core is              -- full core [no records]
+entity tbd_pdp11core is               -- full core [no records]
   port (
     CLK : in slbit;                   -- clock
     RESET : in slbit;                 -- reset
@@ -94,10 +95,10 @@ entity tbd_pdp11_core is              -- full core [no records]
     CP_STAT_cpurust : out slv4;       -- console status port
     CP_DOUT : out slv16               -- console data out
   );
-end tbd_pdp11_core;
+end tbd_pdp11core;
 
 
-architecture syn of tbd_pdp11_core is
+architecture syn of tbd_pdp11core is
   
   signal CE_USEC : slbit := '0';
 
diff --git a/rtl/w11a/tb/tbw.dat b/rtl/w11a/tb/tbw.dat
index 8ee9d091..36729583 100644
--- a/rtl/w11a/tb/tbw.dat
+++ b/rtl/w11a/tb/tbw.dat
@@ -1,12 +1,5 @@
-# $Id: tbw.dat 81 2007-09-09 20:50:42Z mueller $
+# $Id: tbw.dat 351 2010-12-30 21:50:54Z mueller $
 #
-[tb_rritba_pdp11core]
-tb_rritba_stim = tb_rritba_pdp11core_stim.dat
+[tb_rlink_tba_pdp11core]
+tb_rlink_tba_stim = tb_rlink_tba_pdp11core_stim.dat
 #
-[tb_rripdp_pdp11core]
-tb_rripdp_stim = tb_pdp11_core_stim.dat
-#
-[tb_rriext_pdp11core]
-tb_rriext_fifo_rx = <fifo>
-tb_rriext_fifo_tx = <fifo>
-tb_rriext_conf = <null>
diff --git a/tools/bin/pi_rri b/tools/bin/pi_rri
index 00d9a3b8..4326f024 100755
--- a/tools/bin/pi_rri
+++ b/tools/bin/pi_rri
@@ -1,5 +1,5 @@
 #!/usr/bin/perl -w
-# $Id: pi_rri 314 2010-07-09 17:38:41Z mueller $
+# $Id: pi_rri 351 2010-12-30 21:50:54Z mueller $
 #
 # Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 #
@@ -14,6 +14,7 @@
 #
 #  Revision History:
 # Date         Rev Version  Comment
+# 2010-12-29   351   1.6.3  rename rriext->cext and cpmon->rlmon
 # 2010-06-27   310   1.6.2  fix autoflush for fh_log; duplicate exec err to log
 # 2010-06-18   306   1.6.1  PDPCP_ADDR_IBRB now 020, PDPCP_ADDR_IBR now 0200;
 #                           ibrbase now just drops the 6 lsb's; pdpcp mode:
@@ -2089,7 +2090,7 @@ sub rri_close {
 }
 
 #-------------------------------------------------------------------------------
-#  .cpmon 0|1
+#  .rlmon 0|1
 #  .rbmon 0|1
 #  .scntl n 0|1
 #  .sinit g8 g16
@@ -2117,8 +2118,8 @@ sub rri_cexec {
   $cmd_rest = "";
   $cmd_bad  = 0;
 
-  if ($cmd =~ /^(\.cpmon|\.rbmon)\s+([01])/) {  # .cpmon, .rbmon -------------
-    my $ind = ($1 eq ".cpmon") ? 15 : 14;
+  if ($cmd =~ /^(\.rlmon|\.rbmon)\s+([01])/) {  # .rlmon, .rbmon -------------
+    my $ind = ($1 eq ".rlmon") ? 15 : 14;
     $cmd_rest = $';
     rri_sideband(0x00, ($ind<<8) + $2);
 
@@ -2708,7 +2709,7 @@ sub pdpcp_close {
 #  .tostp n
 #  .togo  n
 #  .anena 0|1
-#  .cpmon 0|1
+#  .rlmon 0|1
 #  .rbmon 0|1
 #  .scntl n 0|1
 #  .sinit g8 g16
@@ -2777,9 +2778,9 @@ sub pdpcp_cexec {
 			data     => $ena_data};
     rri_cmdlist_do();
 
-  } elsif ($cmd =~ /^(\.cpmon|\.rbmon)\s+([01])/) { # .cpmon, .rbmon ---------
+  } elsif ($cmd =~ /^(\.rlmon|\.rbmon)\s+([01])/) { # .rlmon, .rbmon ---------
     $cmd_rest = $';
-    my $ind = ($1 eq ".cpmon") ? 15 : 14;
+    my $ind = ($1 eq ".rlmon") ? 15 : 14;
     $cmd_rest = $';
     rri_sideband(0x00, ($ind<<8) + $2);
 
@@ -3237,7 +3238,7 @@ sub serv11_cexec {
       my $val  = cget_bool();
       return if $cmd_bad or cget_chkblank();
       my $ind;
-      $ind = 15 if $pnam eq "cpmon";
+      $ind = 15 if $pnam eq "rlmon";
       $ind = 14 if $pnam eq "rbmon";
       $ind = 13 if $pnam eq "tmu";
       if (defined $ind) {
@@ -6370,7 +6371,7 @@ sub wait_sel_filercv {			    # poll/wait for TX to be ready
 sub fifo_open {				    # chan fifo: open handler
   my ($arg) = @_;
   my ($file,$keep) = split /,/,$arg;
-  my $file_base = $file ? $file : "tb_rriext_fifo";
+  my $file_base = $file ? $file : "rlink_cext_fifo";
   my $file_snd = $file_base . "_rx";
   my $file_rcv = $file_base . "_tx";