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use DM_STAT_EXP for signals exported by pdp11_sys70

Browse Source 
- pdp11_sys70: drop ITIMER,DM_STAT_DP, use DM_STAT_EXP, add PERFEXT port
- pdp11_sequencer: drop ITIMER port, use DM_STAT_SE.itimer
- sys_w11a_*.vhd: use DM_STAT_EXP
- some re-wiring, no functional change to CPU or IO system
This commit is contained in:
wfjm 2018-10-13 15:18:59 +02:00
parent a500e62912
commit c7e606d9b0
22 changed files with 620 additions and 495 deletions
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10
doc/CHANGELOG.md
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@ -50,13 +50,17 @@ The full set of tests is only run for tagged releases.
- Makefile: `make all_tcl` now quiet, use setup_packages_filt
- sys_w11_n4: reduce cache from 64 to 32 kB to keep timing closure
- changes for DM_STAT_* signals (debug and monitoring)
- DM_STAT_SE: add elements cpbusy,idec,pcload
- DM_STAT_SE: add elements cpbusy,idec,pcload,itimer
- DM_STAT_CA: added, used for cache monitoring
- DM_STAT_SY: removed, now replaced by DM_STAT_CA
- pdp11_sys70: instantiate pdp11_dmpcnt, setup performance counter sigs
- pdp11_sequencer: drive DM_STAT_SE.(cpbusy,idec,pcload)
- DM_STAT_EXP: added, for signals exported by pdp11_sys70
- pdp11_sys70:
- instantiate pdp11_dmpcnt, setup performance counter sigs
- drop ITIMER,DM_STAT_DP, use DM_STAT_EXP, add PERFEXT port
- pdp11_sequencer: drive DM_STAT_SE.(cpbusy,idec,pcload,itimer), drop ITIMER
- pdp11_cache: drop CHIT, add DM_STAT_CA port, add detailed monitoring
- pdp11_tmu(_sb): use DM_STAT_CA instead of DM_STAT_SY
- sys_w11a_*.vhd: use DM_STAT_EXP
- RtclRw11Unit: fix for clang: M_virt() now public
- backend code review:
- use for C++ compiles also `-Wpedantic`

25
rtl/sys_gen/w11a/arty_bram/pdp11_hio70_arty.vhd
View File

@ -1,6 +1,6 @@
-- $Id: pdp11_hio70_arty.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: pdp11_hio70_arty.vhd 1055 2018-10-12 17:53:52Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2016-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@ -18,10 +18,11 @@
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: viv 2015.4; ghdl 0.31
-- Tool versions: viv 2015.4-2018.2; ghdl 0.31-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 1.1 use DM_STAT_EXP instead of DM_STAT_DP
-- 2016-02-27 737 1.0 Initial version
------------------------------------------------------------------------------
--
@ -75,7 +76,7 @@ entity pdp11_hio70_arty is -- hio led+rgb for sys70 for arty
MEM_ACT_R : in slbit; -- memory active read
MEM_ACT_W : in slbit; -- memory active write
CP_STAT : in cp_stat_type; -- console port status
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status
DM_STAT_EXP : in dm_stat_exp_type; -- debug and monitor - exports
DISPREG : in slv16; -- display register
IOLEDS : in slv4; -- serport ioleds
ABCLKDIV : in slv16; -- serport clock divider
@ -108,9 +109,9 @@ begin
idat16 := (others=>'0');
case MODE(1 downto 0) is
when "00" => idat16 := ABCLKDIV;
when "01" => idat16 := DM_STAT_DP.pc;
when "01" => idat16 := DM_STAT_EXP.dp_pc;
when "10" => idat16 := DISPREG;
when "11" => idat16 := DM_STAT_DP.dsrc;
when "11" => idat16 := DM_STAT_EXP.dp_dsrc;
when others => null;
end case;
@ -131,10 +132,10 @@ begin
if MODE(0) = '1' then
if CP_STAT.cpugo = '1' then
case DM_STAT_DP.psw.cmode is
case DM_STAT_EXP.dp_psw.cmode is
when c_psw_kmode =>
if CP_STAT.cpuwait = '0' then
if unsigned(DM_STAT_DP.psw.pri) = 0 then
if unsigned(DM_STAT_EXP.dp_psw.pri) = 0 then
irgb_g(2) := '1';
else
irgb_g(3) := '1';
@ -159,10 +160,10 @@ begin
end if;
else -- LED+RGB show DR emulation
iled := DM_STAT_DP.dsrc(15 downto 12);
irgb_b := DM_STAT_DP.dsrc(11 downto 8);
irgb_g := DM_STAT_DP.dsrc( 7 downto 4);
irgb_r := DM_STAT_DP.dsrc( 3 downto 0);
iled := DM_STAT_EXP.dp_dsrc(15 downto 12);
irgb_b := DM_STAT_EXP.dp_dsrc(11 downto 8);
irgb_g := DM_STAT_EXP.dp_dsrc( 7 downto 4);
irgb_r := DM_STAT_EXP.dp_dsrc( 3 downto 0);
end if; -- MODE(2) = '0'
else -- LED+RGB show one of four regs

94
rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vhd
View File

@ -1,4 +1,4 @@
-- $Id: sys_w11a_br_arty.vhd 1045 2018-09-15 15:20:57Z mueller $
-- $Id: sys_w11a_br_arty.vhd 1055 2018-10-12 17:53:52Z mueller $
--
-- Copyright 2016-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@ -53,6 +53,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 1.3 use DM_STAT_EXP
-- 2016-04-02 758 1.2.1 add rbd_usracc (bitfile+jtag timestamp access)
-- 2016-03-28 755 1.2 use serport_2clock2
-- 2016-03-19 748 1.1.2 define rlink SYSID
@ -171,13 +172,13 @@ architecture syn of sys_w11a_br_arty is
signal GRESET : slbit := '0'; -- general reset (from rbus)
signal CRESET : slbit := '0'; -- cpu reset (from cp)
signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
signal ITIMER : slbit := '0';
signal PERFEXT : slv8 := (others=>'0');
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal CP_STAT : cp_stat_type := cp_stat_init;
signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;
signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init;
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
@ -313,33 +314,42 @@ begin
SER_MONI => SER_MONI
);
PERFEXT(0) <= '0';
PERFEXT(1) <= '0';
PERFEXT(2) <= '0';
PERFEXT(3) <= '0';
PERFEXT(4) <= '0';
PERFEXT(5) <= '0';
PERFEXT(6) <= '0';
PERFEXT(7) <= CE_USEC;
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
ITIMER => ITIMER,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_DP => DM_STAT_DP
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
PERFEXT => PERFEXT,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_EXP => DM_STAT_EXP
);
@ -350,7 +360,7 @@ begin
CE_MSEC => CE_MSEC,
RESET => GRESET,
BRESET => BRESET,
ITIMER => ITIMER,
ITIMER => DM_STAT_EXP.se_itimer,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
@ -391,19 +401,19 @@ begin
HIO70 : entity work.pdp11_hio70_arty -- hio from sys70 --------------------
port map (
CLK => CLK,
MODE => SWI,
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_DP => DM_STAT_DP,
DISPREG => DISPREG,
IOLEDS => IOLEDS,
ABCLKDIV => ABCLKDIV,
LED => LED,
RGB_R => RGB_R,
RGB_G => RGB_G,
RGB_B => RGB_B
CLK => CLK,
MODE => SWI,
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_EXP => DM_STAT_EXP,
DISPREG => DISPREG,
IOLEDS => IOLEDS,
ABCLKDIV => ABCLKDIV,
LED => LED,
RGB_R => RGB_R,
RGB_G => RGB_G,
RGB_B => RGB_B
);
HIO : bp_swibtnled

19
rtl/sys_gen/w11a/artys7_bram/pdp11_hio70_artys7.vhd
View File

@ -1,4 +1,4 @@
-- $Id: pdp11_hio70_artys7.vhd 1038 2018-08-11 12:39:52Z mueller $
-- $Id: pdp11_hio70_artys7.vhd 1055 2018-10-12 17:53:52Z mueller $
--
-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@ -22,6 +22,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 1.1 use DM_STAT_EXP instead of DM_STAT_DP
-- 2018-08-05 1038 1.0 Initial version (cloned from pdp11_hio70_artya7)
------------------------------------------------------------------------------
--
@ -71,7 +72,7 @@ entity pdp11_hio70_artys7 is -- hio led+rgb for sys70 for artys7
MEM_ACT_R : in slbit; -- memory active read
MEM_ACT_W : in slbit; -- memory active write
CP_STAT : in cp_stat_type; -- console port status
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status
DM_STAT_EXP : in dm_stat_exp_type; -- debug and monitor - exports
DISPREG : in slv16; -- display register
IOLEDS : in slv4; -- serport ioleds
ABCLKDIV : in slv16; -- serport clock divider
@ -104,9 +105,9 @@ begin
idat16 := (others=>'0');
case MODE(1 downto 0) is
when "00" => idat16 := ABCLKDIV;
when "01" => idat16 := DM_STAT_DP.pc;
when "01" => idat16 := DM_STAT_EXP.dp_pc;
when "10" => idat16 := DISPREG;
when "11" => idat16 := DM_STAT_DP.dsrc;
when "11" => idat16 := DM_STAT_EXP.dp_dsrc;
when others => null;
end case;
@ -127,7 +128,7 @@ begin
if MODE(0) = '1' then
if CP_STAT.cpugo = '1' then
case DM_STAT_DP.psw.cmode is
case DM_STAT_EXP.dp_psw.cmode is
when c_psw_kmode =>
if CP_STAT.cpuwait = '0' then
irgb_g(1) := '1';
@ -149,10 +150,10 @@ begin
end if;
else -- LED+RGB show DR emulation
iled := DM_STAT_DP.dsrc(15 downto 12);
irgb_b := DM_STAT_DP.dsrc( 9 downto 8);
irgb_g := DM_STAT_DP.dsrc( 5 downto 4);
irgb_r := DM_STAT_DP.dsrc( 1 downto 0);
iled := DM_STAT_EXP.dp_dsrc(15 downto 12);
irgb_b := DM_STAT_EXP.dp_dsrc( 9 downto 8);
irgb_g := DM_STAT_EXP.dp_dsrc( 5 downto 4);
irgb_r := DM_STAT_EXP.dp_dsrc( 1 downto 0);
end if; -- MODE(2) = '0'
else -- LED+RGB show one of four regs

94
rtl/sys_gen/w11a/artys7_bram/sys_w11a_br_as7.vhd
View File

@ -1,4 +1,4 @@
-- $Id: sys_w11a_br_as7.vhd 1047 2018-09-16 11:08:41Z mueller $
-- $Id: sys_w11a_br_as7.vhd 1055 2018-10-12 17:53:52Z mueller $
--
-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@ -45,6 +45,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 1.1 use DM_STAT_EXP
-- 2018-08-11 1038 1.0 Initial version (derived from sys_w11a_aa7)
------------------------------------------------------------------------------
--
@ -150,13 +151,13 @@ architecture syn of sys_w11a_br_as7 is
signal GRESET : slbit := '0'; -- general reset (from rbus)
signal CRESET : slbit := '0'; -- cpu reset (from cp)
signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
signal ITIMER : slbit := '0';
signal PERFEXT : slv8 := (others=>'0');
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal CP_STAT : cp_stat_type := cp_stat_init;
signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;
signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init;
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
@ -292,33 +293,42 @@ begin
SER_MONI => SER_MONI
);
PERFEXT(0) <= '0';
PERFEXT(1) <= '0';
PERFEXT(2) <= '0';
PERFEXT(3) <= '0';
PERFEXT(4) <= '0';
PERFEXT(5) <= '0';
PERFEXT(6) <= '0';
PERFEXT(7) <= CE_USEC;
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
ITIMER => ITIMER,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_DP => DM_STAT_DP
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
PERFEXT => PERFEXT,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_EXP => DM_STAT_EXP
);
@ -329,7 +339,7 @@ begin
CE_MSEC => CE_MSEC,
RESET => GRESET,
BRESET => BRESET,
ITIMER => ITIMER,
ITIMER => DM_STAT_EXP.se_itimer,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
@ -370,19 +380,19 @@ begin
HIO70 : entity work.pdp11_hio70_artys7 -- hio from sys70 --------------------
port map (
CLK => CLK,
MODE => SWI,
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_DP => DM_STAT_DP,
DISPREG => DISPREG,
IOLEDS => IOLEDS,
ABCLKDIV => ABCLKDIV,
LED => LED,
RGB_R => RGB_R,
RGB_G => RGB_G,
RGB_B => RGB_B
CLK => CLK,
MODE => SWI,
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_EXP => DM_STAT_EXP,
DISPREG => DISPREG,
IOLEDS => IOLEDS,
ABCLKDIV => ABCLKDIV,
LED => LED,
RGB_R => RGB_R,
RGB_G => RGB_G,
RGB_B => RGB_B
);
HIO : bp_swibtnled

88
rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd
View File

@ -1,4 +1,4 @@
-- $Id: sys_w11a_b3.vhd 1045 2018-09-15 15:20:57Z mueller $
-- $Id: sys_w11a_b3.vhd 1055 2018-10-12 17:53:52Z mueller $
--
-- Copyright 2015-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@ -50,6 +50,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 2.4 use DM_STAT_EXP
-- 2016-04-02 758 2.3.1 add rbd_usracc (bitfile+jtag timestamp access)
-- 2016-03-28 755 2.3 use serport_2clock2
-- 2016-03-19 748 2.2.2 define rlink SYSID
@ -170,13 +171,13 @@ architecture syn of sys_w11a_b3 is
signal GRESET : slbit := '0'; -- general reset (from rbus)
signal CRESET : slbit := '0'; -- cpu reset (from cp)
signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
signal ITIMER : slbit := '0';
signal PERFEXT : slv8 := (others=>'0');
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal CP_STAT : cp_stat_type := cp_stat_init;
signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;
signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init;
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
@ -311,33 +312,42 @@ begin
SER_MONI => SER_MONI
);
PERFEXT(0) <= '0';
PERFEXT(1) <= '0';
PERFEXT(2) <= '0';
PERFEXT(3) <= '0';
PERFEXT(4) <= '0';
PERFEXT(5) <= '0';
PERFEXT(6) <= '0';
PERFEXT(7) <= CE_USEC;
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
ITIMER => ITIMER,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_DP => DM_STAT_DP
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
PERFEXT => PERFEXT,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_EXP => DM_STAT_EXP
);
@ -348,7 +358,7 @@ begin
CE_MSEC => CE_MSEC,
RESET => GRESET,
BRESET => BRESET,
ITIMER => ITIMER,
ITIMER => DM_STAT_EXP.se_itimer,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
@ -392,16 +402,16 @@ begin
LWIDTH => LED'length,
DCWIDTH => 2)
port map (
SEL_LED => SWI(3),
SEL_DSP => SWI(5 downto 4),
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_DP => DM_STAT_DP,
ABCLKDIV => ABCLKDIV,
DISPREG => DISPREG,
LED => LED,
DSP_DAT => DSP_DAT
SEL_LED => SWI(3),
SEL_DSP => SWI(5 downto 4),
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_EXP => DM_STAT_EXP,
ABCLKDIV => ABCLKDIV,
DISPREG => DISPREG,
LED => LED,
DSP_DAT => DSP_DAT
);
HIO : sn_humanio_rbus -- hio manager -----------------------

90
rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vhd
View File

@ -1,4 +1,4 @@
-- $Id: sys_w11a_c7.vhd 1045 2018-09-15 15:20:57Z mueller $
-- $Id: sys_w11a_c7.vhd 1055 2018-10-12 17:53:52Z mueller $
--
-- Copyright 2017-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@ -34,7 +34,7 @@
-- Test bench: tb/tb_sys_w11a_c7
--
-- Target Devices: generic
-- Tool versions: viv 2018.2; ghdl 0.34
-- Tool versions: viv 2017.2-2018.2; ghdl 0.34
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic
@ -45,6 +45,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 1.2 use DM_STAT_EXP
-- 2017-06-27 918 1.1.1 use 16 kB cache (all BRAM's used up)
-- 2017-06-25 916 1.1 add bram_memctl for 672 kB total memory
-- 2017-06-24 914 1.0 Initial version (derived from sys_w11a_n4)
@ -123,13 +124,13 @@ architecture syn of sys_w11a_c7 is
signal GRESET : slbit := '0'; -- general reset (from rbus)
signal CRESET : slbit := '0'; -- cpu reset (from cp)
signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
signal ITIMER : slbit := '0';
signal PERFEXT : slv8 := (others=>'0');
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal CP_STAT : cp_stat_type := cp_stat_init;
signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;
signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init;
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
@ -283,33 +284,42 @@ begin
SER_MONI => SER_MONI
);
PERFEXT(0) <= '0';
PERFEXT(1) <= '0';
PERFEXT(2) <= '0';
PERFEXT(3) <= '0';
PERFEXT(4) <= '0';
PERFEXT(5) <= '0';
PERFEXT(6) <= '0';
PERFEXT(7) <= CE_USEC;
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
ITIMER => ITIMER,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_DP => DM_STAT_DP
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
PERFEXT => PERFEXT,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_EXP => DM_STAT_EXP
);
@ -320,7 +330,7 @@ begin
CE_MSEC => CE_MSEC,
RESET => GRESET,
BRESET => BRESET,
ITIMER => ITIMER,
ITIMER => DM_STAT_EXP.se_itimer,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
@ -430,16 +440,16 @@ begin
LWIDTH => ELED'length,
DCWIDTH => 3)
port map (
SEL_LED => ESWI(3),
SEL_DSP => ESWI(5 downto 4),
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_DP => DM_STAT_DP,
ABCLKDIV => ABCLKDIV,
DISPREG => DISPREG,
LED => ELED,
DSP_DAT => EDSP_DAT
SEL_LED => ESWI(3),
SEL_DSP => ESWI(5 downto 4),
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_EXP => DM_STAT_EXP,
ABCLKDIV => ABCLKDIV,
DISPREG => DISPREG,
LED => ELED,
DSP_DAT => EDSP_DAT
);
EHIO : sn_humanio_emu_rbus -- emulated hio ----------------------

88
rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd
View File

@ -1,4 +1,4 @@
-- $Id: sys_w11a_n2.vhd 1045 2018-09-15 15:20:57Z mueller $
-- $Id: sys_w11a_n2.vhd 1055 2018-10-12 17:53:52Z mueller $
--
-- Copyright 2010-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@ -71,6 +71,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 2.3 use DM_STAT_EXP
-- 2017-04-30 888 2.2 use SWI(7:6) to allow fx2 debug via LEDs
-- 2016-03-19 748 2.1.1 define rlink SYSID
-- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul
@ -274,14 +275,14 @@ architecture syn of sys_w11a_n2 is
signal GRESET : slbit := '0'; -- general reset (from rbus)
signal CRESET : slbit := '0'; -- cpu reset (from cp)
signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
signal ITIMER : slbit := '0';
signal PERFEXT : slv8 := (others=>'0');
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal CP_STAT : cp_stat_type := cp_stat_init;
signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;
signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init;
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
@ -399,33 +400,42 @@ begin
IO_FX2_DATA => IO_FX2_DATA
);
PERFEXT(0) <= '0';
PERFEXT(1) <= '0';
PERFEXT(2) <= '0';
PERFEXT(3) <= '0';
PERFEXT(4) <= '0';
PERFEXT(5) <= '0';
PERFEXT(6) <= '0';
PERFEXT(7) <= CE_USEC;
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
ITIMER => ITIMER,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_DP => DM_STAT_DP
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
PERFEXT => PERFEXT,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_EXP => DM_STAT_EXP
);
IBDR_SYS : ibdr_maxisys -- IO system -------------------------
@ -435,7 +445,7 @@ begin
CE_MSEC => CE_MSEC,
RESET => GRESET,
BRESET => BRESET,
ITIMER => ITIMER,
ITIMER => DM_STAT_EXP.se_itimer,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
@ -500,16 +510,16 @@ begin
LWIDTH => LED'length,
DCWIDTH => 2)
port map (
SEL_LED => SWI(3),
SEL_DSP => SWI(5 downto 4),
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_DP => DM_STAT_DP,
ABCLKDIV => ABCLKDIV,
DISPREG => DISPREG,
LED => LED70,
DSP_DAT => DSP_DAT
SEL_LED => SWI(3),
SEL_DSP => SWI(5 downto 4),
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_EXP => DM_STAT_EXP,
ABCLKDIV => ABCLKDIV,
DISPREG => DISPREG,
LED => LED70,
DSP_DAT => DSP_DAT
);
proc_fx2leds: process (SWI, LED70, FX2_MONI) -- hio LED handler ------------

88
rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd
View File

@ -1,4 +1,4 @@
-- $Id: sys_w11a_n3.vhd 1045 2018-09-15 15:20:57Z mueller $
-- $Id: sys_w11a_n3.vhd 1055 2018-10-12 17:53:52Z mueller $
--
-- Copyright 2011-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@ -56,6 +56,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 2.3 use DM_STAT_EXP
-- 2017-04-30 888 2.2 use SWI(7:6) to allow fx2 debug via LEDs
-- 2016-03-19 748 2.1.1 define rlink SYSID
-- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul
@ -234,14 +235,14 @@ architecture syn of sys_w11a_n3 is
signal GRESET : slbit := '0'; -- general reset (from rbus)
signal CRESET : slbit := '0'; -- cpu reset (from cp)
signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
signal ITIMER : slbit := '0';
signal PERFEXT : slv8 := (others=>'0');
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal CP_STAT : cp_stat_type := cp_stat_init;
signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;
signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init;
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
@ -371,33 +372,42 @@ begin
IO_FX2_DATA => IO_FX2_DATA
);
PERFEXT(0) <= '0';
PERFEXT(1) <= '0';
PERFEXT(2) <= '0';
PERFEXT(3) <= '0';
PERFEXT(4) <= '0';
PERFEXT(5) <= '0';
PERFEXT(6) <= '0';
PERFEXT(7) <= CE_USEC;
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
ITIMER => ITIMER,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_DP => DM_STAT_DP
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
PERFEXT => PERFEXT,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_EXP => DM_STAT_EXP
);
IBDR_SYS : ibdr_maxisys -- IO system -------------------------
@ -407,7 +417,7 @@ begin
CE_MSEC => CE_MSEC,
RESET => GRESET,
BRESET => BRESET,
ITIMER => ITIMER,
ITIMER => DM_STAT_EXP.se_itimer,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
@ -473,16 +483,16 @@ begin
LWIDTH => LED'length,
DCWIDTH => 2)
port map (
SEL_LED => SWI(3),
SEL_DSP => SWI(5 downto 4),
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_DP => DM_STAT_DP,
ABCLKDIV => ABCLKDIV,
DISPREG => DISPREG,
LED => LED70,
DSP_DAT => DSP_DAT
SEL_LED => SWI(3),
SEL_DSP => SWI(5 downto 4),
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_EXP => DM_STAT_EXP,
ABCLKDIV => ABCLKDIV,
DISPREG => DISPREG,
LED => LED70,
DSP_DAT => DSP_DAT
);
proc_fx2leds: process (SWI, LED70, FX2_MONI) -- hio LED handler ------------

88
rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vhd
View File

@ -1,4 +1,4 @@
-- $Id: sys_w11a_n4.vhd 1045 2018-09-15 15:20:57Z mueller $
-- $Id: sys_w11a_n4.vhd 1055 2018-10-12 17:53:52Z mueller $
--
-- Copyright 2013-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@ -53,6 +53,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 2.4 use DM_STAT_EXP
-- 2016-04-02 758 2.3.1 add rbd_usracc (bitfile+jtag timestamp access)
-- 2016-03-28 755 2.3 use serport_2clock2
-- 2016-03-19 748 2.2.1 define rlink SYSID
@ -199,14 +200,14 @@ architecture syn of sys_w11a_n4 is
signal GRESET : slbit := '0'; -- general reset (from rbus)
signal CRESET : slbit := '0'; -- cpu reset (from cp)
signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
signal ITIMER : slbit := '0';
signal PERFEXT : slv8 := (others=>'0');
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal CP_STAT : cp_stat_type := cp_stat_init;
signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;
signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init;
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
@ -347,33 +348,42 @@ begin
SER_MONI => SER_MONI
);
PERFEXT(0) <= '0';
PERFEXT(1) <= '0';
PERFEXT(2) <= '0';
PERFEXT(3) <= '0';
PERFEXT(4) <= '0';
PERFEXT(5) <= '0';
PERFEXT(6) <= '0';
PERFEXT(7) <= CE_USEC;
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
ITIMER => ITIMER,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_DP => DM_STAT_DP
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
PERFEXT => PERFEXT,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_EXP => DM_STAT_EXP
);
IBDR_SYS : ibdr_maxisys -- IO system -------------------------
@ -383,7 +393,7 @@ begin
CE_MSEC => CE_MSEC,
RESET => GRESET,
BRESET => BRESET,
ITIMER => ITIMER,
ITIMER => DM_STAT_EXP.se_itimer,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
@ -440,16 +450,16 @@ begin
LWIDTH => LED'length,
DCWIDTH => 3)
port map (
SEL_LED => SWI(3),
SEL_DSP => SWI(5 downto 4),
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_DP => DM_STAT_DP,
ABCLKDIV => ABCLKDIV,
DISPREG => DISPREG,
LED => LED,
DSP_DAT => DSP_DAT
SEL_LED => SWI(3),
SEL_DSP => SWI(5 downto 4),
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_EXP => DM_STAT_EXP,
ABCLKDIV => ABCLKDIV,
DISPREG => DISPREG,
LED => LED,
DSP_DAT => DSP_DAT
);
HIO : sn_humanio_rbus -- hio manager -----------------------

88
rtl/sys_gen/w11a/nexys4d_bram/sys_w11a_br_n4d.vhd
View File

@ -1,4 +1,4 @@
-- $Id: sys_w11a_br_n4d.vhd 1047 2018-09-16 11:08:41Z mueller $
-- $Id: sys_w11a_br_n4d.vhd 1055 2018-10-12 17:53:52Z mueller $
--
-- Copyright 2017-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@ -42,6 +42,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 1.1 use DM_STAT_EXP
-- 2017-01-04 838 1.0 Initial version (derived from sys_w11a_br_n4)
------------------------------------------------------------------------------
--
@ -167,14 +168,14 @@ architecture syn of sys_w11a_br_n4d is
signal GRESET : slbit := '0'; -- general reset (from rbus)
signal CRESET : slbit := '0'; -- cpu reset (from cp)
signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
signal ITIMER : slbit := '0';
signal PERFEXT : slv8 := (others=>'0');
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal CP_STAT : cp_stat_type := cp_stat_init;
signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;
signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init;
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
@ -307,33 +308,42 @@ begin
SER_MONI => SER_MONI
);
PERFEXT(0) <= '0';
PERFEXT(1) <= '0';
PERFEXT(2) <= '0';
PERFEXT(3) <= '0';
PERFEXT(4) <= '0';
PERFEXT(5) <= '0';
PERFEXT(6) <= '0';
PERFEXT(7) <= CE_USEC;
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
ITIMER => ITIMER,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_DP => DM_STAT_DP
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
PERFEXT => PERFEXT,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_EXP => DM_STAT_EXP
);
IBDR_SYS : ibdr_maxisys -- IO system -------------------------
@ -343,7 +353,7 @@ begin
CE_MSEC => CE_MSEC,
RESET => GRESET,
BRESET => BRESET,
ITIMER => ITIMER,
ITIMER => DM_STAT_EXP.se_itimer,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
@ -387,16 +397,16 @@ begin
LWIDTH => LED'length,
DCWIDTH => 3)
port map (
SEL_LED => SWI(3),
SEL_DSP => SWI(5 downto 4),
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_DP => DM_STAT_DP,
ABCLKDIV => ABCLKDIV,
DISPREG => DISPREG,
LED => LED,
DSP_DAT => DSP_DAT
SEL_LED => SWI(3),
SEL_DSP => SWI(5 downto 4),
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_EXP => DM_STAT_EXP,
ABCLKDIV => ABCLKDIV,
DISPREG => DISPREG,
LED => LED,
DSP_DAT => DSP_DAT
);
HIO : sn_humanio_rbus -- hio manager -----------------------

88
rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd
View File

@ -1,4 +1,4 @@
-- $Id: sys_w11a_s3.vhd 1045 2018-09-15 15:20:57Z mueller $
-- $Id: sys_w11a_s3.vhd 1055 2018-10-12 17:53:52Z mueller $
--
-- Copyright 2007-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@ -77,6 +77,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 2.2 use DM_STAT_EXP
-- 2016-03-19 748 2.1.1 define rlink SYSID
-- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul
-- 2015-05-02 673 2.0 use pdp11_sys70 and pdp11_hio70; now in std form
@ -251,14 +252,14 @@ architecture syn of sys_w11a_s3 is
signal GRESET : slbit := '0'; -- general reset (from rbus)
signal CRESET : slbit := '0'; -- cpu reset (from cp)
signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
signal ITIMER : slbit := '0';
signal PERFEXT : slv8 := (others=>'0');
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal CP_STAT : cp_stat_type := cp_stat_init;
signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;
signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init;
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
@ -349,33 +350,42 @@ begin
SER_MONI => SER_MONI
);
PERFEXT(0) <= '0';
PERFEXT(1) <= '0';
PERFEXT(2) <= '0';
PERFEXT(3) <= '0';
PERFEXT(4) <= '0';
PERFEXT(5) <= '0';
PERFEXT(6) <= '0';
PERFEXT(7) <= CE_USEC;
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
ITIMER => ITIMER,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_DP => DM_STAT_DP
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
PERFEXT => PERFEXT,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_EXP => DM_STAT_EXP
);
IBDR_SYS : ibdr_maxisys -- IO system -------------------------
@ -385,7 +395,7 @@ begin
CE_MSEC => CE_MSEC,
RESET => GRESET,
BRESET => BRESET,
ITIMER => ITIMER,
ITIMER => DM_STAT_EXP.se_itimer,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
@ -431,16 +441,16 @@ begin
LWIDTH => LED'length,
DCWIDTH => 2)
port map (
SEL_LED => SWI(3),
SEL_DSP => SWI(5 downto 4),
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_DP => DM_STAT_DP,
ABCLKDIV => ABCLKDIV,
DISPREG => DISPREG,
LED => LED,
DSP_DAT => DSP_DAT
SEL_LED => SWI(3),
SEL_DSP => SWI(5 downto 4),
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_EXP => DM_STAT_EXP,
ABCLKDIV => ABCLKDIV,
DISPREG => DISPREG,
LED => LED,
DSP_DAT => DSP_DAT
);
HIO : sn_humanio_rbus -- hio manager -----------------------

40
rtl/w11a/pdp11.vhd
View File

@ -1,4 +1,4 @@
-- $Id: pdp11.vhd 1053 2018-10-06 20:34:52Z mueller $
-- $Id: pdp11.vhd 1055 2018-10-12 17:53:52Z mueller $
--
-- Copyright 2006-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@ -20,6 +20,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 1.6.10 add DM_STAT_EXP; add DM_STAT_SE.itimer
-- 2018-10-05 1053 1.6.9 drop DM_STAT_SY; add DM_STAT_CA, use in pdp11_cache
-- add DM_STAT_SE.pcload
-- 2018-09-29 1051 1.6.8 add pdp11_dmpcnt; add DM_STAT_SE.(cpbusy,idec)
@ -607,11 +608,12 @@ package pdp11 is
-- debug and monitoring port definitions -------------------------------------
type dm_stat_se_type is record -- debug and monitor status - sequencer
idle : slbit; -- sequencer ideling
idle : slbit; -- sequencer ideling (for pdp11_dcmon)
cpbusy : slbit; -- in cp states
istart : slbit; -- instruction start
idec : slbit; -- instruction decode
idec : slbit; -- instruction decode (for ibd_kw11p)
idone : slbit; -- instruction done
itimer : slbit; -- instruction timer (for ibdr_rhrp)
pcload : slbit; -- PC loaded (flow change)
vfetch : slbit; -- vector fetch
snum : slv8; -- current state number
@ -619,7 +621,8 @@ package pdp11 is
constant dm_stat_se_init : dm_stat_se_type := (
'0','0', -- idle,cpbusy
'0','0','0','0','0', -- istart,idec,idone,pcload,vfetch
'0','0','0','0', -- istart,idec,idone,itimer
'0','0', -- pcload,vfetch
(others=>'0') -- snum
);
@ -713,6 +716,21 @@ package pdp11 is
constant dm_stat_ca_init : dm_stat_ca_type := (
'0','0','0','0', -- rd,wr,rdhit,wrhit
'0','0','0','0' -- rdmem,wrmem,rdwait,wrwait
);
type dm_stat_exp_type is record -- debug and monitor - sys70 export
dp_pc : slv16; -- DM_STAT_DP: pc
dp_psw : psw_type; -- DM_STAT_DP: psw
dp_dsrc : slv16; -- DM_STAT_DP: dsrc register
se_idec : slbit; -- DM_STAT_SE: instruction decode
se_itimer : slbit; -- DM_STAT_SE: instruction timer
end record dm_stat_exp_type;
constant dm_stat_exp_init : dm_stat_exp_type := (
(others=>'0'), -- dp_pc
psw_init, -- dp_psw
(others=>'0'), -- dp_dsrc
'0','0' -- se_idec,se_itimer
);
-- rbus interface definitions ------------------------------------------------
@ -1022,7 +1040,6 @@ component pdp11_sequencer is -- cpu sequencer
CP_STAT : out cp_stat_type; -- console port status
ESUSP_O : out slbit; -- external suspend output
ESUSP_I : in slbit; -- external suspend input
ITIMER : out slbit; -- instruction timer
HBPT : in slbit; -- hardware bpt
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
@ -1109,7 +1126,6 @@ component pdp11_core is -- full processor core
CP_DOUT : out slv16; -- console data out
ESUSP_O : out slbit; -- external suspend output
ESUSP_I : in slbit; -- external suspend input
ITIMER : out slbit; -- instruction timer
HBPT : in slbit; -- hardware bpt
EI_PRI : in slv3; -- external interrupt priority
EI_VECT : in slv9_2; -- external interrupt vector
@ -1210,7 +1226,7 @@ component pdp11_statleds is -- status leds
MEM_ACT_R : in slbit; -- memory active read
MEM_ACT_W : in slbit; -- memory active write
CP_STAT : in cp_stat_type; -- console port status
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath
DM_STAT_EXP : in dm_stat_exp_type; -- debug and monitor - exports
STATLEDS : out slv8 -- 8 bit CPU status
);
end component;
@ -1221,7 +1237,7 @@ component pdp11_ledmux is -- hio led mux
port (
SEL : in slbit; -- select (0=stat;1=dr)
STATLEDS : in slv8; -- 8 bit CPU status
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath
DM_STAT_EXP : in dm_stat_exp_type; -- debug and monitor - exports
LED : out slv(LWIDTH-1 downto 0) -- hio leds
);
end component;
@ -1232,7 +1248,7 @@ component pdp11_dspmux is -- hio dsp mux
port (
SEL : in slv2; -- select
ABCLKDIV : in slv16; -- serport clock divider
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath
DM_STAT_EXP : in dm_stat_exp_type; -- debug and monitor - exports
DISPREG : in slv16; -- display register
DSP_DAT : out slv(4*(2**DCWIDTH)-1 downto 0) -- display data
);
@ -1273,7 +1289,7 @@ component pdp11_sys70 is -- 11/70 system 1 core +rbus,debug,cache
EI_PRI : in slv3; -- external interrupt priority
EI_VECT : in slv9_2; -- external interrupt vector
EI_ACKM : out slbit; -- external interrupt acknowledge
ITIMER : out slbit; -- instruction timer
PERFEXT : in slv8; -- cpu external perf counter signals
IB_MREQ : out ib_mreq_type; -- ibus request (master)
IB_SRES : in ib_sres_type; -- ibus response (from IO system)
MEM_REQ : out slbit; -- memory: request
@ -1284,7 +1300,7 @@ component pdp11_sys70 is -- 11/70 system 1 core +rbus,debug,cache
MEM_BE : out slv4; -- memory: byte enable
MEM_DI : out slv32; -- memory: data in (memory view)
MEM_DO : in slv32; -- memory: data out (memory view)
DM_STAT_DP : out dm_stat_dp_type -- debug and monitor status - dpath
DM_STAT_EXP : out dm_stat_exp_type -- debug and monitor - sys70 exports
);
end component;
@ -1298,7 +1314,7 @@ component pdp11_hio70 is -- hio led and dsp for sys70
MEM_ACT_R : in slbit; -- memory active read
MEM_ACT_W : in slbit; -- memory active write
CP_STAT : in cp_stat_type; -- console port status
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status
DM_STAT_EXP : in dm_stat_exp_type; -- debug and monitor - exports
ABCLKDIV : in slv16; -- serport clock divider
DISPREG : in slv16; -- display register
LED : out slv(LWIDTH-1 downto 0); -- hio leds

9
rtl/w11a/pdp11_core.vhd
View File

@ -1,6 +1,6 @@
-- $Id: pdp11_core.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: pdp11_core.vhd 1055 2018-10-12 17:53:52Z mueller $
--
-- Copyright 2006-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2006-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@ -27,9 +27,10 @@
-- tb/tb_rlink_tba_pdp11core
--
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.2; ghdl 0.18-0.33
-- Tool versions: ise 8.2-14.7; viv 2014.4-2018.2; ghdl 0.18-0.34
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 1.4.4 drop ITIMER, now routed via DM_STAT_SE.itimer
-- 2016-10-03 812 1.4.3 drop SNUM signal, not used anymore
-- 2015-07-19 702 1.4.2 add DM_STAT_SE port; re-arrange DM_STAT_CO usage
-- 2015-07-05 697 1.4.1 wire istart,istop,cpustep to DM_STAT_CO
@ -77,7 +78,6 @@ entity pdp11_core is -- full processor core
CP_DOUT : out slv16; -- console data out
ESUSP_O : out slbit; -- external suspend output
ESUSP_I : in slbit; -- external suspend input
ITIMER : out slbit; -- instruction timer
HBPT : in slbit; -- hardware bpt
EI_PRI : in slv3; -- external interrupt priority
EI_VECT : in slv9_2; -- external interrupt vector
@ -197,7 +197,6 @@ begin
CP_STAT => CP_STAT_L,
ESUSP_O => ESUSP_O,
ESUSP_I => ESUSP_I,
ITIMER => ITIMER,
HBPT => HBPT,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_SEQ,

27
rtl/w11a/pdp11_dspmux.vhd
View File

@ -1,6 +1,6 @@
-- $Id: pdp11_dspmux.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: pdp11_dspmux.vhd 1055 2018-10-12 17:53:52Z mueller $
--
-- Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2015-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@ -18,27 +18,28 @@
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2014.4; ghdl 0.31
-- Tool versions: ise 14.7; viv 2018.2; ghdl 0.31-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 1.1 use DM_STAT_EXP instead of DM_STAT_DP
-- 2015-02-22 650 1.0 Initial version
-- 2015-02-21 649 0.1 First draft
------------------------------------------------------------------------------
-- selects display data
-- 4 Digit Displays
-- SEL(1:0) 00 ABCLKDIV
-- 01 DM_STAT_DP.pc
-- 01 DM_STAT_EXP.dp_pc
-- 10 DISPREG
-- 11 DM_STAT_DP.dsrc
-- 11 DM_STAT_EXP.dp_dsrc
--
-- 8 Digit Displays
-- SEL(1) select DSP(7:4)
-- 0 ABCLKDIV
-- 1 DM_STAT_DP.pc
-- 1 DM_STAT_EXP.dp_pc
-- SEL(0) select DSP(7:4)
-- 0 DISPREG
-- 1 DM_STAT_DP.dsrc
-- 1 DM_STAT_EXP.dp_dsrc
--
library ieee;
@ -56,7 +57,7 @@ entity pdp11_dspmux is -- hio dsp mux
port (
SEL : in slv2; -- select
ABCLKDIV : in slv16; -- serport clock divider
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath
DM_STAT_EXP : in dm_stat_exp_type; -- debug and monitor - exports
DISPREG : in slv16; -- display register
DSP_DAT : out slv(4*(2**DCWIDTH)-1 downto 0) -- display data
);
@ -73,7 +74,7 @@ begin
report "assert(DCWIDTH=2 or DCWIDTH=3): unsupported DCWIDTH"
severity failure;
proc_mux: process (SEL, ABCLKDIV, DM_STAT_DP, DISPREG)
proc_mux: process (SEL, ABCLKDIV, DM_STAT_EXP, DISPREG)
variable idat : slv(4*(2**DCWIDTH)-1 downto 0) := (others=>'0');
begin
idat := (others=>'0');
@ -84,11 +85,11 @@ begin
when "00" =>
idat(dspdat_lsb) := ABCLKDIV;
when "01" =>
idat(dspdat_lsb) := DM_STAT_DP.pc;
idat(dspdat_lsb) := DM_STAT_EXP.dp_pc;
when "10" =>
idat(dspdat_lsb) := DISPREG;
when "11" =>
idat(dspdat_lsb) := DM_STAT_DP.dsrc;
idat(dspdat_lsb) := DM_STAT_EXP.dp_dsrc;
when others => null;
end case;
@ -97,13 +98,13 @@ begin
if SEL(1) = '0' then
idat(dspdat_msb) := ABCLKDIV;
else
idat(dspdat_msb) := DM_STAT_DP.pc;
idat(dspdat_msb) := DM_STAT_EXP.dp_pc;
end if;
if SEL(0) = '0' then
idat(dspdat_lsb) := DISPREG;
else
idat(dspdat_lsb) := DM_STAT_DP.dsrc;
idat(dspdat_lsb) := DM_STAT_EXP.dp_dsrc;
end if;
end if;

37
rtl/w11a/pdp11_hio70.vhd
View File

@ -1,6 +1,6 @@
-- $Id: pdp11_hio70.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: pdp11_hio70.vhd 1055 2018-10-12 17:53:52Z mueller $
--
-- Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2015-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@ -20,10 +20,11 @@
-- pdp11_dspmux
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2014.4-2015.4; ghdl 0.31
-- Tool versions: ise 14.7; viv 2014.4-2018.2; ghdl 0.31-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 1.1 use DM_STAT_EXP instead of DM_STAT_DP
-- 2015-05-01 672 1.0 Initial version (extracted from sys_w11a_*)
------------------------------------------------------------------------------
@ -46,7 +47,7 @@ entity pdp11_hio70 is -- hio led and dsp for sys70
MEM_ACT_R : in slbit; -- memory active read
MEM_ACT_W : in slbit; -- memory active write
CP_STAT : in cp_stat_type; -- console port status
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status
DM_STAT_EXP : in dm_stat_exp_type; -- debug and monitor - exports
ABCLKDIV : in slv16; -- serport clock divider
DISPREG : in slv16; -- display register
LED : out slv(LWIDTH-1 downto 0); -- hio leds
@ -62,32 +63,32 @@ begin
LED_CPU : pdp11_statleds
port map (
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_DP => DM_STAT_DP,
STATLEDS => STATLEDS
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_EXP => DM_STAT_EXP,
STATLEDS => STATLEDS
);
LED_MUX : pdp11_ledmux
generic map (
LWIDTH => LWIDTH)
port map (
SEL => SEL_LED,
STATLEDS => STATLEDS,
DM_STAT_DP => DM_STAT_DP,
LED => LED
SEL => SEL_LED,
STATLEDS => STATLEDS,
DM_STAT_EXP => DM_STAT_EXP,
LED => LED
);
DSP_MUX : pdp11_dspmux
generic map (
DCWIDTH => DCWIDTH)
port map (
SEL => SEL_DSP,
ABCLKDIV => ABCLKDIV,
DM_STAT_DP => DM_STAT_DP,
DISPREG => DISPREG,
DSP_DAT => DSP_DAT
SEL => SEL_DSP,
ABCLKDIV => ABCLKDIV,
DM_STAT_EXP => DM_STAT_EXP,
DISPREG => DISPREG,
DSP_DAT => DSP_DAT
);
end syn;

15
rtl/w11a/pdp11_ledmux.vhd
View File

@ -1,6 +1,6 @@
-- $Id: pdp11_ledmux.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: pdp11_ledmux.vhd 1055 2018-10-12 17:53:52Z mueller $
--
-- Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2015-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@ -18,10 +18,11 @@
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2014.4; ghdl 0.31
-- Tool versions: ise 14.7; viv 2018.2; ghdl 0.31-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 1.1 use DM_STAT_EXP instead of DM_STAT_DP
-- 2015-02-27 652 1.0 Initial version
-- 2015-02-20 649 0.1 First draft
------------------------------------------------------------------------------
@ -41,7 +42,7 @@ entity pdp11_ledmux is -- hio led mux
port (
SEL : in slbit; -- select (0=stat;1=dr)
STATLEDS : in slv8; -- 8 bit CPU status
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath
DM_STAT_EXP : in dm_stat_exp_type; -- debug and monitor - exports
LED : out slv(LWIDTH-1 downto 0) -- hio leds
);
end pdp11_ledmux;
@ -54,7 +55,7 @@ begin
report "assert(LWIDTH=8 or LWIDTH=16): unsupported LWIDTH"
severity failure;
proc_mux: process (SEL, STATLEDS, DM_STAT_DP.dsrc)
proc_mux: process (SEL, STATLEDS, DM_STAT_EXP)
variable iled : slv(LWIDTH-1 downto 0) := (others=>'0');
begin
iled := (others=>'0');
@ -63,9 +64,9 @@ begin
iled(STATLEDS'range) := STATLEDS;
else
if LWIDTH=8 then
iled := DM_STAT_DP.dsrc(11 downto 4); --take middle part
iled := DM_STAT_EXP.dp_dsrc(11 downto 4); --take middle part
else
iled := DM_STAT_DP.dsrc(iled'range);
iled := DM_STAT_EXP.dp_dsrc(iled'range);
end if;
end if;

6
rtl/w11a/pdp11_sequencer.vhd
View File

@ -1,4 +1,4 @@
-- $Id: pdp11_sequencer.vhd 1053 2018-10-06 20:34:52Z mueller $
-- $Id: pdp11_sequencer.vhd 1055 2018-10-12 17:53:52Z mueller $
--
-- Copyright 2006-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@ -22,6 +22,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 1.6.11 drop ITIMER, use DM_STAT_SE.itimer
-- 2018-10-06 1053 1.6.10 add DM_STAT_SE.(cpbusy,idec,pcload)
-- 2017-04-23 885 1.6.9 not sys_conf_dmscnt: set SNUM from state category;
-- change waitsusp logic; add WAIT to idm_idone
@ -109,7 +110,6 @@ entity pdp11_sequencer is -- CPU sequencer
CP_STAT : out cp_stat_type; -- console port status
ESUSP_O : out slbit; -- external suspend output
ESUSP_I : in slbit; -- external suspend input
ITIMER : out slbit; -- instruction timer
HBPT : in slbit; -- hardware bpt
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
@ -2420,7 +2420,6 @@ begin
CRESET <= R_STATUS.creset;
BRESET <= R_STATUS.breset;
ESUSP_O <= R_STATUS.suspint; -- FIXME_code: handle masking later
ITIMER <= R_STATUS.itimer;
DP_CNTL <= ndpcntl;
VM_CNTL <= nvmcntl;
@ -2435,6 +2434,7 @@ begin
DM_STAT_SE.istart <= nmmumoni.istart;
DM_STAT_SE.idec <= idm_idec;
DM_STAT_SE.idone <= idm_idone;
DM_STAT_SE.itimer <= R_STATUS.itimer;
DM_STAT_SE.pcload <= idm_pcload;
DM_STAT_SE.vfetch <= idm_vfetch;

15
rtl/w11a/pdp11_statleds.vhd
View File

@ -1,6 +1,6 @@
-- $Id: pdp11_statleds.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: pdp11_statleds.vhd 1055 2018-10-12 17:53:52Z mueller $
--
-- Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2015-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@ -18,10 +18,11 @@
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2014.4; ghdl 0.31
-- Tool versions: ise 14.7; viv 2018.2; ghdl 0.31-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 1.1 use DM_STAT_EXP instead of DM_STAT_DP
-- 2015-02-20 649 1.0 Initial version
------------------------------------------------------------------------------
-- LED (7) MEM_ACT_W
@ -51,7 +52,7 @@ entity pdp11_statleds is -- status leds
MEM_ACT_R : in slbit; -- memory active read
MEM_ACT_W : in slbit; -- memory active write
CP_STAT : in cp_stat_type; -- console port status
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath
DM_STAT_EXP : in dm_stat_exp_type; -- debug and monitor - exports
STATLEDS : out slv8 -- 8 bit CPU status
);
end pdp11_statleds;
@ -60,7 +61,7 @@ architecture syn of pdp11_statleds is
begin
proc_led: process (MEM_ACT_W, MEM_ACT_R, CP_STAT, DM_STAT_DP.psw)
proc_led: process (MEM_ACT_W, MEM_ACT_R, CP_STAT, DM_STAT_EXP.dp_psw)
variable iled : slv8 := (others=>'0');
begin
iled := (others=>'0');
@ -69,11 +70,11 @@ begin
iled(6) := MEM_ACT_R;
iled(5) := CP_STAT.cmdbusy;
if CP_STAT.cpugo = '1' then
case DM_STAT_DP.psw.cmode is
case DM_STAT_EXP.dp_psw.cmode is
when c_psw_kmode =>
if CP_STAT.cpuwait = '1' then
iled(2) := '1';
elsif unsigned(DM_STAT_DP.psw.pri) = 0 then
elsif unsigned(DM_STAT_EXP.dp_psw.pri) = 0 then
iled(3) := '1';
else
iled(4) := '1';

53
rtl/w11a/pdp11_sys70.vhd
View File

@ -1,4 +1,4 @@
-- $Id: pdp11_sys70.vhd 1053 2018-10-06 20:34:52Z mueller $
-- $Id: pdp11_sys70.vhd 1055 2018-10-12 17:53:52Z mueller $
--
-- Copyright 2015-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@ -35,6 +35,8 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 1.3 drop ITIMER,DM_STAT_DP out ports, use DM_STAT_EXP
-- add PERFEXT in port
-- 2018-10-06 1053 1.2.3 drop DM_STAT_SY; add DM_STAT_CA; use _SE.pcload
-- 2018-09-29 1051 1.2.2 add pdp11_dmpcnt
-- 2017-04-22 884 1.2.1 pdp11_dmcmon: use SNUM and AWIDTH generics
@ -74,7 +76,7 @@ entity pdp11_sys70 is -- 11/70 system 1 core +rbus,debug,cache
EI_PRI : in slv3; -- external interrupt priority
EI_VECT : in slv9_2; -- external interrupt vector
EI_ACKM : out slbit; -- external interrupt acknowledge
ITIMER : out slbit; -- instruction timer
PERFEXT : in slv8; -- cpu external perf counter signals
IB_MREQ : out ib_mreq_type; -- ibus request (master)
IB_SRES : in ib_sres_type; -- ibus response
MEM_REQ : out slbit; -- memory: request
@ -85,7 +87,7 @@ entity pdp11_sys70 is -- 11/70 system 1 core +rbus,debug,cache
MEM_BE : out slv4; -- memory: byte enable
MEM_DI : out slv32; -- memory: data in (memory view)
MEM_DO : in slv32; -- memory: data out (memory view)
DM_STAT_DP : out dm_stat_dp_type -- debug and monitor status - dpath
DM_STAT_EXP : out dm_stat_exp_type -- debug and monitor - sys70 exports
);
end pdp11_sys70;
@ -121,7 +123,7 @@ architecture syn of pdp11_sys70 is
signal HBPT : slbit := '0';
signal DM_STAT_SE : dm_stat_se_type := dm_stat_se_init;
signal DM_STAT_DP_L : dm_stat_dp_type := dm_stat_dp_init;
signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;
signal DM_STAT_VM : dm_stat_vm_type := dm_stat_vm_init;
signal DM_STAT_CO : dm_stat_co_type := dm_stat_co_init;
signal DM_STAT_CA : dm_stat_ca_type := dm_stat_ca_init;
@ -166,7 +168,6 @@ begin
CP_DOUT => CP_DOUT,
ESUSP_O => open,
ESUSP_I => '0',
ITIMER => ITIMER,
HBPT => HBPT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
@ -178,7 +179,7 @@ begin
IB_MREQ_M => IB_MREQ_M,
IB_SRES_M => IB_SRES_M,
DM_STAT_SE => DM_STAT_SE,
DM_STAT_DP => DM_STAT_DP_L,
DM_STAT_DP => DM_STAT_DP,
DM_STAT_VM => DM_STAT_VM,
DM_STAT_CO => DM_STAT_CO
);
@ -251,7 +252,7 @@ begin
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_DMSCNT,
DM_STAT_SE => DM_STAT_SE,
DM_STAT_DP => DM_STAT_DP_L,
DM_STAT_DP => DM_STAT_DP,
DM_STAT_CO => DM_STAT_CO
);
end generate DMSCNT;
@ -269,7 +270,7 @@ begin
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_DMCMON,
DM_STAT_SE => DM_STAT_SE,
DM_STAT_DP => DM_STAT_DP_L,
DM_STAT_DP => DM_STAT_DP,
DM_STAT_VM => DM_STAT_VM,
DM_STAT_CO => DM_STAT_CO
);
@ -287,7 +288,7 @@ begin
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_DMHBPT,
DM_STAT_SE => DM_STAT_SE,
DM_STAT_DP => DM_STAT_DP_L,
DM_STAT_DP => DM_STAT_DP,
DM_STAT_VM => DM_STAT_VM,
DM_STAT_CO => DM_STAT_CO,
HBPT => HBPT
@ -297,9 +298,9 @@ begin
DMPCNT : if sys_conf_dmpcnt generate
signal PERFSIG : slv32 := (others=>'0');
begin
proc_sig: process (CP_STAT_L, DM_STAT_SE, DM_STAT_DP_L, DM_STAT_DP_L.psw,
proc_sig: process (CP_STAT_L, DM_STAT_SE, DM_STAT_DP, DM_STAT_DP.psw,
DM_STAT_CA, RB_MREQ, RB_SRES_L,
DM_STAT_VM.ibmreq, DM_STAT_VM.ibsres)
DM_STAT_VM.ibmreq, DM_STAT_VM.ibsres, PERFEXT)
variable isig : slv32 := (others=>'0');
begin
@ -308,11 +309,11 @@ begin
if DM_STAT_SE.cpbusy = '1' then
isig(0) := '1'; -- cpu_cpbusy
elsif CP_STAT_L.cpugo = '1' then
case DM_STAT_DP_L.psw.cmode is
case DM_STAT_DP.psw.cmode is
when c_psw_kmode =>
if CP_STAT_L.cpuwait = '1' then
isig(3) := '1'; -- cpu_km_wait
elsif unsigned(DM_STAT_DP_L.psw.pri) = 0 then
elsif unsigned(DM_STAT_DP.psw.pri) = 0 then
isig(2) := '1'; -- cpu_km_pri0
else
isig(1) := '1'; -- cpu_km_prix
@ -359,14 +360,14 @@ begin
end if;
isig(24) := '0'; -- ext_rdrhit
isig(25) := '0'; -- ext_wrrhit
isig(26) := '0'; -- ext_wrflush
isig(27) := '0'; -- ext_rlrdbusy
isig(28) := '0'; -- ext_rlrdback
isig(29) := '0'; -- ext_rlwrbusy
isig(30) := '0'; -- ext_rlwrback
isig(31) := '1'; -- usec (now clock)
isig(24) := PERFEXT(0); -- ext_rdrhit
isig(25) := PERFEXT(1); -- ext_wrrhit
isig(26) := PERFEXT(2); -- ext_wrflush
isig(27) := PERFEXT(3); -- ext_rlrdbusy
isig(28) := PERFEXT(4); -- ext_rlrdback
isig(29) := PERFEXT(5); -- ext_rlwrbusy
isig(30) := PERFEXT(6); -- ext_rlwrback
isig(31) := PERFEXT(7); -- ext_usec
PERFSIG <= isig;
end process proc_sig;
@ -378,7 +379,7 @@ begin
VERS => slv(to_unsigned(1, 8)), -- counter layout version
-- 33222222222211111111110000000000
-- 10987654321098765432109876543210
CENA => "10000000111111111111111111111111") -- counter enables
CENA => "11111111111111111111111111111111") -- counter enables
port map (
CLK => CLK,
RESET => RESET,
@ -411,7 +412,11 @@ begin
BRESET <= BRESET_L;
CP_STAT <= CP_STAT_L;
EI_ACKM <= EI_ACKM_L;
DM_STAT_DP <= DM_STAT_DP_L;
DM_STAT_EXP.dp_psw <= DM_STAT_DP.psw;
DM_STAT_EXP.dp_pc <= DM_STAT_DP.pc;
DM_STAT_EXP.dp_dsrc <= DM_STAT_DP.dsrc;
DM_STAT_EXP.se_idec <= DM_STAT_SE.idec;
DM_STAT_EXP.se_itimer <= DM_STAT_SE.itimer;
-- synthesis translate_off
@ -420,7 +425,7 @@ begin
ENAPIN => sbcntl_sbf_tmu)
port map (
CLK => CLK,
DM_STAT_DP => DM_STAT_DP_L,
DM_STAT_DP => DM_STAT_DP,
DM_STAT_VM => DM_STAT_VM,
DM_STAT_CO => DM_STAT_CO,
DM_STAT_CA => DM_STAT_CA

5
rtl/w11a/tb/tbd_pdp11core.vhd
View File

@ -1,4 +1,4 @@
-- $Id: tbd_pdp11core.vhd 1053 2018-10-06 20:34:52Z mueller $
-- $Id: tbd_pdp11core.vhd 1055 2018-10-12 17:53:52Z mueller $
--
-- Copyright 2007-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@ -41,6 +41,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 1.6.4 drop ITIMER from core
-- 2018-10-05 1053 1.6.3 use DM_STAT_CA instead of DM_STAT_SY
-- 2015-11-01 712 1.6.2 use sbcntl_sbf_tmu
-- 2015-07-03 697 1.6.1 adapt to new DM_STAT_(SY|VM)
@ -176,7 +177,6 @@ begin
CP_DOUT => CP_DOUT,
ESUSP_O => open, -- not tested
ESUSP_I => '0', -- dito
ITIMER => open, -- dito
HBPT => '0', -- dito
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
@ -186,6 +186,7 @@ begin
BRESET => BRESET,
IB_MREQ_M => IB_MREQ_M,
IB_SRES_M => IB_SRES_M,
DM_STAT_SE => open,
DM_STAT_DP => DM_STAT_DP,
DM_STAT_VM => DM_STAT_VM,
DM_STAT_CO => DM_STAT_CO

48
rtl/w11a/tb/tbd_tba_pdp11core.vhd
View File

@ -1,6 +1,6 @@
-- $Id: tbd_tba_pdp11core.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: tbd_tba_pdp11core.vhd 1055 2018-10-12 17:53:52Z mueller $
--
-- Copyright 2008-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2008-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@ -29,9 +29,10 @@
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
--
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.34
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 1.6.1 drop ITIMER from core
-- 2015-05-09 677 1.6 start/stop/suspend overhaul; reset overhaul
-- 2014-08-28 588 1.5.1 use new rlink v4 iface and 4 bit STAT
-- 2014-08-15 583 1.5 rb_mreq addr now 16 bit
@ -159,25 +160,28 @@ begin
W11A : pdp11_core
port map (
CLK => CLK,
RESET => GRESET,
CP_CNTL => CP_CNTL,
CP_ADDR => CP_ADDR,
CP_DIN => CP_DIN,
CP_STAT => CP_STAT,
CP_DOUT => CP_DOUT,
ESUSP_O => open,
ESUSP_I => '0',
ITIMER => open,
HBPT => '0',
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
EM_MREQ => EM_MREQ,
EM_SRES => EM_SRES,
BRESET => BRESET,
IB_MREQ_M => IB_MREQ,
IB_SRES_M => IB_SRES
CLK => CLK,
RESET => GRESET,
CP_CNTL => CP_CNTL,
CP_ADDR => CP_ADDR,
CP_DIN => CP_DIN,
CP_STAT => CP_STAT,
CP_DOUT => CP_DOUT,
ESUSP_O => open,
ESUSP_I => '0',
HBPT => '0',
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
EM_MREQ => EM_MREQ,
EM_SRES => EM_SRES,
BRESET => BRESET,
IB_MREQ_M => IB_MREQ,
IB_SRES_M => IB_SRES,
DM_STAT_SE => open,
DM_STAT_DP => open,
DM_STAT_VM => open,
DM_STAT_CO => open
);
MEM : pdp11_bram