From cb7b906089e2261b579d5c1fe4ba897f0f063f6c Mon Sep 17 00:00:00 2001 From: wfjm Date: Thu, 3 Jan 2019 09:15:07 +0100 Subject: [PATCH] Add memory tester for Arty and MIG - sys_tst_sram_arty: add system and tb - sramif_mig_arty: add SRAM to DDR via MIG adapter for arty - cdc_pulse: add clock domain crossing for a slowly changing value - cdc_vector_s0: add ENA port (now used in cdc_pulse) - tst_mig/util.tcl: test_rwait: add optional lena argument - viv_tools_build.tcl: downgrade SSN critical warnings to warnings --- .travis.yml | 2 +- Makefile | 5 +- doc/CHANGELOG.md | 9 +- rtl/bplib/README.md | 1 + rtl/bplib/arty/sramif_mig_arty.vbom | 13 + rtl/bplib/arty/sramif_mig_arty.vhd | 214 +++++++++ rtl/sys_gen/tst_mig/arty/sys_tst_mig_arty.vhd | 6 +- .../tst_mig/arty/sys_tst_mig_arty.vmfset | 4 +- rtl/sys_gen/tst_mig/tst_mig.vhd | 3 +- rtl/sys_gen/tst_sram/arty/Makefile | 25 + rtl/sys_gen/tst_sram/arty/sys_conf.vhd | 60 +++ .../tst_sram/arty/sys_tst_sram_arty.vbom | 29 ++ .../tst_sram/arty/sys_tst_sram_arty.vhd | 433 ++++++++++++++++++ .../tst_sram/arty/sys_tst_sram_arty.vmfset | 83 ++++ rtl/sys_gen/tst_sram/arty/tb/.gitignore | 2 + rtl/sys_gen/tst_sram/arty/tb/Makefile | 39 ++ rtl/sys_gen/tst_sram/arty/tb/sys_conf_sim.vhd | 57 +++ .../tst_sram/arty/tb/tb_tst_sram_arty.vbom | 9 + .../tst_sram/arty/tb/tb_tst_sram_arty.vhd | 35 ++ rtl/sys_gen/tst_sram/arty/tb/tbrun.yml | 18 + rtl/sys_gen/tst_sram/arty/tb/tbw.dat | 7 + rtl/sys_gen/tst_sram/tbrun.yml | 4 +- rtl/sys_gen/tst_sram/tst_sram.vhd | 3 +- rtl/vlib/cdclib/cdc_value.vbom | 7 + rtl/vlib/cdclib/cdc_value.vhd | 105 +++++ rtl/vlib/cdclib/cdc_vector_s0.vhd | 12 +- rtl/vlib/cdclib/cdc_vector_s0.xdc | 20 +- rtl/vlib/cdclib/cdclib.vhd | 11 +- tools/tcl/tst_mig/util.tcl | 68 +-- tools/vivado/viv_tools_build.tcl | 13 +- 30 files changed, 1238 insertions(+), 59 deletions(-) create mode 100644 rtl/bplib/arty/sramif_mig_arty.vbom create mode 100644 rtl/bplib/arty/sramif_mig_arty.vhd create mode 100644 rtl/sys_gen/tst_sram/arty/Makefile create mode 100644 rtl/sys_gen/tst_sram/arty/sys_conf.vhd create mode 100644 rtl/sys_gen/tst_sram/arty/sys_tst_sram_arty.vbom create mode 100644 rtl/sys_gen/tst_sram/arty/sys_tst_sram_arty.vhd create mode 100644 rtl/sys_gen/tst_sram/arty/sys_tst_sram_arty.vmfset create mode 100644 rtl/sys_gen/tst_sram/arty/tb/.gitignore create mode 100644 rtl/sys_gen/tst_sram/arty/tb/Makefile create mode 100644 rtl/sys_gen/tst_sram/arty/tb/sys_conf_sim.vhd create mode 100644 rtl/sys_gen/tst_sram/arty/tb/tb_tst_sram_arty.vbom create mode 100644 rtl/sys_gen/tst_sram/arty/tb/tb_tst_sram_arty.vhd create mode 100644 rtl/sys_gen/tst_sram/arty/tb/tbrun.yml create mode 100644 rtl/sys_gen/tst_sram/arty/tb/tbw.dat create mode 100644 rtl/vlib/cdclib/cdc_value.vbom create mode 100644 rtl/vlib/cdclib/cdc_value.vhd diff --git a/.travis.yml b/.travis.yml index 56636a5d..a607ef4b 100644 --- a/.travis.yml +++ b/.travis.yml @@ -75,9 +75,9 @@ script: -tag default,sys_tst_rlink,base \ -tag default,sys_tst_rlink_cuff,basefx2 \ -tag default,sys_tst_rlink_cuff,baseser \ + -tag default,sys_tst_mig,base \ -tag default,sys_tst_sram,base \ -tag default,sys_tst_sram,n4 \ - -tag default,sys_tst_mig,base \ -tag default,sys_w11a,stim1 \ -tag default,sys_w11a,n4 - tbfilt -all -sum -comp diff --git a/Makefile b/Makefile index a84007a0..e7e274b8 100644 --- a/Makefile +++ b/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 1100 2019-01-02 10:56:47Z mueller $ +# $Id: Makefile 1101 2019-01-02 21:22:37Z mueller $ # # 'Meta Makefile' for whole retro project # allows to make all synthesis targets @@ -6,6 +6,7 @@ # # Revision History: # Date Rev Version Comment +# 2019-01-02 1101 1.2.10 add tst_{mig,sram}/arty # 2018-10-12 1055 1.2.9 use setup_package_filt # 2017-06-28 918 1.2.8 add cmoda7 port for tst_rlink,tst_sram,w11a # 2017-05-01 891 1.2.7 add all_tcl to all; use njobihtm @@ -76,6 +77,7 @@ SYN_viv += rtl/sys_gen/w11a/nexys4 # Arty --------------------------------------- SYN_viv += rtl/sys_gen/tst_mig/arty SYN_viv += rtl/sys_gen/tst_rlink/arty +SYN_viv += rtl/sys_gen/tst_sram/arty SYN_viv += rtl/sys_gen/w11a/arty_bram # CmodA7 ------------------------------------- @@ -134,6 +136,7 @@ SIM_viv += rtl/sys_gen/w11a/nexys4/tb # Arty --------------------------------------- SIM_viv += rtl/sys_gen/tst_mig/arty/tb SIM_viv += rtl/sys_gen/tst_rlink/arty/tb +SIM_viv += rtl/sys_gen/tst_sram/arty/tb SIM_viv += rtl/sys_gen/w11a/arty_bram/tb # CmodA7 ------------------------------------- diff --git a/doc/CHANGELOG.md b/doc/CHANGELOG.md index 04573c9c..9ae0fec0 100644 --- a/doc/CHANGELOG.md +++ b/doc/CHANGELOG.md @@ -26,13 +26,16 @@ The full set of tests is only run for tagged releases. ### New features - new systems - - sys_tst_mig_arty design: a MIG tester + - sys_tst_mig_arty: low level MIG interface test + - sys_tst_sram_arty: memory test - new components - s7_cmt_sfs_2: dual-channel frequency synthesis MMCM/PLL wrapper - s7_cmt_1ce1ce2c: clocking block for 7-Series: 2 clk+CEs + 2 clk - cdc_signal_s1_as: clock domain crossing for a signal, 2 stage, asyn input + - cdc_pulse: clock domain crossing for a slowly changing value - migui_core_gsim: highly simplified MIG UI simulation model - sramif2migui_core: w11a SRAM to MIG UI interface core + - sramif_mig_arty: SRAM to DDR via MIG adapter for arty ### Changes - general @@ -41,9 +44,11 @@ The full set of tests is only run for tagged releases. - use xenial in matrix - Makefile: drop boost includes and libs (boost not used anymore) - tools changes - - viv_tools_build + - viv_tools_build.tcl - export log and rpt generated in OOC synthesis runs - downgrade SSN critical warnings to warnings +- firmware changes + - cdc_vector_s0: add ENA port (now used in cdc_pulse) ### Bug Fixes - nexys4d_pins.xdc: BUFFIX: Fix faulty IO voltage for I_SWI[8,9] diff --git a/rtl/bplib/README.md b/rtl/bplib/README.md index ad9c4526..2bc2f32b 100644 --- a/rtl/bplib/README.md +++ b/rtl/bplib/README.md @@ -4,6 +4,7 @@ and is organized in | Directory | Content | | --------- | ------- | | [arty](arty) | support for Digilent Arty board | +| [artys7](artys7) | support for Digilent Arty S7 board | | [atlys](atlys) | support for Digilent Atlys board | | [basys3](basys3) | support for Digilent Basys3 board | | [bpgen](bpgen) | interfaces for IO devices common on Digilent boards | diff --git a/rtl/bplib/arty/sramif_mig_arty.vbom b/rtl/bplib/arty/sramif_mig_arty.vbom new file mode 100644 index 00000000..eaaf533d --- /dev/null +++ b/rtl/bplib/arty/sramif_mig_arty.vbom @@ -0,0 +1,13 @@ +# libs +../../vlib/slvtypes.vhd +../../vlib/cdclib/cdclib.vhd +../mig/miglib.vbom +miglib_arty.vbom +# components +../mig/sramif2migui_core.vbom +../../vlib/cdclib/cdc_pulse.vbom +../../vlib/cdclib/cdc_value.vbom +@tcl:mig_arty.tcl +[ghdl,vsim]migui_arty_gsim.vbom +# design +sramif_mig_arty.vhd diff --git a/rtl/bplib/arty/sramif_mig_arty.vhd b/rtl/bplib/arty/sramif_mig_arty.vhd new file mode 100644 index 00000000..b7405289 --- /dev/null +++ b/rtl/bplib/arty/sramif_mig_arty.vhd @@ -0,0 +1,214 @@ +-- $Id: sramif_mig_arty.vhd 1101 2019-01-02 21:22:37Z mueller $ +-- +-- Copyright 2018-2019 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 3, or (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sramif_mig_arty - syn +-- Description: SRAM to DDR via MIG for arty +-- +-- Dependencies: bplib/mig/sramif2migui_core +-- cdclib/cdc_pulse +-- cdclib/cdc_value +-- migui_arty (generated core) +-- Test bench: tb_tst_sram_arty +-- Target Devices: arty board +-- Tool versions: viv 2017.2; ghdl 0.34 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2019-01-02 1101 1.0 Initial version +-- 2018-11-17 1071 0.1 First draft +-- +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.cdclib.all; +use work.miglib.all; +use work.miglib_arty.all; + +entity sramif_mig_arty is -- SRAM to DDR via MIG for arty + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + REQ : in slbit; -- request + WE : in slbit; -- write enable + BUSY : out slbit; -- controller busy + ACK_R : out slbit; -- acknowledge read + ACK_W : out slbit; -- acknowledge write + ACT_R : out slbit; -- signal active read + ACT_W : out slbit; -- signal active write + ADDR : in slv20; -- address (32 bit word address) + BE : in slv4; -- byte enable + DI : in slv32; -- data in (memory view) + DO : out slv32; -- data out (memory view) + CLKMIG : in slbit; -- sys clock for mig core + CLKREF : in slbit; -- ref clock for mig core + TEMP : in slv12; -- xadc die temp for mig core + MONI : out sramif2migui_moni_type;-- monitor signals + DDR3_DQ : inout slv16; -- dram: data in/out + DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p) + DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n) + DDR3_ADDR : out slv14; -- dram: address + DDR3_BA : out slv3; -- dram: bank address + DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low) + DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low) + DDR3_WE_N : out slbit; -- dram: write enable (act.low) + DDR3_RESET_N : out slbit; -- dram: reset (act.low) + DDR3_CK_P : out slv1; -- dram: clock (diff-p) + DDR3_CK_N : out slv1; -- dram: clock (diff-n) + DDR3_CKE : out slv1; -- dram: clock enable + DDR3_CS_N : out slv1; -- dram: chip select (act.low) + DDR3_DM : out slv2; -- dram: data input mask + DDR3_ODT : out slv1 -- dram: on-die termination + ); +end sramif_mig_arty; + + +architecture syn of sramif_mig_arty is + + signal MIG_BUSY : slbit := '0'; + + signal APP_RDY : slbit := '0'; + signal APP_EN : slbit := '0'; + signal APP_CMD : slv3 := (others=>'0'); + signal APP_ADDR : slv(mig_mawidth-1 downto 0) := (others=>'0'); + signal APP_WDF_RDY : slbit := '0'; + signal APP_WDF_WREN : slbit := '0'; + signal APP_WDF_DATA : slv(mig_dwidth-1 downto 0) := (others=>'0'); + signal APP_WDF_MASK : slv(mig_mwidth-1 downto 0) := (others=>'0'); + signal APP_WDF_END : slbit := '0'; + signal APP_RD_DATA_VALID : slbit := '0'; + signal APP_RD_DATA : slv(mig_dwidth-1 downto 0) := (others=>'0'); + signal APP_RD_DATA_END : slbit := '0'; + + signal UI_CLK_SYNC_RST : slbit := '0'; + signal INIT_CALIB_COMPLETE : slbit := '0'; + + signal SYS_RST : slbit := '0'; + signal SYS_RST_BUSY : slbit := '0'; + + signal CLKMUI : slbit := '0'; + signal TEMP_MUI : slv12 := (others=>'0'); -- xadc die temp; on CLKMUI + +begin + + SR2MIG: sramif2migui_core -- SRAM to MIG iface ----------------- + generic map ( + BAWIDTH => mig_bawidth, + MAWIDTH => mig_mawidth) + port map ( + CLK => CLK, + RESET => RESET, + REQ => REQ, + WE => WE, + BUSY => MIG_BUSY, + ACK_R => ACK_R, + ACK_W => ACK_W, + ACT_R => ACT_R, + ACT_W => ACT_W, + ADDR => ADDR, + BE => BE, + DI => DI, + DO => DO, + MONI => MONI, + UI_CLK => CLKMUI, + UI_CLK_SYNC_RST => UI_CLK_SYNC_RST, + INIT_CALIB_COMPLETE => INIT_CALIB_COMPLETE, + APP_RDY => APP_RDY, + APP_EN => APP_EN, + APP_CMD => APP_CMD, + APP_ADDR => APP_ADDR, + APP_WDF_RDY => APP_WDF_RDY, + APP_WDF_WREN => APP_WDF_WREN, + APP_WDF_DATA => APP_WDF_DATA, + APP_WDF_MASK => APP_WDF_MASK, + APP_WDF_END => APP_WDF_END, + APP_RD_DATA_VALID => APP_RD_DATA_VALID, + APP_RD_DATA => APP_RD_DATA, + APP_RD_DATA_END => APP_RD_DATA_END + ); + + CDC_SYSRST: cdc_pulse + generic map ( + POUT_SINGLE => false, + BUSY_WACK => true) + port map ( + CLKM => CLK, + RESET => '0', + CLKS => CLKMIG, + PIN => RESET, + BUSY => SYS_RST_BUSY, + POUT => SYS_RST + ); + + CDC_TEMP: cdc_value + generic map ( + DWIDTH => TEMP'length) + port map ( + CLKI => CLK, + CLKO => CLKMUI, + DI => TEMP, + DO => TEMP_MUI, + UPDT => open + ); + + MIG_CTL: migui_arty + port map ( + DDR3_DQ => DDR3_DQ, + DDR3_DQS_P => DDR3_DQS_P, + DDR3_DQS_N => DDR3_DQS_N, + DDR3_ADDR => DDR3_ADDR, + DDR3_BA => DDR3_BA, + DDR3_RAS_N => DDR3_RAS_N, + DDR3_CAS_N => DDR3_CAS_N, + DDR3_WE_N => DDR3_WE_N, + DDR3_RESET_N => DDR3_RESET_N, + DDR3_CK_P => DDR3_CK_P, + DDR3_CK_N => DDR3_CK_N, + DDR3_CKE => DDR3_CKE, + DDR3_CS_N => DDR3_CS_N, + DDR3_DM => DDR3_DM, + DDR3_ODT => DDR3_ODT, + APP_ADDR => APP_ADDR, + APP_CMD => APP_CMD, + APP_EN => APP_EN, + APP_WDF_DATA => APP_WDF_DATA, + APP_WDF_END => APP_WDF_END, + APP_WDF_MASK => APP_WDF_MASK, + APP_WDF_WREN => APP_WDF_WREN, + APP_RD_DATA => APP_RD_DATA, + APP_RD_DATA_END => APP_RD_DATA_END, + APP_RD_DATA_VALID => APP_RD_DATA_VALID, + APP_RDY => APP_RDY, + APP_WDF_RDY => APP_WDF_RDY, + APP_SR_REQ => '0', + APP_REF_REQ => '0', + APP_ZQ_REQ => '0', + APP_SR_ACTIVE => open, + APP_REF_ACK => open, + APP_ZQ_ACK => open, + UI_CLK => CLKMUI, + UI_CLK_SYNC_RST => UI_CLK_SYNC_RST, + INIT_CALIB_COMPLETE => INIT_CALIB_COMPLETE, + SYS_CLK_I => CLKMIG, + CLK_REF_I => CLKREF, + DEVICE_TEMP_I => TEMP_MUI, + SYS_RST => SYS_RST + ); + + BUSY <= MIG_BUSY or SYS_RST_BUSY; + +end syn; diff --git a/rtl/sys_gen/tst_mig/arty/sys_tst_mig_arty.vhd b/rtl/sys_gen/tst_mig/arty/sys_tst_mig_arty.vhd index d2b4ffad..650148ac 100644 --- a/rtl/sys_gen/tst_mig/arty/sys_tst_mig_arty.vhd +++ b/rtl/sys_gen/tst_mig/arty/sys_tst_mig_arty.vhd @@ -1,6 +1,6 @@ --- $Id: sys_tst_mig_arty.vhd 1096 2018-12-29 07:54:17Z mueller $ +-- $Id: sys_tst_mig_arty.vhd 1101 2019-01-02 21:22:37Z mueller $ -- --- Copyright 2018- by Walter F.J. Mueller +-- Copyright 2018-2019 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -33,7 +33,7 @@ -- -- Synthesized (viv): -- Date Rev viv Target flop lutl lutm bram slic --- 2018-12-28 1096 2017.2 xc7a35t-1l 4320 4773 462 1 1770 +-- 2019-01-02 1101 2017.2 xc7a35t-1l 4320 4773 462 1 1770 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/sys_gen/tst_mig/arty/sys_tst_mig_arty.vmfset b/rtl/sys_gen/tst_mig/arty/sys_tst_mig_arty.vmfset index d83c7d2c..b20b084c 100644 --- a/rtl/sys_gen/tst_mig/arty/sys_tst_mig_arty.vmfset +++ b/rtl/sys_gen/tst_mig/arty/sys_tst_mig_arty.vmfset @@ -1,4 +1,4 @@ -# $Id: sys_tst_mig_arty.vmfset 1095 2018-12-28 11:53:13Z mueller $ +# $Id: sys_tst_mig_arty.vmfset 1101 2019-01-02 21:22:37Z mueller $ # # ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ [syn] @@ -45,8 +45,8 @@ i [Synth 8-3332] R_BREGS_reg[rbinit].* sys_tst_mig_arty [imp] I [Vivado 12-2489] # multiple of 1 ps I [Physopt 32-742] # BRAM Flop Optimization -# --> spurious Invalid VCCINTIO messages # OK 2018-11-25 {:2017.2} +# --> spurious Invalid VCCINTIO messages # OK 2018-11-25 i [Designutils 20-266] Invalid Voltage Source VCCINTIO {:} diff --git a/rtl/sys_gen/tst_mig/tst_mig.vhd b/rtl/sys_gen/tst_mig/tst_mig.vhd index 40596852..1b8c013a 100644 --- a/rtl/sys_gen/tst_mig/tst_mig.vhd +++ b/rtl/sys_gen/tst_mig/tst_mig.vhd @@ -1,4 +1,4 @@ --- $Id: tst_mig.vhd 1096 2018-12-29 07:54:17Z mueller $ +-- $Id: tst_mig.vhd 1101 2019-01-02 21:22:37Z mueller $ -- -- Copyright 2018- by Walter F.J. Mueller -- @@ -18,6 +18,7 @@ -- Dependencies: - -- -- Test bench: arty/tb/tb_tst_mig_arty (with ddr3 via mig) +-- nexys4d/tb/tb_tst_mig_n4d (with ddr2 via mig) -- -- Target Devices: generic -- Tool versions: viv 2017.2; ghdl 0.34 diff --git a/rtl/sys_gen/tst_sram/arty/Makefile b/rtl/sys_gen/tst_sram/arty/Makefile new file mode 100644 index 00000000..da395325 --- /dev/null +++ b/rtl/sys_gen/tst_sram/arty/Makefile @@ -0,0 +1,25 @@ +# $Id: Makefile 1071 2018-11-17 20:53:26Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2018-11-17 1071 1.0 Initial version +# +VBOM_all = sys_tst_sram_arty.vbom +BIT_all = $(VBOM_all:.vbom=.bit) +# +include ${RETROBASE}/rtl/make_viv/viv_default_arty.mk +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : viv_clean +# +#---- +# +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +endif +# diff --git a/rtl/sys_gen/tst_sram/arty/sys_conf.vhd b/rtl/sys_gen/tst_sram/arty/sys_conf.vhd new file mode 100644 index 00000000..2fdf525c --- /dev/null +++ b/rtl/sys_gen/tst_sram/arty/sys_conf.vhd @@ -0,0 +1,60 @@ +-- $Id: sys_conf.vhd 1074 2018-11-25 21:38:59Z mueller $ +-- +-- Copyright 2018- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 3, or (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_sram_arty (for synthesis) +-- +-- Dependencies: - +-- Tool versions: viv 2017.2; ghdl 0.34 +-- Revision History: +-- Date Rev Version Comment +-- 2018-11-17 1071 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz + constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + -- dual clock design, clkser = 120 MHz + constant sys_conf_clkser_vcodivide : positive := 1; + constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz + constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz + constant sys_conf_clkser_gentype : string := "PLL"; + + -- configure rlink and hio interfaces -------------------------------------- + constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud + + -- derived constants + + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_clkser : integer := + ((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) / + sys_conf_clkser_outdivide; + constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000; + + constant sys_conf_ser2rri_cdinit : integer := + (sys_conf_clkser/sys_conf_ser2rri_defbaud)-1; + +end package sys_conf; diff --git a/rtl/sys_gen/tst_sram/arty/sys_tst_sram_arty.vbom b/rtl/sys_gen/tst_sram/arty/sys_tst_sram_arty.vbom new file mode 100644 index 00000000..ceb5f0c7 --- /dev/null +++ b/rtl/sys_gen/tst_sram/arty/sys_tst_sram_arty.vbom @@ -0,0 +1,29 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/cdclib/cdclib.vhd +../../../vlib/serport/serportlib.vbom +../../../vlib/rbus/rblib.vhd +../../../vlib/rbus/rbdlib.vhd +../../../vlib/rlink/rlinklib.vbom +../../../bplib/bpgen/bpgenlib.vbom +../../../bplib/bpgen/bpgenrbuslib.vbom +../../../bplib/sysmon/sysmonrbuslib.vbom +../../../bplib/mig/miglib.vbom +../../../bplib/arty/miglib_arty.vbom +${sys_conf := sys_conf.vhd} +@lib:unisim +# components +../../../bplib/bpgen/s7_cmt_1ce1ce2c.vbom +../../../vlib/cdclib/cdc_signal_s1_as.vbom +../../../bplib/bpgen/bp_rs232_2line_iob.vbom +../../../vlib/rlink/rlink_sp2c.vbom +../tst_sram.vbom +../../../bplib/arty/sramif_mig_arty.vbom +../../../bplib/bpgen/sn_humanio_emu_rbus.vbom +../../../bplib/sysmon/sysmonx_rbus_arty.vbom +../../../vlib/rbus/rbd_usracc.vbom +../../../vlib/rbus/rb_sres_or_4.vbom +# design +sys_tst_sram_arty.vhd +@xdc:../../../bplib/arty/arty_pclk.xdc +@xdc:../../../bplib/arty/arty_pins.xdc diff --git a/rtl/sys_gen/tst_sram/arty/sys_tst_sram_arty.vhd b/rtl/sys_gen/tst_sram/arty/sys_tst_sram_arty.vhd new file mode 100644 index 00000000..ebe1224f --- /dev/null +++ b/rtl/sys_gen/tst_sram/arty/sys_tst_sram_arty.vhd @@ -0,0 +1,433 @@ +-- $Id: sys_tst_sram_arty.vhd 1101 2019-01-02 21:22:37Z mueller $ +-- +-- Copyright 2018-2019 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 3, or (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_tst_sram_arty - syn +-- Description: test of arty ddr and its mig controller +-- +-- Dependencies: bplib/bpgen/s7_cmt_1ce1ce2c +-- cdclib/cdc_signal_s1_as +-- bplib/bpgen/bp_rs232_2line_iob +-- rlink/rlink_sp2c +-- tst_sram +-- bplib/arty/sramif_mig_arty +-- bplib/bpgen/sn_humanio_eum_rbus +-- bplib/sysmon/sysmonx_rbus_arty +-- rbus/rbd_usracc +-- rbus/rb_sres_or_4 +-- +-- Test bench: tb/tb_tst_sram_arty +-- +-- Target Devices: generic +-- Tool versions: viv 2017.2; ghdl 0.34 +-- +-- Synthesized (viv): +-- Date Rev viv Target flop lutl lutm bram slic +-- 2019-01-02 1101 2017.2 xc7a35t-1l 4643 5334 644 5 1929 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2018-12-20 1090 1.0 Initial version +-- 2018-11-17 1071 0.1 First draft (derived from sys_tst_sram_c7) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.cdclib.all; +use work.serportlib.all; +use work.rblib.all; +use work.rbdlib.all; +use work.rlinklib.all; +use work.bpgenlib.all; +use work.bpgenrbuslib.all; +use work.sysmonrbuslib.all; +use work.miglib.all; +use work.miglib_arty.all; +use work.sys_conf.all; + +library unisim; +use unisim.vcomponents.ALL; + +-- ---------------------------------------------------------------------------- + +entity sys_tst_sram_arty is -- top level + -- implements arty_sram_aif + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv4; -- arty switches + I_BTN : in slv4; -- arty buttons + O_LED : out slv4; -- arty leds + O_RGBLED0 : out slv3; -- arty rgb-led 0 + O_RGBLED1 : out slv3; -- arty rgb-led 1 + O_RGBLED2 : out slv3; -- arty rgb-led 2 + O_RGBLED3 : out slv3; -- arty rgb-led 3 + A_VPWRN : in slv4; -- arty pwrmon (neg) + A_VPWRP : in slv4; -- arty pwrmon (pos) + DDR3_DQ : inout slv16; -- dram: data in/out + DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p) + DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n) + DDR3_ADDR : out slv14; -- dram: address + DDR3_BA : out slv3; -- dram: bank address + DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low) + DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low) + DDR3_WE_N : out slbit; -- dram: write enable (act.low) + DDR3_RESET_N : out slbit; -- dram: reset (act.low) + DDR3_CK_P : out slv1; -- dram: clock (diff-p) + DDR3_CK_N : out slv1; -- dram: clock (diff-n) + DDR3_CKE : out slv1; -- dram: clock enable + DDR3_CS_N : out slv1; -- dram: chip select (act.low) + DDR3_DM : out slv2; -- dram: data input mask + DDR3_ODT : out slv1 -- dram: on-die termination + ); +end sys_tst_sram_arty; + +architecture syn of sys_tst_sram_arty is + + signal CLK100_BUF : slbit := '0'; + + signal CLK : slbit := '0'; + + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal CLKS : slbit := '0'; + signal CES_MSEC : slbit := '0'; + + signal CLKMIG : slbit := '0'; + signal CLKREF : slbit := '0'; + + signal LOCKED : slbit := '0'; -- raw LOCKED + signal LOCKED_CLK : slbit := '0'; -- sync'ed to CLK + + signal GBL_RESET : slbit := '0'; + signal MEM_RESET : slbit := '0'; + signal MEM_RESET_RRI : slbit := '0'; + + signal RXD : slbit := '1'; + signal TXD : slbit := '0'; + + signal SWI : slv16 := (others=>'0'); + signal BTN : slv5 := (others=>'0'); + signal LED : slv16 := (others=>'0'); + signal DSP_DAT : slv32 := (others=>'0'); + signal DSP_DP : slv8 := (others=>'0'); + + signal RB_MREQ : rb_mreq_type := rb_mreq_init; + signal RB_SRES : rb_sres_type := rb_sres_init; + signal RB_LAM : slv16 := (others=>'0'); + signal RB_STAT : slv4 := (others=>'0'); + + signal SER_MONI : serport_moni_type := serport_moni_init; + + signal RB_SRES_TST : rb_sres_type := rb_sres_init; + signal RB_SRES_HIO : rb_sres_type := rb_sres_init; + signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init; + signal RB_SRES_USRACC : rb_sres_type := rb_sres_init; + + signal RB_LAM_TST : slbit := '0'; + + signal MEM_REQ : slbit := '0'; + signal MEM_WE : slbit := '0'; + signal MEM_BUSY : slbit := '0'; + signal MEM_ACK_R : slbit := '0'; + signal MEM_ACK_W : slbit := '0'; + signal MEM_ACT_R : slbit := '0'; + signal MEM_ACT_W : slbit := '0'; + signal MEM_ADDR : slv20 := (others=>'0'); + signal MEM_BE : slv4 := (others=>'0'); + signal MEM_DI : slv32 := (others=>'0'); + signal MEM_DO : slv32 := (others=>'0'); + + signal MIG_MONI : sramif2migui_moni_type := sramif2migui_moni_init; + signal XADC_TEMP : slv12 := (others=>'0'); -- xadc die temp; on CLK + + signal R_DIMCNT : slv2 := (others=>'0'); + signal R_DIMFLG : slbit := '0'; + + constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx + constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx + + constant sysid_proj : slv16 := x"0104"; -- tst_sram + constant sysid_board : slv8 := x"07"; -- arty + constant sysid_vers : slv8 := x"00"; + +begin + + CLK100_BUFG: bufg + port map ( + I => I_CLK100, + O => CLK100_BUF + ); + + GEN_CLKALL : s7_cmt_1ce1ce2c -- clock generator system ------------ + generic map ( + CLKIN_PERIOD => 10.0, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + CLK0_VCODIV => sys_conf_clksys_vcodivide, + CLK0_VCOMUL => sys_conf_clksys_vcomultiply, + CLK0_OUTDIV => sys_conf_clksys_outdivide, + CLK0_GENTYPE => sys_conf_clksys_gentype, + CLK0_CDUWIDTH => 7, + CLK0_USECDIV => sys_conf_clksys_mhz, + CLK0_MSECDIV => 1000, + CLK1_VCODIV => sys_conf_clkser_vcodivide, + CLK1_VCOMUL => sys_conf_clkser_vcomultiply, + CLK1_OUTDIV => sys_conf_clkser_outdivide, + CLK1_GENTYPE => sys_conf_clkser_gentype, + CLK1_CDUWIDTH => 7, + CLK1_USECDIV => sys_conf_clkser_mhz, + CLK1_MSECDIV => 1000, + CLK23_VCODIV => 1, + CLK23_VCOMUL => 10, -- vco 1000 MHz + CLK2_OUTDIV => 6, -- mig sys 166.6 MHz + CLK3_OUTDIV => 5, -- mig ref 200.0 MHz + CLK23_GENTYPE => "PLL") + port map ( + CLKIN => CLK100_BUF, + CLK0 => CLK, + CE0_USEC => CE_USEC, + CE0_MSEC => CE_MSEC, + CLK1 => CLKS, + CE1_USEC => open, + CE1_MSEC => CES_MSEC, + CLK2 => CLKMIG, + CLK3 => CLKREF, + LOCKED => LOCKED + ); + + CDC_CLK_LOCKED : cdc_signal_s1_as + port map ( + CLKO => CLK, + DI => LOCKED, + DO => LOCKED_CLK + ); + + GBL_RESET <= not LOCKED_CLK; + + IOB_RS232 : bp_rs232_2line_iob + port map ( + CLK => CLKS, + RXD => RXD, + TXD => TXD, + I_RXD => I_RXD, + O_TXD => O_TXD + ); + + RLINK : rlink_sp2c + generic map ( + BTOWIDTH => 8, -- 256 cycles, for slow mem iface + RTAWIDTH => 12, + SYSID => sysid_proj & sysid_board & sysid_vers, + IFAWIDTH => 5, -- 32 word input fifo + OFAWIDTH => 5, -- 32 word output fifo + ENAPIN_RLMON => sbcntl_sbf_rlmon, + ENAPIN_RBMON => sbcntl_sbf_rbmon, + CDWIDTH => 12, + CDINIT => sys_conf_ser2rri_cdinit, + RBMON_AWIDTH => 0, + RBMON_RBADDR => rbaddr_rbmon) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + CE_INT => CE_MSEC, + RESET => GBL_RESET, + CLKS => CLKS, + CES_MSEC => CES_MSEC, + ENAXON => '1', + ESCFILL => '0', + RXSD => RXD, + TXSD => TXD, + CTS_N => '0', + RTS_N => open, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT, + RL_MONI => open, + SER_MONI => SER_MONI + ); + + TST : entity work.tst_sram + generic map ( + RB_ADDR => slv(to_unsigned(2#0000000000000000#,16)), + AWIDTH => 18) + port map ( + CLK => CLK, + RESET => GBL_RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_TST, + RB_STAT => RB_STAT, + RB_LAM => RB_LAM_TST, + SWI => SWI(7 downto 0), + BTN => BTN(3 downto 0), + LED => LED(7 downto 0), + DSP_DAT => DSP_DAT(15 downto 0), + MEM_RESET => MEM_RESET_RRI, + MEM_REQ => MEM_REQ, + MEM_WE => MEM_WE, + MEM_BUSY => MEM_BUSY, + MEM_ACK_R => MEM_ACK_R, + MEM_ACK_W => MEM_ACK_W, + MEM_ACT_R => MEM_ACT_R, + MEM_ACT_W => MEM_ACT_W, + MEM_ADDR => MEM_ADDR(17 downto 0), -- ?? FIXME ?? allow AWIDTH=20 + MEM_BE => MEM_BE, + MEM_DI => MEM_DI, + MEM_DO => MEM_DO + ); + + MEM_ADDR(19 downto 18) <= (others=>'0'); --?? FIXME ?? allow AWIDTH=20 + + MEM_RESET <= not LOCKED_CLK or MEM_RESET_RRI; + + MEMCTL: sramif_mig_arty -- SRAM to MIG iface ----------------- + port map ( + CLK => CLK, + RESET => MEM_RESET, + REQ => MEM_REQ, + WE => MEM_WE, + BUSY => MEM_BUSY, + ACK_R => MEM_ACK_R, + ACK_W => MEM_ACK_W, + ACT_R => MEM_ACT_R, + ACT_W => MEM_ACT_W, + ADDR => MEM_ADDR, + BE => MEM_BE, + DI => MEM_DI, + DO => MEM_DO, + CLKMIG => CLKMIG, + CLKREF => CLKREF, + TEMP => XADC_TEMP, + MONI => MIG_MONI, + DDR3_DQ => DDR3_DQ, + DDR3_DQS_P => DDR3_DQS_P, + DDR3_DQS_N => DDR3_DQS_N, + DDR3_ADDR => DDR3_ADDR, + DDR3_BA => DDR3_BA, + DDR3_RAS_N => DDR3_RAS_N, + DDR3_CAS_N => DDR3_CAS_N, + DDR3_WE_N => DDR3_WE_N, + DDR3_RESET_N => DDR3_RESET_N, + DDR3_CK_P => DDR3_CK_P, + DDR3_CK_N => DDR3_CK_N, + DDR3_CKE => DDR3_CKE, + DDR3_CS_N => DDR3_CS_N, + DDR3_DM => DDR3_DM, + DDR3_ODT => DDR3_ODT + ); + + HIO : sn_humanio_emu_rbus + generic map ( + SWIDTH => 16, + BWIDTH => 5, + LWIDTH => 16, + DCWIDTH => 3) + port map ( + CLK => CLK, + RESET => '0', + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_HIO, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP + ); + + SMRB: sysmonx_rbus_arty + generic map ( -- use default INIT_ (LP: Vccint=0.95) + CLK_MHZ => sys_conf_clksys_mhz, + RB_ADDR => rbaddr_sysmon) + port map ( + CLK => CLK, + RESET => GBL_RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_SYSMON, + ALM => open, + OT => open, + TEMP => XADC_TEMP, + VPWRN => A_VPWRN, + VPWRP => A_VPWRP + ); + + UARB : rbd_usracc + port map ( + CLK => CLK, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_USRACC + ); + + RB_SRES_OR : rb_sres_or_4 -- rbus or --------------------------- + port map ( + RB_SRES_1 => RB_SRES_TST, + RB_SRES_2 => RB_SRES_HIO, + RB_SRES_3 => RB_SRES_SYSMON, + RB_SRES_4 => RB_SRES_USRACC, + RB_SRES_OR => RB_SRES + ); + + proc_dim: process (CLKMIG) + begin + + if rising_edge(CLKMIG) then + R_DIMCNT <= slv(unsigned(R_DIMCNT) + 1); + if unsigned(R_DIMCNT) = 0 then + R_DIMFLG <= '1'; + else + R_DIMFLG <= '0'; + end if; + end if; + + end process proc_dim; + + RB_LAM(0) <= RB_LAM_TST; + + O_LED(1) <= SER_MONI.txact; + O_LED(0) <= SER_MONI.rxact; + + DSP_DP(3) <= not SER_MONI.txok; + DSP_DP(2) <= SER_MONI.txact; + DSP_DP(1) <= not SER_MONI.rxok; + DSP_DP(0) <= SER_MONI.rxact; + + DSP_DP(7 downto 4) <= "0010"; + DSP_DAT(31 downto 16) <= SER_MONI.abclkdiv(11 downto 0) & + '0' & SER_MONI.abclkdiv_f; + + -- red LED for serious error conditions + O_RGBLED0(0) <= R_DIMFLG and (I_BTN(0) or not LOCKED); + O_RGBLED1(0) <= R_DIMFLG and (I_BTN(0)); + O_RGBLED2(0) <= R_DIMFLG and (I_BTN(0) or MIG_MONI.miguirst); + O_RGBLED3(0) <= R_DIMFLG and (I_BTN(0) or MIG_MONI.migcacow); + + -- green LED for activity + O_RGBLED0(1) <= R_DIMFLG and (I_BTN(1) or MEM_ACT_R); + O_RGBLED1(1) <= R_DIMFLG and (I_BTN(1) or MEM_ACT_W); + O_RGBLED2(1) <= R_DIMFLG and (I_BTN(1) or (MIG_MONI.migcbusy xor I_BTN(3))); + O_RGBLED3(1) <= R_DIMFLG and (I_BTN(1) or MIG_MONI.migwbusy); + + -- blue LED currently unused + O_RGBLED0(2) <= R_DIMFLG and (I_BTN(2)); + O_RGBLED1(2) <= R_DIMFLG and (I_BTN(2)); + O_RGBLED2(2) <= R_DIMFLG and (I_BTN(2)); + O_RGBLED3(2) <= R_DIMFLG and (I_BTN(2)); + +end syn; + diff --git a/rtl/sys_gen/tst_sram/arty/sys_tst_sram_arty.vmfset b/rtl/sys_gen/tst_sram/arty/sys_tst_sram_arty.vmfset new file mode 100644 index 00000000..94824e4d --- /dev/null +++ b/rtl/sys_gen/tst_sram/arty/sys_tst_sram_arty.vmfset @@ -0,0 +1,83 @@ +# $Id: sys_tst_sram_arty.vmfset 1101 2019-01-02 21:22:37Z mueller $ +# +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[syn] +# general issues ----------------------------------------------- +{2018.2:} +# stupid new warning, Xilinx suggests to safely ingnore +i [Constraints 18-5210] # generic +{:} + +# false_path -hold ignored by synth ---------------------------- +I [Designutils 20-1567] # generic + +# port driven by constant -------------------------------------- + +# tying undriven pin to constant ------------------------------- +# upper 8 LEDs unused # OK 2018-11-25 +i [Synth 8-3295] HIO:LED[\d*] +# only few LAMs used # OK 2017-11-25 +i [Synth 8-3295] RLINK:RB_LAM[\d*] + +# unconnected ports -------------------------------------------- +I [Synth 8-3331] RB_MREQ # generic +# --> I_SWI not used # OK 2018-11-25 +i [Synth 8-3331] I_SWI[\d] +# --> O_LED only partially used # OK 2018-11-25 +i [Synth 8-3331] O_LED[(2|3)] +# --> MEM_ACK_W not used by current tst_sram # OK 2018-11-25 +i [Synth 8-3331] tst_sram.*MEM_ACK_W +# --> rlink_sp2c doesn't use CE_USEC and CE_MSEC # OK 2018-11-25 +i [Synth 8-3331] rlink_sp2c.*CE_(USEC|MSEC) +# --> data end marker not used # OK 2018-12-20 +i [Synth 8-3331] sramif2migui_core .*APP_RD_DATA_END + +# sequential element removed (2017.1 nonsense) ----------------- +I [Synth 8-6014] _reg # generic + +# unused sequential element ------------------------------------ +I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic +{:} +# --> only 18 bit address # OK 2018-12-22 +i [Synth 8-3332] R_REGS_reg[wrtag][1(6|7)].* sramif2migui_core +i [Synth 8-3332] R_REGS_reg[rdtag][1(6|7)].* sramif2migui_core +i [Synth 8-3332] R_REGS_reg[req_addr][1(8|9)].* sramif2migui_core +# --> rdnew only used in MONI, that not used in tst_sram # OK 2018-12-22 +i [Synth 8-3332] R_REGS_reg[rdnew].* sramif2migui_core +# --> usec unused # OK 2018-12-22 +i [Synth 8-3332] R_REGS_reg[usec].* sys_tst_sram_arty +# --> only stat 1,2 used , moneop and monattn unused # OK 2018-12-22 +i [Synth 8-3332] R_BREGS_reg[stat][(2|3)].* sys_tst_sram_arty +i [Synth 8-3332] R_LREGS_reg[(moneop|monattn)].* sys_tst_sram_arty +# --> not all led etc used in HIO emu # OK 2018-12-22 +i [Synth 8-3332] R_REGS_reg[led][\d*].* sys_tst_sram_arty +i [Synth 8-3332] R_REGS_reg[dsp_dp][\d*].* sys_tst_sram_arty +i [Synth 8-3332] R_REGS_reg[dsp_dat][\d*].* sys_tst_sram_arty +{:} + +# messages from MIG core ------------------------------------ +#c [Synth 8-3331] mig_7series_v4 +#c [Synth 8-3332] u_migui_arty_mig +#c [Synth 8-3332] mig_7series_v4 +#c [Synth 8-3295] u_migui_arty_mig +#c [Synth 8-3295] ip/migui_arty/migui_arty +#c [Synth 8-3936] ip/migui_arty/migui_arty +#c [Synth 8-3848] mig_7series_v4 +#c [Synth 8-5856] 3D RAM +#{2018.2} +#c [Synth 8-6104] mig_7series_v4 +#{:} + +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[imp] +I [Vivado 12-2489] # multiple of 1 ps +I [Physopt 32-742] # BRAM Flop Optimization +{:2017.2} +# --> spurious Invalid VCCINTIO messages # OK 2018-11-25 +i [Designutils 20-266] Invalid Voltage Source VCCINTIO +{:} + +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[bit] +# see https://www.xilinx.com/support/answers/64180.html # OK 2018-12-22 +i [DRC REQP-1709] PLLE2_ADV diff --git a/rtl/sys_gen/tst_sram/arty/tb/.gitignore b/rtl/sys_gen/tst_sram/arty/tb/.gitignore new file mode 100644 index 00000000..31a98c2b --- /dev/null +++ b/rtl/sys_gen/tst_sram/arty/tb/.gitignore @@ -0,0 +1,2 @@ +tb_tst_sram_arty +sysmon_stim diff --git a/rtl/sys_gen/tst_sram/arty/tb/Makefile b/rtl/sys_gen/tst_sram/arty/tb/Makefile new file mode 100644 index 00000000..86b444bb --- /dev/null +++ b/rtl/sys_gen/tst_sram/arty/tb/Makefile @@ -0,0 +1,39 @@ +# $Id: Makefile 1071 2018-11-17 20:53:26Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2018-11-17 1071 1.0 Initial version +# +EXE_all = tb_tst_sram_arty +# +include ${RETROBASE}/rtl/make_viv/viv_default_arty.mk +# +.PHONY : all all_ssim all_osim clean +.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_osim : $(EXE_all:=_osim) +# +all_XSim : $(EXE_all:=_XSim) +all_XSim_ssim : $(EXE_all:=_XSim_ssim) +all_XSim_osim : $(EXE_all:=_XSim_osim) +all_XSim_tsim : $(EXE_all:=_XSim_tsim) +# +clean : viv_clean ghdl_clean xsim_clean +# +#----- +# +include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk +include ${RETROBASE}/rtl/make_viv/generic_xsim.mk +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(VBOM_all:.vbom=.dep_vsim) +include $(wildcard *.o.dep_ghdl) +endif +# diff --git a/rtl/sys_gen/tst_sram/arty/tb/sys_conf_sim.vhd b/rtl/sys_gen/tst_sram/arty/tb/sys_conf_sim.vhd new file mode 100644 index 00000000..08b8bdc4 --- /dev/null +++ b/rtl/sys_gen/tst_sram/arty/tb/sys_conf_sim.vhd @@ -0,0 +1,57 @@ +-- $Id: sys_conf_sim.vhd 1072 2018-11-18 22:27:35Z mueller $ +-- +-- Copyright 2018- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 3, or (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_sram_arty (for simulation) +-- +-- Dependencies: - +-- Tool versions: viv 2017.2; ghdl 0.34 +-- Revision History: +-- Date Rev Version Comment +-- 2018-11-17 1071 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz + constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + -- dual clock design, clkser = 120 MHz + constant sys_conf_clkser_vcodivide : positive := 1; + constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz + constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz + constant sys_conf_clkser_gentype : string := "PLL"; + + -- configure rlink and hio interfaces -------------------------------------- + constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim + + -- derived constants + + constant sys_conf_clksys : integer := + ((12000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_clkser : integer := + ((12000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) / + sys_conf_clkser_outdivide; + constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000; + +end package sys_conf; diff --git a/rtl/sys_gen/tst_sram/arty/tb/tb_tst_sram_arty.vbom b/rtl/sys_gen/tst_sram/arty/tb/tb_tst_sram_arty.vbom new file mode 100644 index 00000000..48b3e091 --- /dev/null +++ b/rtl/sys_gen/tst_sram/arty/tb/tb_tst_sram_arty.vbom @@ -0,0 +1,9 @@ +# configure tb_arty_dram with sys_tst_sram_arty target; +# use vhdl configure file (tb_tst_sram_arty.vhd) to allow +# that all configurations will co-exist in work library +# configure +arty_dram_aif = ../sys_tst_sram_arty.vbom +sys_conf = sys_conf_sim.vhd +# design +../../../../bplib/arty/tb/tb_arty_dram.vbom +tb_tst_sram_arty.vhd diff --git a/rtl/sys_gen/tst_sram/arty/tb/tb_tst_sram_arty.vhd b/rtl/sys_gen/tst_sram/arty/tb/tb_tst_sram_arty.vhd new file mode 100644 index 00000000..cb07b204 --- /dev/null +++ b/rtl/sys_gen/tst_sram/arty/tb/tb_tst_sram_arty.vhd @@ -0,0 +1,35 @@ +-- $Id: tb_tst_sram_arty.vhd 1071 2018-11-17 20:53:26Z mueller $ +-- +-- Copyright 2018- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 3, or (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_tst_sram_arty +-- Description: Configuration for tb_tst_sram_arty for tb_arty_dram +-- +-- Dependencies: sys_tst_sram_arty +-- +-- To test: sys_tst_sram_arty +-- +-- Revision History: +-- Date Rev Version Comment +-- 2018-11-17 1071 1.0 Initial version +------------------------------------------------------------------------------ + +configuration tb_tst_sram_arty of tb_arty_dram is + + for sim + for all : arty_dram_aif + use entity work.sys_tst_sram_arty; + end for; + end for; + +end tb_tst_sram_arty; diff --git a/rtl/sys_gen/tst_sram/arty/tb/tbrun.yml b/rtl/sys_gen/tst_sram/arty/tb/tbrun.yml new file mode 100644 index 00000000..e3426dbd --- /dev/null +++ b/rtl/sys_gen/tst_sram/arty/tb/tbrun.yml @@ -0,0 +1,18 @@ +# $Id: tbrun.yml 1071 2018-11-17 20:53:26Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2018-11-17 1071 1.0 Initial version +# +- default: + mode: ${viv_modes} +# +- tag: [default, viv, sys_tst_sram, arty, base] + test: | + tbrun_tbwrri --hxon --lsuf base --pack tst_sram tb_tst_sram_arty${ms} \ + tst_sram::setup tst_sram::test_all + +- tag: [default, viv, sys_tst_sram, arty, stress] + test: | + tbrun_tbwrri --hxon --lsuf stress --pack tst_sram tb_tst_sram_arty${ms} \ + tst_sram::setup tst_sram::test_sim diff --git a/rtl/sys_gen/tst_sram/arty/tb/tbw.dat b/rtl/sys_gen/tst_sram/arty/tb/tbw.dat new file mode 100644 index 00000000..4936583f --- /dev/null +++ b/rtl/sys_gen/tst_sram/arty/tb/tbw.dat @@ -0,0 +1,7 @@ +# $Id: tbw.dat 1071 2018-11-17 20:53:26Z mueller $ +# +[tb_tst_sram_arty] +rlink_cext_fifo_rx = +rlink_cext_fifo_tx = +rlink_cext_conf = +sysmon_stim = ../../../../bplib/sysmon/tb/sysmon_stim_arty.dat diff --git a/rtl/sys_gen/tst_sram/tbrun.yml b/rtl/sys_gen/tst_sram/tbrun.yml index dde1b180..b82f8365 100644 --- a/rtl/sys_gen/tst_sram/tbrun.yml +++ b/rtl/sys_gen/tst_sram/tbrun.yml @@ -1,10 +1,12 @@ -# $Id: tbrun.yml 917 2017-06-25 18:05:28Z mueller $ +# $Id: tbrun.yml 1101 2019-01-02 21:22:37Z mueller $ # # Revision History: # Date Rev Version Comment +# 2019-01-02 1101 1.2 add arty # 2017-06-25 917 1.1 add cmoda7 # 2016-08-13 798 1.0 Initial version # +- include: arty/tb/tbrun.yml - include: s3board/tb/tbrun.yml - include: nexys2/tb/tbrun.yml - include: nexys3/tb/tbrun.yml diff --git a/rtl/sys_gen/tst_sram/tst_sram.vhd b/rtl/sys_gen/tst_sram/tst_sram.vhd index e8431582..29909b13 100644 --- a/rtl/sys_gen/tst_sram/tst_sram.vhd +++ b/rtl/sys_gen/tst_sram/tst_sram.vhd @@ -1,4 +1,4 @@ --- $Id: tst_sram.vhd 1092 2018-12-24 08:01:50Z mueller $ +-- $Id: tst_sram.vhd 1101 2019-01-02 21:22:37Z mueller $ -- -- Copyright 2007-2017 by Walter F.J. Mueller -- @@ -19,6 +19,7 @@ -- vlib/memlib/ram_2swsr_wfirst_gen -- -- Test bench: arty/tb/tb_tst_sram_arty (with ddr3 via mig) +-- nexys4d/tb/tb_tst_mig_n4d (with ddr2 via mig) -- cmoda7/tb/tb_tst_sram_c7 (with sram) -- nexys4/tb/tb_tst_sram_n4 (with cram) -- nexys3/tb/tb_tst_sram_n3 (with cram) diff --git a/rtl/vlib/cdclib/cdc_value.vbom b/rtl/vlib/cdclib/cdc_value.vbom new file mode 100644 index 00000000..42b0c1b0 --- /dev/null +++ b/rtl/vlib/cdclib/cdc_value.vbom @@ -0,0 +1,7 @@ +# libs +../slvtypes.vhd +# components +cdc_pulse.vbom +cdc_vector_s0.vbom +# design +cdc_value.vhd diff --git a/rtl/vlib/cdclib/cdc_value.vhd b/rtl/vlib/cdclib/cdc_value.vhd new file mode 100644 index 00000000..fd2c6c73 --- /dev/null +++ b/rtl/vlib/cdclib/cdc_value.vhd @@ -0,0 +1,105 @@ +-- $Id: cdc_value.vhd 1101 2019-01-02 21:22:37Z mueller $ +-- +-- Copyright 2016-2019 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 3, or (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: cdc_value - syn +-- Description: clock domain crossing for a slowly changing value +-- +-- Dependencies: cdc_pulse +-- cdc_vector_s0 +-- Test bench: - +-- Target Devices: generic +-- Tool versions: viv 2017.2; ghdl 0.34 +-- Revision History: +-- Date Rev Version Comment +-- 2019-01-02 1101 2.0 reinplement using cdc_pulse and cdc_vector_s0 +-- 2016-04-08 459 1.0 Initial version +-- +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.cdclib.all; + +entity cdc_value is -- cdc for value (slow change) + generic ( + DWIDTH : positive := 16); -- data port width + port ( + CLKI : in slbit; -- I|input clock + CLKO : in slbit; -- O|output clock + DI : in slv(DWIDTH-1 downto 0); -- I|input data + DO : out slv(DWIDTH-1 downto 0); -- O|output data + UPDT : out slbit -- O|output data updated + ); +end entity cdc_value; + + +architecture syn of cdc_value is + + subtype d_range is integer range DWIDTH-1 downto 0; + + signal R_DI : slv(d_range) := (others=>'0'); + signal R_UPDT : slbit := '0'; + + signal PULSE_PIN : slbit := '0'; + signal PULSE_BUSY : slbit := '0'; + signal PULSE_POUT : slbit := '0'; + +begin + + CDC_ENA: cdc_pulse + generic map ( + POUT_SINGLE => true, + BUSY_WACK => true) + port map ( + CLKM => CLKI, + RESET => '0', + CLKS => CLKO, + PIN => PULSE_PIN, + BUSY => PULSE_BUSY, + POUT => PULSE_POUT + ); + + CDC_DOUT : cdc_vector_s0 + generic map ( + DWIDTH => DWIDTH) + port map ( + CLKO => CLKO, + ENA => PULSE_POUT, + DI => R_DI, + DO => DO + ); + + PULSE_PIN <= not PULSE_BUSY; + + proc_clki: process (CLKI) + begin + if rising_edge(CLKI) then + if PULSE_PIN = '1' then + R_DI <= DI; + end if; + end if; + end process proc_clki; + + proc_clko: process (CLKO) + begin + if rising_edge(CLKO) then + R_UPDT <= PULSE_POUT; + end if; + end process proc_clko; + + UPDT <= R_UPDT; + +end syn; diff --git a/rtl/vlib/cdclib/cdc_vector_s0.vhd b/rtl/vlib/cdclib/cdc_vector_s0.vhd index 370928b7..aa35d424 100644 --- a/rtl/vlib/cdclib/cdc_vector_s0.vhd +++ b/rtl/vlib/cdclib/cdc_vector_s0.vhd @@ -1,6 +1,6 @@ --- $Id: cdc_vector_s0.vhd 984 2018-01-02 20:56:27Z mueller $ +-- $Id: cdc_vector_s0.vhd 1101 2019-01-02 21:22:37Z mueller $ -- --- Copyright 2016- by Walter F.J. Mueller +-- Copyright 2016-2019 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,9 +18,10 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: viv 2015.4; ghdl 0.33 +-- Tool versions: viv 2015.4-2017.2; ghdl 0.33-0.34 -- Revision History: -- Date Rev Version Comment +-- 2019-01-02 1101 1.1 add ENA port -- 2016-04-08 459 1.0 Initial version -- ------------------------------------------------------------------------------ @@ -35,6 +36,7 @@ entity cdc_vector_s0 is -- cdc for vector (1 stage) DWIDTH : positive := 16); -- data port width port ( CLKO : in slbit; -- O|output clock + ENA : in slbit := '1'; -- O|capture enable DI : in slv(DWIDTH-1 downto 0); -- I|input data DO : out slv(DWIDTH-1 downto 0) -- O|output data ); @@ -56,7 +58,9 @@ begin proc_regs: process (CLKO) begin if rising_edge(CLKO) then - R_DO_S0 <= DI; -- synch 0: CLKI->CLKO + if ENA = '1' then + R_DO_S0 <= DI; -- synch 0: CLKI->CLKO + end if; end if; end process proc_regs; diff --git a/rtl/vlib/cdclib/cdc_vector_s0.xdc b/rtl/vlib/cdclib/cdc_vector_s0.xdc index 79a1c861..4dc337e9 100644 --- a/rtl/vlib/cdclib/cdc_vector_s0.xdc +++ b/rtl/vlib/cdclib/cdc_vector_s0.xdc @@ -1,13 +1,14 @@ # -*- tcl -*- -# $Id: cdc_vector_s0.xdc 830 2016-12-26 20:25:49Z mueller $ +# $Id: cdc_vector_s0.xdc 1101 2019-01-02 21:22:37Z mueller $ # -# Copyright 2016- by Walter F.J. Mueller +# Copyright 2016-2019 by Walter F.J. Mueller # License disclaimer see License.txt in $RETROBASE directory # # cdc constraints for cdc_vector_s0 # # Revision History: # Date Rev Version Comment +# 2019-01-02 1101 1.1 contrain on both input and output clock period # 2016-04-08 759 1.0 Initial version # @@ -19,16 +20,19 @@ set clki [get_clocks -of_objects \ [get_pins -filter {DIRECTION==OUT && IS_LEAF==1} -of_objects \ [get_nets -segments -of_objects \ [get_ports -scoped_to_current_instance {DI[0]} ] ] ] ] ] +set clko [get_clocks -of_objects [get_cells {R_DO_S0_reg[*]} ] ] -set clki_per80 [expr {0.8 * [get_property -min PERIOD $clki]}] +set clki_per50 [expr {0.5 * [get_property -min PERIOD $clki]}] +set clko_per50 [expr {0.5 * [get_property -min PERIOD $clko]}] +set maxdly [expr { min($clki_per50,$clko_per50) }] # -# CLKI->CLK0 -# ensure delay and thus skew in DI smaller than a sender clock cycle -# Note: the _s0 form should be used for 'quasi static' cases -# this skew and delay control is therefore bit of an overkill +# CLKI->CLKO +# Ensure delay and thus skew of the DI->R_DO datapath is smaller than +# 80% of both the input and the output clock period. That should be +# save in all usage modes. set_max_delay \ -from $clki \ -to [get_cells {R_DO_S0_reg[*]}] \ - -datapath_only $clki_per80 + -datapath_only $maxdly diff --git a/rtl/vlib/cdclib/cdclib.vhd b/rtl/vlib/cdclib/cdclib.vhd index 9ed3631e..227d51e2 100644 --- a/rtl/vlib/cdclib/cdclib.vhd +++ b/rtl/vlib/cdclib/cdclib.vhd @@ -1,6 +1,6 @@ --- $Id: cdclib.vhd 984 2018-01-02 20:56:27Z mueller $ +-- $Id: cdclib.vhd 1101 2019-01-02 21:22:37Z mueller $ -- --- Copyright 2016- by Walter F.J. Mueller +-- Copyright 2016-2019 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,9 +16,10 @@ -- Description: clock domain crossing components -- -- Dependencies: - --- Tool versions: viv 2016.1-2016.2; ghdl 0.33 +-- Tool versions: viv 2016.1-2017.2; ghdl 0.33-0.34 -- Revision History: -- Date Rev Version Comment +-- 2019-01-02 1101 1.0.2 cdc_vector_s0,cdc_pulse interface changed -- 2016-06-11 774 1.0.1 add cdc_signal_s1_as; add INIT generic -- 2016-04-02 757 1.0 Initial version ------------------------------------------------------------------------------ @@ -55,6 +56,7 @@ component cdc_vector_s0 is -- cdc for vector (1 stage) DWIDTH : positive := 16); -- data port width port ( CLKO : in slbit; -- O|output clock + ENA : in slbit := '1'; -- O|capture enable DI : in slv(DWIDTH-1 downto 0); -- I|input data DO : out slv(DWIDTH-1 downto 0) -- O|output data ); @@ -89,10 +91,11 @@ component cdc_value is -- cdc for value (slow change) generic ( DWIDTH : positive := 16); -- data port width port ( + CLKI : in slbit; -- I|input clock CLKO : in slbit; -- O|output clock DI : in slv(DWIDTH-1 downto 0); -- I|input data DO : out slv(DWIDTH-1 downto 0); -- O|output data - DFIX : out slbit -- O|output data frozen + UPDT : out slbit -- O|output data updated ); end component; diff --git a/tools/tcl/tst_mig/util.tcl b/tools/tcl/tst_mig/util.tcl index 9c7f319d..b20b1164 100644 --- a/tools/tcl/tst_mig/util.tcl +++ b/tools/tcl/tst_mig/util.tcl @@ -1,4 +1,4 @@ -# $Id: util.tcl 1096 2018-12-29 07:54:17Z mueller $ +# $Id: util.tcl 1101 2019-01-02 21:22:37Z mueller $ # # Copyright 2018- by Walter F.J. Mueller # @@ -13,6 +13,7 @@ # # Revision History: # Date Rev Version Comment +# 2019-01-02 1101 1.0.1 test_rwait: add optional lena argument # 2018-12-28 1096 1.0 Initial version # 2018-12-24 1093 0.1 First draft # @@ -387,37 +388,49 @@ namespace eval tst_mig { # # test_rwait: determine read latency with read commands -------------------- # - proc test_rwait {addr {cnt 16} {inc 0x0}} { + proc test_rwait {addr {cnt 16} {inc 0x0} {lena 0}} { set cwaitlist {} set rwaitlist {} set addr0 $addr set addr1 [expr {$addr + 1*$inc}] set addr2 [expr {$addr + 2*$inc}] set addr3 [expr {$addr + 3*$inc}] + for {set i 0} { $i < $cnt } {incr i} { - rlc exec \ - -wreg mt.addrl [expr { $addr0 & 0xffff}] \ - -wreg mt.addrh [expr {($addr0>>16) & 0xffff}] \ - -wreg mt.cntl [regbld tst_mig::CNTL {func "RD"}] \ - -rreg mt.cwait cwait0 \ - -rreg mt.rwait rwait0 \ - -wreg mt.addrl [expr { $addr1 & 0xffff}] \ - -wreg mt.addrh [expr {($addr1>>16) & 0xffff}] \ - -wreg mt.cntl [regbld tst_mig::CNTL {func "RD"}] \ - -rreg mt.cwait cwait1 \ - -rreg mt.rwait rwait1 \ - -wreg mt.addrl [expr { $addr2 & 0xffff}] \ - -wreg mt.addrh [expr {($addr0>>16) & 0xffff}] \ - -wreg mt.cntl [regbld tst_mig::CNTL {func "RD"}] \ - -rreg mt.cwait cwait2 \ - -rreg mt.rwait rwait2 \ - -wreg mt.addrl [expr { $addr3 & 0xffff}] \ - -wreg mt.addrh [expr {($addr3>>16) & 0xffff}] \ - -wreg mt.cntl [regbld tst_mig::CNTL {func "RD"}] \ - -rreg mt.cwait cwait3 \ - -rreg mt.rwait rwait3 - lappend cwaitlist $cwait0 $cwait1 $cwait2 $cwait3 - lappend rwaitlist $rwait0 $rwait1 $rwait2 $rwait3 + if { $lena } { + rlc exec \ + -wreg mt.addrl [expr { $addr0 & 0xffff}] \ + -wreg mt.addrh [expr {($addr0>>16) & 0xffff}] \ + -wreg mt.cntl [regbld tst_mig::CNTL {func "RD"}] \ + -rreg mt.cwait cwait0 \ + -rreg mt.rwait rwait0 \ + -wreg mt.addrl [expr { $addr1 & 0xffff}] \ + -wreg mt.addrh [expr {($addr1>>16) & 0xffff}] \ + -wreg mt.cntl [regbld tst_mig::CNTL {func "RD"}] \ + -rreg mt.cwait cwait1 \ + -rreg mt.rwait rwait1 \ + -wreg mt.addrl [expr { $addr2 & 0xffff}] \ + -wreg mt.addrh [expr {($addr0>>16) & 0xffff}] \ + -wreg mt.cntl [regbld tst_mig::CNTL {func "RD"}] \ + -rreg mt.cwait cwait2 \ + -rreg mt.rwait rwait2 \ + -wreg mt.addrl [expr { $addr3 & 0xffff}] \ + -wreg mt.addrh [expr {($addr3>>16) & 0xffff}] \ + -wreg mt.cntl [regbld tst_mig::CNTL {func "RD"}] \ + -rreg mt.cwait cwait3 \ + -rreg mt.rwait rwait3 + lappend cwaitlist $cwait0 $cwait1 $cwait2 $cwait3 + lappend rwaitlist $rwait0 $rwait1 $rwait2 $rwait3 + } else { + rlc exec \ + -wreg mt.addrl [expr { $addr0 & 0xffff}] \ + -wreg mt.addrh [expr {($addr0>>16) & 0xffff}] \ + -wreg mt.cntl [regbld tst_mig::CNTL {func "RD"}] \ + -rreg mt.cwait cwait0 \ + -rreg mt.rwait rwait0 + lappend cwaitlist $cwait0 + lappend rwaitlist $rwait0 + } } set cwaitlist [lsort -integer $cwaitlist] set rwaitlist [lsort -integer $rwaitlist] @@ -428,6 +441,7 @@ namespace eval tst_mig { set waitmax [expr {max($cwaitmax,$rwaitmax)}] set cwaithist [lrepeat [expr {$waitmax+1}] 0] set rwaithist [lrepeat [expr {$waitmax+1}] 0] + set tcnt [llength $cwaitlist] foreach cwait $cwaitlist { incr cwaitsum $cwait lset cwaithist $cwait [expr {1+[lindex $cwaithist $cwait]}] @@ -438,9 +452,9 @@ namespace eval tst_mig { } set rval "" append rval [format "cwait: min: %3d max: %3d avr: %6.1f" \ - $cwaitmin $cwaitmax [expr {$cwaitsum/(4.*$cnt)}]] + $cwaitmin $cwaitmax [expr {$cwaitsum/(1.*$tcnt)}]] append rval [format "\nrwait: min: %3d max: %3d avr: %6.1f" \ - $rwaitmin $rwaitmax [expr {$rwaitsum/(4.*$cnt)}]] + $rwaitmin $rwaitmax [expr {$rwaitsum/(1.*$tcnt)}]] append rval "\ndistribution histogram:" append rval "\n time: cwait rwait" for {set i 0} { $i <= $waitmax } {incr i} { diff --git a/tools/vivado/viv_tools_build.tcl b/tools/vivado/viv_tools_build.tcl index 3eea59ef..b4707b95 100644 --- a/tools/vivado/viv_tools_build.tcl +++ b/tools/vivado/viv_tools_build.tcl @@ -1,10 +1,11 @@ -# $Id: viv_tools_build.tcl 1090 2018-12-21 12:17:35Z mueller $ +# $Id: viv_tools_build.tcl 1099 2018-12-31 09:07:36Z mueller $ # # Copyright 2015-2018 by Walter F.J. Mueller # License disclaimer see License.txt in $RETROBASE directory # # Revision History: # Date Rev Version Comment +# 2018-12-30 1099 1.2.4 downgrade SSN critical warnings to warnings # 2018-12-19 1090 1.2.3 export log and rpt generated in OOC synthesis runs # 2018-11-18 1072 1.2.2 increase message limits (all 200, some 5000) # 2016-09-18 809 1.2.1 keep hierarchy for synthesis only runs @@ -149,9 +150,9 @@ proc rvtb_default_build {stem step} { # general setups ----------------------------------------- # suppress message which don't convey useful information - set_msg_config -suppress -id {DRC 23-20}; # DSP48 output pilelining - set_msg_config -suppress -id {Project 1-120}; # WebTalk mandatory - set_msg_config -suppress -id {Common 17-186}; # WebTalk info send + set_msg_config -suppress -id {[DRC 23-20]}; # DSP48 output pilelining + set_msg_config -suppress -id {[Project 1-120]}; # WebTalk mandatory + set_msg_config -suppress -id {[Common 17-186]}; # WebTalk info send # set message default limit to 200 (buildin default is 100) set_param messaging.defaultLimit 200 # set message limit to 5000 for some cases @@ -159,6 +160,10 @@ proc rvtb_default_build {stem step} { # Synth 8-3332 : Sequential element xxx is unused .. removed from yyy set_msg_config -id {[Synth 8-3331]} -limit 5000 set_msg_config -id {[Synth 8-3332]} -limit 5000 + # downgrade 'exceed allowable noise margins' from 'critical' to 'warnings' + # otherwise some MIG designs will not accepted to generate a bit file + # see https://www.xilinx.com/support/answers/36141.html + set_msg_config -id {[Designutils 20-923]} -new_severity {WARNING} # Setup list of extra synthesis options (for later rodinMoreOptions) set synth_more_opts {}