diff --git a/doc/CHANGELOG.md b/doc/CHANGELOG.md
index 0fcf9af2..93ba942d 100644
--- a/doc/CHANGELOG.md
+++ b/doc/CHANGELOG.md
@@ -27,11 +27,14 @@ The full set of tests is only run for tagged releases.
 
 ### Summary
 - cleanup tbrun setup, drop nexys4 and add nexys4d ([see blog](https://wfjm.github.io/blogs/w11/2019-07-27-nexys4-obituary.html))
+- add fast mac-only verification codes under tool/tcode, integrated with tbrun
 - add ostest support for rsx11m-31_rk, rsx11m-40_rk and rsx11mp-30_rp oskits
 - all actively used commands have now a man page
 - Doxygen support now for V1.9.4; remove discontinued Tcl support
 - build flow Vivado 2022.1 ready; handle synth 8-3331 -> 8-7129 transition
 ### New features
+- new verification codes
+  - tools/tcode: fast cpu verification codes
 ### Changes
 - tools changes
   - ci.yml: define TBW_GHDL_OPTS and suppress IEEE package warnings at t=0ms
@@ -40,6 +43,8 @@ The full set of tests is only run for tagged releases.
     - njobihtm: add -n and -h options
     - ti_w11: update --help text, add -ar,-n4d,-bn4d
     - tmuconv: add DEUNA defs
+  - tools/tcl
+    - w11/tcodes.tcl: driver for tcode execution
   - tools/dox
     - w11_(cpp|vhd_all).Doxyfile: for Doxygen V1.9.4
     - w11_tcl.Doxyfile: removed, Tcl support removed in Doxygen V1.8.18
@@ -48,6 +53,8 @@ The full set of tests is only run for tagged releases.
 ### Bug Fixes
   - tools/mcode
     - m9312/bootw11.mac: proper init of unit number in getnam
+  - src/librwxxtpp
+    - RtclRw11Cpu.cpp: quit before mem write if asm-11 error seen
 
 <!-- --------------------------------------------------------------------- -->
 ---
diff --git a/rtl/sys_gen/w11a/arty/tb/tbrun.yml b/rtl/sys_gen/w11a/arty/tb/tbrun.yml
index 5a9c7f60..8d35da39 100644
--- a/rtl/sys_gen/w11a/arty/tb/tbrun.yml
+++ b/rtl/sys_gen/w11a/arty/tb/tbrun.yml
@@ -1,7 +1,8 @@
-# $Id: tbrun.yml 1071 2018-11-17 20:53:26Z mueller $
+# $Id: tbrun.yml 1249 2022-07-08 06:27:59Z mueller $
 #
 # Revision History:
 # Date         Rev Version  Comment
+# 2022-07-07  1249   1.1    add rw11::tcodes @cpu_all.dat
 # 2018-11-17  1071   1.0    Initial version
 #
 - default:
@@ -27,3 +28,8 @@
   test: |
     tbrun_tbwrri --hxon --lsuf tbdev  --pack rw11  tb_w11a_arty${ms} \
       "rw11::setup_cpu" "rw11::tbench @dev_all.dat"
+
+- tag:  [default, viv, sys_w11a, arty, tccpu]
+  test: |
+    tbrun_tbwrri --hxon --lsuf tccpu  --pack rw11  tb_w11a_arty${ms} \
+      "rw11::setup_cpu" "rw11::tcodes @cpu_all.dat"
diff --git a/rtl/sys_gen/w11a/arty_bram/tb/tbrun.yml b/rtl/sys_gen/w11a/arty_bram/tb/tbrun.yml
index 2f51856b..c3e43add 100644
--- a/rtl/sys_gen/w11a/arty_bram/tb/tbrun.yml
+++ b/rtl/sys_gen/w11a/arty_bram/tb/tbrun.yml
@@ -1,7 +1,8 @@
-# $Id: tbrun.yml 916 2017-06-25 13:30:07Z mueller $
+# $Id: tbrun.yml 1249 2022-07-08 06:27:59Z mueller $
 #
 # Revision History:
 # Date         Rev Version  Comment
+# 2022-07-07  1249   1.2    add rw11::tcodes @cpu_all.dat
 # 2017-06-25   916   1.1    retire mem70 - now in tbcpu
 # 2016-09-18   809   1.0.1  use 60 sec tout for run_pdpcp tb_pdp11core_stim
 # 2016-08-21   799   1.0    Initial version
@@ -29,3 +30,8 @@
   test: |
     tbrun_tbwrri --hxon --lsuf tbdev  --pack rw11  tb_w11a_br_arty${ms} \
       "rw11::setup_cpu" "rw11::tbench @dev_all.dat"
+
+- tag:  [default, viv, sys_w11a, br_arty, tccpu]
+  test: |
+    tbrun_tbwrri --hxon --lsuf tccpu  --pack rw11  tb_w11a_br_arty${ms} \
+      "rw11::setup_cpu" "rw11::tcodes @cpu_all.dat"
diff --git a/rtl/sys_gen/w11a/artys7/tb/tbrun.yml b/rtl/sys_gen/w11a/artys7/tb/tbrun.yml
index 9ab1331b..685d5082 100644
--- a/rtl/sys_gen/w11a/artys7/tb/tbrun.yml
+++ b/rtl/sys_gen/w11a/artys7/tb/tbrun.yml
@@ -1,7 +1,8 @@
-# $Id: tbrun.yml 1105 2019-01-12 19:52:45Z mueller $
+# $Id: tbrun.yml 1249 2022-07-08 06:27:59Z mueller $
 #
 # Revision History:
 # Date         Rev Version  Comment
+# 2022-07-07  1249   1.1    add rw11::tcodes @cpu_all.dat
 # 2019-01-12  1105   1.0    Initial version
 #
 - default:
@@ -27,3 +28,8 @@
   test: |
     tbrun_tbwrri --hxon --lsuf tbdev  --pack rw11  tb_w11a_as7${ms} \
       "rw11::setup_cpu" "rw11::tbench @dev_all.dat"
+
+- tag:  [viv, sys_w11a, as7, tccpu]
+  test: |
+    tbrun_tbwrri --hxon --lsuf tccpu  --pack rw11  tb_w11a_as7${ms} \
+      "rw11::setup_cpu" "rw11::tcodes @cpu_all.dat"
diff --git a/rtl/sys_gen/w11a/artys7_bram/tb/tbrun.yml b/rtl/sys_gen/w11a/artys7_bram/tb/tbrun.yml
index 4e801fe4..061493bf 100644
--- a/rtl/sys_gen/w11a/artys7_bram/tb/tbrun.yml
+++ b/rtl/sys_gen/w11a/artys7_bram/tb/tbrun.yml
@@ -1,7 +1,8 @@
-# $Id: tbrun.yml 1038 2018-08-11 12:39:52Z mueller $
+# $Id: tbrun.yml 1249 2022-07-08 06:27:59Z mueller $
 #
 # Revision History:
 # Date         Rev Version  Comment
+# 2022-07-07  1249   1.1    add rw11::tcodes @cpu_all.dat
 # 2018-08-11  1038   1.0    Initial version
 #
 - default:
@@ -27,3 +28,8 @@
   test: |
     tbrun_tbwrri --hxon --lsuf tbdev  --pack rw11  tb_w11a_br_as7${ms} \
       "rw11::setup_cpu" "rw11::tbench @dev_all.dat"
+
+- tag:  [viv, sys_w11a, br_as7, tccpu]
+  test: |
+    tbrun_tbwrri --hxon --lsuf tccpu  --pack rw11  tb_w11a_br_as7${ms} \
+      "rw11::setup_cpu" "rw11::tcodes @cpu_all.dat"
diff --git a/rtl/sys_gen/w11a/basys3/tb/tbrun.yml b/rtl/sys_gen/w11a/basys3/tb/tbrun.yml
index 598f472b..642d2c31 100644
--- a/rtl/sys_gen/w11a/basys3/tb/tbrun.yml
+++ b/rtl/sys_gen/w11a/basys3/tb/tbrun.yml
@@ -1,7 +1,8 @@
-# $Id: tbrun.yml 916 2017-06-25 13:30:07Z mueller $
+# $Id: tbrun.yml 1249 2022-07-08 06:27:59Z mueller $
 #
 # Revision History:
 # Date         Rev Version  Comment
+# 2022-07-07  1249   1.3    add rw11::tcodes @cpu_all.dat
 # 2017-06-25   916   1.2    retire mem70 - now in tbcpu
 # 2016-09-18   809   1.0.1  use 60 sec tout for run_pdpcp tb_pdp11core_stim
 # 2016-08-13   798   1.0    Initial version
@@ -29,3 +30,8 @@
   test: |
     tbrun_tbwrri --hxon --lsuf tbdev  --pack rw11  tb_w11a_b3${ms} \
       "rw11::setup_cpu" "rw11::tbench @dev_all.dat"
+
+- tag:  [default, viv, sys_w11a, b3, tccpu]
+  test: |
+    tbrun_tbwrri --hxon --lsuf tccpu  --pack rw11  tb_w11a_b3${ms} \
+      "rw11::setup_cpu" "rw11::tcodes @cpu_all.dat"
diff --git a/rtl/sys_gen/w11a/cmoda7/tb/tbrun.yml b/rtl/sys_gen/w11a/cmoda7/tb/tbrun.yml
index 2d50c392..2950b4f1 100644
--- a/rtl/sys_gen/w11a/cmoda7/tb/tbrun.yml
+++ b/rtl/sys_gen/w11a/cmoda7/tb/tbrun.yml
@@ -1,7 +1,8 @@
-# $Id: tbrun.yml 916 2017-06-25 13:30:07Z mueller $
+# $Id: tbrun.yml 1249 2022-07-08 06:27:59Z mueller $
 #
 # Revision History:
 # Date         Rev Version  Comment
+# 2022-07-07  1249   1.1    add rw11::tcodes @cpu_all.dat
 # 2017-06-24   914   1.0    Initial version
 #
 - default:
@@ -27,3 +28,8 @@
   test: |
     tbrun_tbwrri --hxon --lsuf tbdev  --pack rw11  tb_w11a_c7${ms} \
       "rw11::setup_cpu" "rw11::tbench @dev_all.dat"
+
+- tag:  [default, viv, sys_w11a, c7, tccpu]
+  test: |
+    tbrun_tbwrri --hxon --lsuf tccpu  --pack rw11  tb_w11a_c7${ms} \
+      "rw11::setup_cpu" "rw11::tcodes @cpu_all.dat"
diff --git a/rtl/sys_gen/w11a/nexys2/tb/tbrun.yml b/rtl/sys_gen/w11a/nexys2/tb/tbrun.yml
index 5c36c76a..e38031f3 100644
--- a/rtl/sys_gen/w11a/nexys2/tb/tbrun.yml
+++ b/rtl/sys_gen/w11a/nexys2/tb/tbrun.yml
@@ -1,7 +1,8 @@
-# $Id: tbrun.yml 916 2017-06-25 13:30:07Z mueller $
+# $Id: tbrun.yml 1249 2022-07-08 06:27:59Z mueller $
 #
 # Revision History:
 # Date         Rev Version  Comment
+# 2022-07-07  1249   1.3    add rw11::tcodes @cpu_all.dat
 # 2017-06-25   916   1.2    retire mem70,mem70_n2 - now in tbcpu
 # 2016-09-18   809   1.1.1  use 60 sec tout for run_pdpcp tb_pdp11core_stim
 # 2016-08-28   803   1.1    use ${ise_modes_noisim} when ISim can't be used
@@ -30,3 +31,8 @@
   test: |
     tbrun_tbwrri --cuff --lsuf tbdev --pack rw11  tb_w11a_n2${ms} \
       "rw11::setup_cpu" "rw11::tbench @dev_all.dat"
+
+- tag:  [default, ise, sys_w11a, n2, tccpu]
+  test: |
+    tbrun_tbwrri --cuff --lsuf tccpu --pack rw11  tb_w11a_n2${ms} \
+      "rw11::setup_cpu" "rw11::tcodes @cpu_all.dat"
diff --git a/rtl/sys_gen/w11a/nexys3/tb/tbrun.yml b/rtl/sys_gen/w11a/nexys3/tb/tbrun.yml
index 4c9ebb71..16b45e89 100644
--- a/rtl/sys_gen/w11a/nexys3/tb/tbrun.yml
+++ b/rtl/sys_gen/w11a/nexys3/tb/tbrun.yml
@@ -1,7 +1,8 @@
-# $Id: tbrun.yml 916 2017-06-25 13:30:07Z mueller $
+# $Id: tbrun.yml 1249 2022-07-08 06:27:59Z mueller $
 #
 # Revision History:
 # Date         Rev Version  Comment
+# 2022-07-07  1249   1.3    add rw11::tcodes @cpu_all.dat
 # 2017-06-25   916   1.2    retire mem70,mem70_n2 - now in tbcpu
 # 2016-09-18   809   1.1.1  use 60 sec tout for run_pdpcp tb_pdp11core_stim
 # 2016-08-28   803   1.1    use ${ise_modes_noisim} when ISim can't be used
@@ -30,3 +31,8 @@
   test: |
     tbrun_tbwrri --cuff --lsuf tbdev --pack rw11  tb_w11a_n3${ms} \
       "rw11::setup_cpu" "rw11::tbench @dev_all.dat"
+
+- tag:  [default, ise, sys_w11a, n3, tccpu]
+  test: |
+    tbrun_tbwrri --cuff --lsuf tccpu --pack rw11  tb_w11a_n3${ms} \
+      "rw11::setup_cpu" "rw11::tcodes @cpu_all.dat"
diff --git a/rtl/sys_gen/w11a/nexys4/tb/tbrun.yml b/rtl/sys_gen/w11a/nexys4/tb/tbrun.yml
index 5d60db84..c7b74377 100644
--- a/rtl/sys_gen/w11a/nexys4/tb/tbrun.yml
+++ b/rtl/sys_gen/w11a/nexys4/tb/tbrun.yml
@@ -1,7 +1,8 @@
-# $Id: tbrun.yml 1201 2019-08-10 16:51:22Z mueller $
+# $Id: tbrun.yml 1249 2022-07-08 06:27:59Z mueller $
 #
 # Revision History:
 # Date         Rev Version  Comment
+# 2022-07-07  1249   1.3    add rw11::tcodes @cpu_all.dat
 # 2019-08-10  1201   1.2.1  remove n4 from default
 # 2017-06-25   916   1.2    retire mem70,mem70_n2 - now in tbcpu
 # 2016-09-18   809   1.0.1  use 60 sec tout for run_pdpcp tb_pdp11core_stim
@@ -30,3 +31,8 @@
   test: |
     tbrun_tbwrri --lsuf tbdev  --pack rw11  tb_w11a_n4${ms} \
       "rw11::setup_cpu" "rw11::tbench @dev_all.dat"
+
+- tag:  [viv, sys_w11a, n4, tccpu]
+  test: |
+    tbrun_tbwrri --lsuf tccpu  --pack rw11  tb_w11a_n4${ms} \
+      "rw11::setup_cpu" "rw11::tcodes @cpu_all.dat"
diff --git a/rtl/sys_gen/w11a/nexys4d/tb/tbrun.yml b/rtl/sys_gen/w11a/nexys4d/tb/tbrun.yml
index abbd2641..31090f29 100644
--- a/rtl/sys_gen/w11a/nexys4d/tb/tbrun.yml
+++ b/rtl/sys_gen/w11a/nexys4d/tb/tbrun.yml
@@ -1,7 +1,8 @@
-# $Id: tbrun.yml 1201 2019-08-10 16:51:22Z mueller $
+# $Id: tbrun.yml 1249 2022-07-08 06:27:59Z mueller $
 #
 # Revision History:
 # Date         Rev Version  Comment
+# 2022-07-07  1249   1.1    add rw11::tcodes @cpu_all.dat
 # 2019-08-10  1201   1.0.1  add n4d to default
 # 2019-01-02  1101   1.0    Initial version
 #
@@ -28,3 +29,8 @@
   test: |
     tbrun_tbwrri --lsuf tbdev  --pack rw11  tb_w11a_n4d${ms} \
       "rw11::setup_cpu" "rw11::tbench @dev_all.dat"
+
+- tag:  [default, viv, sys_w11a, n4d, tccpu]
+  test: |
+    tbrun_tbwrri --lsuf tccpu  --pack rw11  tb_w11a_n4d${ms} \
+      "rw11::setup_cpu" "rw11::tcodes @cpu_all.dat"
diff --git a/rtl/sys_gen/w11a/nexys4d_bram/tb/tbrun.yml b/rtl/sys_gen/w11a/nexys4d_bram/tb/tbrun.yml
index 604dbc4d..9219108c 100644
--- a/rtl/sys_gen/w11a/nexys4d_bram/tb/tbrun.yml
+++ b/rtl/sys_gen/w11a/nexys4d_bram/tb/tbrun.yml
@@ -1,8 +1,9 @@
-# $Id: tbrun.yml 916 2017-06-25 13:30:07Z mueller $
+# $Id: tbrun.yml 1249 2022-07-08 06:27:59Z mueller $
 #
 # Revision History:
 # Date         Rev Version  Comment
-# 2017-06-25   916   1.2    retire mem70 - now in tbcpu
+# 2022-07-07  1249   1.2    add rw11::tcodes @cpu_all.dat
+# 2017-06-25   916   1.1    retire mem70 - now in tbcpu
 # 2017-01-04   800   1.0    Initial version
 #
 - default:
@@ -28,3 +29,8 @@
   test: |
     tbrun_tbwrri --lsuf tbdev  --pack rw11  tb_w11a_br_n4d${ms} \
       "rw11::setup_cpu" "rw11::tbench @dev_all.dat"
+
+- tag:  [viv, sys_w11a, br_n4d, tccpu]
+  test: |
+    tbrun_tbwrri --lsuf tccpu  --pack rw11  tb_w11a_br_n4d${ms} \
+      "rw11::setup_cpu" "rw11::tcodes @cpu_all.dat"
diff --git a/rtl/sys_gen/w11a/s3board/tb/tbrun.yml b/rtl/sys_gen/w11a/s3board/tb/tbrun.yml
index 1831b715..0d28be00 100644
--- a/rtl/sys_gen/w11a/s3board/tb/tbrun.yml
+++ b/rtl/sys_gen/w11a/s3board/tb/tbrun.yml
@@ -1,7 +1,8 @@
-# $Id: tbrun.yml 916 2017-06-25 13:30:07Z mueller $
+# $Id: tbrun.yml 1249 2022-07-08 06:27:59Z mueller $
 #
 # Revision History:
 # Date         Rev Version  Comment
+# 2022-07-07  1249   1.3    add rw11::tcodes @cpu_all.dat
 # 2017-06-25   916   1.2    retire mem70,mem70_s3 - now in tbcpu; add --fusp
 # 2016-09-18   809   1.1.1  use 60 sec tout for run_pdpcp tb_pdp11core_stim
 # 2016-08-28   803   1.1    use ${ise_modes_noisim} when ISim can't be used
@@ -30,3 +31,8 @@
   test: |
     tbrun_tbwrri --fusp --lsuf tbdev --pack rw11  tb_w11a_s3${ms} \
       "rw11::setup_cpu" "rw11::tbench @dev_all.dat"
+
+- tag:  [default, ise, sys_w11a, s3, tccpu]
+  test: |
+    tbrun_tbwrri --fusp --lsuf tccpu --pack rw11  tb_w11a_s3${ms} \
+      "rw11::setup_cpu" "rw11::tcodes @cpu_all.dat"
diff --git a/tools/README.md b/tools/README.md
index 8fe9b438..81cc60e6 100644
--- a/tools/README.md
+++ b/tools/README.md
@@ -16,5 +16,6 @@ This directory tree contains **many tools** and is organized in
 | [src](src)       | C++ sources for rlink backend |
 | [sys](sys)       | udev rules for USB device handling |
 | [tbench](tbench) | w11 test bench |
+| [tcode](tcode)   | w11 test codes |
 | [tcl](tcl)       | TCL sources for rlink backend |
 | [vivado](vivado) | scripts for Xilinx Vivado |
diff --git a/tools/src/librwxxtpp/RtclRw11Cpu.cpp b/tools/src/librwxxtpp/RtclRw11Cpu.cpp
index 91569714..a1b39524 100644
--- a/tools/src/librwxxtpp/RtclRw11Cpu.cpp
+++ b/tools/src/librwxxtpp/RtclRw11Cpu.cpp
@@ -1,9 +1,10 @@
-// $Id: RtclRw11Cpu.cpp 1175 2019-06-30 06:13:17Z mueller $
+// $Id: RtclRw11Cpu.cpp 1249 2022-07-08 06:27:59Z mueller $
 // SPDX-License-Identifier: GPL-3.0-or-later
-// Copyright 2013-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+// Copyright 2013-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 // 
 // Revision History: 
 // Date         Rev Version  Comment
+// 2022--7-07  1249   1.2.34 BUGFIX: quit before mem write if asm-11 error seen
 // 2019-06-29  1175   1.2.33 M_ldabs(): add missing OptValid() call
 // 2019-06-07  1160   1.2.32 use RtclStats::Exec()
 // 2019-04-30  1143   1.2.31 add HasM9312() getter
@@ -1213,8 +1214,14 @@ int RtclRw11Cpu::M_ldasm(RtclArgs& args)
     if (!Rtcl::SetVar(interp, varlst, Rtcl::NewLinesObj(los))) return kERR;
   }
 
-  // now, finally, iterate over cmap and write code to memory
+  // in case of asm-11 error quit (after lst and sym processing)
+  if (wexit != 0) {
+    args.AppendResultLines("asm-11 compilation failed with:");
+    args.AppendResultLines(eos);
+    return kERR;
+  }
 
+  // now, finally, iterate over cmap and write code to memory
   vector<uint16_t> block;
   uint16_t base = 0;
   dot = 0;
@@ -1237,12 +1244,6 @@ int RtclRw11Cpu::M_ldasm(RtclArgs& args)
     block.clear();
   }
 
-  if (wexit != 0) {
-    args.AppendResultLines("asm-11 compilation failed with:");
-    args.AppendResultLines(eos);
-    return kERR;
-  }
-
   return kOK;
 }
 
diff --git a/tools/tcl/rw11/tbench.tcl b/tools/tcl/rw11/tbench.tcl
index be43d481..28144f82 100644
--- a/tools/tcl/rw11/tbench.tcl
+++ b/tools/tcl/rw11/tbench.tcl
@@ -1,6 +1,6 @@
-# $Id: tbench.tcl 1177 2019-06-30 12:34:07Z mueller $
+# $Id: tbench.tcl 1249 2022-07-08 06:27:59Z mueller $
 # SPDX-License-Identifier: GPL-3.0-or-later
-# Copyright 2013-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+# Copyright 2013-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 #
 #  Revision History:
 # Date         Rev Version  Comment
@@ -35,7 +35,7 @@ namespace eval rw11 {
   }
 
   #
-  # tbench_file: execute list of tbench steps
+  # tbench_list: execute list of tbench steps
   #
   proc tbench_list {tname tbase} {
     set errcnt 0
diff --git a/tools/tcl/rw11/tcodes.tcl b/tools/tcl/rw11/tcodes.tcl
new file mode 100644
index 00000000..988be556
--- /dev/null
+++ b/tools/tcl/rw11/tcodes.tcl
@@ -0,0 +1,134 @@
+# $Id: tcodes.tcl 1249 2022-07-08 06:27:59Z mueller $
+# SPDX-License-Identifier: GPL-3.0-or-later
+# Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+#
+#  Revision History:
+# Date         Rev Version  Comment
+# 2022-07-07  1249   1.0    Initial version (derived from tbench.tcl)
+#
+
+package provide rw11 1.0
+
+package require rlink
+package require rwxxtpp
+
+namespace eval rw11 {
+
+  #
+  # tcodes: driver for tcode execution
+  #
+  proc tcodes {tname} {
+    set fname $tname
+    set tbase "."
+    if {[string match "@*" $tname]} {
+      set fname [string range $tname 1 end]
+    }
+    if {![file exists $fname]} {set tbase "$::env(RETROBASE)/tools/tcode"}
+
+    rlink::anena 1;             # enable attn notify
+    set errcnt [tcodes_list $tname $tbase]
+    return $errcnt
+  }
+
+  #
+  # tcodes_list: execute list of tcodes
+  #
+  proc tcodes_list {tname tbase} {
+    set errcnt 0
+
+    set rname  $tname
+    set islist 0
+    if {[string match "@*" $tname]} {
+      set islist 1
+      set rname [string range $tname 1 end]
+    }
+
+    set dname [file dirname $rname]
+    set fname [file tail    $rname]
+    if {$dname ne "."} {
+      set tbase [file join $tbase $dname]
+    }
+
+    if {![file readable "$tbase/$fname"]} {
+      puts "-E: file $tbase/$fname not found or readable"
+      error "-E: file $tbase/$fname not found or readable"
+    }
+
+    if {$islist} {
+      set fh [open "$tbase/$fname"]
+      while {[gets $fh line] >= 0} {
+        set line [string trim $line];       # trim white space 
+        if {$line eq ""} {continue};        # skip empty lines
+        if {[string match "#*" $line]} {
+          if {[string match "##*" $line]} { rlc log -bare $line }
+        } elseif {[string match "@*" $line]} {
+          incr errcnt [tcodes_list $line $tbase]
+        } else {
+          incr errcnt [tcodes_exec $line $tbase]
+        }
+      }
+      close $fh
+
+    } else {
+      incr errcnt [tcodes_exec $fname $tbase]
+    }
+
+    if {$islist} {
+      rlc log -bare [format "%s: %s" $tname [rutil::errcnt2txt $errcnt]]
+    }
+    return $errcnt
+  }
+
+  #
+  # tcodes_exec: execute single tcode
+  #
+  proc tcodes_exec {fname tbase} {
+    if {![file readable "$tbase/$fname"]} {
+      error "-E: file $tbase/$fname not found or readable"
+    }
+
+    set cpu "cpu0"
+    set errcnt 0
+    set tout 100.;              # tcode timeout
+    set hascmon [$cpu get hascmon]
+    set mwsup 1;                # dmcmon
+    set imode 1;                # dmcmon
+    set nent 30;                # dmcmon: show last 30 instructions
+
+    if { [catch {$cpu ldasm -file "$tbase/$fname" -sym sym -lst lst} errmsg] } {
+      rlc log -error "$fname FAILed to compile"
+      rlc log -bare $errmsg
+      rlc log -bare [format "%s: %s" $fname "FAIL"]
+      return 1
+    }
+
+    if {$hascmon} {rw11::cm_start $cpu mwsup $mwsup imode $imode}
+    rw11::asmrun  $cpu sym
+    
+    set dt [$cpu wtcpu -reset $tout]
+    if {$hascmon} {rw11::cm_stop}
+    
+    if {$dt < 0.} {
+      rlc log -error "$fname FAILed with timeout after $tout s"
+      incr errcnt 1
+    } else {
+      $cpu cp -rpc rpc
+      if {$rpc != $sym(stop)} {
+        rlc log -error [format "%s FAILed with HALT at %06o" $fname $rpc]
+        incr errcnt 1
+      }
+    }
+
+    if {$errcnt > 0} {                  # in case of an error
+      rlc log -bare [$cpu show -r0ps];  # show registers 
+      if {$hascmon} {                   # show last instructions if cmon present
+        set cmraw [rw11::cm_read $cpu $nent]
+        rlc log -bare [rw11::cm_print $cmraw]
+      }
+    }
+ 
+    rlc log -bare [format "%s: %s" $fname [rutil::errcnt2txt $errcnt]]
+    return $errcnt
+  }
+
+}
diff --git a/tools/tcode/.gitignore b/tools/tcode/.gitignore
new file mode 100644
index 00000000..2529100b
--- /dev/null
+++ b/tools/tcode/.gitignore
@@ -0,0 +1,7 @@
+*.cof
+*.lst
+
+# simulation stuff
+rlink_cext_conf
+rlink_cext_fifo_rx
+rlink_cext_fifo_tx
diff --git a/tools/tcode/README.md b/tools/tcode/README.md
new file mode 100644
index 00000000..f31480d7
--- /dev/null
+++ b/tools/tcode/README.md
@@ -0,0 +1 @@
+This directory contains the **w11 test codes**
diff --git a/tools/tcode/cpu_all.dat b/tools/tcode/cpu_all.dat
new file mode 100644
index 00000000..ea589ef4
--- /dev/null
+++ b/tools/tcode/cpu_all.dat
@@ -0,0 +1,5 @@
+# $Id: cpu_all.dat 1249 2022-07-08 06:27:59Z mueller $
+#
+## steering file for all cpu tests
+#
+cpu_basics.mac
diff --git a/tools/tcode/cpu_basics.mac b/tools/tcode/cpu_basics.mac
new file mode 100644
index 00000000..c049876c
--- /dev/null
+++ b/tools/tcode/cpu_basics.mac
@@ -0,0 +1,1369 @@
+; $Id: cpu_basics.mac 1249 2022-07-08 06:27:59Z mueller $
+; SPDX-License-Identifier: GPL-3.0-or-later
+; Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+;
+; Revision History:
+; Date         Rev Version  Comment
+; 2015-08-30   710   0.1    First draft
+;
+; Test CPU basics
+;
+        .include        |lib/tcode_std_base.mac|
+;
+; Section A: ccops + flow control bxx, sob, jmp, jsr, rts, mark ==============
+;
+; Test A1.1 -- ccop + bxx ++++++++++++++++++++++++++++++++++++++++++++++++++++
+;   This sub-section verifies
+;     x xxx xxx xxx xxx xxx NZVC Instruction / Remark
+;     0 000 000 010 10n zvc NZVC CLx
+;     0 000 000 010 11n zvc NZVC SEx
+;
+;     0 000 000 1bb bbb bbb ---- BR  always
+;
+;     0 000 001 0bb bbb bbb ---- BNE if Z = 0
+;     0 000 001 1bb bbb bbb ---- BEQ if Z = 1
+;     0 000 010 0bb bbb bbb ---- BGE if (N xor V) = 0
+;     0 000 010 1bb bbb bbb ---- BLT if (N xor V) = 1
+;     0 000 011 0bb bbb bbb ---- BGT if (Z or (N xor V)) = 0
+;     0 000 011 1bb bbb bbb ---- BLE if (Z or (N xor V)) = 1
+;
+;     1 000 000 0bb bbb bbb ---- BPL  if N = 0
+;     1 000 000 1bb bbb bbb ---- BMI  if N = 1
+;     1 000 001 0bb bbb bbb ---- BHI  if (C or Z) = 0
+;     1 000 001 1bb bbb bbb ---- BLOS if (C or Z) = 1
+;     1 000 010 0bb bbb bbb ---- BVC  if V = 0
+;     1 000 010 1bb bbb bbb ---- BVS  if V = 1
+;     1 000 011 0bb bbb bbb ---- BCC  if C = 0
+;     1 000 011 1bb bbb bbb ---- BCS  if C = 1
+;
+;   This test sets all possible combinations of condition code bits
+;   (with cc ops) and verifies the branch instruction response
+;   Note: after normal compares N will never be 1 if Z=1 (a number can not
+;         zero and negative simultaneously). Thus not all combinations are
+;         used in normal code execution. 
+;
+ta0101: clr     @#cp.psw
+        ;
+        ; case NZVC = 0000 -- N=0 Z=0 V=0 C=0 ------------------------
+        ;
+        ccc
+        ;
+        ;
+        bne     1$              ; yes Z=0
+        halt
+1$:     beq     99$             ; no  Z=1
+        ;
+2$:     bge     3$              ; yes (N xor V) = 0
+        halt
+3$:     blt     99$             ; no  (N xor V) = 1
+        ;
+4$:     bgt     5$              ; yes (Z or (N xor V)) = 0
+        halt
+5$:     ble     99$             ; no  (Z or (N xor V)) = 1
+        ;
+6$:     bpl     7$              ; yes N = 0
+        halt
+7$:     bmi     99$             ; no  N = 1
+        ;
+8$:     bhi     9$              ; yes (C or Z) = 0
+        halt
+9$:     blos    99$             ; no  (C or Z) = 1
+        ;
+10$:    bvc     11$             ; yes V = 0
+        halt
+11$:    bvs     99$             ; no  V = 1
+        ;
+12$:    bcc     13$             ; yes C = 0
+        halt
+13$:    bcs     99$             ; no  C = 1
+        ;
+14$:    br      100$
+99$:    halt
+        ;
+        ; case NZVC = 0001 -- N=0 Z=0 V=0 C=1 ------------------------
+        ;
+100$:   ccc
+        sec
+        ;
+        bne     101$            ; yes Z=0
+        halt
+101$:   beq     199$            ; no  Z=1
+        ;
+102$:   bge     103$            ; yes (N xor V) = 0
+        halt
+103$:   blt     199$            ; no  (N xor V) = 1
+        ;
+104$:   bgt     105$            ; yes (Z or (N xor V)) = 0
+        halt
+105$:   ble     199$            ; no  (Z or (N xor V)) = 1
+        ;
+106$:   bpl     107$            ; yes N = 0
+        halt
+107$:   bmi     199$            ; no  N = 1
+        ;
+108$:   bhi     199$            ; no  (C or Z) = 0
+        ;
+109$:   blos    110$            ; yes (C or Z) = 1
+        halt
+110$:   bvc     111$            ; yes V = 0
+        halt
+111$:   bvs     199$            ; no  V = 1
+        ;
+112$:   bcc     199$            ; no  C = 0
+        ;
+113$:   bcs     114$            ; yes C = 1
+        halt
+114$:   br      200$
+199$:   halt
+        ;
+        ; case NZVC = 0010 -- N=0 Z=0 V=1 C=0 ------------------------
+        ;
+200$:   ccc
+        sev
+        ;
+        bne     201$            ; yes Z=0
+        halt
+201$:   beq     299$            ; no  Z=1
+        ;
+202$:   bge     299$            ; no  (N xor V) = 0
+        ;
+203$:   blt     204$            ; yes (N xor V) = 1
+        halt
+204$:   bgt     299$            ; no  (Z or (N xor V)) = 0
+        ;
+205$:   ble     206$            ; yes (Z or (N xor V)) = 1
+        halt
+206$:   bpl     207$            ; yes N = 0
+        halt
+207$:   bmi     299$            ; no  N = 1
+        ;
+208$:   bhi     209$            ; yes (C or Z) = 0
+        halt
+209$:   blos    299$            ; no  (C or Z) = 1
+        ;
+210$:   bvc     299$            ; no  V = 0
+        ;
+211$:   bvs     212$            ; yes V = 1
+        halt
+212$:   bcc     213$            ; yes C = 0
+        halt
+213$:   bcs     299$            ; no  C = 1
+        ;
+214$:   br      300$
+299$:   halt
+        ;
+        ; case NZVC = 0011 -- N=0 Z=0 V=1 C=1 ------------------------
+        ;
+300$:   ccc
+        <sev!sec>
+        ;
+        bne     301$            ; yes Z=0
+        halt
+301$:   beq     399$            ; no  Z=1
+        ;
+302$:   bge     399$            ; no  (N xor V) = 0
+        ;
+303$:   blt     304$            ; yes (N xor V) = 1
+        halt
+304$:   bgt     399$            ; no  (Z or (N xor V)) = 0
+        ;
+305$:   ble     306$            ; yes (Z or (N xor V)) = 1
+        halt
+306$:   bpl     307$            ; yes N = 0
+        halt
+307$:   bmi     399$            ; no  N = 1
+        ;
+308$:   bhi     399$            ; no  (C or Z) = 0
+        ;
+309$:   blos    310$            ; yes (C or Z) = 1
+        halt
+310$:   bvc     399$            ; no  V = 0
+        ;
+311$:   bvs     312$            ; yes V = 1
+        halt
+312$:   bcc     399$            ; no  C = 0
+        ;
+313$:   bcs     314$            ; yes C = 1
+        halt
+314$:   br      400$
+399$:   halt
+        ;
+        ; case NZVC = 0100 -- N=0 Z=1 V=0 C=0 ------------------------
+        ;
+400$:   ccc
+        sez
+        ;
+        bne     499$            ; no  Z=0
+        ;
+401$:   beq     402$            ; yes Z=1
+        halt
+402$:   bge     403$            ; yes (N xor V) = 0
+        halt
+403$:   blt     499$            ; no  (N xor V) = 1
+        ;
+404$:   bgt     499$            ; no  (Z or (N xor V)) = 0
+        ;
+405$:   ble     406$            ; yes (Z or (N xor V)) = 1
+        halt
+406$:   bpl     407$            ; yes N = 0
+        halt
+407$:   bmi     499$            ; no  N = 1
+        ;
+408$:   bhi     499$            ; no  (C or Z) = 0
+        ;
+409$:   blos    410$            ; yes (C or Z) = 1
+        halt
+410$:   bvc     411$            ; yes V = 0
+        halt
+411$:   bvs     499$            ; no  V = 1
+        ;
+412$:   bcc     413$            ; yes C = 0
+        halt
+413$:   bcs     499$            ; no  C = 1
+        ;
+414$:   br      500$
+499$:   halt
+        ;
+        ; case NZVC = 0101 -- N=0 Z=1 V=0 C=1 ------------------------
+        ;
+500$:   ccc
+        <sez!sec>
+        ;
+        bne     599$            ; no  Z=0
+        ;
+501$:   beq     502$            ; yes Z=1
+        halt
+502$:   bge     503$            ; yes (N xor V) = 0
+        halt
+503$:   blt     599$            ; no  (N xor V) = 1
+        ;
+504$:   bgt     599$            ; no  (Z or (N xor V)) = 0
+        ;
+505$:   ble     506$            ; yes (Z or (N xor V)) = 1
+        halt
+506$:   bpl     507$            ; yes N = 0
+        halt
+507$:   bmi     599$            ; no  N = 1
+        ;
+508$:   bhi     599$            ; no  (C or Z) = 0
+        ;
+509$:   blos    510$            ; yes (C or Z) = 1
+        halt
+510$:   bvc     511$            ; yes V = 0
+        halt
+511$:   bvs     599$            ; no  V = 1
+        ;
+512$:   bcc     599$            ; no  C = 0
+        ;
+513$:   bcs     514$            ; yes C = 1
+        halt
+514$:   br      600$
+599$:   halt
+        ;
+        ; case NZVC = 0110 -- N=0 Z=1 V=1 C=0 ------------------------
+        ;
+600$:   ccc
+        <sez!sev>
+        ;
+        bne     699$            ; no  Z=0
+        ;
+601$:   beq     602$            ; yes Z=1
+        halt
+602$:   bge     699$            ; no  (N xor V) = 0
+        ;
+603$:   blt     604$            ; yes (N xor V) = 1
+        halt
+604$:   bgt     699$            ; no  (Z or (N xor V)) = 0
+        ;
+605$:   ble     606$            ; yes (Z or (N xor V)) = 1
+        halt
+606$:   bpl     607$            ; yes N = 0
+        halt
+607$:   bmi     699$            ; no  N = 1
+        ;
+608$:   bhi     699$            ; no  (C or Z) = 0
+        ;
+609$:   blos    610$            ; yes (C or Z) = 1
+        halt
+610$:   bvc     699$            ; no  V = 0
+        ;
+611$:   bvs     612$            ; yes V = 1
+        halt
+612$:   bcc     613$            ; yes C = 0
+        halt
+613$:   bcs     699$            ; no  C = 1
+        ;
+614$:   br      700$
+699$:   halt
+        ;
+        ; case NZVC = 0111 -- N=0 Z=1 V=1 C=1 ------------------------
+        ;
+700$:   scc
+        cln
+        ;
+        bne     799$            ; no  Z=0
+        ;
+701$:   beq     702$            ; yes Z=1
+        halt
+702$:   bge     799$            ; no  (N xor V) = 0
+        ;
+703$:   blt     704$            ; yes (N xor V) = 1
+        halt
+704$:   bgt     799$            ; no  (Z or (N xor V)) = 0
+        ;
+705$:   ble     706$            ; yes (Z or (N xor V)) = 1
+        halt
+706$:   bpl     707$            ; yes N = 0
+        halt
+707$:   bmi     799$            ; no  N = 1
+        ;
+708$:   bhi     799$            ; no  (C or Z) = 0
+        ;
+709$:   blos    710$            ; yes (C or Z) = 1
+        halt
+710$:   bvc     799$            ; no  V = 0
+        ;
+711$:   bvs     712$            ; yes V = 1
+        halt
+712$:   bcc     799$            ; no  C = 0
+        ;
+713$:   bcs     714$            ; yes C = 1
+        halt
+714$:   br      1000$
+799$:   halt
+        ;
+        ; case NZVC = 1000 -- N=1 Z=0 V=0 C=0 ------------------------
+        ;
+1000$:  ccc
+        sen
+        ;
+        bne     1001$           ; yes Z=0
+        halt
+1001$:  beq     1099$           ; no  Z=1
+        ;
+1002$:  bge     1099$           ; no  (N xor V) = 0
+        ;
+1003$:  blt     1004$           ; yes (N xor V) = 1
+        halt
+1004$:  bgt     1099$           ; no  (Z or (N xor V)) = 0
+        ;
+1005$:  ble     1006$           ; yes (Z or (N xor V)) = 1
+        halt
+1006$:  bpl     1099$           ; no  N = 0
+        ;
+1007$:  bmi     1008$           ; yes N = 1
+        halt
+1008$:  bhi     1009$           ; yes (C or Z) = 0
+        halt
+1009$:  blos    1099$           ; no  (C or Z) = 1
+        ;
+1010$:  bvc     1011$           ; yes V = 0
+        halt
+1011$:  bvs     1099$           ; no  V = 1
+        ;
+1012$:  bcc     1013$           ; yes C = 0
+        halt
+1013$:  bcs     1099$           ; no  C = 1
+        ;
+1014$:  br      1100$
+1099$:  halt
+        ;
+        ; case NZVC = 1001 -- N=1 Z=0 V=0 C=1 ------------------------
+        ;
+1100$:  ccc
+        <sen!sec>
+        ;
+        bne     1101$           ; yes Z=0
+        halt
+1101$:  beq     1199$           ; no  Z=1
+        ;
+1102$:  bge     1199$           ; no  (N xor V) = 0
+        ;
+1103$:  blt     1104$           ; yes (N xor V) = 1
+        halt
+1104$:  bgt     1199$           ; no  (Z or (N xor V)) = 0
+        ;
+1105$:  ble     1106$           ; yes (Z or (N xor V)) = 1
+        halt
+1106$:  bpl     1199$           ; no  N = 0
+        ;
+1107$:  bmi     1108$           ; yes N = 1
+        halt
+1108$:  bhi     1199$           ; no  (C or Z) = 0
+        ;
+1109$:  blos    1110$           ; yes (C or Z) = 1
+        halt
+1110$:  bvc     1111$           ; yes V = 0
+        halt
+1111$:  bvs     1199$           ; no  V = 1
+        ;
+1112$:  bcc     1199$           ; no  C = 0
+        ;
+1113$:  bcs     1114$           ; yes C = 1
+        halt
+1114$:  br      1200$
+1199$:  halt
+        ;
+        ; case NZVC = 1010 -- N=1 Z=0 V=1 C=0 ------------------------
+        ;
+1200$:  ccc
+        <sen!sev>
+        ;
+        bne     1201$           ; yes Z=0
+        halt
+1201$:  beq     1299$           ; no  Z=1
+        ;
+1202$:  bge     1203$           ; yes (N xor V) = 0
+        halt
+1203$:  blt     1299$           ; no  (N xor V) = 1
+        ;
+1204$:  bgt     1205$           ; yes (Z or (N xor V)) = 0
+        halt
+1205$:  ble     1299$           ; no  (Z or (N xor V)) = 1
+        ;
+1206$:  bpl     1299$           ; no  N = 0
+        ;
+1207$:  bmi     1208$           ; yes N = 1
+        halt
+1208$:  bhi     1209$           ; yes (C or Z) = 0
+        halt
+1209$:  blos    1299$           ; no  (C or Z) = 1
+        ;
+1210$:  bvc     1299$           ; no  V = 0
+        ;
+1211$:  bvs     1212$           ; yes V = 1
+        halt
+1212$:  bcc     1213$           ; yes C = 0
+        halt
+1213$:  bcs     1299$           ; no  C = 1
+        ;
+1214$:  br      1300$
+1299$:  halt
+        ;
+        ; case NZVC = 1011 -- N=1 Z=0 V=1 C=1 ------------------------
+        ;
+1300$:  scc
+        clz
+        ;
+        bne     1301$           ; yes Z=0
+        halt
+1301$:  beq     1399$           ; no  Z=1
+        ;
+1302$:  bge     1303$           ; yes (N xor V) = 0
+        halt
+1303$:  blt     1399$           ; no  (N xor V) = 1
+        ;
+1304$:  bgt     1305$           ; yes (Z or (N xor V)) = 0
+        halt
+1305$:  ble     1399$           ; no  (Z or (N xor V)) = 1
+        ;
+1306$:  bpl     1399$           ; no  N = 0
+        ;
+1307$:  bmi     1308$           ; yes N = 1
+        halt
+1308$:  bhi     1399$           ; no  (C or Z) = 0
+        ;
+1309$:  blos    1310$           ; yes (C or Z) = 1
+        halt
+1310$:  bvc     1399$           ; no  V = 0
+        ;
+1311$:  bvs     1312$           ; yes V = 1
+        halt
+1312$:  bcc     1399$           ; no  C = 0
+        ;
+1313$:  bcs     1314$           ; yes C = 1
+        halt
+1314$:  br      1400$
+1399$:  halt
+        ;
+        ; case NZVC = 1100 -- N=1 Z=1 V=0 C=0 ------------------------
+        ;
+1400$:  ccc
+        <sen!sez>
+        ;
+        bne     1499$           ; no  Z=0
+        ;
+1401$:  beq     1402$           ; yes Z=1
+        halt
+1402$:  bge     1499$           ; no  (N xor V) = 0
+        ;
+1403$:  blt     1404$           ; yes (N xor V) = 1
+        halt
+1404$:  bgt     1499$           ; no  (Z or (N xor V)) = 0
+        ;
+1405$:  ble     1406$           ; yes (Z or (N xor V)) = 1
+        halt
+1406$:  bpl     1499$           ; no  N = 0
+        ;
+1407$:  bmi     1408$           ; yes N = 1
+        halt
+1408$:  bhi     1499$           ; no  (C or Z) = 0
+        ;
+1409$:  blos    1410$           ; yes (C or Z) = 1
+        halt
+1410$:  bvc     1411$           ; yes V = 0
+        halt
+1411$:  bvs     1499$           ; no  V = 1
+        ;
+1412$:  bcc     1413$           ; yes C = 0
+        halt
+1413$:  bcs     1499$           ; no  C = 1
+        ;
+1414$:  br      1500$
+1499$:  halt
+        ;
+        ; case NZVC = 1101 -- N=1 Z=1 V=0 C=1 ------------------------
+        ;
+1500$:  scc
+        clv
+        ;
+        bne     1599$           ; no  Z=0
+        ;
+1501$:  beq     1502$           ; yes Z=1
+        halt
+1502$:  bge     1599$           ; no  (N xor V) = 0
+        ;
+1503$:  blt     1504$           ; yes (N xor V) = 1
+        halt
+1504$:  bgt     1599$           ; no  (Z or (N xor V)) = 0
+        ;
+1505$:  ble     1506$           ; yes (Z or (N xor V)) = 1
+        halt
+1506$:  bpl     1599$           ; no  N = 0
+        ;
+1507$:  bmi     1508$           ; yes N = 1
+        halt
+1508$:  bhi     1599$           ; no  (C or Z) = 0
+        ;
+1509$:  blos    1510$           ; yes (C or Z) = 1
+        halt
+1510$:  bvc     1511$           ; yes V = 0
+        halt
+1511$:  bvs     1599$           ; no  V = 1
+        ;
+1512$:  bcc     1599$           ; no  C = 0
+        ;
+1513$:  bcs     1514$           ; yes C = 1
+        halt
+1514$:  br      1600$
+1599$:  halt
+        ;
+        ; case NZVC = 1110 -- N=1 Z=1 V=1 C=0 ------------------------
+        ;
+1600$:  scc
+        clc
+        ;
+        bne     1699$           ; no  Z=0
+        ;
+1601$:  beq     1602$           ; yes Z=1
+        halt
+1602$:  bge     1603$           ; yes (N xor V) = 0
+        halt
+1603$:  blt     1699$           ; no  (N xor V) = 1
+        ;
+1604$:  bgt     1699$           ; no  (Z or (N xor V)) = 0
+        ;
+1605$:  ble     1606$           ; yes (Z or (N xor V)) = 1
+        halt
+1606$:  bpl     1699$           ; no  N = 0
+        ;
+1607$:  bmi     1608$           ; yes N = 1
+        halt
+1608$:  bhi     1699$           ; no  (C or Z) = 0
+        ;
+1609$:  blos    1610$           ; yes (C or Z) = 1
+        halt
+1610$:  bvc     1699$           ; no  V = 0
+        ;
+1611$:  bvs     1612$           ; yes V = 1
+        halt
+1612$:  bcc     1613$           ; yes C = 0
+        halt
+1613$:  bcs     1699$           ; no  C = 1
+        ;
+1614$:  br      1700$
+1699$:  halt
+        ;
+        ; case NZVC = 1111 -- N=1 Z=1 V=1 C=1 ------------------------
+        ;
+1700$:  scc
+        ;
+        bne     1799$           ; no  Z=0
+        ;
+1701$:  beq     1702$           ; yes Z=1
+        halt
+1702$:  bge     1703$           ; yes (N xor V) = 0
+        halt
+1703$:  blt     1799$           ; no  (N xor V) = 1
+        ;
+1704$:  bgt     1799$           ; no  (Z or (N xor V)) = 0
+        ;
+1705$:  ble     1706$           ; yes (Z or (N xor V)) = 1
+        halt
+1706$:  bpl     1799$           ; no  N = 0
+        ;
+1707$:  bmi     1708$           ; yes N = 1
+        halt
+1708$:  bhi     1799$           ; no  (C or Z) = 0
+        ;
+1709$:  blos    1710$           ; yes (C or Z) = 1
+        halt
+1710$:  bvc     1799$           ; no  V = 0
+        ;
+1711$:  bvs     1712$           ; yes V = 1
+        halt
+1712$:  bcc     1799$           ; no  C = 0
+        ;
+1713$:  bcs     1714$           ; yes C = 1
+        ;
+1714$:  br      9999$
+1799$:  halt
+        ;
+;;;
+9999$:  iot                     ; end of test A1.1
+;
+; Test A1.2 -- ccop + psw ++++++++++++++++++++++++++++++++++++++++++++++++++++
+;   This test sets and clears all four condition codes and verifies that
+;   the psw properly reflects this.
+;
+ta0102: mov     #cp.psw,r0
+        clr     (r0)
+;
+        ccc                     ; nzvc = 0000
+        cmp     (r0),#cp0000
+        beq     .+4
+        halt
+;
+        ccc
+        sec                     ; nzvc = 0001
+        cmp     (r0),#cp000c
+        beq     .+4
+        halt
+;
+        ccc
+        sev                     ; nzvc = 0010
+        cmp     (r0),#cp00v0
+        beq     .+4
+        halt
+;
+        ccc
+        sez                     ; nzvc = 0100
+        cmp     (r0),#cp0z00
+        beq     .+4
+        halt
+;
+        ccc
+        sen                     ; nzvc = 1000
+        cmp     (r0),#cpn000
+        beq     .+4
+        halt
+;
+        scc                     ; nzvc = 1111
+        cmp     (r0),#cpnzvc
+        beq     .+4
+        halt
+;
+        scc
+        clc                     ; nzvc = 1110
+        cmp     (r0),#cpnzv0
+        beq     .+4
+        halt
+;
+        scc
+        clv                     ; nzvc = 1101
+        cmp     (r0),#cpnz0c
+        beq     .+4
+        halt
+;
+        scc
+        clz                     ; nzvc = 1011
+        cmp     (r0),#cpn0vc
+        beq     .+4
+        halt
+;
+        scc
+        cln                     ; nzvc = 0111
+        cmp     (r0),#cp0zvc
+        beq     .+4
+        halt
+;
+9999$:  iot                     ; end of test A1.2
+;
+; Test A2 -- sob +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+;   This sub-section verifies
+;     x xxx xxx xxx xxx xxx NZVC Instruction / Remark
+;     0 111 111 rrr bbb bbb ---- SOB
+;
+; Test A2.1 -- sob +++++++++++++++++++++++++++++++++++++++++++++++++++
+;   check that SOB
+;     a. decrements register
+;     b. does not change cc
+;     c. only falls through when register decremented to zero
+;
+ta0201: mov     #cp.psw,r5
+        clr     (r5)
+        mov     #3,r0           ; setup loop count
+        ccc                     ; nzvc = 0000
+        br      11$             ; branch to 1st SOB
+;
+10$:    cmp     (r5),#cp0000    ; cc still 0000 ?
+        beq     .+4
+        halt
+        cmp     r0,#2           ; counter dec-ed ?
+        beq     .+4
+        halt
+        scc                     ; now nzvc = 1111
+        br      21$             ; branch to 2nd SOB
+;
+11$:    sob     r0,10$          ; 1st SOB (r0=3)
+        halt                    ; should not fall through
+;
+20$:    cmp     (r5),#cpnzvc    ; cc still 1111 ?
+        beq     .+4
+        halt
+        cmp     r0,#1          ; counter dec-ed ?
+        beq     .+4
+        halt
+        ccc
+        <sen!sez>               ; now nzvc = 1100
+        br      31$             ; branch to 3rd SOB
+;
+21$:    sob     r0,20$          ; 2nd SOB (r0=2)
+        halt                    ; should not fall through
+;
+30$:    halt                    ; should not branch now !
+31$:    sob     r0,30$          ; 3rd SOB (r0=1 -> fall through)
+        cmp     (r5),#cpnz00    ; cc still 1100 ?
+        beq     .+4
+        halt
+        tst     r0              ; counter dec-ed ?
+        beq     .+4
+        halt
+;
+; finally a typical simple SOB loop
+;
+        mov     #2,r0
+        clr     r1
+100$:   inc     r1
+        sob     r0,100$
+;
+        tst     r0
+        beq     .+4
+        halt
+        cmp     r1,#2
+        beq     .+4
+        halt
+;
+9999$:  iot                     ; end of test A1.3
+;
+; Test A3 -- jmp +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+;   This sub-section verifies
+;     x xxx xxx xxx xxx xxx NZVC Instruction / Remark
+;     0 000 000 001 ddd ddd ---- JMP (mode /= R !!)
+;
+; Test A3.1 -- jmp + dsta +++++++++++++++++++++++++++++++++++++++++++++
+;   check that JMP works for all modes
+;
+ta0301: mov     #10$,r2
+        jmp     (r2)            ; mode = 1,reg
+        halt
+;
+10$:    mov     #20$,r2
+        jmp     (r2)+           ; mode = 2,reg
+        halt
+20$:    cmp     r2,#20$+2
+        beq     .+4
+        halt
+;
+        mov     #40$+2,r2
+        jmp     -(r2)           ; mode = 4,reg
+        halt
+40$:    cmp     r2,#40$
+        beq     .+4
+        halt
+;
+        mov     #60$-10,r2
+        jmp     10(r2)          ; mode = 6,reg
+;
+60$:    jmp     67$             ; mode = 6,pc  (rel)
+        halt
+;
+67$:    jmp     @#37$           ; mode = 3,pc  (abs)
+        halt
+;
+37$:    mov     #1030$,r3
+        jmp     @(r3)+          ; mode = 3,reg
+        halt
+30$:    cmp     r3,#1030$+2
+        beq     .+4
+        halt
+;
+        mov     #1050$+2,r3
+        jmp     @-(r3)          ; mode = 5,reg
+        halt
+50$:    cmp     r3,#1050$
+        beq     .+4
+        halt
+;
+        mov     #1070$-20,r3
+        jmp     @20(r3)         ; mode = 7,reg
+        halt
+;
+70$:    jmp     @1077$          ; mode = 7,pc  (ind)
+        halt
+;
+77$:    br      9999$
+;
+1030$:  .word   30$
+1050$:  .word   50$
+1070$:  .word   70$
+1077$:  .word   77$
+;        
+9999$:  iot                     ; end of test A3.1
+;
+; Test A3.2 -- jmp + cc +++++++++++++++++++++++++++++++++++++++++++++++
+;   check that JMP doesnt change cc
+;
+ta0302: mov     #cp.psw,r5
+        clr     (r5)
+;
+        ccc                     ; nzvc = 0000
+        jmp     1$
+        halt
+1$:     cmp     (r5),#cp0000    ; cc still 0000 ?
+        beq     .+4
+        halt
+;
+        scc                     ; nzvc = 1111
+        jmp     @1002$
+        halt
+2$:     cmp     (r5),#cpnzvc    ; cc still 1111 ?
+        beq     .+4
+        halt
+        br      9999$        
+;
+1002$:  .word   2$
+;
+9999$:  iot                     ; end of test A3.2
+;
+;
+; Section B: unary instructions ==============================================
+;
+        jmp     tb0101
+;
+; test driver for unary instruction tests
+;
+top1br: 
+top1wr: mov     (r5),101$       ; setup cc setter
+        mov     2(r5),102$      ; setup instruction
+        mov     4(r5),r4        ; setup expect data pointer
+        mov     6(r5),r3        ; setup expect end
+        mov     #cp.psw,r2
+;
+100$:   mov     (r4)+,r1        ; setup dst
+        ccc                     ; clear cc
+101$:   nop                     ; REPLACED with cc setter
+102$:   nop                     ; REPLACED with instruction, e.g. inc r1
+        cmp     (r2),(r4)+      ; check psw
+        beq     .+4
+        halt
+        cmp     r1,(r4)+        ; check new dst
+        beq     .+4
+        halt
+        cmp     r4,r3           ; more to do ?
+        blo     100$
+        rts     pc
+;
+top1bm: 
+top1wm: mov     (r5),101$       ; setup cc setter
+        mov     2(r5),102$      ; setup instruction
+        mov     4(r5),r4        ; setup expect data pointer
+        mov     6(r5),r3        ; setup expect end
+        mov     #200$,r1        ; setup dst pointer
+        mov     #cp.psw,r2
+;
+100$:   mov     (r4)+,(r1)      ; setup old dst
+        ccc                     ; clear cc
+101$:   nop                     ; REPLACED with cc setter
+102$:   nop                     ; REPLACED with instruction, e.g. inc (r1)
+        cmp     (r2),(r4)+      ; check psw
+        beq     .+4
+        halt
+        cmp     (r1),(r4)+      ; check new dst
+        beq     .+4
+        halt
+        cmp     r4,r3           ; more to do ?
+        blo     100$
+        rts     pc
+;
+200$:   .word   0
+;         
+; Test B1 -- inc +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+;   This sub-section verifies
+;     x xxx xxx xxx xxx xxx NZVC Instruction / Remark
+;     0 000 101 010 ddd ddd NZV- INC
+;
+; Test B1.1 -- inc instruction ++++++++++++++++++++++++++++++++++++++++
+;
+tb0101: clr     cp.psw
+        mov     #1000$,r5       ; reg mode tests
+        jsr     pc,top1wr
+        mov     #2000$,r5       ; mem mode tests
+        jsr     pc,top1wm
+        jmp     9999$
+;
+1000$:  ccc
+        inc     r1
+        .word   1010$
+        .word   1011$
+;
+;               olddst  psw     newdst
+1010$:  .word   000000, cp0000, 000001
+        .word   000001, cp0000, 000002
+        .word   077776, cp0000, 077777
+        .word   077777, cpn0v0, 100000
+        .word   100000, cpn000, 100001
+        .word   100001, cpn000, 100002
+        .word   177776, cpn000, 177777
+        .word   177777, cp0z00, 000000
+1011$:  
+;
+2000$:  scc
+        inc     (r1)
+        .word   2010$
+        .word   2011$
+;
+;               olddst     psw  newdst
+2010$:  .word   000000, cp000c, 000001
+        .word   000001, cp000c, 000002
+        .word   077776, cp000c, 077777
+        .word   077777, cpn0vc, 100000
+        .word   100000, cpn00c, 100001
+        .word   100001, cpn00c, 100002
+        .word   177776, cpn00c, 177777
+        .word   177777, cp0z0c, 000000
+2011$:  
+;
+9999$:  iot                     ; end of test B1.1
+;        
+; Test B2 -- dec +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+;   This sub-section verifies
+;     x xxx xxx xxx xxx xxx NZVC Instruction / Remark
+;     0 000 101 011 ddd ddd NZV- DEC
+;
+; Test B2.1 -- dec instruction ++++++++++++++++++++++++++++++++++++++++
+;
+tb0201: clr     cp.psw
+        mov     #1000$,r5       ; reg mode tests
+        jsr     pc,top1wr
+        mov     #2000$,r5       ; mem mode tests
+        jsr     pc,top1wm
+        jmp     9999$
+;
+1000$:  ccc                     ; c=0
+        dec     r1              ; dec preserves c, so stays 0
+        .word   1010$
+        .word   1011$
+;
+;               olddst  psw     newdst
+1010$:  .word   000000, cpn000, 177777
+        .word   000001, cp0z00, 000000
+        .word   077776, cp0000, 077775
+        .word   077777, cp0000, 077776
+        .word   100000, cp00v0, 077777
+        .word   100001, cpn000, 100000
+        .word   177776, cpn000, 177775
+        .word   177777, cpn000, 177776
+1011$:  
+;
+2000$:  scc                     ; c=1
+        dec     (r1)            ; dec preserves c, so stays 1
+        .word   2010$
+        .word   2011$
+;
+;               olddst     psw  newdst
+2010$:  .word   000000, cpn00c, 177777
+        .word   000001, cp0z0c, 000000
+        .word   077776, cp000c, 077775
+        .word   077777, cp000c, 077776
+        .word   100000, cp00vc, 077777
+        .word   100001, cpn00c, 100000
+        .word   177776, cpn00c, 177775
+        .word   177777, cpn00c, 177776 
+2011$:  
+;
+9999$:  iot                     ; end of test B2.1
+
+;
+; Section C: binary instructions =============================================
+;
+        jmp     tc0101
+;
+; test driver for binary instruction tests
+;
+top2br: 
+top2wr: mov     (r5),101$       ; setup cc setter
+        mov     2(r5),102$      ; setup instruction
+        mov     4(r5),r4        ; setup expect data pointer
+        mov     6(r5),r3        ; setup expect end
+        mov     #cp.psw,r2
+;
+100$:   mov     (r4)+,r0        ; setup src
+        mov     (r4)+,r1        ; setup old dst
+        ccc                     ; clear cc
+101$:   nop                     ; REPLACED with cc setter
+102$:   nop                     ; REPLACED with instruction, e.g. add r0,r1
+        cmp     (r2),(r4)+      ; check psw
+        beq     .+4
+        halt
+        cmp     r1,(r4)+        ; check new dst
+        beq     .+4
+        halt
+        cmp     r4,r3           ; more to do ?
+        blo     100$
+        rts     pc
+;
+top2bm: 
+top2wm: mov     (r5),101$       ; setup cc setter
+        mov     2(r5),102$      ; setup instruction
+        mov     4(r5),r4        ; setup expect data pointer
+        mov     6(r5),r3        ; setup expect end
+        mov     #200$,r0        ; setup src pointer
+        mov     #300$,r1        ; setup dst pointer
+        mov     #cp.psw,r2
+;
+100$:   mov     (r4)+,(r0)      ; setup src
+        mov     (r4)+,(r1)      ; setup old dst
+        ccc                     ; clear cc
+101$:   nop                     ; REPLACED with cc setter
+102$:   nop                     ; REPLACED with instruction, e.g. add (r0),(r1)
+        cmp     (r2),(r4)+      ; check psw
+        beq     .+4
+        halt
+        cmp     (r1),(r4)+      ; check new dst
+        beq     .+4
+        halt
+        cmp     r4,r3           ; more to do ?
+        blo     100$
+        rts     pc
+;
+200$:   .word   0
+300$:   .word   0
+;
+;        
+; Test C1 -- add +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+;   This sub-section verifies
+;     x xxx xxx xxx xxx xxx NZVC Instruction / Remark
+;     0 110 sss sss ddd ddd NZVC ADD
+;
+; Test C1.1 -- add instructions ++++++++++++++++++++++++++++++++++++++
+;
+tc0101: clr     cp.psw
+        mov     #1000$,r5       ; reg mode tests
+        jsr     pc,top2wr
+        mov     #2000$,r5       ; mem mode tests
+        jsr     pc,top2wm
+        jmp     9999$
+;
+1000$:  ccc
+        add     r0,r1
+        .word   1010$
+        .word   1011$
+;
+;                  src  olddst     psw  newdst
+1010$:  .word   000000, 000000, cp0z00, 000000
+        .word   000001, 000000, cp0000, 000001
+        .word   077777, 000000, cp0000, 077777
+        .word   100000, 000000, cpn000, 100000
+        .word   100001, 000000, cpn000, 100001
+        .word   177777, 000000, cpn000, 177777
+
+        .word   000000, 000001, cp0000, 000001
+        .word   000001, 000001, cp0000, 000002
+        .word   077776, 000001, cp0000, 077777
+        .word   077777, 000001, cpn0v0, 100000
+        .word   100000, 000001, cpn000, 100001
+        .word   100001, 000001, cpn000, 100002
+        .word   177776, 000001, cpn000, 177777
+        .word   177777, 000001, cp0z0c, 000000
+
+        .word   000001, 077776, cp0000, 077777
+        .word   000002, 077776, cpn0v0, 100000
+        .word   077777, 077776, cpn0v0, 177775
+        .word   100000, 077776, cpn000, 177776
+        .word   100001, 077776, cpn000, 177777
+        .word   100002, 077776, cp0z0c, 000000
+        .word   100003, 077776, cp000c, 000001
+        .word   177776, 077776, cp000c, 077774
+        .word   177777, 077776, cp000c, 077775
+
+        .word   000001, 077777, cpn0v0, 100000
+        .word   000002, 077777, cpn0v0, 100001
+        .word   077777, 077777, cpn0v0, 177776
+        .word   100000, 077777, cpn000, 177777
+        .word   100001, 077777, cp0z0c, 000000
+        .word   100002, 077777, cp000c, 000001
+        .word   177776, 077777, cp000c, 077775
+        .word   177777, 077777, cp000c, 077776
+
+        .word   000001, 100000, cpn000, 100001
+        .word   000002, 100000, cpn000, 100002
+        .word   077777, 100000, cpn000, 177777
+        .word   100000, 100000, cp0zvc, 000000
+        .word   100001, 100000, cp00vc, 000001
+        .word   100002, 100000, cp00vc, 000002
+        .word   177776, 100000, cp00vc, 077776
+        .word   177777, 100000, cp00vc, 077777
+
+        .word   000001, 100001, cpn000, 100002
+        .word   000002, 100001, cpn000, 100003
+        .word   077777, 100001, cp0z0c, 000000
+        .word   100000, 100001, cp00vc, 000001
+        .word   100001, 100001, cp00vc, 000002
+        .word   177776, 100001, cp00vc, 077777
+        .word   177777, 100001, cpn00c, 100000
+
+        .word   000001, 177776, cpn000, 177777
+        .word   000002, 177776, cp0z0c, 000000
+        .word   077777, 177776, cp000c, 077775
+        .word   100000, 177776, cp00vc, 077776
+        .word   100001, 177776, cp00vc, 077777
+        .word   100002, 177776, cpn00c, 100000
+        .word   177776, 177776, cpn00c, 177774
+        .word   177777, 177776, cpn00c, 177775
+
+        .word   000001, 177777, cp0z0c, 000000
+        .word   000002, 177777, cp000c, 000001
+        .word   077777, 177777, cp000c, 077776
+        .word   100000, 177777, cp00vc, 077777
+        .word   100001, 177777, cpn00c, 100000
+        .word   100002, 177777, cpn00c, 100001
+        .word   177776, 177777, cpn00c, 177775
+        .word   177777, 177777, cpn00c, 177776
+1011$:  
+;
+2000$:  scc
+        add     (r0),(r1)
+        .word   1010$
+        .word   1011$
+;
+9999$:  iot                     ; end of test C1.1
+;
+; Test C2 -- sub +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+;   This sub-section verifies
+;     x xxx xxx xxx xxx xxx NZVC Instruction / Remark
+;     1 110 sss sss ddd ddd NZVC SUB
+;
+; Test C2.1 -- sub instruction +++++++++++++++++++++++++++++++++++++++
+;
+tc0201: clr     cp.psw
+        mov     #1000$,r5       ; reg mode tests
+        jsr     pc,top2wr
+        mov     #2000$,r5       ; mem mode tests
+        jsr     pc,top2wm
+        jmp     9999$
+;
+1000$:  ccc
+        sub     r0,r1
+        .word   1010$
+        .word   1011$
+;
+;                  src  olddst     psw  newdst
+1010$:  .word   000000, 000000, cp0z00, 000000
+        .word   000001, 000000, cpn00c, 177777
+        .word   077777, 000000, cpn00c, 100001
+        .word   100000, 000000, cpn0vc, 100000
+        .word   100001, 000000, cp000c, 077777
+        .word   177777, 000000, cp000c, 000001
+
+        .word   000000, 000001, cp0000, 000001
+        .word   000001, 000001, cp0z00, 000000
+        .word   077777, 000001, cpn00c, 100002
+        .word   100000, 000001, cpn0vc, 100001
+        .word   100001, 000001, cpn0vc, 100000
+        .word   100002, 000001, cp000c, 077777
+        .word   177776, 000001, cp000c, 000003
+        .word   177777, 000001, cp000c, 000002
+
+        .word   000001, 077776, cp0000, 077775
+        .word   077775, 077776, cp0000, 000001
+        .word   077776, 077776, cp0z00, 000000
+        .word   077777, 077776, cpn00c, 177777
+        .word   100000, 077776, cpn0vc, 177776
+        .word   100001, 077776, cpn0vc, 177775
+        .word   177775, 077776, cpn0vc, 100001
+        .word   177776, 077776, cpn0vc, 100000
+        .word   177777, 077776, cp000c, 077777
+
+        .word   000001, 077777, cp0000, 077776
+        .word   077775, 077777, cp0000, 000002
+        .word   077776, 077777, cp0000, 000001
+        .word   077777, 077777, cp0z00, 000000
+        .word   100000, 077777, cpn0vc, 177777
+        .word   100001, 077777, cpn0vc, 177776
+        .word   177776, 077777, cpn0vc, 100001
+        .word   177777, 077777, cpn0vc, 100000
+
+        .word   000001, 100000, cp00v0, 077777
+        .word   000002, 100000, cp00v0, 077776
+        .word   077776, 100000, cp00v0, 000002
+        .word   077777, 100000, cp00v0, 000001
+        .word   100000, 100000, cp0z00, 000000
+        .word   100001, 100000, cpn00c, 177777
+        .word   177776, 100000, cpn00c, 100002
+        .word   177777, 100000, cpn00c, 100001
+
+        .word   000001, 100001, cpn000, 100000
+        .word   000002, 100001, cp00v0, 077777
+        .word   077776, 100001, cp00v0, 000003
+        .word   077777, 100001, cp00v0, 000002
+        .word   100000, 100001, cp0000, 000001
+        .word   100001, 100001, cp0z00, 000000
+        .word   177776, 100001, cpn00c, 100003
+        .word   177777, 100001, cpn00c, 100002
+
+        .word   000001, 177776, cpn000, 177775
+        .word   077775, 177776, cpn000, 100001
+        .word   077776, 177776, cpn000, 100000
+        .word   077777, 177776, cp00v0, 077777
+        .word   100000, 177776, cp0000, 077776
+        .word   100001, 177776, cp0000, 077775
+        .word   177775, 177776, cp0000, 000001
+        .word   177776, 177776, cp0z00, 000000
+        .word   177777, 177776, cpn00c, 177777
+
+        .word   000001, 177777, cpn000, 177776
+        .word   077776, 177777, cpn000, 100001
+        .word   077777, 177777, cpn000, 100000
+        .word   100000, 177777, cp0000, 077777
+        .word   100001, 177777, cp0000, 077776
+        .word   177776, 177777, cp0000, 000001
+        .word   177777, 177777, cp0z00, 000000
+1011$:  
+;
+2000$:  scc
+        sub     (r0),(r1)
+        .word   1010$
+        .word   1011$
+;
+9999$:  iot                     ; end of test C2.1
+;
+; Test C3 -- bic +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+;   This sub-section verifies
+;     x xxx xxx xxx xxx xxx NZVC Instruction / Remark
+;     0 100 sss sss ddd ddd NZ0- BIC
+;
+; Test C3.1 -- bic instruction +++++++++++++++++++++++++++++++++++++++
+;
+tc0301: clr     cp.psw
+        mov     #1000$,r5       ; reg mode tests
+        jsr     pc,top2wr
+        mov     #2000$,r5       ; mem mode tests
+        jsr     pc,top2wm
+        jmp     9999$
+;
+1000$:  ccc
+        bic     r0,r1
+        .word   1010$
+        .word   1011$
+;
+;                  src  olddst     psw  newdst
+1010$:  .word   000000, 000000, cp0z00, 000000
+        .word   177777, 000000, cp0z00, 000000
+
+        .word   000000, 077077, cp0000, 077077
+        .word   070007, 077077, cp0000, 007070
+        .word   177777, 077077, cp0z00, 000000
+
+        .word   000000, 100770, cpn000, 100770
+        .word   000070, 100770, cpn000, 100700
+        .word   100700, 100770, cp0000, 000070
+        .word   177777, 100770, cp0z00, 000000
+
+1011$:  
+;
+2000$:  scc
+        bic     (r0),(r1)
+        .word   2010$
+        .word   2011$
+;
+;                  src  olddst     psw  newdst
+2010$:  .word   000000, 000000, cp0z0c, 000000
+        .word   177777, 000000, cp0z0c, 000000
+
+        .word   000000, 077077, cp000c, 077077
+        .word   070007, 077077, cp000c, 007070
+        .word   177777, 077077, cp0z0c, 000000
+
+        .word   000000, 100770, cpn00c, 100770
+        .word   000070, 100770, cpn00c, 100700
+        .word   100700, 100770, cp000c, 000070
+        .word   177777, 100770, cp0z0c, 000000
+
+2011$:  
+;
+9999$:  iot                     ; end of test C3.1
+;
+; Test C4 -- bis +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+;   This sub-section verifies
+;     x xxx xxx xxx xxx xxx NZVC Instruction / Remark
+;     0 101 sss sss ddd ddd NZ0- BIS
+;
+; Test C4.1 -- bis instructions ++++++++++++++++++++++++++++++++++++++
+;
+tc0401: clr     cp.psw
+        mov     #1000$,r5       ; reg mode tests
+        jsr     pc,top2wr
+        mov     #2000$,r5       ; mem mode tests
+        jsr     pc,top2wm
+        jmp     9999$
+;
+1000$:  ccc
+        bis     r0,r1
+        .word   1010$
+        .word   1011$
+;
+;                  src  olddst     psw  newdst
+1010$:  .word   000000, 000000, cp0z00, 000000
+        .word   077077, 000000, cp0000, 077077
+        .word   100770, 000000, cpn000, 100770
+
+        .word   000000, 070007, cp0000, 070007
+        .word   007070, 070007, cp0000, 077077
+        .word   100770, 070007, cpn000, 170777
+
+        .word   000000, 100770, cpn000, 100770
+        .word   007070, 100770, cpn000, 107770
+
+1011$:  
+;
+2000$:  scc
+        bis     (r0),(r1)
+        .word   2010$
+        .word   2011$
+;
+;                  src  olddst     psw  newdst
+2010$:  .word   000000, 000000, cp0z0c, 000000
+        .word   077077, 000000, cp000c, 077077
+        .word   100770, 000000, cpn00c, 100770
+
+        .word   000000, 070007, cp000c, 070007
+        .word   007070, 070007, cp000c, 077077
+        .word   100770, 070007, cpn00c, 170777
+
+        .word   000000, 100770, cpn00c, 100770
+        .word   007070, 100770, cpn00c, 107770
+
+2011$:  
+;
+9999$:  iot                     ; end of test C4.1
+;
+;
+; END OF ALL TESTS - loop closure ============================================
+;
+        mov     tstno,r0        ; hack, for easy monitoring ...
+        cmp     tstno,#11.      ; all tests done ?
+        beq     .+4
+        halt
+;
+        jmp     loop