diff --git a/.cvsignore b/.cvsignore index 2a117623..8ae24a0b 100644 --- a/.cvsignore +++ b/.cvsignore @@ -1,6 +1,7 @@ -*.dep_ghdl -*.dep_isim -*.dep_xst +*.gz +*.tar +*.tgz +*.dep_* work-obj93.cf *.vcd *.ghw @@ -14,20 +15,28 @@ xflow.his *.pcf *.bit *.msk +*.svf +*.log isim -isim.log -isim.wdb -fuse.log -*_[sft]sim.vhd +*_[sfot]sim.vhd *_tsim.sdf -*_xst.log -*_tra.log -*_twr.log -*_map.log -*_par.log -*_tsi.log -*_pad.log -*_bgn.log -*_svn.log -*_sum.log -*_[dsft]sim.log +rlink_cext_fifo_[rt]x +rlink_cext_conf +tmu_ofile +*.dsk +*.tap +*.lst +*.cof +.Xil +project_mflow +xsim.dir +webtalk_* +*_[sfot]sim +*_[IX]Sim +*_[IX]Sim_[sfot]sim +*.dcp +*.jou +*.pb +*.prj +*.rpt +*.wdb diff --git a/Makefile b/Makefile index 6c364742..8ca3a213 100644 --- a/Makefile +++ b/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 682 2015-05-15 18:35:29Z mueller $ +# $Id: Makefile 745 2016-03-18 22:10:34Z mueller $ # # 'Meta Makefile' for whole retro project # allows to make all synthesis targets @@ -6,6 +6,7 @@ # # Revision History: # Date Rev Version Comment +# 2016-02-19 732 1.2.1 remove dispunit syn and sim entries # 2015-02-01 640 1.2 add vivado targets, separate from ise targets # 2015-01-25 638 1.1 drop as type fx2 targets # 2014-06-14 562 1.0.8 suspend nexys4 syn targets @@ -47,8 +48,6 @@ SYN_ise += rtl/sys_gen/tst_serloop/nexys3 SYN_ise += rtl/sys_gen/tst_snhumanio/nexys3 SYN_ise += rtl/sys_gen/w11a/nexys3 -# xc2 ---------------------------------------- - # Vivado based targets, by board type -------------------- # Basys3 ------------------------------------- SYN_viv += rtl/sys_gen/tst_snhumanio/basys3 @@ -62,6 +61,10 @@ SYN_viv += rtl/sys_gen/tst_serloop/nexys4 SYN_viv += rtl/sys_gen/tst_snhumanio/nexys4 SYN_viv += rtl/sys_gen/w11a/nexys4 +# Arty --------------------------------------- +SYN_viv += rtl/sys_gen/tst_rlink/arty +SYN_viv += rtl/sys_gen/w11a/arty_bram + # Simulation targets ------------------------------------------------- # ISE flow ----------------------------------------------- @@ -89,17 +92,21 @@ SIM_ise += rtl/sys_gen/tst_rlink_cuff/nexys3/ic/tb SIM_ise += rtl/sys_gen/tst_serloop/nexys3/tb SIM_ise += rtl/sys_gen/w11a/nexys3/tb -# xc2 ---------------------------------------- - # Vivado flow -------------------------------------------- # Basys3 ------------------------------------- SIM_viv += rtl/sys_gen/tst_rlink/basys3/tb #SIM_viv += rtl/sys_gen/tst_serloop/basys3/tb SIM_viv += rtl/sys_gen/w11a/basys3/tb + # Nexys4 ------------------------------------- SIM_viv += rtl/sys_gen/tst_rlink/nexys4/tb SIM_viv += rtl/sys_gen/tst_serloop/nexys4/tb SIM_viv += rtl/sys_gen/w11a/nexys4/tb + +# Arty --------------------------------------- +SIM_viv += rtl/sys_gen/tst_rlink/arty/tb +SIM_viv += rtl/sys_gen/w11a/arty_bram/tb + # .PHONY : default .PHONY : all all_ise all_viv diff --git a/doc/ECO-027-trap_mmu.txt b/doc/ECO-027-trap_mmu.txt new file mode 100644 index 00000000..93223772 --- /dev/null +++ b/doc/ECO-027-trap_mmu.txt @@ -0,0 +1,46 @@ +$Id: ECO-027-trap_mmu.txt 708 2015-08-03 06:41:43Z mueller $ + +Scope: + Introduced in release w11a_V0.71 + Affects: all w11a systems + +Symptom summary: + A mmu trap could be lost or vectored through 014 (bpt) rather 250 (mmu). + +Background: + The PDP-11/70 and 11/45 MMU offers a 'mmu trap' feature, which can cause + a trap when a memory location is read or written. This can be enabled with + special ACF values in the page descriptor registers for each segment end + globally enabled with an enable bit in SSR0. + + Since only 11/70 and 11/45 offer this (and J11 does not) this feature is + in general not used by operations systems. + +Summary of issues: + When an instruction does more than one memory access and the mmu trap + condition occurs not on the last access + - an mmu trap could be missed + - an mmu trap might be vectored through 014 (the bpt vector) + The later happens for all read-modify-write accesses. + +Analysis: + The VM_STAT.trap_mmu flag was copied into the R_STATUS.trap_mmu state bit + in do_memcheck, which is called for each memory wait. In case of a + read-modify-write the initial read will signal trap_mmu, while the + rmw completion will not (the mmu doesn't check on rmw completions). + This leads to + - lost mmu traps (e.g. when mmu trap comes on 1st of 2 access) + - mmu traps vectored through 014 (the bpt vector) + The later happens due to the logic of state s_opg_gen_rmw_w: + - do_memcheck can clear R_STATUS.trap_mmu + - do_fork_next still branches to s_trap_disp because R_STATUS.trap_mmu='1' + - s_trap_disp sees R_STATUS.trap_mmu='0' and miscalculates the vector + +Fixes: + pdp11_sequencer was modified to ensure that R_STATUS.trap_mmu is only set + in do_memcheck. Same for trap_ysv (which had the same potential bug) + +Provisos: + The issue was found by systematic testing of mmu fault and trap behavior. + Because known OS don't use mmu traps the issue should not have any impact + on practical usage with OS like rsx or 211bsd. diff --git a/doc/README.txt b/doc/README.txt index 54b70220..bc4d6a87 100644 --- a/doc/README.txt +++ b/doc/README.txt @@ -1,4 +1,4 @@ -$Id: README.txt 722 2015-12-30 19:45:46Z mueller $ +$Id: README.txt 746 2016-03-19 13:08:36Z mueller $ Release notes for w11a @@ -22,6 +22,108 @@ Release notes for w11a 2. Change Log ---------------------------------------------------------------- +- trunk (2016-03-19: svn rev 35(oc) 746(wfjm); untagged w11a_V0.72) +++++++++ + - Preface + - The new low-cost Digilent Arty board is a very attractive platform. + The DDR3 memory will take some time to integrate, in this release thus + only designs using the BRAMs. + - added support for the Vivado simulator. Simple test benches work fine. + Rlink based test benches don't work due to a bug in Vivado 2015.4. + - A rather esoteric CPU bug was fixed in release V0.71 but forgotten to + mention in the README. See ECO-027-trap_mmu.txt for details. + + - Summary + - added Arty support. The w11a design uses BRAMs as memory, like the + Basys3 version. This gives 176 KByte memory, not enough for 2.11BSD, + but for many other less demanding OS available for a PDP11. + - added support for SYSMON/XADC (see README_xadc.txt) + - Vivado flow is now default for test benches of components and all Artix + based systems. If applicable an ISE flow is available under Makefile.ise + (resolves known issues V0.64-4 and V0.64-5). + - re-factored tbcore_rlink to support DPI and VHPI + - Vivado supports with DPI (from SystemVerilog) a mechanism to call + external C code. The rlink test bench code so far relies on VHPI, which + is supported by ghdl, but not by ISE ISim or Vivado xsim. The code was + restructured and can use now DPI or VHPI to support both ghdl and + Vivado. Unfortunately has Vivado 2015.4 a bug, DPI doesn't work in a + mixed vhdl-verilog language environment (see Known issues), so the + code base is there, but utilization will habe to wait. + - Vivado synthesis by default keeps hierarchy. This leads to doubly defined + modules if a component is used in both test bench and unit under test. + To avoid this copies of s7_cmt_sfs and some serport_* modules were + created and are now used in the test benches. + + - New features + - new directory trees for + - rtl/bplib/arty - board support files for arty + - rtl/bplib/sysmon - driver + rbus iface for SYSMON/XADC + - rtl/vlib/rlink/tbcore - new location for rlink tb iface code + - tools/tcl/rbsysmon - sysmon/xadc support + - new modules + - rtl/bplib/bpgen + - rgbdrv_* - driver + rbus iface for 3 color RGBLED + - rtl/vlib/rlink/tbcore + - rlink_cext_iface_dpi.sv - DPI based cext iface + - rlink_cext_iface_vhpi.vhd - VHPI based cext iface + - rlink_cext_dpi.c - dpi to vhpi adapter + - rtl/vlib/serport/tb + - serport_uart_*_tb - added copies for tb usage + - rtl/vlib/xlib/tb + - s7_cmt_sfs_tb - added copy for tb usage + - + - new files + - doc/man/man1 + - tbrun_tbw.1 - man file for tbrun_tbw + - tbrun_tbwrri.1 - man file for tbrun_tbwrri + - new systems + - rtl/sys_gen/tst_rlink - rlink tester + - arty/sys_tst_rlink_arty - for Arty + - rtl/sys_gen/w11a - w11a + - arty_bram/sys_w11a_br_arty - for Arty (BRAM only, 176 MByte) + + - Changes + - */.cvsignore - all ignore files re-organized + - */tb/Makefile - Vivado now default, keep Makefile.ise + - rtl/bplib/*/tb/tb_*.vhd - use s7_cmt_sfs_tb and serport_master_tb + - rtl/vlib/comlib + - comlib.vhd - add work-around for vivado 2015.4 issue + - rtl/vlib/rbus + - rb_sres_or_mon - supports 6 inputs now + - rtl/vlib/serport + - serport_master - moved to tb, _tb appended to name + - rtl/vlib/rlink/tbcore + - tbcore_rlink - re-structured to use rlink_cext_iface + - rtl/sys_gen/... + - sys_tst_rlink_b3 - hardwire XON=1, support XADC + - sys_tst_rlink_n4 - support XADC and RGBLEDs + - sys_w11a_b3 - hardwire XON=1, support XADC; 72 MHz now + - sys_w11a_n4 - support XADC + - tools/bin + - tbrun_tbw - add vivado xsim and Makefile.ise support + - tbrun_tbwrri - use --sxon and --hxon instead of --xon + - tbw - add XSim support + - ti_w11 - add arty support, add -fx + - vbomconv - add [ise,viv]; add @uut tag handling; + add preliminary --(vsyn|vsim)_export; + add vivado xsim support; + - xtwi,xtwv - add BARE_PATH to provide clean environment + + - Bug fixes + - tools/tcl/rutil + - regdsc.tcl - regdsc: fix variable name in error msg + + - Known issues + - all issues: see README_known_issues.txt + - resolved issues: + - V0.64-4: support added for Vivado xsim. See however issue V0.72-1+2. + - V0.64-5: w11a_tb_guide.txt covers xsim tests too. + + - new issues: + - V0.72-1: Vivado 2015.4 xelab crashes when DPI is used in a mxied + vhdl-verilog language environment. This prevents currently to + build a xsim simulation model for rlink based test benches. + - V0.72-2: xsim simulations with timing annotation not yet available. + - trunk (2015-12-30: svn rev 34(oc) 722(wfjm); untagged w11a_V0.71) +++++++++ - Preface - the w11a so far lacked any 'hardware debugger' support, which made the diff --git a/doc/README_buildsystem_Vivado.txt b/doc/README_buildsystem_Vivado.txt index 9896e534..63f48bfa 100644 --- a/doc/README_buildsystem_Vivado.txt +++ b/doc/README_buildsystem_Vivado.txt @@ -1,4 +1,4 @@ -# $Id: README_buildsystem_Vivado.txt 651 2015-02-26 21:32:15Z mueller $ +# $Id: README_buildsystem_Vivado.txt 745 2016-03-18 22:10:34Z mueller $ Guide to the Build System (Xilinx Vivado Version) @@ -10,6 +10,7 @@ Guide to the Build System (Xilinx Vivado Version) b. Compile UNISIM/UNIMACRO libraries for ghdl 3. Building test benches a. With ghdl + b. With Vivado xsim 4. Building systems 5. Configuring FPGAs (via make flow) 6. Note on ISE @@ -127,6 +128,28 @@ Guide to the Build System (Xilinx Vivado Version) - post synthesis or optimize models currently very often fail to compile in ghdl due to a bug in the ghdl code generator. +3b. With Vivado xsim ------------------------------------------------- + + To compile a Vivado xsim based test bench named all is needed is + + make _XSim + + The make file will use .vbom, create all make dependency files, + and generate the needed Vivado xsim project files and commands. + + In many cases the test benches can also be compiled against the gate + level models derived after the synthesis, optimize or routing step. + + make _XSim_ssim # for post-synthesis + make _XSim_osim # for post-optimize + make _XSim_tsim # for post-routing + + Notes: + - xsim currently (as of Vivado 2015.4) crashes when DPI is used in a mixed + vhdl verilog context. + Since DPI is used in the rlink simulation all system test benches with + an rlink interface, thus most, will only run with ghdl and not with XSim. + 4. Building systems ------------------------------------------------------- To generate a bit file for a system named all is needed is diff --git a/doc/README_known_issues.txt b/doc/README_known_issues.txt index c66f4345..df3d0a02 100644 --- a/doc/README_known_issues.txt +++ b/doc/README_known_issues.txt @@ -1,8 +1,13 @@ -$Id: README_known_issues.txt 693 2015-06-21 14:02:46Z mueller $ +$Id: README_known_issues.txt 746 2016-03-19 13:08:36Z mueller $ Known issues for this release. The case id indicates the release when the issue was first recognized. +- V0.72-2: xsim simulations with timing annotation not yet available. +- V0.72-1: Vivado 2015.4 xelab crashes when DPI is used in a mxied vhdl-verilog + language environment. This prevents currently to build a xsim simulation + model for rlink based test benches. + - V0.66-1: the TM11 controller transfers data byte wise (all disk do it 16bit word wise) and allows for odd byte length transfers. Odd length transfers are currently not supported and rejected as invalid command. Odd byte @@ -24,9 +29,6 @@ The case id indicates the release when the issue was first recognized. flow control issue (likely since V0.63). - V0.64-6: IO delays still unconstraint in vivado. All critical IOs use explicitly IOB flops, thus timing well defined. -- V0.64-5: w11a_tb_guide.txt covers only ISE based tests (see also V0.64-4). -- V0.64-4: No support for the Vivado simulator (xsim) yet. With ghdl only - functional simulations, post synthesis (_ssim) fails to compile. - V0.64-3: Highest baud rate with basys3 and nexys4 is 10 MBaud. 10 MBaud is not supported according to FTDI, but works. 12 MBaud in an upcoming release. - V0.64-2: rlink throughput on basys3/nexys4 limited by serial port stack diff --git a/doc/README_xadc.txt b/doc/README_xadc.txt new file mode 100644 index 00000000..61e23727 --- /dev/null +++ b/doc/README_xadc.txt @@ -0,0 +1,49 @@ +# $Id: README_xadc.txt 746 2016-03-19 13:08:36Z mueller $ + +The Artix-7 based designs contain now a module which makes the data of the +FPGA system monitor, called XADC in 7Series and SYSMON otherwise, available +on the rbus and therefore from ti_rri. + +To set this up in ti_rri or ti_w11 use + + package require rbsysmon + rbsysmon::setup_xadc_arty; # for arty + rbsysmon::setup_xadc_base; # for b3,n4 + +Two procedures allow to read and nicely print the XADC data + + rbsysmon::print + --> gives on an Arty for example + Value cur val min val max val low lim high lim alarm + temp 34.3 d 30.8 36.0 60.0 85.0 + Vccint 0.948 V 0.944 0.953 0.920 0.980 + Vccaux 1.799 V 1.787 1.802 1.710 1.890 + Vccbram 0.948 V 0.944 0.954 0.920 0.980 + V 5V0 4.978 V + V VU 0.088 V + A 5V0 0.173 A + A 0V95 0.087 A + + rbsysmon::print_raw + --> produces a full list of all defined registers, like + name description : hex other + sm.temp cur temp : 9a50 30.6 deg + sm.vint cur Vccint : 50ce 0.947 V + sm.vaux cur Vccaux : 9962 1.797 V + sm.vrefp cur Vrefp : 0000 0.000 V + .... + sm.flag flag reg : 0000 0000000000000000 + sm.conf0 conf 0 : 9000 1001000000000000 + sm.conf1 conf 1 : 2ef0 0010111011110000 + sm.conf2 conf 2 : 0400 0000010000000000 + .... + +For simulation proper setup files are included and activated by tbw to that +one sees in simulation nominal readings for the power monitor values. To +test this do for example + + cd $RETROBASE/rtl/sys_gen/tst_rlink/arty/tb + make + ti_rri --fifo=,xon --run='tbw tb_tst_rlink_arty' + + .. commands above ... diff --git a/doc/man/man1/tbrun_tbw.1 b/doc/man/man1/tbrun_tbw.1 new file mode 100644 index 00000000..469f1f97 --- /dev/null +++ b/doc/man/man1/tbrun_tbw.1 @@ -0,0 +1,92 @@ +.\" -*- nroff -*- +.\" $Id: tbrun_tbw.1 745 2016-03-18 22:10:34Z mueller $ +.\" +.\" Copyright 2016- by Walter F.J. Mueller +.\" +.\" ------------------------------------------------------------------ +. +.TH TBRUN_TBW 1 2016-03-18 "Retro Project" "Retro Project Manual" +.\" ------------------------------------------------------------------ +.SH NAME +tbrun_tbw \- \fBtbw\fP based test bench starter +.\" ------------------------------------------------------------------ +.SH SYNOPSIS +. +.SY tbrun_tbw +.OP OPTIONS +.I TBENCH +.OP STIMFILE +.YS +. +.\" ------------------------------------------------------------------ +.SH DESCRIPTION +\fBtbrun_tbw\fP is a convenience script for starting \fBtbw\fP(1) based +test benches. It will + +.RS 2 +.PD 0 +.IP "-" 2 +issue a \fBmake\fP(1) command to (re)-build \fITBENCH\fP. +.IP "-" +build a \fBtbw\fP(1) command, using \fISTIMFILE\fP if specified. +.IP "-" +create a shell pipe to which runs tbw and handles the output with +.IP " -" 4 +\fBghdl_assert_filter\fP(1) to suppress irrelevant diagnostics +created by \fBghdl\fP(1) and it's IEEE libs +.IP " -" +\fBtee\fP(1) to save the output to a log file. The log file +name is build as "_.log" +.IP " -" +\fBegrep\fP(1) to filter out only essential lines to stdout +.PD +.RE +.PP +. +.\" ------------------------------------------------------------------ +.SH OPTIONS +Note: \fBtbrun_tbw\fP is implemented as shell script. If options have an +argument it is separated white space and not by '='! So write '--ghw\ xxx' +and not '--ghw=xxx' ! +. +.\" -- --dry ------------------------------------- +.IP \fB\-\-dry\fP +dry run, prints the commands but doesn't execute +. +.\" -- --lsuf ------------------------------------ +.IP \fB\-\-lsuf\ \fIsuff\fR +use '_\fIsuff\fR.log' as suffix for log file. Default is '_dsim.log' +. +.\" -- --stack ----------------------------------- +.IP \fB\-\-stack\ \fInnn\fR +use \fInnn\fP as \fBghdl\fP(1) stack size +. +.\" -- --ghw fname ------------------------------- +.IP \fB\-\-ghw\ \fIfname\fR +write a ghw file with name '\fIfname\fP.ghw' +. +.\" -- --tbw opts -------------------------------- +.IP \fB\-\-tbw\ \fIopts\fR +append \fIopts\fP to the \fBtbw\fP(1) command +. +.\" ------------------------------------------------------------------ +.SH EXAMPLES +.IP "\fBtbrun_tbw tb_serport_uart_rx" 4 +Simplest default case, will execute +.EX + make tb_serport_uart_rx + time tbw tb_serport_uart_rx 2>&1 |\\ + ghdl_assert_filter |\\ + tee tb_serport_uart_rx_dsim.log |\\ + egrep "(-[EFW]:|ERROR|FAIL|PASS|DONE)" +.EE + +.\" ------------------------------------------------------------------ +.SH "SEE ALSO" +.BR tbw (1), +.BR ghdl_assert_filter (1), +.BR ghdl (1) + +.\" ------------------------------------------------------------------ +.SH AUTHOR +Walter F.J. Mueller diff --git a/doc/man/man1/tbrun_tbwrri.1 b/doc/man/man1/tbrun_tbwrri.1 new file mode 100644 index 00000000..cc51e45e --- /dev/null +++ b/doc/man/man1/tbrun_tbwrri.1 @@ -0,0 +1,126 @@ +.\" -*- nroff -*- +.\" $Id: tbrun_tbwrri.1 745 2016-03-18 22:10:34Z mueller $ +.\" +.\" Copyright 2016- by Walter F.J. Mueller +.\" +.\" ------------------------------------------------------------------ +. +.TH TBRUN_TBWRRI 1 2016-03-18 "Retro Project" "Retro Project Manual" +.\" ------------------------------------------------------------------ +.SH NAME +tbrun_tbw \- \fBti_rri\fP plus \fBtbw\fP based test bench starter +.\" ------------------------------------------------------------------ +.SH SYNOPSIS +. +.SY tbrun_tbwrri +.OP OPTIONS +.I TBENCH +.OP COMMANDS +.YS +. +.\" ------------------------------------------------------------------ +.SH DESCRIPTION +\fBtbrun_tbwrri\fP is a convenience script for starting \fBti_rri\fP(1) plus +\fBtbw\fP(1) based test benches. It will + +.RS 2 +.PD 0 +.IP "-" 2 +issue a \fBmake\fP(1) command to (re)-build \fITBENCH\fP. +.IP "-" +build a \fBtbw\fP(1) command to start \fITBENCH\fP. +.IP "-" +build a \fBti_rri\fP(1) command which starts \fBtbw\fP via \fB\-\-run\fP +.IP "-" +create a ti_rri command list with +.IP " -" 4 +setup commands resulting from \fB\-\-cuff\fP, \fB\-\-fusp\fP, ... +.IP " -" +all optional \fICOMMANDS\fP +.IP "-" 2 +create shell pipes to filter the output with +.IP " -" 4 +\fBghdl_assert_filter\fP(1) to suppress irrelevant diagnostics +created by \fBghdl\fP(1) and it's IEEE libs +.IP " -" +\fBtee\fP(1) to save the output to a log file. The log file +name is build as "_.log" +.IP " -" +\fBegrep\fP(1) to filter out only essential lines to stdout +.PD +.RE +.PP +. +.\" ------------------------------------------------------------------ +.SH OPTIONS +Note: \fBtbrun_tbwrri\fP is implemented as shell script. If options have an +argument it is separated white space and not by '='! So write '--ghw\ xxx' +and not '--ghw=xxx' ! +. +.\" -- --dry ------------------------------------- +.IP \fB\-\-dry\fP +dry run, prints the commands but doesn't execute +. +.\" -- --lsuf ------------------------------------ +.IP \fB\-\-lsuf\ \fIsuff\fR +use '_\fIsuff\fR.log' as suffix for log file. Default is '_dsim.log' +. +.\" -- --stack ----------------------------------- +.IP \fB\-\-stack\ \fInnn\fR +use \fInnn\fP as \fBghdl\fP(1) stack size +. +.\" -- --ghw fname ------------------------------- +.IP \fB\-\-ghw\ \fIfname\fR +write a ghw file with name '\fIfname\fP.ghw' +. +.\" -- --tbw opts -------------------------------- +.IP \fB\-\-tbw\ \fIopts\fR +append \fIopts\fP to the \fBtbw\fP command +. +.\" -- --rri opts -------------------------------- +.IP \fB\-\-rri\ \fIopts\fR +append \fIopts\fP to the \fBti_rri\fP command +. +.\" -- --pack plist ------------------------------ +.IP \fB\-\-pack\ \fIplist\fR +add a '\-\-pack=\fIplist\fR' option to \fBti_rri\fP command +. +.\" -- --cuff ------------------------------------ +.IP \fB\-\-cuff\fR +use Cypress FX2 instead of serport, will generate appropriate 'rlc oob' commands. +For nexys2 and nexys3 designs. +. +.\" -- --fusp ------------------------------------ +.IP \fB\-\-fusp\fR +use 2nd serport, will generate appropriate 'rlc oob' commands. +For s3board, nexys2, and nexys3 designs. +. +.\" -- --sxon ------------------------------------ +.IP \fB\-\-sxon\fR +switched\ XON: enable XON flow control with SWI(1), will generate appropriate +'rlc oob' commands and ti_rri \-\-fifo options. +For nexys4 designs. +. +.\" -- --hxon ------------------------------------ +.IP \fB\-\-hxon\fR +hardwired\ XON: will generate appropriate \fBti_rri\fP \fB\-\-fifo\fP options. +For basys3 and arty designs. +. +.\" -- --pcom ------------------------------------ +.IP \fB\-\-pcom\fR +enables that test bench comments are passed to stdout. +. +.\" -- --help ------------------------------------ +.IP \fB\-\-help\fR +print help message and quit. +. +.\" ------------------------------------------------------------------ +.SH "SEE ALSO" +.BR tbw (1), +.BR ti_rri (1), +.BR ghdl_assert_filter (1), +.BR ghdl (1) + +.\" ------------------------------------------------------------------ +.SH AUTHOR +Walter F.J. Mueller diff --git a/doc/man/man1/tbw.1 b/doc/man/man1/tbw.1 index 1bb6c331..9f6e1ce9 100644 --- a/doc/man/man1/tbw.1 +++ b/doc/man/man1/tbw.1 @@ -1,11 +1,11 @@ .\" -*- nroff -*- -.\" $Id: tbw.1 620 2014-12-25 10:48:35Z mueller $ +.\" $Id: tbw.1 727 2016-02-07 13:58:47Z mueller $ .\" -.\" Copyright 2013-2014 by Walter F.J. Mueller +.\" Copyright 2013-2016 by Walter F.J. Mueller .\" .\" ------------------------------------------------------------------ . -.TH TBW 1 2011-11-06 "Retro Project" "Retro Project Manual" +.TH TBW 1 2016-02-06 "Retro Project" "Retro Project Manual" .\" ------------------------------------------------------------------ .SH NAME tbw \- wrapper script to start ghdl based VHDL test benches @@ -71,7 +71,8 @@ defined via the \fItbw.dat\fP file, for details see section FILES. The options \fB\-run\fP, \fB\-fifo\fP and \fB\-verbose\fP are processed by tbw itself. If more than one is given they must be in this order. .IP \fB\-run\fR -Used for _ISim tb's, runs the tb with a 'run all' command. +Used for _ISim or _XSim tb's, ensures that simulation runs till end. Will +issue a 'run all' command for ISim and a '-R' option for XSim. .IP \fB\-fifo\fR Forces usage of rlink_cext fifo, will ignore tbw.dat .IP \fB\-verbose\fR diff --git a/doc/man/man1/ti_rri.1 b/doc/man/man1/ti_rri.1 index 8486fb52..89fa507a 100644 --- a/doc/man/man1/ti_rri.1 +++ b/doc/man/man1/ti_rri.1 @@ -1,11 +1,11 @@ .\" -*- nroff -*- -.\" $Id: ti_rri.1 666 2015-04-12 21:17:54Z mueller $ +.\" $Id: ti_rri.1 742 2016-03-13 14:40:19Z mueller $ .\" -.\" Copyright 2013-2015 by Walter F.J. Mueller +.\" Copyright 2013-2016 by Walter F.J. Mueller .\" .\" ------------------------------------------------------------------ . -.TH TI_RRI 1 2015-04-12 "Retro Project" "Retro Project Manual" +.TH TI_RRI 1 2016-03-13 "Retro Project" "Retro Project Manual" .\" ------------------------------------------------------------------ .SH NAME ti_rri \- \fBRlink\fP Backend Server @@ -87,7 +87,12 @@ software flow control (xon/xoff) defer link initialization (debug or test benches) .PD .RE + +Note: in general the default pipe names are used, thus \fIname\fP is almost +never specified. If only options are given an empty \fIname\fP field must be +specified like in \fB\-\-fifo=,xon\fP. .RE + . .\" -- --term ------------------------------------ .IP \fB\-\-term\fR[=\fIname\fR[,\fIbaud\fR[,\fIopts\fR]]] @@ -207,10 +212,15 @@ with eval. . .\" ------------------------------------------------------------------ .SH EXAMPLES -.IP "\fBti_rri --fifo --run='tbw tb_tst_rlink_n3'" 4 -Starts the \fBghdl\fP(1) test bench 'tb_tst_rlink_n3' located in CWD via +.IP "\fBti_rri --fifo --run='tbw tb_tst_rlink_n4'" 4 +Starts the \fBghdl\fP(1) test bench 'tb_tst_rlink_n4' located in CWD via \fBtbw\fP(1). It is assumed that the local \fItbw.dat\fP file configures fifo communication for the test bench. +. +.IP "\fBti_rri --fifo=,xon --run='tbw tb_tst_rlink_arty'" 4 +Like above, starts arty rather n4 test bench. The rlink is operated with +software flow control. Note the comma in front of \fIxon\fP, required to +ensure that default pipe name is used ! .\" ------------------------------------------------------------------ .SH "SEE ALSO" diff --git a/doc/man/man1/ti_w11.1 b/doc/man/man1/ti_w11.1 index 8543661d..7c113459 100644 --- a/doc/man/man1/ti_w11.1 +++ b/doc/man/man1/ti_w11.1 @@ -1,5 +1,5 @@ .\" -*- nroff -*- -.\" $Id: ti_w11.1 712 2015-11-01 22:53:45Z mueller $ +.\" $Id: ti_w11.1 745 2016-03-18 22:10:34Z mueller $ .\" .\" Copyright 2013-2015 by Walter F.J. Mueller .\" @@ -51,15 +51,19 @@ use /dev/ttyUSB* (* is device number \fIN\fP) .SS "setup options for ghdl simulation runs" .PD 0 .IP \fB-b3\fP -start \fItb_w11a_b3\fP simulation (w11a on Basys3, default \fB-f1x\fP) +start \fItb_w11a_b3\fP simulation (Basys3, default \fB-fx\fP) .IP \fB-n4\fP -start \fItb_w11a_n4\fP simulation (w11a on Nexys4) +start \fItb_w11a_n4\fP simulation (Nexys4) +.IP \fB-bn4\fP +start \fItb_w11a_br_n4\fP simulation (Nexys4, BRAM only) +.IP \fB-bar\fP +start \fItb_w11a_br_arty\fP simulation (Arty, BRAM only, default \fB-fx\fP) .IP \fB-n3\fP -start \fItb_w11a_n3\fP simulation (w11a on Nexys3, default \fB-fc\fP) +start \fItb_w11a_n3\fP simulation (Nexys3, default \fB-fc\fP) .IP \fB-n2\fP -start \fItb_w11a_n2\fP simulation (w11a on Nexys2, default \fB-fc\fP) +start \fItb_w11a_n2\fP simulation (Nexys2, default \fB-fc\fP) .IP \fB-s3\fP -start \fItb_w11a_s3\fP simulation (w11a on S3board, default \fB-f2\fP) +start \fItb_w11a_s3\fP simulation (S3board, default \fB-f2\fP) .PD .IP \fB-f\fIm\fR select communication mode for simulation. The \fB-f\fIm\fR can be used after @@ -69,14 +73,16 @@ for mode \fIm\fP are .PD 0 .IP \fBc\fP 4 use Cypress FX2 data path (cuff, only for -n2 and -n3) +.IP \fBx\fP 4 +use 1st serport with hardwired xon (for -b3 and -arty) .IP \fB1\fP 4 use 1st serport .IP \fB1x\fP 4 -use 1st serport with xon +use 1st serport with switched xon .IP \fB2\fP 4 use 2nd serport (fusp, only for -s3,-n2,-n3) .IP \fB2x\fP 4 -use 2nd serport with xon +use 2nd serport with switched xon .PD .RE .IP \fB-tmu\fP @@ -91,6 +97,8 @@ activate ghw wave file writing load and execute \fIfile\fP. If the file type is '.mac' the file will be on the fly compiled with \fBasm-11\fP(1), for all other file types it is assumed that they are in \fBlda\fP(5) format. +.IP \fB-dry\fR +dry run, prints the commands but doesn't execute . .\" ------------------------------------------------------------------ .SH EXAMPLES diff --git a/doc/man/man1/vbomconv.1 b/doc/man/man1/vbomconv.1 index 40ec6dee..e89c3a19 100644 --- a/doc/man/man1/vbomconv.1 +++ b/doc/man/man1/vbomconv.1 @@ -1,38 +1,18 @@ .\" -*- nroff -*- -.\" $Id: vbomconv.1 646 2015-02-15 12:04:55Z mueller $ +.\" $Id: vbomconv.1 746 2016-03-19 13:08:36Z mueller $ .\" -.\" Copyright 2010-2015 by Walter F.J. Mueller +.\" Copyright 2010-2016 by Walter F.J. Mueller .\" .\" .\" ------------------------------------------------------------------ . -.TH VBOMCONV 1 2015-02-15 "Retro Project" "Retro Project Manual" +.TH VBOMCONV 1 2016-03-19 "Retro Project" "Retro Project Manual" .\" ------------------------------------------------------------------ .SH NAME vbomconv \- generate files and actions from vbom manifest files .\" ------------------------------------------------------------------ .SH SYNOPSIS -. -.SY vbomconv -.B \-\-help -. -.SY vbomconv -.OP \-\-trace -.B \-\-dep_ghdl -.I vbom -. -.SY vbomconv -.OP \-\-trace -.B \-\-dep_xst -| -.B \-\-dep_isim -.I vbom -. -.SY vbomconv -.OP \-\-trace -.B \-\-dep_vsyn -.I vbom -. +.\" --- ghdl .SY vbomconv .OP \-\-trace .B \-\-ghdl_i_cmd @@ -60,9 +40,25 @@ vbomconv \- generate files and actions from vbom manifest files .OP \-\-trace .BI \-\-ghdl_export "\fR=\fPpath" .I vbom + +.\" --- vivado +.SY vbomconv +.OP \-\-trace +.B \-\-vsyn_prj +| +.B \-\-vsim_prj +.I vbom . .SY vbomconv .OP \-\-trace +.BI \-\-vsyn_export "\fR=\fPpath" +| +.BI \-\-vsim_export "\fR=\fPpath" +.I vbom + +.\" --- ise +.SY vbomconv +.OP \-\-trace .B \-\-xst_prj | .B \-\-isim_prj @@ -74,14 +70,30 @@ vbomconv \- generate files and actions from vbom manifest files | .BI \-\-isim_export "\fR=\fPpath" .I vbom + +.\" --- dep_ +.SY vbomconv +.OP \-\-trace +.B \-\-dep_ghdl +.I vbom . .SY vbomconv .OP \-\-trace -.B \-\-vsyn_prj +.B \-\-dep_xst +| +.B \-\-dep_isim .I vbom . .SY vbomconv .OP \-\-trace +.B \-\-dep_vsyn +| +.B \-\-dep_vsim +.I vbom + +.\" --- general +.SY vbomconv +.OP \-\-trace .B \-\-get_top .I vbom . @@ -89,6 +101,8 @@ vbomconv \- generate files and actions from vbom manifest files .OP \-\-trace .B \-\-flist .I vbom +.SY vbomconv +.B \-\-help .YS . .\" ------------------------------------------------------------------ @@ -112,18 +126,21 @@ The \fBvbomconv\fP tool does this traversal of \fBvbom\fP files and generates, depending on command line options, the files and/or commands needed to run a synthesis tool or to build a simulation model. Currently supported is synthesis with Xilinx ISE \fBxst\fP Xilinx Vivado -and simulation with \fBghdl\fP(1) or Xilinx ISE \fBISim\fP. +and simulation with \fBghdl\fP(1), Xilinx ISE \fBISim\fP or +Xilinx Vivado \fBxsim\fP. \fBvbomconv\fP therefore currently generates .PD 0 .IP "\fB- ghdl\fP" 8 commands for analysis, inspection and make step -.IP "\fB- xst\fP" 8 -project files -.IP "\fB- ISim\fP" 8 -project files .IP "\fB- vsyn\fP" 8 project setups for Vivado synthesis +.IP "\fB- vsim\fP" 8 +project setups for Vivado simulation +.IP "\fB- xst\fP" 8 +project files for ISE synthesis +.IP "\fB- ISim\fP" 8 +project files for ISE simulation .IP "\fB- make\fP" 8 dependency files .PD @@ -191,7 +208,7 @@ The first definition seen in the \fIvbom\fP traversal is taken, all others are ignored. The filename in the usage clause is the default used in case the logical name wasn't defined. -Last but not least are 3 directives defined in the \fBvbom\fP +Last but not least are 5 directives defined in the \fBvbom\fP file format: . .IP "\fB@top\fP:\fIname\fP" @@ -203,8 +220,19 @@ allows to specify additional system libraries. Currently used to indicate that the \fIunisim\fP, \fIunimacro\fP or \fIsimprim\fP libraries are needed by \fBghdl\fP. . +.IP "\fB@uut\fP:\fIfile\fP" +signals that the \fIvbom\fP descibes a test bench and that \fIfile\fP is +the 'unit under test'. This allows to split the sources into a simulation +only test bench part and a synthesizable 'unit under test' part. \fIfile\fP +is typically a \fIvbom\fP in case of a functional simulation or the file +name of a generated post synthesis model. +. +.IP "\fB@xdc\fP:\fIfile\fP" +specifies that \fIfile\fP is a constraint file for Vivado synthesis and should +be included in the constraints fileset. +. .IP "\fB@ucf_cpp\fP:\fIfile\fP" -indicates that a \fIfile\fP.ucf file is to be generated by \fBcpp\fP(1) +specifies that a \fIfile\fP.ucf file is to be generated by \fBcpp\fP(1) from a \fIfile\fP.ucf_cpp source file. This allows to modularize ISE ucf files. .PP The full description of the file format and examples are given in a @@ -258,6 +286,8 @@ one not requiring a \fIvbom\fP file. .B \-\-dep_isim .TQ .B \-\-dep_vsyn +.TQ +.B \-\-dep_vsim These four actions write to \fIstdout\fP dependency rules for inclusion in \fIMakefile\fPs. Together with an appropruate pattern rule they allow to automatitize @@ -314,6 +344,14 @@ and produces the following types of dependencies \fI\fP_rou.dcp : \fB*\fP.vhd \fB*\fP.xdc \fI\fP.dep_vsyn : \fB*\fP.vbom .EE + +\fB\-\-dep_vsim\fP creates the dependencies for Vivado \fBxim\fP +based simulation models and produces the following types of dependencies +.EX + \fI\fP_XSim : \fI\fP.dep_vsim + \fI\fP_XSim : \fB*\fP.vhd + \fI\fP.dep_vsim : \fB*\fP.vbom +.EE . .\" ---------------------------------------------- .TP @@ -359,19 +397,30 @@ the EXAMPLES section for practical usage in a make flow. .\" ---------------------------------------------- .TP .B \-\-vsym_prj -This action write to \fIstdout\fP a Tcl script suitable as project definition +This action writes to \fIstdout\fP a Tcl script suitable as project definition for Vivado synthesis. This script is source'ed or eval'ed and defines the source fileset and the constraints fileset. The vhdl source files are in proper compilation order. . .\" ---------------------------------------------- .TP -.BI \-\-xst_export \fR=\fPpath -.TQ +.B \-\-vsim_prj +This action writes to \fIstdout\fP a shell script which will generated the +Vivado simulation snapshot and a short forwarder script for starting the +simulation. +. +.\" ---------------------------------------------- +.TP .BI \-\-ghdl_export \fR=\fPpath .TQ +.BI \-\-vsyn_export \fR=\fPpath +.TQ +.BI \-\-vsim_export \fR=\fPpath +.TQ +.BI \-\-xst_export \fR=\fPpath +.TQ .BI \-\-isim_export \fR=\fPpath -These three actions create a flat copy of all source files needed for a +These actions create a flat copy of all source files needed for a \fBxst\fP synthesis or a \fBghdl\fP or \fBISim\fP simulation model in the directory \fIpath\fP. The sub directory structure is lost, all files will be in directory @@ -508,6 +557,7 @@ output like in .BR rm_dep (1), .BR ghdl (1), .BR xtwi (1), +.BR xtwv (1), .BR cpp (1), .br .BR xise_ghdl_simprim (1), diff --git a/doc/man/man1/xtwi.1 b/doc/man/man1/xtwi.1 index fd02bd98..ab8b15a3 100644 --- a/doc/man/man1/xtwi.1 +++ b/doc/man/man1/xtwi.1 @@ -1,11 +1,11 @@ .\" -*- nroff -*- -.\" $Id: xtwi.1 651 2015-02-26 21:32:15Z mueller $ +.\" $Id: xtwi.1 746 2016-03-19 13:08:36Z mueller $ .\" -.\" Copyright 2014- by Walter F.J. Mueller +.\" Copyright 2014-2016 by Walter F.J. Mueller .\" .\" ------------------------------------------------------------------ . -.TH XTWI 1 2013-11-10 "Retro Project" "Retro Project Manual" +.TH XTWI 1 2016-03-19 "Retro Project" "Retro Project Manual" .\" ------------------------------------------------------------------ .SH NAME xtwi \- Xilinx Tool Wrapper script for ISE @@ -31,6 +31,9 @@ by the ISE installation procedure. and execs the \fICOMMAND\fP. This way \fICOMMAND\fP is executed in the ISE environment, while the login shell stays clean. +\fBxtwi\fP can also setup a clean environment when BARE_PATH and +BARE_LD_LIBRARY_PATH are defined. + . .\" ------------------------------------------------------------------ .SH ENVIRONMENT @@ -38,6 +41,23 @@ ISE environment, while the login shell stays clean. .B XTWI_PATH Install path of ISE, without the /ISE_DS/ appended by ISE installation . +.TP +.B BARE_PATH +Optional. If defined \fBxtwi\fP will set +.EX + export PATH=$BARE_PATH:$RETROBASE/tools/bin +.EE +LD_LIBRARY_PATH will be unset unless BARE_LD_LIBRARY_PATH is +defined too. +. +.TP +.B BARE_LD_LIBRARY_PATH +Optional. If defined \fBxtwi\fP will set +.EX + export LD_LIBRARY_PATH=$BARE_LD_LIBRARY_PATH +.EE +Used only when BARE_PATH is defined. +. .\" ------------------------------------------------------------------ .SH FILES .TP 4 diff --git a/doc/man/man1/xtwv.1 b/doc/man/man1/xtwv.1 index 008b7f59..5d3255bb 100644 --- a/doc/man/man1/xtwv.1 +++ b/doc/man/man1/xtwv.1 @@ -1,11 +1,11 @@ .\" -*- nroff -*- -.\" $Id: xtwv.1 651 2015-02-26 21:32:15Z mueller $ +.\" $Id: xtwv.1 746 2016-03-19 13:08:36Z mueller $ .\" -.\" Copyright 2014- by Walter F.J. Mueller +.\" Copyright 2014-2016 by Walter F.J. Mueller .\" .\" ------------------------------------------------------------------ . -.TH XTWV 1 2014-04-21 "Retro Project" "Retro Project Manual" +.TH XTWV 1 2016-03-19 "Retro Project" "Retro Project Manual" .\" ------------------------------------------------------------------ .SH NAME xtwv \- Xilinx Tool Wrapper script for Vivado @@ -30,6 +30,9 @@ of the Vivado version to be used. and execs the \fICOMMAND\fP. This way \fICOMMAND\fP is executed in the Vivado environment, while the login shell stays clean. +\fBxtwi\fP can also setup a clean environment when BARE_PATH and +BARE_LD_LIBRARY_PATH are defined. + . .\" ------------------------------------------------------------------ .SH ENVIRONMENT @@ -37,6 +40,23 @@ Vivado environment, while the login shell stays clean. .B BXTWV_PATH Install path of Vivado . +.TP +.B BARE_PATH +Optional. If defined \fBxtwi\fP will set +.EX + export PATH=$BARE_PATH:$RETROBASE/tools/bin +.EE +LD_LIBRARY_PATH will be unset unless BARE_LD_LIBRARY_PATH is +defined too. +. +.TP +.B BARE_LD_LIBRARY_PATH +Optional. If defined \fBxtwi\fP will set +.EX + export LD_LIBRARY_PATH=$BARE_LD_LIBRARY_PATH +.EE +Used only when BARE_PATH is defined. +. .\" ------------------------------------------------------------------ .SH FILES .TP 4 diff --git a/doc/man/man5/vbom.5 b/doc/man/man5/vbom.5 index 97442f85..e105ad60 100644 --- a/doc/man/man5/vbom.5 +++ b/doc/man/man5/vbom.5 @@ -1,11 +1,11 @@ .\" -*- nroff -*- -.\" $Id: vbom.5 646 2015-02-15 12:04:55Z mueller $ +.\" $Id: vbom.5 746 2016-03-19 13:08:36Z mueller $ .\" -.\" Copyright 2010-2015 by Walter F.J. Mueller +.\" Copyright 2010-2016 by Walter F.J. Mueller .\" .\" ------------------------------------------------------------------ . -.TH VBOM 2015-02-15 "Retro Project" "Retro Project Manual" +.TH VBOM 2016-03-19 "Retro Project" "Retro Project Manual" .\" ------------------------------------------------------------------ .SH NAME vbom \- vhdl manifest file format - 'vhdl bill of material' @@ -44,6 +44,14 @@ refers to a source file. Usually used for libraries refered to in 'use' clauses, and as last file, the source file of the entity which is described by this \fBvbom\fP file. . +.TP +.B "\fB.v\fP" +.TQ +.B "\fB.sv\fP" +refers to a verilog or system-verilog source file. Accepted by the vivado +xsim simulator. Typically used for DPI wrappers or simprim based models +in vivado. +. .IP "\fB.c\fP" refers to the C source which implements a \fIvhdl\fP function or procedure via the \fIvhpi\fP mechanism. Supported only in conjunction with \fBghdl\fP. @@ -74,14 +82,18 @@ Currently supported \fItag\fP names are .PD 0 .IP "\fBghdl\fP" 6 included in conjunction with ghdl simulation -.IP "\fBxst\fP" 6 -included in conjunction with ISE xst synthesis -.IP "\fBisim\fP" 6 -included in conjunction with ISE ISim simulation +.IP "\fBviv\fP" 6 +included in conjunction with Vivado targets .IP "\fBvsyn\fP" 6 included in conjunction with Vivado synthesis .IP "\fBvsim\fP" 6 included in conjunction with Vivado simulation +.IP "\fBise\fP" 6 +included in conjunction with ISE targets +.IP "\fBxst\fP" 6 +included in conjunction with ISE xst synthesis +.IP "\fBisim\fP" 6 +included in conjunction with ISE ISim simulation .IP "\fBsim\fP" 6 included in conjunction with simulation (ghdl,isim,vsim) .PD @@ -122,13 +134,20 @@ Specifies an additional system library. Allowed values for \fIname\fP are Currently used to generate the appropriate -L options for \fBghdl\fP commands, e.g. generated by the \fBvbomconv\fP action \fB\-\-ghdl_m\fP. . -.IP "\fB@ucf_cpp\fP:\fIfile\fP" -Specifies that a \fIfile\fP.ucf file is to be generated by \fBcpp\fP(1) -from a \fIfile\fP.ucf_cpp source file. This allows to modularize ISE ucf files. +.IP "\fB@uut\fP:\fIfile\fP" +Signals that the \fIvbom\fP descibes a test bench and that \fIfile\fP is +the 'unit under test'. This allows to split the sources into a simulation +only test bench part and a synthesizable 'unit under test' part. \fIfile\fP +is typically a \fIvbom\fP in case of a functional simulation or the file +name of a generated post synthesis model. . .IP "\fB@xdc\fP:\fIfile\fP" Specifies that \fIfile\fP is a constraint file for Vivado synthesis and should be included in the constraints fileset. +. +.IP "\fB@ucf_cpp\fP:\fIfile\fP" +Specifies that a \fIfile\fP.ucf file is to be generated by \fBcpp\fP(1) +from a \fIfile\fP.ucf_cpp source file. This allows to modularize ISE ucf files. .RE . .\" ------------------------------------------------------------------ diff --git a/doc/w11a_os_guide.txt b/doc/w11a_os_guide.txt index 915f9d4e..b5f0895b 100644 --- a/doc/w11a_os_guide.txt +++ b/doc/w11a_os_guide.txt @@ -1,4 +1,4 @@ -# $Id: w11a_os_guide.txt 680 2015-05-14 13:29:46Z mueller $ +# $Id: w11a_os_guide.txt 745 2016-03-18 22:10:34Z mueller $ Guide to run operating system images on w11a systems @@ -20,7 +20,7 @@ Guide to run operating system images on w11a systems - Serial port - via an integrated USB-UART bridge - - on basys3 and nexys4 with a FT2232HQ, allows up to 12M Baud + - on arty, basys3, and nexys4 with a FT2232HQ, allows up to 12M Baud - on nexys3 with a FT232R, allows up to 2M Baud - via RS232 port, as on s3board and nexys2 - using a serial port (/dev/ttySx) is limited to 115 kBaud on most PCs. @@ -45,18 +45,24 @@ Guide to run operating system images on w11a systems Recommended setup for best performance (boards ordered by vintage): - Board Channel/Interface nom. speed peak transfer rate + Board Channel/Interface nom. speed peak transfer rate - basys3 USB-UART bridge 10M Baud 910 kB/sec - nexys4 USB-UART bridge 10M Baud 910 kb/sec - nexys3 Cypress FX2 USB USB2.0 speed 30000 kB/sec - nexys2 Cypress FX2 USB USB2.0 speed 30000 kB/sec - s3board RS232+USB-RS232 cable 460k Baud 41 kB/sec + arty USB-UART bridge 10M Baud 910 kB/sec + basys3 USB-UART bridge 10M Baud 910 kB/sec + nexys4 USB-UART bridge 10M Baud 910 kb/sec + nexys3 Cypress FX2 USB USB2.0 speed 30000 kB/sec + nexys2 Cypress FX2 USB USB2.0 speed 30000 kB/sec + s3board RS232+USB-RS232 cable 460k Baud 41 kB/sec 2. FPGA Board setup ------------------------------------------------------- Recommended setups + - Arty + - connect USB cable to micro-USB connector labeled 'J10' + - to configure via vivado hardware server + make .vconfig + - Basys3 - connect USB cable to micro-USB connector labeled 'PROG' - to configure via vivado hardware server @@ -99,16 +105,24 @@ Guide to run operating system images on w11a systems are in the indicated positions (SWI=...). The concrete boot script name is given in the following sections - - for b3 over serial - SWI = 00000000 00101010 + - for arty over serial + SWI = 0110 (gives console light emulation...) ti_w11 -tu,10M,break,xon @_boot.tcl + NOTE: the arty w11a has currently only 176 kB memory (all from BRAMS!) + unix-v5 works fine. XXDP, RT11 and RSX-11M should work. + 211bsd will not boot, either most RSX-11M+ systems. + + - for b3 over serial + SWI = 00000000 00101000 (gives console light display on LEDS) + ti_w11 -tu,12M,break,xon @_boot.tcl + NOTE: the basys3 w11a has only 176 kB memory (all from BRAMS!) unix-v5 works fine. XXDP, RT11 and RSX-11M should work. 211bsd will not boot, either most RSX-11M+ systems. - for n4 over serial - SWI = 00000000 00101000 + SWI = 00000000 00101000 (gives console light display on LEDS) ti_w11 -tu,10M,break,cts @_boot.tcl - for n2,n3 over fx2 @@ -122,10 +136,10 @@ Guide to run operating system images on w11a systems Notes: - on , the serial device number - check with 'ls /dev/ttyUSB*' to see what is available - - is typically '1' if only a single basys3 or nexys4 is connected - Initially two ttyUSB devices show up, the lower is for FPGA config - and will disappear when Vivado hardware server is used once. The - upper provides the data connection. + - is typically '1' if a single FT2232HQ based boardis connected, + like a arty, basys3, or nexys4. Initially two ttyUSB devices show up, + the lower is for FPGA config and will disappear when Vivado hardware + server is used once. The upper provides the data connection. - is typically '0' if only a single USB-RS232 cable is connected - on LED display diff --git a/doc/w11a_tb_guide.txt b/doc/w11a_tb_guide.txt index c4de2626..cba088ca 100644 --- a/doc/w11a_tb_guide.txt +++ b/doc/w11a_tb_guide.txt @@ -1,7 +1,10 @@ -# $Id: w11a_tb_guide.txt 722 2015-12-30 19:45:46Z mueller $ +# $Id: w11a_tb_guide.txt 745 2016-03-18 22:10:34Z mueller $ -Note: Only ISE based test benches are currently documented ! - The Vivado test environemnt is still in it's infancy ! +Note: - Ghdl is used to all functional simulations + - Optionally Vivado xsim can be used (with some limitations) + - For post synthesis or post implementation simulations either + Ghdl or Vivado xsim (with some limitations) can be used. + - ISE isim is also available, but considered legacy support Guide to running w11a test benches @@ -45,15 +48,26 @@ Guide to running w11a test benches - Most tests can be run against - the functional model - - gate level models at three stages + + - gate level models at three stages (vivado flow) + - the post synthesis model (from *_syn.dcp) + - the post optimization model (from *_opt.dcp) + - the post routing model (from *_rou.dcp) + This is simply done using + make _ssim for post-synthesis + make _osim for post-optimization + make _tsim for post-routing + + - gate level models at three stages (ISE flow) - the post-xst model (produced by netgen from ngc xst output) - the post-map model (produced by netgen from ncd ngdbuild output) - the post-par model (produced by netgen from ncd par output) - This is simply done using - make _ssim for post-xst - make _fsim for post-map - make _tsim for post-par - all the rest is handled by the build environment. + This is simply done using + make _ssim for post-xst + make _fsim for post-map + make _tsim for post-par + + All the rest is handled by the build environment. An example of a post-synthesis model is given for the w11a core test. - for convenience a wrapper script 'tbrun_tbw' is used to generate the @@ -71,68 +85,69 @@ Guide to running w11a test benches cd $RETROBASE/rtl/vlib/serport/tb tbrun_tbw tb_serport_uart_rx -> 1269955.0 ns 63488: DONE - -> real 0m01.178s user 0m01.172s sys 0m00.020s + -> real 0m0.444s user 0m0.453s sys 0m0.007s - serport receiver/transmitter test tbrun_tbw tb_serport_uart_rxtx -> 52335.0 ns 2607: DONE - -> real 0m00.094s user 0m00.092s sys 0m00.008s + -> real 0m0.074s user 0m0.077s sys 0m0.010s - serport autobauder test tbrun_tbw tb_serport_autobaud -> 367475.0 ns 18364: DONE - -> real 0m00.610s user 0m00.612s sys 0m00.004s + -> real 0m0.247s user 0m0.258s sys 0m0.007s + - 9 bit comma,data to Byte stream converter test cd $RETROBASE/rtl/vlib/comlib/tb tbrun_tbw tb_cdata2byte - -> 7261.0 ns 354: DONE - -> real 0m0.385s user 0m0.041s sys 0m0.006s + -> 7261.0 ns 354: DONE + -> real 0m0.042s user 0m0.042s sys 0m0.019s - rlink core test cd $RETROBASE/rtl/vlib/rlink/tb tbrun_tbw tb_rlink_direct -> 78975.0 ns 3939: DONE - -> real 0m00.508s user 0m00.262s sys 0m00.028s + -> real 0m0.225s user 0m0.226s sys 0m0.025s - rlink core test via serial port interface cd $RETROBASE/rtl/vlib/rlink/tb tbrun_tbw --lsuf stim2_dsim tb_rlink_sp1c tb_rlink_sp1c_stim.dat -> 27595.0 ns 1370: DONE - -> real 0m0.250s user 0m0.108s sys 0m0.011s + -> real 0m0.098s user 0m0.111s sys 0m0.007s tbrun_tbw --lsuf stim1_dsim tb_rlink_sp1c tb_rlink_stim.dat -> 420295.0 ns 21005: DONE - -> real 0m02.271s user 0m01.360s sys 0m00.040s + -> real 0m0.942s user 0m0.947s sys 0m0.012s - w11a core test (using behavioural model) cd $RETROBASE/rtl/w11a/tb tbrun_tbw tb_pdp11core - -> 1220255.0 ns 61073: DONE - -> real 0m10.736s user 0m10.713s sys 0m00.060s + -> 225355.0 ns 61258: DONE + -> real 0m6.280s user 0m6.284s sys 0m0.018s - - w11a core test (using post-synthesis model) + - w11a core test (using Vivado post-synthesis model) tbrun_tbw tb_pdp11core_ssim - -> 1220255.0 ns 61073: DONE - -> real 1m09.738s user 1m09.588s sys 0m00.096s + -> 225355.0 ns 61258: DONE + -> real 2m4.138s user 2m4.063s sys 0m0.050s - s3board sram controller test cd $RETROBASE/rtl/bplib/s3board/tb tbrun_tbw tb_s3_sram_memctl -> 5015.0 ns 241: DONE - -> real 0m00.113s user 0m00.068s sys 0m00.016s + -> real 0m0.107s user 0m0.055s sys 0m0.020s - nexys2/nexys3 cram controller test cd $RETROBASE/rtl/bplib/nxcramlib/tb tbrun_tbw tb_nx_cram_memctl_as -> 24272.5 ns 1204: DONE - -> real 0m00.343s user 0m00.248s sys 0m00.100s + -> real 0m0.189s user 0m0.149s sys 0m0.055s 3. System tests benches --------------------------------------------------- @@ -162,62 +177,112 @@ Guide to running w11a test benches cd $RETROBASE/rtl/sys_gen/tst_serloop/s3board/tb tbrun_tbw tb_tst_serloop_s3 -> 301353.3 ns 18068: DONE - -> real 0m1.422s user 0m1.372s sys 0m0.024s + -> real 0m0.765s user 0m0.781s sys 0m0.013s - sys_tst_serloop_n2 test bench cd $RETROBASE/rtl/sys_gen/tst_serloop/nexys2/tb tbrun_tbw tb_tst_serloop1_n2 -> 361560.0 ns 18068: DONE - -> real 0m1.341s user 0m1.340s sys 0m0.016s + -> real 0m0.994s user 0m0.991s sys 0m0.022s tbrun_tbw tb_tst_serloop2_n2 -> 304353.3 ns 18248: DONE - -> real 0m1.933s user 0m1.924s sys 0m0.024s + -> real 0m1.543s user 0m1.561s sys 0m0.007s - sys_tst_serloop_n3 test bench cd $RETROBASE/rtl/sys_gen/tst_serloop/nexys3/tb tbrun_tbw tb_tst_serloop1_n3 -> 361560.0 ns 18068: DONE - -> real 0m1.371s user 0m1.372s sys 0m0.016s + -> real 0m0.740s user 0m0.755s sys 0m0.012s 4b. rlink tester ----------------------------------------------------- - The sys_tst_rlink design is a test target for validating the rlink - and rbus functionality at all levels. + The sys_tst_rlink design is a test target for validating the rlink and + rbus functionality at all levels. - - sys_tst_rlink_s3 test bench + - Artix based systems - cd $RETROBASE/rtl/sys_gen/tst_rlink/s3board/tb - tbrun_tbwrri --pack tst_rlink tb_tst_rlink_s3 \ - "tst_rlink::setup" "tst_rlink::test_all" - -> 1377680.0 ns 68874: DONE - -> real 0m6.876s user 0m6.790s sys 0m0.060s + - sys_tst_rlink_arty test bench + + cd $RETROBASE/rtl/sys_gen/tst_rlink/arty/tb + tbrun_tbwrri --hxon --pack tst_rlink tb_tst_rlink_arty \ + "tst_rlink::setup" "tst_rlink::test_all" + -> 764400.0 ns 76419: DONE + -> real 0m9.323s user 0m9.233s sys 0m0.080s - - sys_tst_rlink_n2 test bench + - sys_tst_rlink_b3 test bench + + cd $RETROBASE/rtl/sys_gen/tst_rlink/basys3/tb + tbrun_tbwrri --hxon --pack tst_rlink tb_tst_rlink_b3 \ + "tst_rlink::setup" "tst_rlink::test_all" + -> 763900.0 ns 76369: DONE + -> real 0m6.804s user 0m6.696s sys 0m0.085s + + - sys_tst_rlink_n4 test bench + + cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys4/tb + tbrun_tbwrri --pack tst_rlink tb_tst_rlink_n4 \ + "tst_rlink::setup" "tst_rlink::test_all" + -> 758010.0 ns 75780: DONE + -> real 0m10.198s user 0m10.081s sys 0m0.104s - cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys2/tb - tbrun_tbwrri --pack tst_rlink tb_tst_rlink_n2 \ + + - Spartan based systems + + - sys_tst_rlink_n3 test bench + + cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys3/tb + tbrun_tbwrri --fusp --pack tst_rlink tb_tst_rlink_n3 \ + "tst_rlink::setup" "tst_rlink::test_all" + -> 763770.0 ns 76356: DONE + -> real 0m5.955s user 0m5.834s sys 0m0.094s + + - sys_tst_rlink_n2 test bench + + cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys2/tb + tbrun_tbwrri --fusp --pack tst_rlink tb_tst_rlink_n2 \ + "tst_rlink::setup" "tst_rlink::test_all" + -> 1526860.0 ns 76332: DONE + -> real 0m8.607s user 0m8.448s sys 0m0.150s + + - sys_tst_rlink_s3 test bench + + cd $RETROBASE/rtl/sys_gen/tst_rlink/s3board/tb + tbrun_tbwrri --fusp --pack tst_rlink tb_tst_rlink_s3 \ + "tst_rlink::setup" "tst_rlink::test_all" + -> 1526540.0 ns 76317: DONE + -> real 0m5.650s user 0m5.571s sys 0m0.052s + +4c. rlink tester, Cypress FX2 based version -------------------------- + + The sys_tst_rlink_cuff design is a test target for validating the rlink and + rbus functionality at all levels over the Cypress FX2 USB interface which + is provided by the Nexys2 abd Nexys3 boards. + + - sys_tst_rlink_cuff_ic_n3 test bench + + cd $RETROBASE/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/tb + tbrun_tbwrri --cuff --pack tst_rlink tb_tst_rlink_cuff_ic_n3 \ "tst_rlink::setup" "tst_rlink::test_all" - -> 1378200.0 ns 68899: DONE - -> real 0m10.320s user 0m10.110s sys 0m0.204s + -> 440440.0 ns 44023: DONE + -> real 0m4.062s user 0m3.922s sys 0m0.111s - - sys_tst_rlink_n3 test bench + - sys_tst_rlink_cuff_ic_n2 test bench - cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys3/tb - tbrun_tbwrri --pack tst_rlink tb_tst_rlink_n3 \ + cd $RETROBASE/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb + tbrun_tbwrri --cuff --pack tst_rlink tb_tst_rlink_cuff_ic_n2 \ "tst_rlink::setup" "tst_rlink::test_all" - -> 689210.0 ns 68900: DONE - -> real 0m7.098s user 0m6.874s sys 0m0.191s + -> 466940.0 ns 23336: DONE + -> real 0m2.831s user 0m2.696s sys 0m0.101s -4c. w11a systems ----------------------------------------------------- +4d. w11a systems ----------------------------------------------------- - The stimulus file used in the w11a core test can be executed in the - full system context (both s3board and nexys2 versions) with the - following commands. Note that the cycle number printed in the DONE - line can now vary slightly because the response time of the rlink - backend process and thus scheduling of backend vs. ghdl process + The stimulus file used in the w11a core test can be executed in the full + system context with the following commands. Note that the cycle number + printed in the DONE line can now vary slightly because the response time of + the rlink backend process and thus scheduling of backend vs. ghdl process can affect the result. For convenience a wrapper script 'tbrun_tbwrri' is used to generate the @@ -225,32 +290,43 @@ Guide to running w11a test benches checks with 'make' whether the test bench is up-to-date or must be (re)-compiled. - - sys_w11a_s3 test bench + - Artix based systems - cd $RETROBASE/rtl/sys_gen/w11a/s3board/tb - tbrun_tbwrri --pack rw11 tb_w11a_s3 \ - "rw11::setup_cpu" \ - "rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat" - -> 9864500.0 ns 493215: DONE - -> real 0m59.728s user 0m58.586s sys 0m0.576s + cd $RETROBASE/rtl/sys_gen/w11a/nexys4/tb + tbrun_tbwrri --pack rw11 tb_w11a_n4 \ + "rw11::setup_cpu" \ + "rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat" + -> 6681310.0 ns 534488: DONE + -> real 1m26.253s user 1m26.139s sys 0m0.430s - - sys_w11a_n2 test bench + - Spartan based systems + - sys_w11a_n3 test bench + + cd $RETROBASE/rtl/sys_gen/w11a/nexys3/tb + tbrun_tbwrri --cuff --pack rw11 tb_w11a_n3 \ + "rw11::setup_cpu" \ + "rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat" + -> 3614866.2 ns 231338: DONE + -> real 0m47.290s user 0m46.975s sys 0m0.537s - cd $RETROBASE/rtl/sys_gen/w11a/nexys2/tb - tbrun_tbwrri --pack rw11 --cuff tb_w11a_n2 \ - "rw11::setup_cpu" \ - "rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat" - -> 3809180.0 ns 190448: DONE - -> real 0m55.733s user 0m55.504s sys 0m0.592s - - - sys_w11a_n3 test bench - - cd $RETROBASE/rtl/sys_gen/w11a/nexys3/tb - tbrun_tbwrri --pack rw11 --cuff tb_w11a_n3 \ - "rw11::setup_cpu" \ - "rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat" - -> 279834.9 ns 236133: DONE - -> real 0m59.998s user 0m59.676s sys 0m0.618s + - sys_w11a_n2 test bench + + cd $RETROBASE/rtl/sys_gen/w11a/nexys2/tb + tbrun_tbwrri --cuff --pack rw11 tb_w11a_n2 \ + "rw11::setup_cpu" \ + "rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat" + -> 4007500.0 ns 200364: DONE + -> real 0m43.803s user 0m43.698s sys 0m0.400s + + - sys_w11a_s3 test bench + + cd $RETROBASE/rtl/sys_gen/w11a/s3board/tb + tbrun_tbwrri --fusp --pack rw11 tb_w11a_s3 \ + "rw11::setup_cpu" \ + "rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat" + -> 10526060.0 ns 526293: DONE + -> real 1m13.659s user 1m13.467s sys 0m0.431s + A new, modular w11a test bench is under construction. So far it is very incomplete. This very preliminary version can be executed with @@ -258,14 +334,13 @@ Guide to running w11a test benches - sys_w11a_n2 test bench cd $RETROBASE/rtl/sys_gen/w11a/nexys2/tb - tbrun_tbwrri --lsuf tbench_dsim --pack rw11 --cuff tb_w11a_n2 \ + tbrun_tbwrri --cuff --lsuf tbench_dsim --pack rw11 tb_w11a_n2 \ "rw11::setup_cpu" "rw11::tbench @cpu_all.dat" - -> 3204500.0 ns 160214: DONE - -> real 0m44.753s user 0m45.361s sys 0m0.616s + -> 3280220.0 ns 164000: DONE + -> real 0m30.190s user 0m30.843s sys 0m0.577s - tbrun_tbwrri --lsuf tbench_dsim --pack rw11 --cuff tb_w11a_n2 \ + tbrun_tbwrri --cuff --lsuf tbench_dsim --pack rw11 tb_w11a_n2 \ "rw11::setup_cpu" "rw11::tbench @dev_all.dat" - -> 1369960.0 ns 68487: DONE - -> real 0m21.399s user 0m21.480s sys 0m0.254s - + -> 1387300.0 ns 69354: DONE + -> real 0m14.298s user 0m14.314s sys 0m0.240s diff --git a/rtl/bplib/arty/arty_pclk.xdc b/rtl/bplib/arty/arty_pclk.xdc new file mode 100644 index 00000000..2cf32046 --- /dev/null +++ b/rtl/bplib/arty/arty_pclk.xdc @@ -0,0 +1,14 @@ +# -*- tcl -*- +# $Id: arty_pclk.xdc 726 2016-01-31 23:02:31Z mueller $ +# +# Copyright 2016- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# Primary clocks for Digilent Arty +# +# Revision History: +# Date Rev Version Comment +# 2016-01-31 726 1.0 Initial version +# + +create_clock -name I_CLK100 -period 10 -waveform {0 5} [get_ports I_CLK100] diff --git a/rtl/bplib/arty/arty_pins.xdc b/rtl/bplib/arty/arty_pins.xdc new file mode 100644 index 00000000..e47a6cc9 --- /dev/null +++ b/rtl/bplib/arty/arty_pins.xdc @@ -0,0 +1,100 @@ +# -*- tcl -*- +# $Id: arty_pins.xdc 740 2016-03-06 20:56:56Z mueller $ +# +# Copyright 2016- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# Pin locks for Digilent Arty core functionality +# - USB UART +# - human I/O (switches, buttons, leds) +# +# Revision History: +# Date Rev Version Comment +# 2016-03-06 740 1.1 add A_VPWRP/N to baseline config +# 2016-01-31 726 1.0 Initial version +# + +# config setup -------------------------------------------------------------- +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] + +# clocks -- in bank 35 ------------------------------------------------------ +set_property PACKAGE_PIN e3 [get_ports {I_CLK100}] +set_property IOSTANDARD LVCMOS33 [get_ports {I_CLK100}] + +# +# USB UART Interface -- in bank 16 ------------------------------------------ +set_property PACKAGE_PIN a9 [get_ports {I_RXD}] +set_property PACKAGE_PIN d10 [get_ports {O_TXD}] + +set_property IOSTANDARD LVCMOS33 [get_ports {I_RXD O_TXD}] +set_property DRIVE 12 [get_ports {O_TXD}] +set_property SLEW SLOW [get_ports {O_TXD}] + +# +# switches -- in bank 16 ---------------------------------------------------- +set_property PACKAGE_PIN a8 [get_ports {I_SWI[0]}] +set_property PACKAGE_PIN c11 [get_ports {I_SWI[1]}] +set_property PACKAGE_PIN c10 [get_ports {I_SWI[2]}] +set_property PACKAGE_PIN a10 [get_ports {I_SWI[3]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {I_SWI[*]}] + +# +# buttons -- in bank 16 ----------------------------------------------------- +set_property PACKAGE_PIN d9 [get_ports {I_BTN[0]}] +set_property PACKAGE_PIN c9 [get_ports {I_BTN[1]}] +set_property PACKAGE_PIN b9 [get_ports {I_BTN[2]}] +set_property PACKAGE_PIN b8 [get_ports {I_BTN[3]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {I_BTN[*]}] + +# +# LEDs -- in bank 14+35 ----------------------------------------------------- +set_property PACKAGE_PIN h5 [get_ports {O_LED[0]}] +set_property PACKAGE_PIN j5 [get_ports {O_LED[1]}] +set_property PACKAGE_PIN t9 [get_ports {O_LED[2]}] +set_property PACKAGE_PIN t10 [get_ports {O_LED[3]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {O_LED[*]}] +set_property DRIVE 12 [get_ports {O_LED[*]}] +set_property SLEW SLOW [get_ports {O_LED[*]}] + +# +# RGB-LEDs -- in bank 35 ---------------------------------------------------- +# Note: [0] red [1] green [2] blue +set_property PACKAGE_PIN g6 [get_ports {O_RGBLED0[0]}] +set_property PACKAGE_PIN f6 [get_ports {O_RGBLED0[1]}] +set_property PACKAGE_PIN e1 [get_ports {O_RGBLED0[2]}] + +set_property PACKAGE_PIN g3 [get_ports {O_RGBLED1[0]}] +set_property PACKAGE_PIN j4 [get_ports {O_RGBLED1[1]}] +set_property PACKAGE_PIN g4 [get_ports {O_RGBLED1[2]}] + +set_property PACKAGE_PIN j3 [get_ports {O_RGBLED2[0]}] +set_property PACKAGE_PIN j2 [get_ports {O_RGBLED2[1]}] +set_property PACKAGE_PIN h4 [get_ports {O_RGBLED2[2]}] + +set_property PACKAGE_PIN k1 [get_ports {O_RGBLED3[0]}] +set_property PACKAGE_PIN h6 [get_ports {O_RGBLED3[1]}] +set_property PACKAGE_PIN k2 [get_ports {O_RGBLED3[2]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {O_RGBLED0[*] O_RGBLED1[*]}] +set_property DRIVE 12 [get_ports {O_RGBLED0[*] O_RGBLED1[*]}] +set_property SLEW SLOW [get_ports {O_RGBLED0[*] O_RGBLED1[*]}] +set_property IOSTANDARD LVCMOS33 [get_ports {O_RGBLED2[*] O_RGBLED3[*]}] +set_property DRIVE 12 [get_ports {O_RGBLED2[*] O_RGBLED3[*]}] +set_property SLEW SLOW [get_ports {O_RGBLED2[*] O_RGBLED3[*]}] + +# +# power measurements -- in bank 15 ------------------------------------------ +set_property PACKAGE_PIN c12 [get_ports {A_VPWRP[0]}]; # ad1p -> vaux(1) +set_property PACKAGE_PIN b12 [get_ports {A_VPWRN[0]}]; # ad1n (VU volt) +set_property PACKAGE_PIN b16 [get_ports {A_VPWRP[1]}]; # ad2p -> vaux(2) +set_property PACKAGE_PIN b17 [get_ports {A_VPWRN[1]}]; # ad2n (5V0 volt) +set_property PACKAGE_PIN f13 [get_ports {A_VPWRP[2]}]; # ad9p -> vaux(9) +set_property PACKAGE_PIN f14 [get_ports {A_VPWRN[2]}]; # ad9n (5V0 curr) +set_property PACKAGE_PIN a15 [get_ports {A_VPWRP[3]}]; # ad10p -> vaux(10) +set_property PACKAGE_PIN a16 [get_ports {A_VPWRN[3]}]; # ad10n (0V95 curr) + +set_property IOSTANDARD LVCMOS33 [get_ports {A_VPWRP[*] A_VPWRN[*]}] diff --git a/rtl/bplib/arty/arty_setup.tcl b/rtl/bplib/arty/arty_setup.tcl new file mode 100644 index 00000000..d710e353 --- /dev/null +++ b/rtl/bplib/arty/arty_setup.tcl @@ -0,0 +1,4 @@ +# $Id: arty_setup.tcl 726 2016-01-31 23:02:31Z mueller $ +# +set rvtb_part "xc7a35ticsg324-1l" +set rvtb_board "arty" diff --git a/rtl/bplib/arty/artylib.vhd b/rtl/bplib/arty/artylib.vhd new file mode 100644 index 00000000..4b2c7b85 --- /dev/null +++ b/rtl/bplib/arty/artylib.vhd @@ -0,0 +1,51 @@ +-- $Id: artylib.vhd 740 2016-03-06 20:56:56Z mueller $ +-- +-- Copyright 2016- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: artylib +-- Description: Digilent Arty components +-- +-- Dependencies: - +-- Tool versions: viv 2015.4; ghdl 0.33 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2016-03-06 740 1.1 add A_VPWRN/P to baseline config +-- 2016-01-31 726 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package artylib is + +component arty_aif is -- ARTY, abstract iface, base + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv4; -- arty switches + I_BTN : in slv4; -- arty buttons + O_LED : out slv4; -- arty leds + O_RGBLED0 : out slv3; -- arty rgb-led 0 + O_RGBLED1 : out slv3; -- arty rgb-led 1 + O_RGBLED2 : out slv3; -- arty rgb-led 2 + O_RGBLED3 : out slv3; -- arty rgb-led 3 + A_VPWRN : in slv4; -- arty pwrmon (neg) + A_VPWRP : in slv4 -- arty pwrmon (pos) + ); +end component; + +end package artylib; diff --git a/rtl/bplib/arty/tb/.cvsignore b/rtl/bplib/arty/tb/.cvsignore new file mode 100644 index 00000000..309dc6f9 --- /dev/null +++ b/rtl/bplib/arty/tb/.cvsignore @@ -0,0 +1 @@ +tb_arty_dummy diff --git a/rtl/bplib/arty/tb/Makefile b/rtl/bplib/arty/tb/Makefile new file mode 100644 index 00000000..1f091bcb --- /dev/null +++ b/rtl/bplib/arty/tb/Makefile @@ -0,0 +1,30 @@ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2016-01-31 726 1.0 Initial version +# +EXE_all = tb_arty_dummy +# +include ${RETROBASE}/rtl/make_viv/viv_default_arty.mk +# +.PHONY : all all_ssim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +# +clean : viv_clean ghdl_clean +# +#----- +# +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk +include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(wildcard *.o.dep_ghdl) +endif +# diff --git a/rtl/bplib/arty/tb/arty_dummy.vbom b/rtl/bplib/arty/tb/arty_dummy.vbom new file mode 100644 index 00000000..fd927542 --- /dev/null +++ b/rtl/bplib/arty/tb/arty_dummy.vbom @@ -0,0 +1,5 @@ +# libs +../../../vlib/slvtypes.vhd +# components +# design +arty_dummy.vhd diff --git a/rtl/bplib/arty/tb/arty_dummy.vhd b/rtl/bplib/arty/tb/arty_dummy.vhd new file mode 100644 index 00000000..fe7742f3 --- /dev/null +++ b/rtl/bplib/arty/tb/arty_dummy.vhd @@ -0,0 +1,65 @@ +-- $Id: arty_dummy.vhd 740 2016-03-06 20:56:56Z mueller $ +-- +-- Copyright 2016- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: arty_dummy - syn +-- Description: arty minimal target (base; serport loopback) +-- +-- Dependencies: - +-- To test: tb_arty +-- Target Devices: generic +-- Tool versions: viv 2015.4; ghdl 0.33 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2016-03-06 740 1.1 add A_VPWRN/P to baseline config +-- 2016-01-31 726 1.0 Initial version (cloned from basys3) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +entity arty_dummy is -- ARTY dummy (base; loopback) + -- implements arty_aif + port ( + I_CLK100 : in slbit; -- 100 MHz board clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv4; -- arty switches + I_BTN : in slv4; -- arty buttons + O_LED : out slv4; -- arty leds + O_RGBLED0 : out slv3; -- arty rgb-led 0 + O_RGBLED1 : out slv3; -- arty rgb-led 1 + O_RGBLED2 : out slv3; -- arty rgb-led 2 + O_RGBLED3 : out slv3; -- arty rgb-led 3 + A_VPWRN : in slv4; -- arty pwrmon (neg) + A_VPWRP : in slv4 -- arty pwrmon (pos) + ); +end arty_dummy; + +architecture syn of arty_dummy is + +begin + + O_TXD <= I_RXD; -- loop back serport + + O_LED <= I_SWI; -- mirror SWI on LED + + O_RGBLED0 <= I_BTN(2 downto 0); -- mirror BTN on RGBLED0 + O_RGBLED1 <= (others=>'0'); + O_RGBLED2 <= (others=>'0'); + O_RGBLED3 <= (others=>'0'); + +end syn; diff --git a/rtl/bplib/arty/tb/tb_arty.vbom b/rtl/bplib/arty/tb/tb_arty.vbom new file mode 100644 index 00000000..d10c6c8e --- /dev/null +++ b/rtl/bplib/arty/tb/tb_arty.vbom @@ -0,0 +1,23 @@ +# Not meant for direct top level usage. Used with +# tb_arty_(....)[_ssim].vbom and config +# lines to generate the different cases. +# +# libs +../../../vlib/slvtypes.vhd +../../../vlib/rlink/rlinklib.vbom +../../../vlib/xlib/xlib.vhd +../artylib.vhd +../../../vlib/simlib/simlib.vhd +../../../vlib/simlib/simbus.vhd +${sys_conf := sys_conf_sim.vhd} +# components +../../../vlib/simlib/simclk.vbom +../../../vlib/simlib/simclkcnt.vbom +../../../vlib/rlink/tbcore/tbcore_rlink.vbom +../../../vlib/xlib/tb/s7_cmt_sfs_tb.vbom +tb_arty_core.vbom +../../../vlib/serport/tb/serport_master_tb.vbom +@uut: ${arty_aif := arty_dummy.vbom} +# design +tb_arty.vhd +@top:tb_arty diff --git a/rtl/bplib/arty/tb/tb_arty.vhd b/rtl/bplib/arty/tb/tb_arty.vhd new file mode 100644 index 00000000..54f5a1d6 --- /dev/null +++ b/rtl/bplib/arty/tb/tb_arty.vhd @@ -0,0 +1,186 @@ +-- $Id: tb_arty.vhd 740 2016-03-06 20:56:56Z mueller $ +-- +-- Copyright 2016- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_arty - sim +-- Description: Test bench for arty (base) +-- +-- Dependencies: simlib/simclk +-- simlib/simclkcnt +-- rlink/tbcore/tbcore_rlink +-- xlib/tb/s7_cmt_sfs_tb +-- tb_basys3_core +-- serport/tb/serport_master_tb +-- arty_aif [UUT] +-- +-- To test: generic, any arty_aif target +-- +-- Target Devices: generic +-- Tool versions: viv 2015.4; ghdl 0.33 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2016-03-06 740 1.1 add A_VPWRN/P to baseline config +-- 2016-02-20 734 1.0.2 use s7_cmt_sfs_tb to avoid xsim conflict +-- 2016-02-13 730 1.0.1 direct instantiation of tbcore_rlink +-- 2016-01-31 726 1.0 Initial version (derived from tb_basys3) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.rlinklib.all; +use work.xlib.all; +use work.artylib.all; +use work.simlib.all; +use work.simbus.all; +use work.sys_conf.all; + +entity tb_arty is +end tb_arty; + +architecture sim of tb_arty is + + signal CLKOSC : slbit := '0'; -- board clock (100 Mhz) + signal CLKCOM : slbit := '0'; -- communication clock + + signal CLK_STOP : slbit := '0'; + signal CLKCOM_CYCLE : integer := 0; + + signal RESET : slbit := '0'; + signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !! + signal RXDATA : slv8 := (others=>'0'); + signal RXVAL : slbit := '0'; + signal RXERR : slbit := '0'; + signal RXACT : slbit := '0'; + signal TXDATA : slv8 := (others=>'0'); + signal TXENA : slbit := '0'; + signal TXBUSY : slbit := '0'; + + signal I_RXD : slbit := '1'; + signal O_TXD : slbit := '1'; + signal I_SWI : slv4 := (others=>'0'); + signal I_BTN : slv4 := (others=>'0'); + signal O_LED : slv4 := (others=>'0'); + signal O_RGBLED0 : slv3 := (others=>'0'); + signal O_RGBLED1 : slv3 := (others=>'0'); + signal O_RGBLED2 : slv3 := (others=>'0'); + signal O_RGBLED3 : slv3 := (others=>'0'); + + constant clock_period : time := 10 ns; + constant clock_offset : time := 200 ns; + +begin + + CLKGEN : simclk + generic map ( + PERIOD => clock_period, + OFFSET => clock_offset) + port map ( + CLK => CLKOSC, + CLK_STOP => CLK_STOP + ); + + CLKGEN_COM : entity work.s7_cmt_sfs_tb + generic map ( + VCO_DIVIDE => sys_conf_clkser_vcodivide, + VCO_MULTIPLY => sys_conf_clkser_vcomultiply, + OUT_DIVIDE => sys_conf_clkser_outdivide, + CLKIN_PERIOD => 10.0, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clkser_gentype) + port map ( + CLKIN => CLKOSC, + CLKFX => CLKCOM, + LOCKED => open + ); + + CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE); + + TBCORE : entity work.tbcore_rlink + port map ( + CLK => CLKCOM, + CLK_STOP => CLK_STOP, + RX_DATA => TXDATA, + RX_VAL => TXENA, + RX_HOLD => TXBUSY, + TX_DATA => RXDATA, + TX_ENA => RXVAL + ); + + ARTYCORE : entity work.tb_arty_core + port map ( + I_SWI => I_SWI, + I_BTN => I_BTN + ); + + UUT : arty_aif + port map ( + I_CLK100 => CLKOSC, + I_RXD => I_RXD, + O_TXD => O_TXD, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_RGBLED0 => O_RGBLED0, + O_RGBLED1 => O_RGBLED1, + O_RGBLED2 => O_RGBLED2, + O_RGBLED3 => O_RGBLED3, + A_VPWRN => (others=>'0'), + A_VPWRP => (others=>'0') + ); + + SERMSTR : entity work.serport_master_tb + generic map ( + CDWIDTH => CLKDIV'length) + port map ( + CLK => CLKCOM, + RESET => RESET, + CLKDIV => CLKDIV, + ENAXON => '0', -- FIXME: or 1 ??? + ENAESC => '0', + RXDATA => RXDATA, + RXVAL => RXVAL, + RXERR => RXERR, + RXOK => '1', + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY, + RXSD => O_TXD, + TXSD => I_RXD, + RXRTS_N => open, + TXCTS_N => '0' + ); + + proc_moni: process + variable oline : line; + begin + + loop + wait until rising_edge(CLKCOM); + + if RXERR = '1' then + writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1"); + writeline(output, oline); + end if; + + end loop; + + end process proc_moni; + +end sim; diff --git a/rtl/bplib/arty/tb/tb_arty_core.vbom b/rtl/bplib/arty/tb/tb_arty_core.vbom new file mode 100644 index 00000000..4516afc8 --- /dev/null +++ b/rtl/bplib/arty/tb/tb_arty_core.vbom @@ -0,0 +1,6 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/simlib/simbus.vhd +# components +# design +tb_arty_core.vhd diff --git a/rtl/bplib/arty/tb/tb_arty_core.vhd b/rtl/bplib/arty/tb/tb_arty_core.vhd new file mode 100644 index 00000000..af7b2325 --- /dev/null +++ b/rtl/bplib/arty/tb/tb_arty_core.vhd @@ -0,0 +1,70 @@ +-- $Id: tb_arty_core.vhd 726 2016-01-31 23:02:31Z mueller $ +-- +-- Copyright 2016- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_arty_core - sim +-- Description: Test bench for arty - core device handling +-- +-- Dependencies: - +-- +-- To test: generic, any arty target +-- +-- Target Devices: generic +-- Tool versions: viv 2015.4; ghdl 0.33 +-- Revision History: +-- Date Rev Version Comment +-- 2016-01-31 726 1.0 Initial version (derived from tb_basys3_core) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.simbus.all; + +entity tb_arty_core is + port ( + I_SWI : out slv4; -- arty switches + I_BTN : out slv4 -- arty buttons + ); +end tb_arty_core; + +architecture sim of tb_arty_core is + + signal R_SWI : slv4 := (others=>'0'); + signal R_BTN : slv4 := (others=>'0'); + + constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8)); + constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8)); + +begin + + proc_simbus: process (SB_VAL) + begin + if SB_VAL'event and to_x01(SB_VAL)='1' then + if SB_ADDR = sbaddr_swi then + R_SWI <= to_x01(SB_DATA(R_SWI'range)); + end if; + if SB_ADDR = sbaddr_btn then + R_BTN <= to_x01(SB_DATA(R_BTN'range)); + end if; + end if; + end process proc_simbus; + + I_SWI <= R_SWI; + I_BTN <= R_BTN; + +end sim; diff --git a/rtl/bplib/basys3/basys3_pclk.xdc b/rtl/bplib/basys3/basys3_pclk.xdc index 5029f0a9..968f200a 100644 --- a/rtl/bplib/basys3/basys3_pclk.xdc +++ b/rtl/bplib/basys3/basys3_pclk.xdc @@ -1,10 +1,10 @@ # -*- tcl -*- -# $Id: basys3_pclk.xdc 639 2015-01-30 18:12:19Z mueller $ +# $Id: basys3_pclk.xdc 726 2016-01-31 23:02:31Z mueller $ # # Copyright 2015- by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory # -# Primary clocks for Basys3 +# Primary clocks for Digilent Basys3 # # Revision History: # Date Rev Version Comment diff --git a/rtl/bplib/basys3/basys3_pins.xdc b/rtl/bplib/basys3/basys3_pins.xdc index ac82a8ca..a5f9de88 100644 --- a/rtl/bplib/basys3/basys3_pins.xdc +++ b/rtl/bplib/basys3/basys3_pins.xdc @@ -1,10 +1,10 @@ # -*- tcl -*- -# $Id: basys3_pins.xdc 640 2015-02-01 09:56:53Z mueller $ +# $Id: basys3_pins.xdc 726 2016-01-31 23:02:31Z mueller $ # # Copyright 2015- by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory # -# Pin locks for Basys 3 core functionality +# Pin locks for Digilent Basys 3 core functionality # - USB UART # - human I/O (switches, buttons, leds, display) # diff --git a/rtl/bplib/basys3/basys3lib.vhd b/rtl/bplib/basys3/basys3lib.vhd index e2bb6a2d..22de759b 100644 --- a/rtl/bplib/basys3/basys3lib.vhd +++ b/rtl/bplib/basys3/basys3lib.vhd @@ -1,4 +1,4 @@ --- $Id: basys3lib.vhd 635 2015-01-16 17:37:08Z mueller $ +-- $Id: basys3lib.vhd 726 2016-01-31 23:02:31Z mueller $ -- -- Copyright 2015- by Walter F.J. Mueller -- @@ -12,7 +12,7 @@ -- for complete details. -- ------------------------------------------------------------------------------ --- Package Name: basys3ib +-- Package Name: basys3lib -- Description: Basys 3 components -- -- Dependencies: - diff --git a/rtl/bplib/basys3/tb/tb_basys3.vbom b/rtl/bplib/basys3/tb/tb_basys3.vbom index b33dbe91..d2a55abb 100644 --- a/rtl/bplib/basys3/tb/tb_basys3.vbom +++ b/rtl/bplib/basys3/tb/tb_basys3.vbom @@ -5,8 +5,6 @@ # libs ../../../vlib/slvtypes.vhd ../../../vlib/rlink/rlinklib.vbom -../../../vlib/rlink/tb/rlinktblib.vhd -../../../vlib/serport/serportlib.vbom ../../../vlib/xlib/xlib.vhd ../basys3lib.vhd ../../../vlib/simlib/simlib.vhd @@ -15,11 +13,11 @@ ${sys_conf := sys_conf_sim.vhd} # components ../../../vlib/simlib/simclk.vbom ../../../vlib/simlib/simclkcnt.vbom -../../../vlib/rlink/tb/tbcore_rlink.vbom -../../../vlib/xlib/s7_cmt_sfs_gsim.vbom +../../../vlib/rlink/tbcore/tbcore_rlink.vbom +../../../vlib/xlib/tb/s7_cmt_sfs_tb.vbom tb_basys3_core.vbom -../../../vlib/serport/serport_master.vbom -${basys3_aif := basys3_dummy.vbom} +../../../vlib/serport/tb/serport_master_tb.vbom +@uut: ${basys3_aif := basys3_dummy.vbom} # design tb_basys3.vhd @top:tb_basys3 diff --git a/rtl/bplib/basys3/tb/tb_basys3.vhd b/rtl/bplib/basys3/tb/tb_basys3.vhd index 257fb381..1bbbd21e 100644 --- a/rtl/bplib/basys3/tb/tb_basys3.vhd +++ b/rtl/bplib/basys3/tb/tb_basys3.vhd @@ -1,6 +1,6 @@ --- $Id: tb_basys3.vhd 666 2015-04-12 21:17:54Z mueller $ +-- $Id: tb_basys3.vhd 734 2016-02-20 22:43:20Z mueller $ -- --- Copyright 2015- by Walter F.J. Mueller +-- Copyright 2015-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -17,19 +17,22 @@ -- -- Dependencies: simlib/simclk -- simlib/simclkcnt --- rlink/tb/tbcore_rlink --- xlib/s7_cmt_sfs +-- rlink/tbcore/tbcore_rlink +-- xlib/tb/s7_cmt_sfs_tb -- tb_basys3_core --- serport/serport_master +-- serport/tb/serport_master_tb -- basys3_aif [UUT] -- -- To test: generic, any basys3_aif target -- -- Target Devices: generic --- Tool versions: viv 2014.4; ghdl 0.31 +-- Tool versions: viv 2014.4-2015.4; ghdl 0.31 -- -- Revision History: -- Date Rev Version Comment +-- 2016-02-20 734 1.1.3 use s7_cmt_sfs_tb to avoid xsim conflict +-- 2016-02-13 730 1.1.2 direct instantiation of tbcore_rlink +-- 2016-01-03 724 1.1.1 use serport/tb/serport_master_tb -- 2015-04-12 666 1.1 use serport_master instead of serport_uart_rxtx -- 2015-02-18 648 1.0 Initial version (derived from tb_nexys4) ------------------------------------------------------------------------------ @@ -42,8 +45,6 @@ use std.textio.all; use work.slvtypes.all; use work.rlinklib.all; -use work.rlinktblib.all; -use work.serportlib.all; use work.xlib.all; use work.basys3lib.all; use work.simlib.all; @@ -97,7 +98,7 @@ begin CLK_STOP => CLK_STOP ); - CLKGEN_COM : s7_cmt_sfs + CLKGEN_COM : entity work.s7_cmt_sfs_tb generic map ( VCO_DIVIDE => sys_conf_clkser_vcodivide, VCO_MULTIPLY => sys_conf_clkser_vcomultiply, @@ -105,7 +106,7 @@ begin CLKIN_PERIOD => 10.0, CLKIN_JITTER => 0.01, STARTUP_WAIT => false, - GEN_TYPE => sys_conf_clksys_gentype) + GEN_TYPE => sys_conf_clkser_gentype) port map ( CLKIN => CLKOSC, CLKFX => CLKCOM, @@ -114,7 +115,7 @@ begin CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE); - TBCORE : tbcore_rlink + TBCORE : entity work.tbcore_rlink port map ( CLK => CLKCOM, CLK_STOP => CLK_STOP, @@ -125,7 +126,7 @@ begin TX_ENA => RXVAL ); - N4CORE : entity work.tb_basys3_core + B3CORE : entity work.tb_basys3_core port map ( I_SWI => I_SWI, I_BTN => I_BTN @@ -143,7 +144,7 @@ begin O_SEG_N => O_SEG_N ); - SERMSTR : serport_master + SERMSTR : entity work.serport_master_tb generic map ( CDWIDTH => CLKDIV'length) port map ( diff --git a/rtl/bplib/basys3/tb/tb_basys3_core.vbom b/rtl/bplib/basys3/tb/tb_basys3_core.vbom index a84f8ad3..ded44405 100644 --- a/rtl/bplib/basys3/tb/tb_basys3_core.vbom +++ b/rtl/bplib/basys3/tb/tb_basys3_core.vbom @@ -1,9 +1,6 @@ # libs ../../../vlib/slvtypes.vhd -../../../vlib/serport/serportlib.vbom ../../../vlib/simlib/simbus.vhd # components -../../../vlib/serport/serport_uart_rx.vbom -../../../vlib/serport/serport_uart_tx.vbom # design tb_basys3_core.vhd diff --git a/rtl/bplib/basys3/tb/tb_basys3_core.vhd b/rtl/bplib/basys3/tb/tb_basys3_core.vhd index c0400fdd..46df67e9 100644 --- a/rtl/bplib/basys3/tb/tb_basys3_core.vhd +++ b/rtl/bplib/basys3/tb/tb_basys3_core.vhd @@ -1,4 +1,4 @@ --- $Id: tb_basys3_core.vhd 648 2015-02-20 20:16:21Z mueller $ +-- $Id: tb_basys3_core.vhd 724 2016-01-03 22:53:53Z mueller $ -- -- Copyright 2015- by Walter F.J. Mueller -- @@ -33,7 +33,6 @@ use ieee.std_logic_textio.all; use std.textio.all; use work.slvtypes.all; -use work.serportlib.all; use work.simbus.all; entity tb_basys3_core is diff --git a/rtl/bplib/bpgen/Makefile b/rtl/bplib/bpgen/Makefile index 68c92e49..f8e67068 100644 --- a/rtl/bplib/bpgen/Makefile +++ b/rtl/bplib/bpgen/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -14,7 +14,7 @@ NGC_all = $(VBOM_all:.vbom=.ngc) ifndef XTW_BOARD XTW_BOARD=nexys3 endif -include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk +include ${RETROBASE}/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # .PHONY : all clean # @@ -24,7 +24,7 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/bplib/bpgen/bpgenlib.vhd b/rtl/bplib/bpgen/bpgenlib.vhd index 3e60bec6..02d464b2 100644 --- a/rtl/bplib/bpgen/bpgenlib.vhd +++ b/rtl/bplib/bpgen/bpgenlib.vhd @@ -1,6 +1,6 @@ --- $Id: bpgenlib.vhd 637 2015-01-25 18:36:40Z mueller $ +-- $Id: bpgenlib.vhd 737 2016-02-28 09:07:18Z mueller $ -- --- Copyright 2011-2015 by Walter F.J. Mueller +-- Copyright 2011-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,9 +16,10 @@ -- Description: Generic Board/Part components -- -- Dependencies: - --- Tool versions: ise 12.1-14.7; viv 2014.4; ghdl 0.26-0.31 +-- Tool versions: ise 12.1-14.7; viv 2014.4-2015.4; ghdl 0.26-0.31 -- Revision History: -- Date Rev Version Comment +-- 2016-02-27 737 1.2 add rgbdrv entity -- 2015-01-24 637 1.1.2 add generics to sn_humanio and sn_7segctl -- 2013-09-21 534 1.1.1 add bp_rs232_4l4l_iob -- 2013-01-26 476 1.1 moved rbus depended components to bpgenrbuslib @@ -180,4 +181,60 @@ component sn_humanio_demu is -- human i/o handling: swi,btn,led only ); end component; +component rgbdrv_master is -- rgbled driver: master + generic ( + DWIDTH : positive := 8); -- dimmer width + port ( + CLK : in slbit; -- clock + RESET : in slbit := '0'; -- reset + CE_USEC : in slbit; -- 1 us clock enable + RGBCNTL : out slv3; -- rgb control + DIMCNTL : out slv(DWIDTH-1 downto 0) -- dim control + ); +end component; + +component rgbdrv_analog is -- rgbled driver: analog channel + generic ( + DWIDTH : positive := 8); -- dimmer width + port ( + CLK : in slbit; -- clock + RESET : in slbit := '0'; -- reset + RGBCNTL : in slv3; -- rgb control + DIMCNTL : in slv(DWIDTH-1 downto 0);-- dim control + DIMR : in slv(DWIDTH-1 downto 0); -- dim red + DIMG : in slv(DWIDTH-1 downto 0); -- dim green + DIMB : in slv(DWIDTH-1 downto 0); -- dim blue + O_RGBLED : out slv3 -- pad-o: rgb led + ); +end component; + +component rgbdrv_binary is -- rgbled driver: binary channel + generic ( + DWIDTH : positive := 8); -- dimmer width + port ( + CLK : in slbit; -- clock + RESET : in slbit := '0'; -- reset + RGBCNTL : in slv3; -- rgb control + DIMCNTL : in slv(DWIDTH-1 downto 0);-- dim control + DIM : in slv(DWIDTH-1 downto 0); -- dim + ENARGB : in slv3; -- enable [0] red [1] green [2] blue + O_RGBLED : out slv3 -- pad-o: rgb led + ); +end component; + +component rgbdrv_3x4mux is -- rgbled driver: mux three 4bit inputs + port ( + CLK : in slbit; -- clock + RESET : in slbit := '0'; -- reset + CE_USEC : in slbit; -- 1 us clock enable + DATR : in slv4; -- red data + DATG : in slv4; -- green data + DATB : in slv4; -- blue data + O_RGBLED0 : out slv3; -- pad-o: rgb led 0 + O_RGBLED1 : out slv3; -- pad-o: rgb led 1 + O_RGBLED2 : out slv3; -- pad-o: rgb led 2 + O_RGBLED3 : out slv3 -- pad-o: rgb led 3 + ); +end component; + end package bpgenlib; diff --git a/rtl/bplib/bpgen/bpgenrbuslib.vhd b/rtl/bplib/bpgen/bpgenrbuslib.vhd index e73e2b9d..4fa989fa 100644 --- a/rtl/bplib/bpgen/bpgenrbuslib.vhd +++ b/rtl/bplib/bpgen/bpgenrbuslib.vhd @@ -1,6 +1,6 @@ --- $Id: bpgenrbuslib.vhd 637 2015-01-25 18:36:40Z mueller $ +-- $Id: bpgenrbuslib.vhd 734 2016-02-20 22:43:20Z mueller $ -- --- Copyright 2013-2015 by Walter F.J. Mueller +-- Copyright 2013-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,9 +16,10 @@ -- Description: Generic Board/Part components using rbus -- -- Dependencies: - --- Tool versions: ise 12.1-14.7; viv 2014.4; ghdl 0.26-0.31 +-- Tool versions: ise 12.1-14.7; viv 2014.4-2015.4; ghdl 0.26-0.31 -- Revision History: -- Date Rev Version Comment +-- 2016-02-20 734 1.3 add rgbdrv_analog_rbus -- 2015-01-25 637 1.2 add generics to sn_humanio_rbus -- 2014-08-15 583 1.1 rb_mreq addr now 16 bit -- 2013-01-26 476 1.0 Initial version (extracted from bpgenlib) @@ -103,4 +104,19 @@ component sn_humanio_demu_rbus is -- human i/o swi,btn,led only /w rbus ); end component; +component rgbdrv_analog_rbus is -- rgb analog from rbus + generic ( + DWIDTH : positive := 8; -- dimmer width + RB_ADDR : slv16 := slv(to_unsigned(16#0000#,16))); + port ( + CLK : in slbit; -- clock + RESET : in slbit := '0'; -- reset + RB_MREQ : in rb_mreq_type; -- rbus: request + RB_SRES : out rb_sres_type; -- rbus: response + RGBCNTL : in slv3; -- rgb control + DIMCNTL : in slv(DWIDTH-1 downto 0);-- dim control + O_RGBLED : out slv3 -- pad-o: rgb led + ); +end component; + end package bpgenrbuslib; diff --git a/rtl/bplib/bpgen/rgbdrv_3x4mux.vbom b/rtl/bplib/bpgen/rgbdrv_3x4mux.vbom new file mode 100644 index 00000000..c8b9bb78 --- /dev/null +++ b/rtl/bplib/bpgen/rgbdrv_3x4mux.vbom @@ -0,0 +1,7 @@ +# libs +../../vlib/slvtypes.vhd +../../vlib/xlib/xlib.vhd +# components +../../vlib/xlib/iob_reg_o_gen.vbom +# design +rgbdrv_3x4mux.vhd diff --git a/rtl/bplib/bpgen/rgbdrv_3x4mux.vhd b/rtl/bplib/bpgen/rgbdrv_3x4mux.vhd new file mode 100644 index 00000000..cf093c7b --- /dev/null +++ b/rtl/bplib/bpgen/rgbdrv_3x4mux.vhd @@ -0,0 +1,120 @@ +-- $Id: rgbdrv_3x4mux.vhd 737 2016-02-28 09:07:18Z mueller $ +-- +-- Copyright 2016- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: rgbdrv_3x4mux - syn +-- Description: rgbled driver: mux three 4bit inputs +-- +-- Dependencies: xlib/iob_reg_o_gen +-- Test bench: - +-- Target Devices: generic +-- Tool versions: viv 2015.4; ghdl 0.31 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2016-02-27 737 1.0 Initial version (re-write, new logic) +-- 2016-02-20 734 0.1 First draft +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.xlib.all; + +entity rgbdrv_3x4mux is -- rgbled driver: mux three 4bit inputs + port ( + CLK : in slbit; -- clock + RESET : in slbit := '0'; -- reset + CE_USEC : in slbit; -- 1 us clock enable + DATR : in slv4; -- red data + DATG : in slv4; -- green data + DATB : in slv4; -- blue data + O_RGBLED0 : out slv3; -- pad-o: rgb led 0 + O_RGBLED1 : out slv3; -- pad-o: rgb led 1 + O_RGBLED2 : out slv3; -- pad-o: rgb led 2 + O_RGBLED3 : out slv3 -- pad-o: rgb led 3 + ); +end rgbdrv_3x4mux; + + +architecture syn of rgbdrv_3x4mux is + + signal R_LED : slv4 := "0001"; + signal R_COL : slv3 := "001"; + signal R_DIM : slbit := '1'; + + signal RGB0 : slv3 := (others=>'0'); + signal RGB1 : slv3 := (others=>'0'); + signal RGB2 : slv3 := (others=>'0'); + signal RGB3 : slv3 := (others=>'0'); + +begin + + IOB_RGB0: iob_reg_o_gen + generic map (DWIDTH => 3) + port map (CLK => CLK, CE => '1', DO => RGB0, PAD => O_RGBLED0); + IOB_RGB1: iob_reg_o_gen + generic map (DWIDTH => 3) + port map (CLK => CLK, CE => '1', DO => RGB1, PAD => O_RGBLED1); + IOB_RGB2: iob_reg_o_gen + generic map (DWIDTH => 3) + port map (CLK => CLK, CE => '1', DO => RGB2, PAD => O_RGBLED2); + IOB_RGB3: iob_reg_o_gen + generic map (DWIDTH => 3) + port map (CLK => CLK, CE => '1', DO => RGB3, PAD => O_RGBLED3); + + proc_regs: process (CLK) + begin + + if rising_edge(CLK) then + if RESET = '1' then + R_LED <= "0001"; + R_COL <= "001"; + R_DIM <= '1'; + else + if CE_USEC = '1' then + R_DIM <= not R_DIM; + if R_DIM = '1' then + R_COL <= R_COL(1) & R_COL(0) & R_COL(2); + if R_COL(2) = '1' then + R_LED <= R_LED(2) & R_LED(1) & R_LED(0) & R_LED(3); + end if; + end if; + end if; + end if; + end if; + + end process proc_regs; + + proc_mux: process (R_DIM, R_COL, R_LED, DATR, DATG, DATB) + begin + RGB0(0) <= (not R_DIM) and R_COL(0) and R_LED(0) and DATR(0); + RGB0(1) <= (not R_DIM) and R_COL(1) and R_LED(0) and DATG(0); + RGB0(2) <= (not R_DIM) and R_COL(2) and R_LED(0) and DATB(0); + + RGB1(0) <= (not R_DIM) and R_COL(0) and R_LED(1) and DATR(1); + RGB1(1) <= (not R_DIM) and R_COL(1) and R_LED(1) and DATG(1); + RGB1(2) <= (not R_DIM) and R_COL(2) and R_LED(1) and DATB(1); + + RGB2(0) <= (not R_DIM) and R_COL(0) and R_LED(2) and DATR(2); + RGB2(1) <= (not R_DIM) and R_COL(1) and R_LED(2) and DATG(2); + RGB2(2) <= (not R_DIM) and R_COL(2) and R_LED(2) and DATB(2); + + RGB3(0) <= (not R_DIM) and R_COL(0) and R_LED(3) and DATR(3); + RGB3(1) <= (not R_DIM) and R_COL(1) and R_LED(3) and DATG(3); + RGB3(2) <= (not R_DIM) and R_COL(2) and R_LED(3) and DATB(3); + end process proc_mux; + +end syn; diff --git a/rtl/bplib/bpgen/rgbdrv_analog.vbom b/rtl/bplib/bpgen/rgbdrv_analog.vbom new file mode 100644 index 00000000..21372b60 --- /dev/null +++ b/rtl/bplib/bpgen/rgbdrv_analog.vbom @@ -0,0 +1,7 @@ +# libs +../../vlib/slvtypes.vhd +../../vlib/xlib/xlib.vhd +# components +../../vlib/xlib/iob_reg_o_gen.vbom +# design +rgbdrv_analog.vhd diff --git a/rtl/bplib/bpgen/rgbdrv_analog.vhd b/rtl/bplib/bpgen/rgbdrv_analog.vhd new file mode 100644 index 00000000..961df751 --- /dev/null +++ b/rtl/bplib/bpgen/rgbdrv_analog.vhd @@ -0,0 +1,98 @@ +-- $Id: rgbdrv_analog.vhd 734 2016-02-20 22:43:20Z mueller $ +-- +-- Copyright 2016- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: rgbdrv_analog - syn +-- Description: rgbled driver: analog channel +-- +-- Dependencies: - +-- Test bench: - +-- Target Devices: generic +-- Tool versions: viv 2015.4; ghdl 0.31 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2016-02-20 734 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.xlib.all; + +entity rgbdrv_analog is -- rgbled driver: analog channel + generic ( + DWIDTH : positive := 8); -- dimmer width + port ( + CLK : in slbit; -- clock + RESET : in slbit := '0'; -- reset + RGBCNTL : in slv3; -- rgb control + DIMCNTL : in slv(DWIDTH-1 downto 0);-- dim control + DIMR : in slv(DWIDTH-1 downto 0); -- dim red + DIMG : in slv(DWIDTH-1 downto 0); -- dim green + DIMB : in slv(DWIDTH-1 downto 0); -- dim blue + O_RGBLED : out slv3 -- pad-o: rgb led + ); +end rgbdrv_analog; + +architecture syn of rgbdrv_analog is + + signal R_RGB : slv3 := (others=>'0'); -- state registers + signal N_RGB : slv3 := (others=>'0'); -- next value state regs + +begin + + IOB_RGB : iob_reg_o_gen + generic map (DWIDTH => 3) + port map (CLK => CLK, CE => '1', DO => R_RGB, PAD => O_RGBLED); + + proc_regs: process (CLK) + begin + + if rising_edge(CLK) then + if RESET = '1' then + R_RGB <= (others=>'0'); + else + R_RGB <= N_RGB; + end if; + end if; + + end process proc_regs; + + + proc_next: process (R_RGB, RGBCNTL, DIMCNTL, DIMR, DIMG, DIMB) + variable irgb : slv3 := (others=>'0'); + begin + + irgb := (others=>'0'); + + if unsigned(DIMCNTL) < unsigned(DIMR) then + irgb(0) := RGBCNTL(0); + end if; + + if unsigned(DIMCNTL) < unsigned(DIMG) then + irgb(1) := RGBCNTL(1); + end if; + + if unsigned(DIMCNTL) < unsigned(DIMB) then + irgb(2) := RGBCNTL(2); + end if; + + N_RGB <= irgb; + + end process proc_next; + + +end syn; diff --git a/rtl/bplib/bpgen/rgbdrv_analog_rbus.vbom b/rtl/bplib/bpgen/rgbdrv_analog_rbus.vbom new file mode 100644 index 00000000..0521b5ce --- /dev/null +++ b/rtl/bplib/bpgen/rgbdrv_analog_rbus.vbom @@ -0,0 +1,8 @@ +# libs +../../vlib/slvtypes.vhd +../../vlib/rbus/rblib.vhd +bpgenlib.vbom +# components +rgbdrv_analog.vbom +# design +rgbdrv_analog_rbus.vhd diff --git a/rtl/bplib/bpgen/rgbdrv_analog_rbus.vhd b/rtl/bplib/bpgen/rgbdrv_analog_rbus.vhd new file mode 100644 index 00000000..871da233 --- /dev/null +++ b/rtl/bplib/bpgen/rgbdrv_analog_rbus.vhd @@ -0,0 +1,193 @@ +-- $Id: rgbdrv_analog_rbus.vhd 734 2016-02-20 22:43:20Z mueller $ +-- +-- Copyright 2016- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: rgbdrv_analog_rbus - syn +-- Description: rgb analog from rbus +-- +-- Dependencies: bpgen/rgbdrv_analog +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: ise 14.7; viv 2015.4; ghdl 0.31 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2016-02-20 724 1.0 Initial version +------------------------------------------------------------------------------ +-- +-- rbus registers: +-- +-- Addr Bits Name r/w/f Function +-- 00 red r/w/- red channel +-- 01 green r/w/- green channel +-- 10 blue r/w/- blue channel +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.rblib.all; +use work.bpgenlib.all; + +-- ---------------------------------------------------------------------------- + +entity rgbdrv_analog_rbus is -- rgb analog from rbus + generic ( + DWIDTH : positive := 8; -- dimmer width + RB_ADDR : slv16 := slv(to_unsigned(16#0000#,16))); + port ( + CLK : in slbit; -- clock + RESET : in slbit := '0'; -- reset + RB_MREQ : in rb_mreq_type; -- rbus: request + RB_SRES : out rb_sres_type; -- rbus: response + RGBCNTL : in slv3; -- rgb control + DIMCNTL : in slv(DWIDTH-1 downto 0);-- dim control + O_RGBLED : out slv3 -- pad-o: rgb led + ); +end rgbdrv_analog_rbus; + +architecture syn of rgbdrv_analog_rbus is + + type regs_type is record + rbsel : slbit; -- rbus select + dimr : slv(DWIDTH-1 downto 0); -- dim red + dimg : slv(DWIDTH-1 downto 0); -- dim green + dimb : slv(DWIDTH-1 downto 0); -- dim blue + end record regs_type; + + constant dimzero : slv(DWIDTH-1 downto 0) := (others=>'0'); + + constant regs_init : regs_type := ( + '0', -- rbsel + dimzero, -- dimr + dimzero, -- dimg + dimzero -- dimb + ); + + signal R_REGS : regs_type := regs_init; -- state registers + signal N_REGS : regs_type := regs_init; -- next value state regs + + subtype dim_rbf is integer range DWIDTH-1 downto 0; + + constant rbaddr_dimr: slv2 := "00"; -- 0 r/w/- + constant rbaddr_dimg: slv2 := "01"; -- 1 r/w/- + constant rbaddr_dimb: slv2 := "10"; -- 2 r/w/- + +begin + + assert DWIDTH<=16 + report "assert (DWIDTH<=16)" + severity failure; + + RGB : rgbdrv_analog + generic map ( + DWIDTH => DWIDTH) + port map ( + CLK => CLK, + RESET => RESET, + RGBCNTL => RGBCNTL, + DIMCNTL => DIMCNTL, + DIMR => R_REGS.dimr, + DIMG => R_REGS.dimg, + DIMB => R_REGS.dimb, + O_RGBLED => O_RGBLED + ); + + proc_regs: process (CLK) + begin + + if rising_edge(CLK) then + if RESET = '1' then + R_REGS <= regs_init; + else + R_REGS <= N_REGS; + end if; + end if; + + end process proc_regs; + + proc_next: process (R_REGS, RB_MREQ) + + variable r : regs_type := regs_init; + variable n : regs_type := regs_init; + + variable irb_ack : slbit := '0'; + variable irb_busy : slbit := '0'; + variable irb_err : slbit := '0'; + variable irb_dout : slv16 := (others=>'0'); + variable irbena : slbit := '0'; + + begin + + r := R_REGS; + n := R_REGS; + + irb_ack := '0'; + irb_busy := '0'; + irb_err := '0'; + irb_dout := (others=>'0'); + + irbena := RB_MREQ.re or RB_MREQ.we; + + -- rbus address decoder + n.rbsel := '0'; + if RB_MREQ.aval='1' and RB_MREQ.addr(15 downto 2)=RB_ADDR(15 downto 2) then + n.rbsel := '1'; + end if; + + -- rbus transactions + if r.rbsel = '1' then + irb_ack := irbena; -- ack all accesses + + case RB_MREQ.addr(1 downto 0) is + + when rbaddr_dimr => + irb_dout(dim_rbf) := r.dimr; + if RB_MREQ.we = '1' then + n.dimr := RB_MREQ.din(dim_rbf); + end if; + + when rbaddr_dimg => + irb_dout(dim_rbf) := r.dimg; + if RB_MREQ.we = '1' then + n.dimg := RB_MREQ.din(dim_rbf); + end if; + + when rbaddr_dimb => + irb_dout(dim_rbf) := r.dimb; + if RB_MREQ.we = '1' then + n.dimb := RB_MREQ.din(dim_rbf); + end if; + + when others => + irb_ack := '0'; + + end case; + + end if; + + N_REGS <= n; + + RB_SRES <= rb_sres_init; + RB_SRES.ack <= irb_ack; + RB_SRES.busy <= irb_busy; + RB_SRES.err <= irb_err; + RB_SRES.dout <= irb_dout; + + end process proc_next; + +end syn; diff --git a/rtl/bplib/bpgen/rgbdrv_master.vbom b/rtl/bplib/bpgen/rgbdrv_master.vbom new file mode 100644 index 00000000..a8ef5c1b --- /dev/null +++ b/rtl/bplib/bpgen/rgbdrv_master.vbom @@ -0,0 +1,5 @@ +# libs +../../vlib/slvtypes.vhd +# components +# design +rgbdrv_master.vhd diff --git a/rtl/bplib/bpgen/rgbdrv_master.vhd b/rtl/bplib/bpgen/rgbdrv_master.vhd new file mode 100644 index 00000000..29a1b5ea --- /dev/null +++ b/rtl/bplib/bpgen/rgbdrv_master.vhd @@ -0,0 +1,103 @@ +-- $Id: rgbdrv_master.vhd 734 2016-02-20 22:43:20Z mueller $ +-- +-- Copyright 2016- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: rgbdrv_master - syn +-- Description: rgbled driver: master +-- +-- Dependencies: - +-- Test bench: - +-- Target Devices: generic +-- Tool versions: viv 2015.4; ghdl 0.31 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2016-02-20 734 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; + +entity rgbdrv_master is -- rgbled driver: master + generic ( + DWIDTH : positive := 8); -- dimmer width (must be >= 1) + port ( + CLK : in slbit; -- clock + RESET : in slbit := '0'; -- reset + CE_USEC : in slbit; -- 1 us clock enable + RGBCNTL : out slv3; -- rgb control + DIMCNTL : out slv(DWIDTH-1 downto 0) -- dim control + ); +end rgbdrv_master; + +architecture syn of rgbdrv_master is + + type regs_type is record + rgbena : slv3; -- rgb enables + dimcnt : slv(DWIDTH-1 downto 0); -- dim counter + end record regs_type; + + constant dimones : slv(DWIDTH-1 downto 0) := (others=>'1'); + + constant regs_init : regs_type := ( + "001", -- rgbena + dimones -- dimcnt + ); + + signal R_REGS : regs_type := regs_init; -- state registers + signal N_REGS : regs_type := regs_init; -- next value state regs + +begin + + proc_regs: process (CLK) + begin + + if rising_edge(CLK) then + if RESET = '1' then + R_REGS <= regs_init; + else + R_REGS <= N_REGS; + end if; + end if; + + end process proc_regs; + + + proc_next: process (R_REGS, CE_USEC) + variable r : regs_type := regs_init; + variable n : regs_type := regs_init; + begin + + r := R_REGS; + n := R_REGS; + + if CE_USEC = '1' then + n.dimcnt := slv(unsigned(r.dimcnt) + 1); + if r.dimcnt = dimones then + n.rgbena(2) := r.rgbena(1); + n.rgbena(1) := r.rgbena(0); + n.rgbena(0) := r.rgbena(2); + end if; + end if; + + N_REGS <= n; + + end process proc_next; + + RGBCNTL <= R_REGS.rgbena; + DIMCNTL <= R_REGS.dimcnt; + +end syn; diff --git a/rtl/bplib/bpgen/sn_humanio.vhd b/rtl/bplib/bpgen/sn_humanio.vhd index 4228dbd0..45c4ea16 100644 --- a/rtl/bplib/bpgen/sn_humanio.vhd +++ b/rtl/bplib/bpgen/sn_humanio.vhd @@ -1,4 +1,4 @@ --- $Id: sn_humanio.vhd 637 2015-01-25 18:36:40Z mueller $ +-- $Id: sn_humanio.vhd 731 2016-02-14 21:07:14Z mueller $ -- -- Copyright 2010-2015 by Walter F.J. Mueller -- @@ -93,7 +93,7 @@ begin generic map (DWIDTH => 8) port map (CLK => CLK, CE => '1', DO => N_SEG_N, PAD => O_SEG_N); - HIO : bp_swibtnled + HIO : bp_swibtnled generic map ( SWIDTH => SWIDTH, BWIDTH => BWIDTH, diff --git a/rtl/bplib/fx2lib/Makefile b/rtl/bplib/fx2lib/Makefile index 174b8dac..c7a6940e 100644 --- a/rtl/bplib/fx2lib/Makefile +++ b/rtl/bplib/fx2lib/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -13,7 +13,7 @@ NGC_all = $(VBOM_all:.vbom=.ngc) ifndef XTW_BOARD XTW_BOARD=nexys3 endif -include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk +include ${RETROBASE}/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # .PHONY : all clean # @@ -23,7 +23,7 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/bplib/fx2rlink/Makefile b/rtl/bplib/fx2rlink/Makefile index 214305b8..668af311 100644 --- a/rtl/bplib/fx2rlink/Makefile +++ b/rtl/bplib/fx2rlink/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -12,7 +12,7 @@ NGC_all = $(VBOM_all:.vbom=.ngc) ifndef XTW_BOARD XTW_BOARD=nexys3 endif -include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk +include ${RETROBASE}/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # .PHONY : all clean # @@ -22,7 +22,7 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/bplib/issi/Makefile b/rtl/bplib/issi/Makefile index 58da1088..b9fe24d9 100644 --- a/rtl/bplib/issi/Makefile +++ b/rtl/bplib/issi/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -12,7 +12,7 @@ clean : ghdl_clean # #----- # -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/bplib/nexys2/Makefile b/rtl/bplib/nexys2/Makefile index 4df28ce4..54e6478b 100644 --- a/rtl/bplib/nexys2/Makefile +++ b/rtl/bplib/nexys2/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -12,7 +12,7 @@ NGC_all = $(VBOM_all:.vbom=.ngc) ifndef XTW_BOARD XTW_BOARD=nexys2 endif -include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk +include ${RETROBASE}/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # .PHONY : all clean # @@ -22,7 +22,7 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/bplib/nexys2/tb/Makefile b/rtl/bplib/nexys2/tb/Makefile index 91976da8..531afc30 100644 --- a/rtl/bplib/nexys2/tb/Makefile +++ b/rtl/bplib/nexys2/tb/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -17,7 +17,7 @@ EXE_all += tb_nexys2_fusp_cuff_dummy ifndef XTW_BOARD XTW_BOARD=nexys2 endif -include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk +include ${RETROBASE}/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # .PHONY : all all_ssim all_tsim clean # @@ -29,9 +29,9 @@ clean : ise_clean ghdl_clean isim_clean # #----- # -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk -include $(RETROBASE)/rtl/make_ise/generic_isim.mk -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_isim.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/bplib/nexys2/tb/tb_nexys2_core.vbom b/rtl/bplib/nexys2/tb/tb_nexys2_core.vbom index 62976481..0ce5071b 100644 --- a/rtl/bplib/nexys2/tb/tb_nexys2_core.vbom +++ b/rtl/bplib/nexys2/tb/tb_nexys2_core.vbom @@ -1,10 +1,7 @@ # libs ../../../vlib/slvtypes.vhd -../../../vlib/serport/serportlib.vbom ../../../vlib/simlib/simbus.vhd # components -../../../vlib/serport/serport_uart_rx.vbom -../../../vlib/serport/serport_uart_tx.vbom ../../micron/mt45w8mw16b.vbom # design tb_nexys2_core.vhd diff --git a/rtl/bplib/nexys2/tb/tb_nexys2_core.vhd b/rtl/bplib/nexys2/tb/tb_nexys2_core.vhd index 57fc897a..7f29f4bf 100644 --- a/rtl/bplib/nexys2/tb/tb_nexys2_core.vhd +++ b/rtl/bplib/nexys2/tb/tb_nexys2_core.vhd @@ -1,4 +1,4 @@ --- $Id: tb_nexys2_core.vhd 649 2015-02-21 21:10:16Z mueller $ +-- $Id: tb_nexys2_core.vhd 724 2016-01-03 22:53:53Z mueller $ -- -- Copyright 2010-2011 by Walter F.J. Mueller -- @@ -36,7 +36,6 @@ use ieee.std_logic_textio.all; use std.textio.all; use work.slvtypes.all; -use work.serportlib.all; use work.simbus.all; entity tb_nexys2_core is diff --git a/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vbom b/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vbom index 072d7eea..ebc62f73 100644 --- a/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vbom +++ b/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vbom @@ -5,8 +5,6 @@ # libs ../../../vlib/slvtypes.vhd ../../../vlib/rlink/rlinklib.vbom -../../../vlib/rlink/tb/rlinktblib.vhd -../../../vlib/serport/serportlib.vbom ../../../vlib/xlib/xlib.vhd ../nexys2lib.vhd ../../../vlib/simlib/simlib.vhd @@ -15,11 +13,11 @@ ${sys_conf := sys_conf_sim.vhd} # components ../../../vlib/simlib/simclk.vbom ../../../vlib/simlib/simclkcnt.vbom -../../../vlib/rlink/tb/tbcore_rlink.vbom +../../../vlib/rlink/tbcore/tbcore_rlink.vbom ../../../vlib/xlib/dcm_sfs_gsim.vbom tb_nexys2_core.vbom -../../../vlib/serport/serport_master.vbom -${nexys2_fusp_aif := nexys2_fusp_dummy.vbom} +../../../vlib/serport/tb/serport_master_tb.vbom +@uut: ${nexys2_fusp_aif := nexys2_fusp_dummy.vbom} # design tb_nexys2_fusp.vhd @top:tb_nexys2_fusp diff --git a/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vhd b/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vhd index 596f1455..740d8989 100644 --- a/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vhd +++ b/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vhd @@ -1,6 +1,6 @@ --- $Id: tb_nexys2_fusp.vhd 666 2015-04-12 21:17:54Z mueller $ +-- $Id: tb_nexys2_fusp.vhd 730 2016-02-13 16:22:03Z mueller $ -- --- Copyright 2010-2015 by Walter F.J. Mueller +-- Copyright 2010-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,9 +18,9 @@ -- Dependencies: simlib/simclk -- simlib/simclkcnt -- xlib/dcm_sfs --- rlink/tb/tbcore_rlink +-- rlink/tbcore/tbcore_rlink -- tb_nexys2_core --- serport/serport_master +-- serport/tb/serport_master_tb -- nexys2_fusp_aif [UUT] -- -- To test: generic, any nexys2_fusp_aif target @@ -30,6 +30,8 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2016-02-13 730 3.3.2 direct instantiation of tbcore_rlink +-- 2016-01-03 724 3.3.1 use serport/tb/serport_master_tb -- 2015-04-12 666 3.3 use serport_master instead of serport_uart_rxtx -- 2011-12-23 444 3.2 new system clock scheme, new tbcore_rlink iface -- 2011-11-26 433 3.1.1 remove O_FLA_CE_N from tb_nexys2_core @@ -49,8 +51,6 @@ use std.textio.all; use work.slvtypes.all; use work.rlinklib.all; -use work.rlinktblib.all; -use work.serportlib.all; use work.xlib.all; use work.nexys2lib.all; use work.simlib.all; @@ -143,7 +143,7 @@ begin CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE); - TBCORE : tbcore_rlink + TBCORE : entity work.tbcore_rlink port map ( CLK => CLKCOM, CLK_STOP => CLK_STOP, @@ -199,7 +199,7 @@ begin O_FUSP_TXD => O_FUSP_TXD ); - SERMSTR : serport_master + SERMSTR : entity work.serport_master_tb generic map ( CDWIDTH => CLKDIV'length) port map ( diff --git a/rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vbom b/rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vbom index ec5397f6..14c839aa 100644 --- a/rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vbom +++ b/rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vbom @@ -5,8 +5,6 @@ # libs ../../../vlib/slvtypes.vhd ../../../vlib/rlink/rlinklib.vbom -../../../vlib/rlink/tb/rlinktblib.vhd -../../../vlib/serport/serportlib.vbom ../../../vlib/xlib/xlib.vhd ../nexys2lib.vhd ../../../vlib/simlib/simlib.vhd @@ -15,12 +13,12 @@ ${sys_conf := sys_conf_sim.vhd} # components ../../../vlib/simlib/simclk.vbom ../../../vlib/simlib/simclkcnt.vbom -../../../vlib/rlink/tb/tbcore_rlink.vbom +../../../vlib/rlink/tbcore/tbcore_rlink.vbom ../../../vlib/xlib/dcm_sfs_gsim.vbom tb_nexys2_core.vbom -../../../vlib/serport/serport_master.vbom +../../../vlib/serport/tb/serport_master_tb.vbom ../../../bplib/fx2lib/tb/fx2_2fifo_core.vbom -${nexys2_fusp_cuff_aif := nexys2_fusp_cuff_dummy.vbom} +@uut: ${nexys2_fusp_cuff_aif := nexys2_fusp_cuff_dummy.vbom} # design tb_nexys2_fusp_cuff.vhd @top:tb_nexys2_fusp_cuff diff --git a/rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vhd b/rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vhd index 24bbd31b..44a49d00 100644 --- a/rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vhd +++ b/rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vhd @@ -1,6 +1,6 @@ --- $Id: tb_nexys2_fusp_cuff.vhd 666 2015-04-12 21:17:54Z mueller $ +-- $Id: tb_nexys2_fusp_cuff.vhd 730 2016-02-13 16:22:03Z mueller $ -- --- Copyright 2013-2015 by Walter F.J. Mueller +-- Copyright 2013-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,9 +18,9 @@ -- Dependencies: simlib/simclk -- simlib/simclkcnt -- xlib/dcm_sfs --- rlink/tb/tbcore_rlink_dcm +-- rlink/tbcore/tbcore_rlink_dcm -- tb_nexys2_core --- serport/serport_master +-- serport/tb/serport_master_tb -- fx2lib/tb/fx2_2fifo_core -- nexys2_fusp_cuff_aif [UUT] -- @@ -31,6 +31,8 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2016-02-13 730 1.2.2 direct instantiation of tbcore_rlink +-- 2016-01-03 724 1.2.1 use serport/tb/serport_master_tb -- 2015-04-12 666 1.2 use serport_master instead of serport_uart_rxtx -- 2013-01-03 469 1.1 add fx2 model and data path -- 2013-01-01 467 1.0 Initial version (derived from tb_nexys2_fusp) @@ -44,8 +46,6 @@ use std.textio.all; use work.slvtypes.all; use work.rlinklib.all; -use work.rlinktblib.all; -use work.serportlib.all; use work.xlib.all; use work.nexys2lib.all; use work.simlib.all; @@ -161,7 +161,7 @@ begin CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE); - TBCORE : tbcore_rlink + TBCORE : entity work.tbcore_rlink port map ( CLK => CLKCOM, CLK_STOP => CLK_STOP, @@ -223,7 +223,7 @@ begin IO_FX2_DATA => IO_FX2_DATA ); - SERMSTR : serport_master + SERMSTR : entity work.serport_master_tb generic map ( CDWIDTH => CLKDIV'length) port map ( diff --git a/rtl/bplib/nexys3/tb/Makefile b/rtl/bplib/nexys3/tb/Makefile index 7d334b44..e612e66a 100644 --- a/rtl/bplib/nexys3/tb/Makefile +++ b/rtl/bplib/nexys3/tb/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -11,7 +11,7 @@ EXE_all += tb_nexys3_fusp_cuff_dummy ifndef XTW_BOARD XTW_BOARD=nexys3 endif -include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk +include ${RETROBASE}/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # .PHONY : all all_ssim all_tsim clean # @@ -23,9 +23,9 @@ clean : ise_clean ghdl_clean isim_clean # #----- # -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk -include $(RETROBASE)/rtl/make_ise/generic_isim.mk -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_isim.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/bplib/nexys3/tb/tb_nexys3_core.vbom b/rtl/bplib/nexys3/tb/tb_nexys3_core.vbom index 8349482e..d7ffefd3 100644 --- a/rtl/bplib/nexys3/tb/tb_nexys3_core.vbom +++ b/rtl/bplib/nexys3/tb/tb_nexys3_core.vbom @@ -1,10 +1,7 @@ # libs ../../../vlib/slvtypes.vhd -../../../vlib/serport/serportlib.vbom ../../../vlib/simlib/simbus.vhd # components -../../../vlib/serport/serport_uart_rx.vbom -../../../vlib/serport/serport_uart_tx.vbom ../../micron/mt45w8mw16b.vbom # design tb_nexys3_core.vhd diff --git a/rtl/bplib/nexys3/tb/tb_nexys3_core.vhd b/rtl/bplib/nexys3/tb/tb_nexys3_core.vhd index b8ee4f43..74cb2f87 100644 --- a/rtl/bplib/nexys3/tb/tb_nexys3_core.vhd +++ b/rtl/bplib/nexys3/tb/tb_nexys3_core.vhd @@ -1,4 +1,4 @@ --- $Id: tb_nexys3_core.vhd 649 2015-02-21 21:10:16Z mueller $ +-- $Id: tb_nexys3_core.vhd 724 2016-01-03 22:53:53Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -33,7 +33,6 @@ use ieee.std_logic_textio.all; use std.textio.all; use work.slvtypes.all; -use work.serportlib.all; use work.simbus.all; entity tb_nexys3_core is diff --git a/rtl/bplib/nexys3/tb/tb_nexys3_fusp.vbom b/rtl/bplib/nexys3/tb/tb_nexys3_fusp.vbom index a2e141c0..814c610d 100644 --- a/rtl/bplib/nexys3/tb/tb_nexys3_fusp.vbom +++ b/rtl/bplib/nexys3/tb/tb_nexys3_fusp.vbom @@ -5,8 +5,6 @@ # libs ../../../vlib/slvtypes.vhd ../../../vlib/rlink/rlinklib.vbom -../../../vlib/rlink/tb/rlinktblib.vhd -../../../vlib/serport/serportlib.vbom ../../../vlib/xlib/xlib.vhd ../nexys3lib.vhd ../../../vlib/simlib/simlib.vhd @@ -15,11 +13,11 @@ ${sys_conf := sys_conf_sim.vhd} # components ../../../vlib/simlib/simclk.vbom ../../../vlib/simlib/simclkcnt.vbom -../../../vlib/rlink/tb/tbcore_rlink.vbom +../../../vlib/rlink/tbcore/tbcore_rlink.vbom ../../../vlib/xlib/s6_cmt_sfs_gsim.vbom tb_nexys3_core.vbom -../../../vlib/serport/serport_master.vbom -${nexys3_fusp_aif := nexys3_fusp_dummy.vbom} +../../../vlib/serport/tb/serport_master_tb.vbom +@uut: ${nexys3_fusp_aif := nexys3_fusp_dummy.vbom} # design tb_nexys3_fusp.vhd @top:tb_nexys3_fusp diff --git a/rtl/bplib/nexys3/tb/tb_nexys3_fusp.vhd b/rtl/bplib/nexys3/tb/tb_nexys3_fusp.vhd index 6a3ef480..1b6f12fd 100644 --- a/rtl/bplib/nexys3/tb/tb_nexys3_fusp.vhd +++ b/rtl/bplib/nexys3/tb/tb_nexys3_fusp.vhd @@ -1,6 +1,6 @@ --- $Id: tb_nexys3_fusp.vhd 666 2015-04-12 21:17:54Z mueller $ +-- $Id: tb_nexys3_fusp.vhd 730 2016-02-13 16:22:03Z mueller $ -- --- Copyright 2011-2015 by Walter F.J. Mueller +-- Copyright 2011-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,9 +18,9 @@ -- Dependencies: simlib/simclk -- simlib/simclkcnt -- xlib/s6_cmt_sfs --- rlink/tb/tbcore_rlink +-- rlink/tbcore/tbcore_rlink -- tb_nexys3_core --- serport/serport_master +-- serport/tb/serport_master_tb -- nexys3_fusp_aif [UUT] -- -- To test: generic, any nexys3_fusp_aif target @@ -30,6 +30,8 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2016-02-13 730 1.3.2 direct instantiation of tbcore_rlink +-- 2016-01-03 724 1.3.1 use serport/tb/serport_master_tb -- 2015-04-12 666 1.3 use serport_master instead of serport_uart_rxtx -- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect -- 2011-12-23 444 1.1 new system clock scheme, new tbcore_rlink iface @@ -44,8 +46,6 @@ use std.textio.all; use work.slvtypes.all; use work.rlinklib.all; -use work.rlinktblib.all; -use work.serportlib.all; use work.xlib.all; use work.nexys3lib.all; use work.simlib.all; @@ -143,7 +143,7 @@ begin CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE); - TBCORE : tbcore_rlink + TBCORE : entity work.tbcore_rlink port map ( CLK => CLKCOM, CLK_STOP => CLK_STOP, @@ -200,7 +200,7 @@ begin O_FUSP_TXD => O_FUSP_TXD ); - SERMSTR : serport_master + SERMSTR : entity work.serport_master_tb generic map ( CDWIDTH => CLKDIV'length) port map ( diff --git a/rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vbom b/rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vbom index 2d7e2d45..fe8704a1 100644 --- a/rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vbom +++ b/rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vbom @@ -5,8 +5,6 @@ # libs ../../../vlib/slvtypes.vhd ../../../vlib/rlink/rlinklib.vbom -../../../vlib/rlink/tb/rlinktblib.vhd -../../../vlib/serport/serportlib.vbom ../../../vlib/xlib/xlib.vhd ../nexys3lib.vhd ../../../vlib/simlib/simlib.vhd @@ -15,12 +13,12 @@ ${sys_conf := sys_conf_sim.vhd} # components ../../../vlib/simlib/simclk.vbom ../../../vlib/simlib/simclkcnt.vbom -../../../vlib/rlink/tb/tbcore_rlink.vbom +../../../vlib/rlink/tbcore/tbcore_rlink.vbom ../../../vlib/xlib/s6_cmt_sfs_gsim.vbom tb_nexys3_core.vbom -../../../vlib/serport/serport_master.vbom +../../../vlib/serport/tb/serport_master_tb.vbom ../../../bplib/fx2lib/tb/fx2_2fifo_core.vbom -${nexys3_fusp_cuff_aif := nexys3_fusp_cuff_dummy.vbom} +@uut: ${nexys3_fusp_cuff_aif := nexys3_fusp_cuff_dummy.vbom} # design tb_nexys3_fusp_cuff.vhd @top:tb_nexys3_fusp_cuff diff --git a/rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vhd b/rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vhd index ffde64df..2faa4393 100644 --- a/rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vhd +++ b/rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vhd @@ -1,6 +1,6 @@ --- $Id: tb_nexys3_fusp_cuff.vhd 666 2015-04-12 21:17:54Z mueller $ +-- $Id: tb_nexys3_fusp_cuff.vhd 730 2016-02-13 16:22:03Z mueller $ -- --- Copyright 2013-2015 by Walter F.J. Mueller +-- Copyright 2013-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,9 +18,9 @@ -- Dependencies: simlib/simclk -- simlib/simclkcnt -- xlib/s6_cmt_sfs --- rlink/tb/tbcore_rlink +-- rlink/tbcore/tbcore_rlink -- tb_nexys3_core --- serport/serport_master +-- serport/tb/serport_master_tb -- fx2lib/tb/fx2_2fifo_core -- nexys3_fusp_cuff_aif [UUT] -- @@ -31,6 +31,8 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2016-02-13 730 1.2.2 direct instantiation of tbcore_rlink +-- 2016-01-03 724 1.2.1 use serport/tb/serport_master_tb -- 2015-04-12 666 1.2 use serport_master instead of serport_uart_rxtx -- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect -- 2013-04-21 509 1.0 Initial version (derived from tb_nexys3_fusp and @@ -45,8 +47,6 @@ use std.textio.all; use work.slvtypes.all; use work.rlinklib.all; -use work.rlinktblib.all; -use work.serportlib.all; use work.xlib.all; use work.nexys3lib.all; use work.simlib.all; @@ -166,7 +166,7 @@ begin CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE); - TBCORE : tbcore_rlink + TBCORE : entity work.tbcore_rlink port map ( CLK => CLKCOM, CLK_STOP => CLK_STOP, @@ -229,7 +229,7 @@ begin IO_FX2_DATA => IO_FX2_DATA ); - SERMSTR : serport_master + SERMSTR : entity work.serport_master_tb generic map ( CDWIDTH => CLKDIV'length) port map ( diff --git a/rtl/bplib/nexys4/nexys4_pins.xdc b/rtl/bplib/nexys4/nexys4_pins.xdc index 7f426076..c5288103 100644 --- a/rtl/bplib/nexys4/nexys4_pins.xdc +++ b/rtl/bplib/nexys4/nexys4_pins.xdc @@ -1,5 +1,5 @@ # -*- tcl -*- -# $Id: nexys4_pins.xdc 643 2015-02-07 17:41:53Z mueller $ +# $Id: nexys4_pins.xdc 726 2016-01-31 23:02:31Z mueller $ # # Pin locks for Nexys 4 core functionality # - USB UART @@ -94,6 +94,7 @@ set_property SLEW SLOW [get_ports {O_LED[*]}] set_property PACKAGE_PIN k5 [get_ports {O_RGBLED0[0]}] set_property PACKAGE_PIN f13 [get_ports {O_RGBLED0[1]}] set_property PACKAGE_PIN f6 [get_ports {O_RGBLED0[2]}] + set_property PACKAGE_PIN k6 [get_ports {O_RGBLED1[0]}] set_property PACKAGE_PIN h6 [get_ports {O_RGBLED1[1]}] set_property PACKAGE_PIN l16 [get_ports {O_RGBLED1[2]}] diff --git a/rtl/bplib/nexys4/tb/.cvsignore b/rtl/bplib/nexys4/tb/.cvsignore index b4a99093..6c69b8e0 100644 --- a/rtl/bplib/nexys4/tb/.cvsignore +++ b/rtl/bplib/nexys4/tb/.cvsignore @@ -2,4 +2,3 @@ tb_nexys4_dummy tb_nexys4_cram_dummy nexys4_dummy.ucf nexys4_cram_dummy.ucf -*.dep_ucf_cpp diff --git a/rtl/bplib/nexys4/tb/Makefile b/rtl/bplib/nexys4/tb/Makefile new file mode 100644 index 00000000..de3a39d7 --- /dev/null +++ b/rtl/bplib/nexys4/tb/Makefile @@ -0,0 +1,30 @@ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2016-01-03 724 1.0 Initial version +# +EXE_all = tb_nexys4_dummy tb_nexys4_cram_dummy +# +include ${RETROBASE}/rtl/make_viv/viv_default_nexys4.mk +# +.PHONY : all all_ssim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +# +clean : viv_clean ghdl_clean +# +#----- +# +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk +include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(wildcard *.o.dep_ghdl) +endif +# diff --git a/rtl/bplib/nexys4/tb/Makefile.ise b/rtl/bplib/nexys4/tb/Makefile.ise index 6b0cd113..f0371c4a 100644 --- a/rtl/bplib/nexys4/tb/Makefile.ise +++ b/rtl/bplib/nexys4/tb/Makefile.ise @@ -1,4 +1,5 @@ -# $Id: Makefile.ise 648 2015-02-20 20:16:21Z mueller $ +# -*- makefile-gmake -*- +# $Id: Makefile.ise 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -12,7 +13,7 @@ EXE_all = tb_nexys4_dummy tb_nexys4_cram_dummy ifndef XTW_BOARD XTW_BOARD=nexys4 endif -include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk +include ${RETROBASE}/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # .PHONY : all all_ssim all_tsim clean # @@ -24,9 +25,9 @@ clean : ise_clean ghdl_clean isim_clean # #----- # -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk -include $(RETROBASE)/rtl/make_ise/generic_isim.mk -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_isim.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/bplib/nexys4/tb/tb_nexys4.vbom b/rtl/bplib/nexys4/tb/tb_nexys4.vbom index 9a272f2a..039933b6 100644 --- a/rtl/bplib/nexys4/tb/tb_nexys4.vbom +++ b/rtl/bplib/nexys4/tb/tb_nexys4.vbom @@ -5,8 +5,6 @@ # libs ../../../vlib/slvtypes.vhd ../../../vlib/rlink/rlinklib.vbom -../../../vlib/rlink/tb/rlinktblib.vhd -../../../vlib/serport/serportlib.vbom ../../../vlib/xlib/xlib.vhd ../nexys4lib.vhd ../../../vlib/simlib/simlib.vhd @@ -15,11 +13,11 @@ ${sys_conf := sys_conf_sim.vhd} # components ../../../vlib/simlib/simclk.vbom ../../../vlib/simlib/simclkcnt.vbom -../../../vlib/rlink/tb/tbcore_rlink.vbom -../../../vlib/xlib/s7_cmt_sfs_gsim.vbom +../../../vlib/rlink/tbcore/tbcore_rlink.vbom +../../../vlib/xlib/tb/s7_cmt_sfs_tb.vbom tb_nexys4_core.vbom -../../../vlib/serport/serport_master.vbom -${nexys4_aif := nexys4_dummy.vbom} +../../../vlib/serport/tb/serport_master_tb.vbom +@uut: ${nexys4_aif := nexys4_dummy.vbom} # design tb_nexys4.vhd @top:tb_nexys4 diff --git a/rtl/bplib/nexys4/tb/tb_nexys4.vhd b/rtl/bplib/nexys4/tb/tb_nexys4.vhd index 3af73e7e..5b170b83 100644 --- a/rtl/bplib/nexys4/tb/tb_nexys4.vhd +++ b/rtl/bplib/nexys4/tb/tb_nexys4.vhd @@ -1,6 +1,6 @@ --- $Id: tb_nexys4.vhd 666 2015-04-12 21:17:54Z mueller $ +-- $Id: tb_nexys4.vhd 734 2016-02-20 22:43:20Z mueller $ -- --- Copyright 2013-2015 by Walter F.J. Mueller +-- Copyright 2013-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -17,10 +17,10 @@ -- -- Dependencies: simlib/simclk -- simlib/simclkcnt --- rlink/tb/tbcore_rlink --- xlib/s7_cmt_sfs +-- rlink/tbcore/tbcore_rlink +-- xlib/tb/s7_cmt_sfs_tb -- tb_nexys4_core --- serport/serport_master +-- serport/tb/serport_master_tb -- nexys4_aif [UUT] -- -- To test: generic, any nexys4_aif target @@ -30,6 +30,9 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2016-02-20 734 1.3.3 use s7_cmt_sfs_tb to avoid xsim conflict +-- 2016-02-13 730 1.3.2 direct instantiation of tbcore_rlink +-- 2016-01-03 724 1.3.1 use serport/tb/serport_master_tb -- 2015-04-12 666 1.3 use serport_master instead of serport_uart_rxtx -- 2015-02-06 643 1.2 factor out memory -- 2015-02-01 641 1.1 separate I_BTNRST_N @@ -45,8 +48,6 @@ use std.textio.all; use work.slvtypes.all; use work.rlinklib.all; -use work.rlinktblib.all; -use work.serportlib.all; use work.xlib.all; use work.nexys4lib.all; use work.simlib.all; @@ -105,7 +106,7 @@ begin CLK_STOP => CLK_STOP ); - CLKGEN_COM : s7_cmt_sfs + CLKGEN_COM : entity work.s7_cmt_sfs_tb generic map ( VCO_DIVIDE => sys_conf_clkser_vcodivide, VCO_MULTIPLY => sys_conf_clkser_vcomultiply, @@ -113,7 +114,7 @@ begin CLKIN_PERIOD => 10.0, CLKIN_JITTER => 0.01, STARTUP_WAIT => false, - GEN_TYPE => sys_conf_clksys_gentype) + GEN_TYPE => sys_conf_clkser_gentype) port map ( CLKIN => CLKOSC, CLKFX => CLKCOM, @@ -122,7 +123,7 @@ begin CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE); - TBCORE : tbcore_rlink + TBCORE : entity work.tbcore_rlink port map ( CLK => CLKCOM, CLK_STOP => CLK_STOP, @@ -157,7 +158,7 @@ begin O_SEG_N => O_SEG_N ); - SERMSTR : serport_master + SERMSTR : entity work.serport_master_tb generic map ( CDWIDTH => CLKDIV'length) port map ( diff --git a/rtl/bplib/nexys4/tb/tb_nexys4_core.vbom b/rtl/bplib/nexys4/tb/tb_nexys4_core.vbom index 1c980cc1..57557d84 100644 --- a/rtl/bplib/nexys4/tb/tb_nexys4_core.vbom +++ b/rtl/bplib/nexys4/tb/tb_nexys4_core.vbom @@ -1,9 +1,6 @@ # libs ../../../vlib/slvtypes.vhd -../../../vlib/serport/serportlib.vbom ../../../vlib/simlib/simbus.vhd # components -../../../vlib/serport/serport_uart_rx.vbom -../../../vlib/serport/serport_uart_tx.vbom # design tb_nexys4_core.vhd diff --git a/rtl/bplib/nexys4/tb/tb_nexys4_core.vhd b/rtl/bplib/nexys4/tb/tb_nexys4_core.vhd index 592275d0..a4eb7b58 100644 --- a/rtl/bplib/nexys4/tb/tb_nexys4_core.vhd +++ b/rtl/bplib/nexys4/tb/tb_nexys4_core.vhd @@ -1,4 +1,4 @@ --- $Id: tb_nexys4_core.vhd 643 2015-02-07 17:41:53Z mueller $ +-- $Id: tb_nexys4_core.vhd 724 2016-01-03 22:53:53Z mueller $ -- -- Copyright 2013-2015 by Walter F.J. Mueller -- @@ -35,7 +35,6 @@ use ieee.std_logic_textio.all; use std.textio.all; use work.slvtypes.all; -use work.serportlib.all; use work.simbus.all; entity tb_nexys4_core is diff --git a/rtl/bplib/nexys4/tb/tb_nexys4_cram.vbom b/rtl/bplib/nexys4/tb/tb_nexys4_cram.vbom index 6ae0a3bd..6daca7b2 100644 --- a/rtl/bplib/nexys4/tb/tb_nexys4_cram.vbom +++ b/rtl/bplib/nexys4/tb/tb_nexys4_cram.vbom @@ -5,8 +5,6 @@ # libs ../../../vlib/slvtypes.vhd ../../../vlib/rlink/rlinklib.vbom -../../../vlib/rlink/tb/rlinktblib.vhd -../../../vlib/serport/serportlib.vbom ../../../vlib/xlib/xlib.vhd ../nexys4lib.vhd ../../../vlib/simlib/simlib.vhd @@ -15,12 +13,12 @@ ${sys_conf := sys_conf_sim.vhd} # components ../../../vlib/simlib/simclk.vbom ../../../vlib/simlib/simclkcnt.vbom -../../../vlib/rlink/tb/tbcore_rlink.vbom -../../../vlib/xlib/s7_cmt_sfs_gsim.vbom +../../../vlib/rlink/tbcore/tbcore_rlink.vbom +../../../vlib/xlib/tb/s7_cmt_sfs_tb.vbom tb_nexys4_core.vbom ../../micron/mt45w8mw16b.vbom -../../../vlib/serport/serport_master.vbom -${nexys4_cram_aif := nexys4_cram_dummy.vbom} +../../../vlib/serport/tb/serport_master_tb.vbom +@uut: ${nexys4_cram_aif := nexys4_cram_dummy.vbom} # design tb_nexys4_cram.vhd @top:tb_nexys4_cram diff --git a/rtl/bplib/nexys4/tb/tb_nexys4_cram.vhd b/rtl/bplib/nexys4/tb/tb_nexys4_cram.vhd index 119c8884..7b8f7a8f 100644 --- a/rtl/bplib/nexys4/tb/tb_nexys4_cram.vhd +++ b/rtl/bplib/nexys4/tb/tb_nexys4_cram.vhd @@ -1,6 +1,6 @@ --- $Id: tb_nexys4_cram.vhd 666 2015-04-12 21:17:54Z mueller $ +-- $Id: tb_nexys4_cram.vhd 734 2016-02-20 22:43:20Z mueller $ -- --- Copyright 2013-2015 by Walter F.J. Mueller +-- Copyright 2013-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -17,10 +17,10 @@ -- -- Dependencies: simlib/simclk -- simlib/simclkcnt --- rlink/tb/tbcore_rlink --- xlib/s7_cmt_sfs +-- rlink/tbcore/tbcore_rlink +-- xlib/tb/s7_cmt_sfs_tb -- tb_nexys4_core --- serport/serport_master +-- serport/tb/serport_master_tb -- nexys4_cram_aif [UUT] -- vlib/parts/micron/mt45w8mw16b -- @@ -31,6 +31,9 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2016-02-20 734 1.2.3 use s7_cmt_sfs_tb to avoid xsim conflict +-- 2016-02-13 730 1.2.2 direct instantiation of tbcore_rlink +-- 2016-01-03 724 1.2.1 use serport/tb/serport_master_tb -- 2015-04-12 666 1.2 use serport_master instead of serport_uart_rxtx -- 2015-02-01 641 1.1 separate I_BTNRST_N -- 2013-09-28 535 1.0.1 use proper clock manager @@ -45,8 +48,6 @@ use std.textio.all; use work.slvtypes.all; use work.rlinklib.all; -use work.rlinktblib.all; -use work.serportlib.all; use work.xlib.all; use work.nexys4lib.all; use work.simlib.all; @@ -115,7 +116,7 @@ begin CLK_STOP => CLK_STOP ); - CLKGEN_COM : s7_cmt_sfs + CLKGEN_COM : entity work.s7_cmt_sfs_tb generic map ( VCO_DIVIDE => sys_conf_clkser_vcodivide, VCO_MULTIPLY => sys_conf_clkser_vcomultiply, @@ -123,7 +124,7 @@ begin CLKIN_PERIOD => 10.0, CLKIN_JITTER => 0.01, STARTUP_WAIT => false, - GEN_TYPE => sys_conf_clksys_gentype) + GEN_TYPE => sys_conf_clkser_gentype) port map ( CLKIN => CLKOSC, CLKFX => CLKCOM, @@ -132,7 +133,7 @@ begin CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE); - TBCORE : tbcore_rlink + TBCORE : entity work.tbcore_rlink port map ( CLK => CLKCOM, CLK_STOP => CLK_STOP, @@ -192,7 +193,7 @@ begin DATA => IO_MEM_DATA ); - SERMSTR : serport_master + SERMSTR : entity work.serport_master_tb generic map ( CDWIDTH => CLKDIV'length) port map ( diff --git a/rtl/bplib/nxcramlib/Makefile b/rtl/bplib/nxcramlib/Makefile index cc4063d0..46045e37 100644 --- a/rtl/bplib/nxcramlib/Makefile +++ b/rtl/bplib/nxcramlib/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -12,7 +12,7 @@ NGC_all = $(VBOM_all:.vbom=.ngc) ifndef XTW_BOARD XTW_BOARD=nexys3 endif -include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk +include ${RETROBASE}/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # .PHONY : all clean # @@ -22,7 +22,7 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/bplib/nxcramlib/tb/.cvsignore b/rtl/bplib/nxcramlib/tb/.cvsignore index c986ff40..46df519b 100644 --- a/rtl/bplib/nxcramlib/tb/.cvsignore +++ b/rtl/bplib/nxcramlib/tb/.cvsignore @@ -1,5 +1,2 @@ tb_nx_cram_memctl_as -tb_nx_cram_memctl_as_[sft]sim -tb_nx_cram_memctl_as_ISim -tb_nx_cram_memctl_as_ISim_[sft]sim tb_nx_cram_memctl_stim diff --git a/rtl/bplib/nxcramlib/tb/Makefile b/rtl/bplib/nxcramlib/tb/Makefile index 9930caf8..fabed81e 100644 --- a/rtl/bplib/nxcramlib/tb/Makefile +++ b/rtl/bplib/nxcramlib/tb/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -11,7 +11,7 @@ EXE_all = tb_nx_cram_memctl_as ifndef XTW_BOARD XTW_BOARD=nexys3 endif -include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk +include ${RETROBASE}/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # .PHONY : all all_ssim all_tsim clean # @@ -23,9 +23,9 @@ clean : ise_clean ghdl_clean isim_clean # #----- # -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk -include $(RETROBASE)/rtl/make_ise/generic_isim.mk -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_isim.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl.vbom b/rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl.vbom index 76ba9435..4054920f 100644 --- a/rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl.vbom +++ b/rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl.vbom @@ -9,7 +9,7 @@ ../../../vlib/simlib/simclk.vbom ../../../vlib/simlib/simclkcnt.vbom ../../micron/mt45w8mw16b.vbom -${uut := tbd_nx_cram_memctl_as.vbom} +@uut: ${uut := tbd_nx_cram_memctl_as.vbom} # design tb_nx_cram_memctl.vhd @top:tb_nx_cram_memctl diff --git a/rtl/bplib/s3board/Makefile b/rtl/bplib/s3board/Makefile index 7864f63d..a6bf5ac0 100644 --- a/rtl/bplib/s3board/Makefile +++ b/rtl/bplib/s3board/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -13,7 +13,7 @@ NGC_all = $(VBOM_all:.vbom=.ngc) ifndef XTW_BOARD XTW_BOARD=s3board endif -include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk +include ${RETROBASE}/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # .PHONY : all clean # @@ -23,7 +23,7 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/bplib/s3board/tb/.cvsignore b/rtl/bplib/s3board/tb/.cvsignore index e2f2023b..7deca6cc 100644 --- a/rtl/bplib/s3board/tb/.cvsignore +++ b/rtl/bplib/s3board/tb/.cvsignore @@ -1,13 +1,4 @@ tb_s3board_dummy -tb_s3board_dummy_[sft]sim -tb_s3board_dummy_ISim -tb_s3board_dummy_ISim_[sft]sim tb_s3board_fusp_dummy -rlink_cext_fifo_rx -rlink_cext_fifo_tx -rlink_cext_conf tb_s3_sram_memctl -tb_s3_sram_memctl_[sft]sim tb_s3_sram_memctl_stim -tb_s3_sram_memctl_ISim -tb_s3_sram_memctl_ISim_[sft]sim diff --git a/rtl/bplib/s3board/tb/Makefile b/rtl/bplib/s3board/tb/Makefile index fd086f48..3f3a5f45 100644 --- a/rtl/bplib/s3board/tb/Makefile +++ b/rtl/bplib/s3board/tb/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -17,7 +17,7 @@ EXE_all += tb_s3_sram_memctl ifndef XTW_BOARD XTW_BOARD=s3board endif -include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk +include ${RETROBASE}/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # .PHONY : all all_ssim all_tsim clean # @@ -29,9 +29,9 @@ clean : ise_clean ghdl_clean isim_clean # #----- # -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk -include $(RETROBASE)/rtl/make_ise/generic_isim.mk -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_isim.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/bplib/s3board/tb/tb_s3board_core.vbom b/rtl/bplib/s3board/tb/tb_s3board_core.vbom index 72ab0ac2..50b70675 100644 --- a/rtl/bplib/s3board/tb/tb_s3board_core.vbom +++ b/rtl/bplib/s3board/tb/tb_s3board_core.vbom @@ -1,10 +1,7 @@ # libs ../../../vlib/slvtypes.vhd -../../../vlib/serport/serportlib.vbom ../../../vlib/simlib/simbus.vhd # components -../../../vlib/serport/serport_uart_rx.vbom -../../../vlib/serport/serport_uart_tx.vbom ../../issi/is61lv25616al.vbom # design tb_s3board_core.vhd diff --git a/rtl/bplib/s3board/tb/tb_s3board_core.vhd b/rtl/bplib/s3board/tb/tb_s3board_core.vhd index dc46872d..60ddd4ca 100644 --- a/rtl/bplib/s3board/tb/tb_s3board_core.vhd +++ b/rtl/bplib/s3board/tb/tb_s3board_core.vhd @@ -1,6 +1,6 @@ --- $Id: tb_s3board_core.vhd 649 2015-02-21 21:10:16Z mueller $ +-- $Id: tb_s3board_core.vhd 724 2016-01-03 22:53:53Z mueller $ -- --- Copyright 2010-2011 by Walter F.J. Mueller +-- Copyright 2010-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -35,7 +35,6 @@ use ieee.std_logic_textio.all; use std.textio.all; use work.slvtypes.all; -use work.serportlib.all; use work.simbus.all; entity tb_s3board_core is diff --git a/rtl/bplib/s3board/tb/tb_s3board_fusp.vbom b/rtl/bplib/s3board/tb/tb_s3board_fusp.vbom index c2b2230d..cc6f377c 100644 --- a/rtl/bplib/s3board/tb/tb_s3board_fusp.vbom +++ b/rtl/bplib/s3board/tb/tb_s3board_fusp.vbom @@ -5,18 +5,16 @@ # libs ../../../vlib/slvtypes.vhd ../../../vlib/rlink/rlinklib.vbom -../../../vlib/rlink/tb/rlinktblib.vhd -../../../vlib/serport/serportlib.vbom ../s3boardlib.vbom ../../../vlib/simlib/simlib.vhd ../../../vlib/simlib/simbus.vhd # components ../../../vlib/simlib/simclk.vbom ../../../vlib/simlib/simclkcnt.vbom -../../../vlib/rlink/tb/tbcore_rlink.vbom +../../../vlib/rlink/tbcore/tbcore_rlink.vbom tb_s3board_core.vbom -../../../vlib/serport/serport_master.vbom -${s3board_fusp_aif := s3board_fusp_dummy.vbom} +../../../vlib/serport/tb/serport_master_tb.vbom +@uut: ${s3board_fusp_aif := s3board_fusp_dummy.vbom} # design tb_s3board_fusp.vhd @top:tb_s3board_fusp diff --git a/rtl/bplib/s3board/tb/tb_s3board_fusp.vhd b/rtl/bplib/s3board/tb/tb_s3board_fusp.vhd index 8740d9dd..70a78a0d 100644 --- a/rtl/bplib/s3board/tb/tb_s3board_fusp.vhd +++ b/rtl/bplib/s3board/tb/tb_s3board_fusp.vhd @@ -1,6 +1,6 @@ --- $Id: tb_s3board_fusp.vhd 666 2015-04-12 21:17:54Z mueller $ +-- $Id: tb_s3board_fusp.vhd 730 2016-02-13 16:22:03Z mueller $ -- --- Copyright 2010-2015 by Walter F.J. Mueller +-- Copyright 2010-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -17,10 +17,10 @@ -- -- Dependencies: simlib/simclk -- simlib/simclkcnt --- rlink/tb/tbcore_rlink +-- rlink/tbcore/tbcore_rlink -- tb_s3board_core -- s3board_fusp_aif [UUT] --- serport/serport_master +-- serport/tb/serport_master_tb -- -- To test: generic, any s3board_fusp_aif target -- @@ -28,6 +28,8 @@ -- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment +-- 2016-02-13 730 1.3.2 direct instantiation of tbcore_rlink +-- 2016-01-03 724 1.3.1 use serport/tb/serport_master_tb -- 2015-04-12 666 1.3 use serport_master instead of serport_uart_rxtx -- 2011-12-23 444 3.1 new system clock scheme, new tbcore_rlink iface -- 2011-11-19 427 3.0.1 now numeric_std clean @@ -47,8 +49,6 @@ use std.textio.all; use work.slvtypes.all; use work.rlinklib.all; -use work.rlinktblib.all; -use work.serportlib.all; use work.s3boardlib.all; use work.simlib.all; use work.simbus.all; @@ -122,7 +122,7 @@ begin CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE); - TBCORE : tbcore_rlink + TBCORE : entity work.tbcore_rlink port map ( CLK => CLK, CLK_STOP => CLK_STOP, @@ -169,7 +169,7 @@ begin O_FUSP_TXD => O_FUSP_TXD ); - SERMSTR : serport_master + SERMSTR : entity work.serport_master_tb generic map ( CDWIDTH => CLKDIV'length) port map ( diff --git a/rtl/bplib/sysmon/sysmon_rbus_core.vbom b/rtl/bplib/sysmon/sysmon_rbus_core.vbom new file mode 100644 index 00000000..12e72177 --- /dev/null +++ b/rtl/bplib/sysmon/sysmon_rbus_core.vbom @@ -0,0 +1,6 @@ +# libs +../../vlib/slvtypes.vhd +../../vlib/rbus/rblib.vhd +# components +# design +sysmon_rbus_core.vhd diff --git a/rtl/bplib/sysmon/sysmon_rbus_core.vhd b/rtl/bplib/sysmon/sysmon_rbus_core.vhd new file mode 100644 index 00000000..aaab1c26 --- /dev/null +++ b/rtl/bplib/sysmon/sysmon_rbus_core.vhd @@ -0,0 +1,372 @@ +-- $Id: sysmon_rbus_core.vhd 741 2016-03-12 23:49:03Z mueller $ +-- +-- Copyright 2016- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sysmon_rbus_core - syn +-- Description: SYSMON interface to rbus (generic) +-- +-- Dependencies: - +-- +-- Test bench: - +-- +-- Target Devices: generic (all with SYSMON or XADC) +-- Tool versions: viv 2015.4; ghdl 0.33 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2016-03-12 741 1.0 Initial version +-- 2016-03-06 738 0.1 First draft +------------------------------------------------------------------------------ +-- +-- rbus registers: +-- - in general 1-to-1 mapping to sysmon/xadc address space +-- --> see function in sysmon/xadc user guide +-- - 8 addresses are implemented on the controller (base is ibase, default x"78") +-- --> see function below +-- +-- Addr Bits Name r/w/f Function +-- 000 cntl -/-/f cntl +-- 15 reset -/-/f reset SYSMON +-- 001 stat r/w/- stat +-- 3 jlock r/c/- JTAGLOCKED seen +-- 2 jmod r/c/- JTAGMODIFIED seen +-- 1 jbusy r/c/- JTAGBUSY seen +-- 0 ot r/c/- OT seen +-- 010 almh r/w/- alm history +-- *:00 alm r/c/- ALM(*:0) seen +-- 011 -/-/- +-- 100 temp r/-/- current temp value +-- 101 alm r/-/- current alm value +-- *:00 alm r/-/- alm(*:0) +-- 110 -/-/- +-- 111 eos r/-/- eos counter +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.rblib.all; +use work.sysmonrbuslib.all; + +-- ---------------------------------------------------------------------------- + +entity sysmon_rbus_core is -- SYSMON interface to rbus + generic ( + DAWIDTH : positive := 7; -- drp address bus width + ALWIDTH : positive := 8; -- alm width + TEWIDTH : positive := 12; -- temp width + IBASE : slv8 := x"78"; -- base of controller register window + RB_ADDR : slv16 := slv(to_unsigned(16#0000#,16))); + port ( + CLK : in slbit; -- clock + RESET : in slbit := '0'; -- reset + RB_MREQ : in rb_mreq_type; -- rbus: request + RB_SRES : out rb_sres_type; -- rbus: response + SM_DEN : out slbit; -- sysmon: drp enable + SM_DWE : out slbit; -- sysmon: drp write enable + SM_DADDR : out slv(DAWIDTH-1 downto 0); -- sysmon: drp address + SM_DI : out slv16; -- sysmon: data input + SM_DO : in slv16; -- sysmon: data output + SM_DRDY : in slbit; -- sysmon: data ready + SM_EOS : in slbit; -- sysmon: end of scan + SM_RESET : out slbit; -- sysmon: reset + SM_ALM : in slv(ALWIDTH-1 downto 0);-- sysmon: alarms + SM_OT : in slbit; -- sysmon: overtemperature + SM_JTAGBUSY : in slbit; -- sysmon: JTAGBUSY + SM_JTAGLOCKED : in slbit; -- sysmon: JTAGLOCKED + SM_JTAGMODIFIED : in slbit; -- sysmon: JTAGMODIFIED + TEMP : out slv(TEWIDTH-1 downto 0) -- die temp + ); +end sysmon_rbus_core; + +architecture syn of sysmon_rbus_core is + + type state_type is ( + s_init, -- init: wait for jtaglocked down + s_idle, -- idle: dispatch + s_wait, -- wait: wait on drdy + s_twait -- twait: wait on drdy of temp read + ); + + type regs_type is record + rbsel : slbit; -- rbus select + state : state_type; -- state + eoscnt : slv16; -- eos counter + stat_ot : slbit; -- stat: ot + stat_jlock : slbit; -- stat: jtag locked + stat_jmod : slbit; -- stat: jtag modified + stat_jbusy : slbit; -- stat: jtag busy + almh : slv(ALWIDTH-1 downto 0); -- almh + temp : slv(TEWIDTH-1 downto 0); -- temp value + tpend : slbit; -- temp pending + end record regs_type; + + constant regs_init : regs_type := ( + '0', -- rbsel + s_idle, -- state + (others=>'0'), -- eoscnt + '0','0','0','0', -- stat_ot, stat_j* + slv(to_unsigned(0,ALWIDTH)), -- almh + slv(to_unsigned(0,TEWIDTH)), -- temp + '0' -- tpend + ); + + signal R_REGS : regs_type := regs_init; -- state registers + signal N_REGS : regs_type := regs_init; -- next value state regs + + -- only internal regs have names, only 3 LSB in constant + constant rbaddr_cntl: slv3 := "000"; -- 0 -/-/f + constant rbaddr_stat: slv3 := "001"; -- 1 r/w/- + constant rbaddr_almh: slv3 := "010"; -- 2 r/w/- + constant rbaddr_temp: slv3 := "100"; -- 4 r/-/- + constant rbaddr_alm: slv3 := "101"; -- 5 r/-/- + constant rbaddr_eos: slv3 := "111"; -- 7 r/-/- + + constant cntl_rbf_reset: integer := 15; + + constant stat_rbf_jlock: integer := 3; + constant stat_rbf_jmod: integer := 2; + constant stat_rbf_jbusy: integer := 1; + constant stat_rbf_ot: integer := 0; + +begin + + assert DAWIDTH=7 or DAWIDTH=8 + report "assert(DAWIDTH=7 or DAWIDTH=8): unsupported DAWIDTH" + severity failure; + assert ALWIDTH<=16 + report "assert ALWIDTH<16: unsupported ALWIDTH" + severity failure; + assert TEWIDTH=10 or TEWIDTH=12 + report "assert(TEWIDTH=10 or TEWIDTH=12): unsupported TEWIDTH" + severity failure; + assert IBASE(2 downto 0) = "000" + report "assert IBASE(2:0) = 000: invalid IBASE" + severity failure; + + proc_regs: process (CLK) + begin + + if rising_edge(CLK) then + if RESET = '1' then + R_REGS <= regs_init; + else + R_REGS <= N_REGS; + end if; + end if; + + end process proc_regs; + + proc_next: process (R_REGS, RB_MREQ, SM_DO, SM_DRDY, SM_EOS, SM_ALM, SM_OT, + SM_JTAGLOCKED, SM_JTAGMODIFIED, SM_JTAGBUSY) + + variable r : regs_type := regs_init; + variable n : regs_type := regs_init; + + variable irb_ack : slbit := '0'; + variable irb_busy : slbit := '0'; + variable irb_err : slbit := '0'; + variable irb_dout : slv16 := (others=>'0'); + variable irbena : slbit := '0'; + + variable irb_addr_ext : slbit := '0'; + variable irb_addr_int : slbit := '0'; + + variable ism_den : slbit := '0'; + variable ism_dwe : slbit := '0'; + variable ism_daddr : slv(DAWIDTH-1 downto 0) := (others=>'0'); + variable ism_reset : slbit := '0'; + + begin + + r := R_REGS; + n := R_REGS; + + irb_ack := '0'; + irb_busy := '0'; + irb_err := '0'; + irb_dout := (others=>'0'); + + irbena := RB_MREQ.re or RB_MREQ.we; + + -- check for internal rbus controler register window + irb_addr_int := '0'; + if RB_MREQ.addr(DAWIDTH-1 downto 3) = IBASE(DAWIDTH-1 downto 3) then + irb_addr_int := '1'; + end if; + + ism_den := '0'; + ism_dwe := '0'; + ism_daddr := RB_MREQ.addr(DAWIDTH-1 downto 0); -- default + ism_reset := '0'; + + -- handle EOS + if SM_EOS = '1' then + n.tpend := '1'; -- queue temp read + n.eoscnt := slv(unsigned(r.eoscnt) + 1); -- and count it + end if; + + -- update stat and almh register fields + n.stat_ot := r.stat_ot or SM_OT; + n.stat_jlock := r.stat_jlock or SM_JTAGLOCKED; + n.stat_jmod := r.stat_jmod or SM_JTAGMODIFIED; + n.stat_jbusy := r.stat_jbusy or SM_JTAGBUSY; + n.almh := r.almh or SM_ALM; + + -- rbus address decoder + n.rbsel := '0'; + if RB_MREQ.aval='1' and RB_MREQ.addr(15 downto 7)=RB_ADDR(15 downto 7) then + n.rbsel := '1'; + end if; + + irb_ack := r.rbsel and irbena; -- ack all accesses + irb_busy := irb_ack; -- busy is default + + -- internal state machine + case r.state is + when s_init => -- init: wait for jtaglocked down ---- + if SM_JTAGLOCKED = '0' then + n.stat_jlock := '0'; -- clear status + n.state := s_idle; -- start working + end if; + + when s_idle => -- idle: dispatch -------------------- + if r.tpend = '1' then -- temp update pending ? + n.tpend := '0'; -- mark done + if SM_JTAGLOCKED = '0' then -- if not jlocked + ism_daddr := "0000000"; -- temp is reg 00h + ism_dwe := '0'; -- do read + ism_den := '1'; -- start drp cycle + n.state := s_twait; + end if; + + elsif r.rbsel = '1' then -- rbus access ? + if irb_addr_int ='1' then -- internal controller regs + irb_busy := '0'; + case RB_MREQ.addr(2 downto 0) is + when rbaddr_cntl => + if RB_MREQ.we = '1' then + ism_reset := RB_MREQ.din(cntl_rbf_reset); + end if; + + when rbaddr_stat => + if RB_MREQ.we = '1' then + n.stat_jlock := r.stat_jlock and + not RB_MREQ.din(stat_rbf_jlock); + n.stat_jmod := r.stat_jmod and + not RB_MREQ.din(stat_rbf_jmod); + n.stat_jbusy := r.stat_jbusy and + not RB_MREQ.din(stat_rbf_jbusy); + n.stat_ot := r.stat_ot and + not RB_MREQ.din(stat_rbf_ot); + end if; + + when rbaddr_almh => + if RB_MREQ.we = '1' then + n.almh := r.almh and not RB_MREQ.din(r.almh'range); + end if; + + when rbaddr_temp => + irb_err := RB_MREQ.we; + when rbaddr_alm => + irb_err := RB_MREQ.we; + when rbaddr_eos => + irb_err := RB_MREQ.we; + + when others => + irb_err := irbena; + end case; + + else -- sysmon reg access + if irbena = '1' then + if SM_JTAGLOCKED = '0' then -- if not jlocked + ism_daddr := RB_MREQ.addr(ism_daddr'range); + ism_dwe := RB_MREQ.we; + ism_den := '1'; -- start drp cycle + n.state := s_wait; + else + irb_err := '1'; -- quit with error if jlocked + end if; + end if; + + end if; + end if; + + when s_wait => -- wait: wait on drdy ---------------- + n.state := s_wait; + if SM_DRDY = '1' then + irb_busy := '0'; + n.state := s_idle; + end if; + + when s_twait => -- twait: wait on drdy of temp read -- + n.state := s_twait; + if SM_DRDY = '1' then + n.temp := SM_DO(15 downto 16-TEWIDTH); -- take msb's + n.state := s_idle; + end if; + + when others => null; -- <> ------------------------------ + end case; -- case r.state + + -- rbus output driver + if r.rbsel = '1' then + if irb_addr_int = '1' then + case RB_MREQ.addr(2 downto 0) is + when rbaddr_stat => + irb_dout(stat_rbf_jlock) := r.stat_jlock; + irb_dout(stat_rbf_jmod) := r.stat_jmod; + irb_dout(stat_rbf_jbusy) := r.stat_jbusy; + irb_dout(stat_rbf_ot) := r.stat_ot; + + when rbaddr_almh => + irb_dout(r.almh'range) := r.almh; + + when rbaddr_temp => + irb_dout(r.temp'range) := r.temp; + + when rbaddr_alm => + irb_dout(SM_ALM'range) := SM_ALM; + + when rbaddr_eos => + irb_dout := r.eoscnt; + + when others => + irb_dout := (others=>'0'); + end case; + else + irb_dout := SM_DO; + end if; + end if; + + N_REGS <= n; + + SM_DEN <= ism_den; + SM_DWE <= ism_dwe; + SM_DADDR <= ism_daddr; + SM_DI <= RB_MREQ.din; + SM_RESET <= ism_reset; + + TEMP <= r.temp; + + RB_SRES <= rb_sres_init; + RB_SRES.ack <= irb_ack; + RB_SRES.busy <= irb_busy; + RB_SRES.err <= irb_err; + RB_SRES.dout <= irb_dout; + + end process proc_next; + +end syn; diff --git a/rtl/bplib/sysmon/sysmonrbuslib.vbom b/rtl/bplib/sysmon/sysmonrbuslib.vbom new file mode 100644 index 00000000..8c00cda9 --- /dev/null +++ b/rtl/bplib/sysmon/sysmonrbuslib.vbom @@ -0,0 +1,3 @@ +# libs +../../vlib/slvtypes.vhd +sysmonrbuslib.vhd diff --git a/rtl/bplib/sysmon/sysmonrbuslib.vhd b/rtl/bplib/sysmon/sysmonrbuslib.vhd new file mode 100644 index 00000000..0f1b6ba3 --- /dev/null +++ b/rtl/bplib/sysmon/sysmonrbuslib.vhd @@ -0,0 +1,213 @@ +-- $Id: sysmonrbuslib.vhd 742 2016-03-13 14:40:19Z mueller $ +-- +-- Copyright 2016- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sysmonrbuslib +-- Description: generic (all with SYSMON or XADC) +-- +-- Dependencies: - +-- Tool versions: viv2015.4; ghdl 0.33 +-- Revision History: +-- Date Rev Version Comment +-- 2016-03-13 742 1.0 Initial version +-- 2016-03-06 738 0.1 First draft +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.rblib.all; + +package sysmonrbuslib is + +subtype bv is bit_vector; -- vector +subtype bv16 is bit_vector(15 downto 0); -- 16 bit word + +-- config reg #0 fields as bit masks (to be or'ed) +constant xadc_conf0_cavg: bv16 := x"8000"; -- 15 dis calib avr +constant xadc_conf0_avg_off: bv16 := x"0000"; -- 13:12 avr mode: off +constant xadc_conf0_avg_16: bv16 := x"1000"; -- " avr mode: 16 samples +constant xadc_conf0_avg_64: bv16 := x"2000"; -- " avr mode: 64 samples +constant xadc_conf0_avg_256: bv16 := x"3000"; -- " avr mode: 256 samples +constant xadc_conf0_mux: bv16 := x"0800"; -- 11 ena ext mux +constant xadc_conf0_bu: bv16 := x"0400"; -- 10 ena bipolar +constant xadc_conf0_ec: bv16 := x"0200"; -- 9 ena event mode +constant xadc_conf0_acq: bv16 := x"0100"; -- 8 ena inc settle +-- bit 4:0 holds channel select, not used, only for single channel mode + +-- config reg #1 fields as bit masks (to be or'ed) +constant xadc_conf1_seq_default: bv16 := x"0000"; -- 15:12 seq mode: default +constant xadc_conf1_seq_spass: bv16 := x"1000"; -- " seq mode: single pass +constant xadc_conf1_seq_cont: bv16 := x"2000"; -- " seq mode: continuous +constant xadc_conf1_seq_schan: bv16 := x"3000"; -- " seq mode: single chan +constant xadc_conf1_dis_alm6: bv16 := x"0800"; -- 11 dis alm(6) +constant xadc_conf1_dis_alm5: bv16 := x"0400"; -- 10 dis alm(5) +constant xadc_conf1_dis_alm4: bv16 := x"0200"; -- 9 dis alm(4) +constant xadc_conf1_dis_alm3: bv16 := x"0100"; -- 8 dis alm(3) + +constant xadc_conf1_cal3_supog: bv16 := x"0080"; -- 7 ena sup off+gain +constant xadc_conf1_cal2_supo: bv16 := x"0040"; -- 6 ena sup off +constant xadc_conf1_cal1_adcog: bv16 := x"0020"; -- 5 ena adc off+gain +constant xadc_conf1_cal0_adco: bv16 := x"0010"; -- 4 ena adc off + +constant xadc_conf1_dis_alm2: bv16 := x"0008"; -- 3 dis alm(2) +constant xadc_conf1_dis_alm1: bv16 := x"0004"; -- 2 dis alm(1) +constant xadc_conf1_dis_alm0: bv16 := x"0002"; -- 1 dis alm(0) +constant xadc_conf1_dis_ot: bv16 := x"0001"; -- 0 dis ot + +-- bit numbers for sequence registers (even word for build-in channels) +constant xadc_select_vccbram: integer := 14; +constant xadc_select_vrefn: integer := 13; +constant xadc_select_vrefp: integer := 12; +constant xadc_select_vpvn: integer := 11; +constant xadc_select_vccaux: integer := 10; +constant xadc_select_vccint: integer := 9; +constant xadc_select_temp: integer := 8; +constant xadc_select_vccoddr: integer := 7; +constant xadc_select_vccpaux: integer := 6; +constant xadc_select_vccpint: integer := 5; +constant xadc_select_calib: integer := 0; + +-- defaults for plain build-in power monitoring +constant xadc_init_40_default: bv16 := xadc_conf0_cavg or + xadc_conf0_avg_16; + +constant xadc_init_41_default: bv16 := xadc_conf1_seq_cont or + xadc_conf1_dis_alm6 or + xadc_conf1_dis_alm5 or + xadc_conf1_dis_alm4 or + xadc_conf1_cal3_supog or + xadc_conf1_cal2_supo or + xadc_conf1_cal1_adcog or + xadc_conf1_cal0_adco; + +constant xadc_init_48_default: bv16 := (xadc_select_vccbram => '1', + xadc_select_vccaux => '1', + xadc_select_vccint => '1', + xadc_select_temp => '1', + xadc_select_calib => '1', + others => '0'); + +-- OT limit and reset are in general hardwired to 125 and 70 deg +-- the 4 lsbs of reg 53 contain the 'automatic shutdown enable' +-- must be set to "0011' to enable. done by default, seems prudent +constant xadc_init_53_default: bv16 := x"ca33"; -- OT LIMIT (125) + OT ENABLE +constant xadc_init_57_default: bv16 := x"ae40"; -- OT RESET (70) + +constant xadc_init_4a_default: bv16 := (others => '0'); + +pure function xadc_temp2alim(temp : real) return bv16; +pure function xadc_svolt2alim (volt : real) return bv16; + +component sysmon_rbus_core is -- SYSMON interface to rbus + generic ( + DAWIDTH : positive := 7; -- drp address bus width + ALWIDTH : positive := 8; -- alm width + TEWIDTH : positive := 12; -- temp width + IBASE : slv8 := x"78"; -- base of controller register window + RB_ADDR : slv16 := slv(to_unsigned(16#0000#,16))); + port ( + CLK : in slbit; -- clock + RESET : in slbit := '0'; -- reset + RB_MREQ : in rb_mreq_type; -- rbus: request + RB_SRES : out rb_sres_type; -- rbus: response + SM_DEN : out slbit; -- sysmon: drp enable + SM_DWE : out slbit; -- sysmon: drp write enable + SM_DADDR : out slv(DAWIDTH-1 downto 0); -- sysmon: drp address + SM_DI : out slv16; -- sysmon: data input + SM_DO : in slv16; -- sysmon: data output + SM_DRDY : in slbit; -- sysmon: data ready + SM_EOS : in slbit; -- sysmon: end of scan + SM_RESET : out slbit; -- sysmon: reset + SM_ALM : in slv(ALWIDTH-1 downto 0);-- sysmon: alarms + SM_OT : in slbit; -- sysmon: overtemperature + SM_JTAGBUSY : in slbit; -- sysmon: JTAGBUSY + SM_JTAGLOCKED : in slbit; -- sysmon: JTAGLOCKED + SM_JTAGMODIFIED : in slbit; -- sysmon: JTAGMODIFIED + TEMP : out slv(TEWIDTH-1 downto 0) -- die temp + ); +end component; + +component sysmonx_rbus_base is -- XADC interface to rbus (basic monitor) + generic ( + INIT_TEMP_UP : real := 85.0; -- INIT_50 (default for C grade) + INIT_TEMP_LOW : real := 60.0; -- INIT_54 + INIT_VCCINT_UP : real := 1.05; -- INIT_51 (default for non-L types) + INIT_VCCINT_LOW : real := 0.95; -- INIT_55 (default for non-L types) + INIT_VCCAUX_UP : real := 1.89; -- INIT_52 + INIT_VCCAUX_LOW : real := 1.71; -- INIT_56 + INIT_VCCBRAM_UP : real := 1.05; -- INIT_58 (default for non-L types) + INIT_VCCBRAM_LOW : real := 0.95; -- INIT_5C (default for non-L types) + CLK_MHZ : integer := 250; -- clock frequency in MHz + RB_ADDR : slv16 := slv(to_unsigned(16#0000#,16))); + port ( + CLK : in slbit; -- clock + RESET : in slbit := '0'; -- reset + RB_MREQ : in rb_mreq_type; -- rbus: request + RB_SRES : out rb_sres_type; -- rbus: response + ALM : out slv8; -- xadc: alarms + OT : out slbit; -- xadc: over temp + TEMP : out slv12 -- xadc: die temp + ); +end component; + +component sysmonx_rbus_arty is -- XADC interface to rbus (arty pwrmon) + generic ( + INIT_TEMP_UP : real := 85.0; -- INIT_50 (default for C grade) + INIT_TEMP_LOW : real := 60.0; -- INIT_54 + INIT_VCCINT_UP : real := 0.98; -- INIT_51 (default for -1L types) + INIT_VCCINT_LOW : real := 0.92; -- INIT_55 (default for -1L types) + INIT_VCCAUX_UP : real := 1.89; -- INIT_52 + INIT_VCCAUX_LOW : real := 1.71; -- INIT_56 + INIT_VCCBRAM_UP : real := 0.98; -- INIT_58 (default for -1L types) + INIT_VCCBRAM_LOW : real := 0.92; -- INIT_5C (default for -1L types) + CLK_MHZ : integer := 250; -- clock frequency in MHz + RB_ADDR : slv16 := slv(to_unsigned(16#0000#,16))); + port ( + CLK : in slbit; -- clock + RESET : in slbit := '0'; -- reset + RB_MREQ : in rb_mreq_type; -- rbus: request + RB_SRES : out rb_sres_type; -- rbus: response + ALM : out slv8; -- xadc: alarms + OT : out slbit; -- xadc: over temp + TEMP : out slv12; -- xadc: die temp + VPWRN : in slv4 := (others=>'0'); -- xadc: vpwr neg (4 chan pwrmon) + VPWRP : in slv4 := (others=>'0') -- xadc: vpwr pos (4 chan pwrmon) + ); +end component; + +end package sysmonrbuslib; + +-- ---------------------------------------------------------------------------- +package body sysmonrbuslib is + +-- ------------------------------------- +pure function xadc_temp2alim(temp : real) return bv16 is + variable ival : integer := 0; +begin + ival := integer(((temp + 273.14) * 16.0 * 4096.0) / 503.975); + return to_bitvector(slv(to_unsigned(ival,16))); +end function xadc_temp2alim; + +-- ------------------------------------- +pure function xadc_svolt2alim (volt : real) return bv16 is + variable ival : integer := 0; +begin + ival := integer((volt * 16.0 * 4096.0) / 3.0); + return to_bitvector(slv(to_unsigned(ival,16))); +end function xadc_svolt2alim; + + +end package body sysmonrbuslib; diff --git a/rtl/bplib/sysmon/sysmonx_rbus_arty.vbom b/rtl/bplib/sysmon/sysmonx_rbus_arty.vbom new file mode 100644 index 00000000..5be7218c --- /dev/null +++ b/rtl/bplib/sysmon/sysmonx_rbus_arty.vbom @@ -0,0 +1,9 @@ +# libs +../../vlib/slvtypes.vhd +../../vlib/rbus/rblib.vhd +sysmonrbuslib.vbom +@lib:unisim +# components +sysmon_rbus_core.vbom +# design +sysmonx_rbus_arty.vhd diff --git a/rtl/bplib/sysmon/sysmonx_rbus_arty.vhd b/rtl/bplib/sysmon/sysmonx_rbus_arty.vhd new file mode 100644 index 00000000..f6a0f708 --- /dev/null +++ b/rtl/bplib/sysmon/sysmonx_rbus_arty.vhd @@ -0,0 +1,226 @@ +-- $Id: sysmonx_rbus_arty.vhd 742 2016-03-13 14:40:19Z mueller $ +-- +-- Copyright 2016- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sysmonx_rbus_arty - syn +-- Description: 7series XADC interface to rbus (arty pwrmon version) +-- +-- Dependencies: sysmon_rbus_core +-- +-- Test bench: - +-- +-- Target Devices: 7series +-- Tool versions: viv 2015.4; ghdl 0.33 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2016-03-12 741 1.0 Initial version +-- 2016-03-06 738 0.1 First draft +------------------------------------------------------------------------------ +-- +-- rbus registers: see sysmon_rbus_core and XADC user guide +-- +-- XADC usage: +-- - build-in sensors: temp, Vccint, Vccaux, Vccbram +-- - arty power monitoring: +-- VAUX( 1) VPWR(0) <- 1/5.99 of JPR5V0 (main 5 V line) +-- VAUX( 2) VPWR(1) <- 1/16 of VU (external power jack) +-- VAUX( 9) VPWR(2) <- 250mV/A from shunt on JPR5V0 (main 5 V line) +-- VAUX(10) VPWR(3) <- 500mV/A from shunt on VCC0V95 (FPGA core) +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library unisim; +use unisim.vcomponents.ALL; + +use work.slvtypes.all; +use work.rblib.all; +use work.sysmonrbuslib.all; + +-- ---------------------------------------------------------------------------- + +entity sysmonx_rbus_arty is -- XADC interface to rbus (for arty) + generic ( + INIT_OT_LIMIT : real := 125.0; -- INIT_53 + INIT_OT_RESET : real := 70.0; -- INIT_57 + INIT_TEMP_UP : real := 85.0; -- INIT_50 (default for C grade) + INIT_TEMP_LOW : real := 60.0; -- INIT_54 + INIT_VCCINT_UP : real := 0.98; -- INIT_51 (default for -1L types) + INIT_VCCINT_LOW : real := 0.92; -- INIT_55 (default for -1L types) + INIT_VCCAUX_UP : real := 1.89; -- INIT_52 + INIT_VCCAUX_LOW : real := 1.71; -- INIT_56 + INIT_VCCBRAM_UP : real := 0.98; -- INIT_58 (default for -1L types) + INIT_VCCBRAM_LOW : real := 0.92; -- INIT_5C (default for -1L types) + CLK_MHZ : integer := 250; -- clock frequency in MHz + RB_ADDR : slv16 := slv(to_unsigned(16#0000#,16))); + port ( + CLK : in slbit; -- clock + RESET : in slbit := '0'; -- reset + RB_MREQ : in rb_mreq_type; -- rbus: request + RB_SRES : out rb_sres_type; -- rbus: response + ALM : out slv8; -- xadc: alarms + OT : out slbit; -- xadc: over temp + TEMP : out slv12; -- xadc: die temp + VPWRN : in slv4 := (others=>'0'); -- xadc: vpwr neg (4 chan pwrmon) + VPWRP : in slv4 := (others=>'0') -- xadc: vpwr pos (4 chan pwrmon) + ); +end sysmonx_rbus_arty; + +architecture syn of sysmonx_rbus_arty is + + constant vpwrmap_0 : integer := 1; -- map vpwr(0) -> xadc vaux + constant vpwrmap_1 : integer := 2; -- map vpwr(1) -> xadc vaux + constant vpwrmap_2 : integer := 9; -- map vpwr(2) -> xadc vaux + constant vpwrmap_3 : integer := 10; -- map vpwr(3) -> xadc vaux + + constant conf2_cd : integer := (CLK_MHZ+25)/26; -- clock division ratio + constant init_42 : bv16 := to_bitvector(slv(to_unsigned(256*conf2_cd,16))); + + constant init_49 : bv16 := (vpwrmap_0 => '1', -- seq #1: (enable pwrmon) + vpwrmap_1 => '1', + vpwrmap_2 => '1', + vpwrmap_3 => '1', + others => '0'); + + signal VAUXN : slv16 := (others=>'0'); + signal VAUXP : slv16 := (others=>'0'); + + signal SM_DEN : slbit := '0'; + signal SM_DWE : slbit := '0'; + signal SM_DADDR : slv7 := (others=>'0'); + signal SM_DI : slv16 := (others=>'0'); + signal SM_DO : slv16 := (others=>'0'); + signal SM_DRDY : slbit := '0'; + signal SM_EOS : slbit := '0'; + signal SM_EOC : slbit := '0'; + signal SM_RESET : slbit := '0'; + signal SM_CHAN : slv5 := (others=>'0'); + signal SM_ALM : slv8 := (others=>'0'); + signal SM_OT : slbit := '0'; + signal SM_JTAGLOCKED : slbit := '0'; + signal SM_JTAGMODIFIED : slbit := '0'; + signal SM_JTAGBUSY : slbit := '0'; + +begin + + SM : XADC + generic map ( + INIT_40 => xadc_init_40_default, -- conf #0 + INIT_41 => xadc_init_41_default, -- conf #1 + INIT_42 => init_42, + INIT_43 => x"0000", -- test #0 - don't use, stay 0 + INIT_44 => x"0000", -- test #1 - " + INIT_45 => x"0000", -- test #2 - " + INIT_46 => x"0000", -- test #3 - " + INIT_47 => x"0000", -- test #4 - " + INIT_48 => xadc_init_48_default, -- seq #0: sel 0 + INIT_49 => init_49, -- seq #1: sel 1 (enable pwrmon) + INIT_4A => xadc_init_4a_default, -- seq #2: avr 0 + INIT_4B => x"0000", -- seq #3: avr 1: " + INIT_4C => x"0000", -- seq #4: mode 0: unipolar + INIT_4D => x"0000", -- seq #5: mode 1: " + INIT_4E => x"0000", -- seq #6: time 0: fast + INIT_4F => x"0000", -- seq #7: time 1: " + INIT_50 => xadc_temp2alim(INIT_TEMP_UP), -- alm #00: temp up (0) + INIT_51 => xadc_svolt2alim(INIT_VCCINT_UP), -- alm #01: ccint up (1) + INIT_52 => xadc_svolt2alim(INIT_VCCAUX_UP), -- alm #02: ccaux up (2) + INIT_53 => xadc_init_53_default, -- alm #03: OT limit OT + INIT_54 => xadc_temp2alim(INIT_TEMP_LOW), -- alm #04: temp low (0) + INIT_55 => xadc_svolt2alim(INIT_VCCINT_LOW), -- alm #05: ccint low (1) + INIT_56 => xadc_svolt2alim(INIT_VCCAUX_LOW), -- alm #06: ccaux low (2) + INIT_57 => xadc_init_57_default, -- alm #07: OT reset OT + INIT_58 => xadc_svolt2alim(INIT_VCCBRAM_UP), -- alm #08: ccbram up (3) + INIT_59 => x"0000", -- alm #09: ccpint up (4) + INIT_5A => x"0000", -- alm #10: ccpaux up (5) + INIT_5B => x"0000", -- alm #11: ccdram up (6) + INIT_5C => xadc_svolt2alim(INIT_VCCBRAM_LOW),-- alm #12: ccbram low (3) + INIT_5D => x"0000", -- alm #13: ccpint low (4) + INIT_5E => x"0000", -- alm #14: ccpaux low (5) + INIT_5F => x"0000", -- alm #15: ccdram low (6) +-- IS_CONVSTCLK_INVERTED => '0', +-- IS_DCLK_INVERTED => '0', + SIM_DEVICE => "7SERIES", + SIM_MONITOR_FILE => "sysmon_stim") + port map ( + DCLK => CLK, + DEN => SM_DEN, + DWE => SM_DWE, + DADDR => SM_DADDR, + DI => SM_DI, + DO => SM_DO, + DRDY => SM_DRDY, + EOC => SM_EOC, -- connected for tb usage + EOS => SM_EOS, + BUSY => open, + RESET => SM_RESET, + CHANNEL => SM_CHAN, -- connected for tb usage + MUXADDR => open, + ALM => SM_ALM, + OT => SM_OT, + CONVST => '0', + CONVSTCLK => '0', + JTAGBUSY => SM_JTAGBUSY, + JTAGLOCKED => SM_JTAGLOCKED, + JTAGMODIFIED => SM_JTAGMODIFIED, + VAUXN => VAUXN, + VAUXP => VAUXP, + VN => '0', + VP => '0' + ); + + VAUXN <= (vpwrmap_0 => VPWRN(0), + vpwrmap_1 => VPWRN(1), + vpwrmap_2 => VPWRN(2), + vpwrmap_3 => VPWRN(3), + others=>'0'); + VAUXP <= (vpwrmap_0 => VPWRP(0), + vpwrmap_1 => VPWRP(1), + vpwrmap_2 => VPWRP(2), + vpwrmap_3 => VPWRP(3), + others=>'0'); + + SMRB : sysmon_rbus_core + generic map ( + DAWIDTH => 7, + ALWIDTH => 8, + TEWIDTH => 12, + IBASE => x"78", + RB_ADDR => RB_ADDR) + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES, + SM_DEN => SM_DEN, + SM_DWE => SM_DWE, + SM_DADDR => SM_DADDR, + SM_DI => SM_DI, + SM_DO => SM_DO, + SM_DRDY => SM_DRDY, + SM_EOS => SM_EOS, + SM_RESET => SM_RESET, + SM_ALM => SM_ALM, + SM_OT => SM_OT, + SM_JTAGBUSY => SM_JTAGBUSY, + SM_JTAGLOCKED => SM_JTAGLOCKED, + SM_JTAGMODIFIED => SM_JTAGMODIFIED, + TEMP => TEMP + ); + + ALM <= SM_ALM; + OT <= SM_OT; + +end syn; diff --git a/rtl/bplib/sysmon/sysmonx_rbus_base.vbom b/rtl/bplib/sysmon/sysmonx_rbus_base.vbom new file mode 100644 index 00000000..82aabcaf --- /dev/null +++ b/rtl/bplib/sysmon/sysmonx_rbus_base.vbom @@ -0,0 +1,9 @@ +# libs +../../vlib/slvtypes.vhd +../../vlib/rbus/rblib.vhd +sysmonrbuslib.vbom +@lib:unisim +# components +sysmon_rbus_core.vbom +# design +sysmonx_rbus_base.vhd diff --git a/rtl/bplib/sysmon/sysmonx_rbus_base.vhd b/rtl/bplib/sysmon/sysmonx_rbus_base.vhd new file mode 100644 index 00000000..00b60133 --- /dev/null +++ b/rtl/bplib/sysmon/sysmonx_rbus_base.vhd @@ -0,0 +1,192 @@ +-- $Id: sysmonx_rbus_base.vhd 742 2016-03-13 14:40:19Z mueller $ +-- +-- Copyright 2016- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sysmonx_rbus_base - syn +-- Description: 7series XADC interface to rbus (basic supply monitor version) +-- +-- Dependencies: sysmon_rbus_core +-- +-- Test bench: - +-- +-- Target Devices: 7series +-- Tool versions: viv 2015.4; ghdl 0.33 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2016-03-13 742 1.0 Initial version +-- 2016-03-06 738 0.1 First draft +------------------------------------------------------------------------------ +-- +-- rbus registers: see sysmon_rbus_core and XADC user guide +-- +-- XADC usage: +-- - only build-in sensors: temp, Vccint, Vccaux, Vccbram +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library unisim; +use unisim.vcomponents.ALL; + +use work.slvtypes.all; +use work.rblib.all; +use work.sysmonrbuslib.all; + +-- ---------------------------------------------------------------------------- + +entity sysmonx_rbus_base is -- XADC interface to rbus (basic monitor) + generic ( + INIT_TEMP_UP : real := 85.0; -- INIT_50 (default for C grade) + INIT_TEMP_LOW : real := 60.0; -- INIT_54 + INIT_VCCINT_UP : real := 1.05; -- INIT_51 (default for non-L types) + INIT_VCCINT_LOW : real := 0.95; -- INIT_55 (default for non-L types) + INIT_VCCAUX_UP : real := 1.89; -- INIT_52 + INIT_VCCAUX_LOW : real := 1.71; -- INIT_56 + INIT_VCCBRAM_UP : real := 1.05; -- INIT_58 (default for non-L types) + INIT_VCCBRAM_LOW : real := 0.95; -- INIT_5C (default for non-L types) + CLK_MHZ : integer := 250; -- clock frequency in MHz + RB_ADDR : slv16 := slv(to_unsigned(16#0000#,16))); + port ( + CLK : in slbit; -- clock + RESET : in slbit := '0'; -- reset + RB_MREQ : in rb_mreq_type; -- rbus: request + RB_SRES : out rb_sres_type; -- rbus: response + ALM : out slv8; -- xadc: alarms + OT : out slbit; -- xadc: over temp + TEMP : out slv12 -- xadc: die temp + ); +end sysmonx_rbus_base; + +architecture syn of sysmonx_rbus_base is + + constant conf2_cd : integer := (CLK_MHZ+25)/26; -- clock division ratio + constant init_42 : bv16 := to_bitvector(slv(to_unsigned(256*conf2_cd,16))); + + signal SM_DEN : slbit := '0'; + signal SM_DWE : slbit := '0'; + signal SM_DADDR : slv7 := (others=>'0'); + signal SM_DI : slv16 := (others=>'0'); + signal SM_DO : slv16 := (others=>'0'); + signal SM_DRDY : slbit := '0'; + signal SM_EOS : slbit := '0'; + signal SM_EOC : slbit := '0'; + signal SM_RESET : slbit := '0'; + signal SM_CHAN : slv5 := (others=>'0'); + signal SM_ALM : slv8 := (others=>'0'); + signal SM_OT : slbit := '0'; + signal SM_JTAGLOCKED : slbit := '0'; + signal SM_JTAGMODIFIED : slbit := '0'; + signal SM_JTAGBUSY : slbit := '0'; + +begin + + SM : XADC + generic map ( + INIT_40 => xadc_init_40_default, -- conf #0 + INIT_41 => xadc_init_41_default, -- conf #1 + INIT_42 => init_42, + INIT_43 => x"0000", -- test #0 - don't use, stay 0 + INIT_44 => x"0000", -- test #1 - " + INIT_45 => x"0000", -- test #2 - " + INIT_46 => x"0000", -- test #3 - " + INIT_47 => x"0000", -- test #4 - " + INIT_48 => xadc_init_48_default, -- seq #0: sel 0 + INIT_49 => x"0000", -- seq #1: sel 1: no aux + INIT_4A => xadc_init_4a_default, -- seq #2: avr 0 + INIT_4B => x"0000", -- seq #3: avr 1: " + INIT_4C => x"0000", -- seq #4: mode 0: unipolar + INIT_4D => x"0000", -- seq #5: mode 1: " + INIT_4E => x"0000", -- seq #6: time 0: fast + INIT_4F => x"0000", -- seq #7: time 1: " + INIT_50 => xadc_temp2alim(INIT_TEMP_UP), -- alm #00: temp up (0) + INIT_51 => xadc_svolt2alim(INIT_VCCINT_UP), -- alm #01: ccint up (1) + INIT_52 => xadc_svolt2alim(INIT_VCCAUX_UP), -- alm #02: ccaux up (2) + INIT_53 => xadc_init_53_default, -- alm #03: OT limit OT + INIT_54 => xadc_temp2alim(INIT_TEMP_LOW), -- alm #04: temp low (0) + INIT_55 => xadc_svolt2alim(INIT_VCCINT_LOW), -- alm #05: ccint low (1) + INIT_56 => xadc_svolt2alim(INIT_VCCAUX_LOW), -- alm #06: ccaux low (2) + INIT_57 => xadc_init_57_default, -- alm #07: OT reset OT + INIT_58 => xadc_svolt2alim(INIT_VCCBRAM_UP), -- alm #08: ccbram up (3) + INIT_59 => x"0000", -- alm #09: ccpint up (4) + INIT_5A => x"0000", -- alm #10: ccpaux up (5) + INIT_5B => x"0000", -- alm #11: ccdram up (6) + INIT_5C => xadc_svolt2alim(INIT_VCCBRAM_LOW),-- alm #12: ccbram low (3) + INIT_5D => x"0000", -- alm #13: ccpint low (4) + INIT_5E => x"0000", -- alm #14: ccpaux low (5) + INIT_5F => x"0000", -- alm #15: ccdram low (6) +-- IS_CONVSTCLK_INVERTED => '0', +-- IS_DCLK_INVERTED => '0', + SIM_DEVICE => "7SERIES", + SIM_MONITOR_FILE => "sysmon_stim") + port map ( + DCLK => CLK, + DEN => SM_DEN, + DWE => SM_DWE, + DADDR => SM_DADDR, + DI => SM_DI, + DO => SM_DO, + DRDY => SM_DRDY, + EOC => SM_EOC, -- connected for tb usage + EOS => SM_EOS, + BUSY => open, + RESET => SM_RESET, + CHANNEL => SM_CHAN, -- connected for tb usage + MUXADDR => open, + ALM => SM_ALM, + OT => SM_OT, + CONVST => '0', + CONVSTCLK => '0', + JTAGBUSY => SM_JTAGBUSY, + JTAGLOCKED => SM_JTAGLOCKED, + JTAGMODIFIED => SM_JTAGMODIFIED, + VAUXN => (others=>'0'), + VAUXP => (others=>'0'), + VN => '0', + VP => '0' + ); + + SMRB : sysmon_rbus_core + generic map ( + DAWIDTH => 7, + ALWIDTH => 8, + TEWIDTH => 12, + IBASE => x"78", + RB_ADDR => RB_ADDR) + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES, + SM_DEN => SM_DEN, + SM_DWE => SM_DWE, + SM_DADDR => SM_DADDR, + SM_DI => SM_DI, + SM_DO => SM_DO, + SM_DRDY => SM_DRDY, + SM_EOS => SM_EOS, + SM_RESET => SM_RESET, + SM_ALM => SM_ALM, + SM_OT => SM_OT, + SM_JTAGBUSY => SM_JTAGBUSY, + SM_JTAGLOCKED => SM_JTAGLOCKED, + SM_JTAGMODIFIED => SM_JTAGMODIFIED, + TEMP => TEMP + ); + + ALM <= SM_ALM; + OT <= SM_OT; + +end syn; diff --git a/rtl/bplib/sysmon/tb/sysmon_stim_arty.dat b/rtl/bplib/sysmon/tb/sysmon_stim_arty.dat new file mode 100644 index 00000000..cadda0aa --- /dev/null +++ b/rtl/bplib/sysmon/tb/sysmon_stim_arty.dat @@ -0,0 +1,2 @@ + TIME TEMP VCCINT VCCAUX VCCBRAM VAUXP[1] VAUXN[1] VAUXP[2] VAUXN[2] VAUXP[9] VAUXN[9] VAUXP[10] VAUXN[10] + 00000 25.0 0.95 1.80 0.95 0.840 0.000 0.000 0.000 0.062 0.000 0.050 0.000 diff --git a/rtl/bplib/sysmon/tb/sysmon_stim_n4.dat b/rtl/bplib/sysmon/tb/sysmon_stim_n4.dat new file mode 100644 index 00000000..8c366411 --- /dev/null +++ b/rtl/bplib/sysmon/tb/sysmon_stim_n4.dat @@ -0,0 +1,2 @@ + TIME TEMP VCCINT VCCAUX VCCBRAM + 00000 25.0 1.00 1.80 1.00 diff --git a/rtl/ibus/Makefile b/rtl/ibus/Makefile index 21f8a321..ed92a827 100644 --- a/rtl/ibus/Makefile +++ b/rtl/ibus/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -13,7 +13,7 @@ NGC_all = $(VBOM_all:.vbom=.ngc) ifndef XTW_BOARD XTW_BOARD=nexys3 endif -include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk +include ${RETROBASE}/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # .PHONY : all clean # @@ -23,7 +23,7 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/make_ise/generic_ghdl.mk b/rtl/make_ise/generic_ghdl.mk index 10cbf692..9cb1c822 100644 --- a/rtl/make_ise/generic_ghdl.mk +++ b/rtl/make_ise/generic_ghdl.mk @@ -1,4 +1,4 @@ -# $Id: generic_ghdl.mk 646 2015-02-15 12:04:55Z mueller $ +# $Id: generic_ghdl.mk 733 2016-02-20 12:24:13Z mueller $ # # Copyright 2007-2015 by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory @@ -16,7 +16,7 @@ # 2007-06-10 52 1.0 Initial version # GHDLIEEE = --ieee=synopsys -GHDLXLPATH = $(XTWI_PATH)/ISE_DS/ISE/ghdl +GHDLXLPATH = ${XTWI_PATH}/ISE_DS/ISE/ghdl # % : %.vbom vbomconv --ghdl_i $< @@ -35,7 +35,7 @@ GHDLXLPATH = $(XTWI_PATH)/ISE_DS/ISE/ghdl %.dep_ghdl: %.vbom vbomconv --dep_ghdl $< > $@ # -include $(RETROBASE)/rtl/make_ise/dontincdep.mk +include ${RETROBASE}/rtl/make_ise/dontincdep.mk # .PHONY: ghdl_clean ghdl_tmp_clean # diff --git a/rtl/make_ise/generic_isim.mk b/rtl/make_ise/generic_isim.mk index 6c7a0738..9d73fdcb 100644 --- a/rtl/make_ise/generic_isim.mk +++ b/rtl/make_ise/generic_isim.mk @@ -1,4 +1,4 @@ -# $Id: generic_isim.mk 642 2015-02-06 18:53:12Z mueller $ +# $Id: generic_isim.mk 733 2016-02-20 12:24:13Z mueller $ # # Copyright 2009-2013 by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory @@ -40,7 +40,7 @@ FUSE = fuse %.dep_isim: %.vbom vbomconv --dep_isim $< > $@ # -include $(RETROBASE)/rtl/make_ise/dontincdep.mk +include ${RETROBASE}/rtl/make_ise/dontincdep.mk # .PHONY: isim_clean isim_tmp_clean # diff --git a/rtl/make_ise/generic_xflow.mk b/rtl/make_ise/generic_xflow.mk index 75c3452e..e9d76e88 100644 --- a/rtl/make_ise/generic_xflow.mk +++ b/rtl/make_ise/generic_xflow.mk @@ -1,4 +1,4 @@ -# $Id: generic_xflow.mk 672 2015-05-02 21:58:28Z mueller $ +# $Id: generic_xflow.mk 733 2016-02-20 12:24:13Z mueller $ # # Copyright 2007-2015 by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory @@ -311,7 +311,7 @@ endif # # Cleanup # -include $(RETROBASE)/rtl/make_ise/dontincdep.mk +include ${RETROBASE}/rtl/make_ise/dontincdep.mk # .PHONY : ise_clean ise_tmp_clean # diff --git a/rtl/make_viv/generic_ghdl.mk b/rtl/make_viv/generic_ghdl.mk index 602f3cee..a4bd1688 100644 --- a/rtl/make_viv/generic_ghdl.mk +++ b/rtl/make_viv/generic_ghdl.mk @@ -1,4 +1,4 @@ -# $Id: generic_ghdl.mk 646 2015-02-15 12:04:55Z mueller $ +# $Id: generic_ghdl.mk 733 2016-02-20 12:24:13Z mueller $ # # Copyright 2015- by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory @@ -8,7 +8,7 @@ # 2015-02-14 646 1.0 Initial version (cloned from make_ise) # GHDLIEEE = --ieee=synopsys -GHDLXLPATH = $(XTWV_PATH)/ghdl +GHDLXLPATH = ${XTWV_PATH}/ghdl # % : %.vbom vbomconv --ghdl_i $< @@ -23,7 +23,7 @@ GHDLXLPATH = $(XTWV_PATH)/ghdl %.dep_ghdl: %.vbom vbomconv --dep_ghdl $< > $@ # -include $(RETROBASE)/rtl/make_ise/dontincdep.mk +include ${RETROBASE}/rtl/make_ise/dontincdep.mk # .PHONY: ghdl_clean ghdl_tmp_clean # diff --git a/rtl/make_viv/generic_vivado.mk b/rtl/make_viv/generic_vivado.mk index 2dc81deb..0aa755c2 100644 --- a/rtl/make_viv/generic_vivado.mk +++ b/rtl/make_viv/generic_vivado.mk @@ -1,4 +1,4 @@ -# $Id: generic_vivado.mk 646 2015-02-15 12:04:55Z mueller $ +# $Id: generic_vivado.mk 733 2016-02-20 12:24:13Z mueller $ # # Copyright 2015- by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory @@ -18,16 +18,16 @@ endif # ensure that default tools and flows are defined # ifndef VIV_INIT -VIV_INIT = $(RETROBASE)/rtl/make_viv/viv_init.tcl +VIV_INIT = ${RETROBASE}/rtl/make_viv/viv_init.tcl endif ifndef VIV_BUILD_FLOW -VIV_BUILD_FLOW = $(RETROBASE)/rtl/make_viv/viv_default_build.tcl +VIV_BUILD_FLOW = ${RETROBASE}/rtl/make_viv/viv_default_build.tcl endif ifndef VIV_CONFIG_FLOW -VIV_CONFIG_FLOW = $(RETROBASE)/rtl/make_viv/viv_default_config.tcl +VIV_CONFIG_FLOW = ${RETROBASE}/rtl/make_viv/viv_default_config.tcl endif ifndef VIV_MODEL_FLOW -VIV_MODEL_FLOW = $(RETROBASE)/rtl/make_viv/viv_default_model.tcl +VIV_MODEL_FLOW = ${RETROBASE}/rtl/make_viv/viv_default_model.tcl endif # # $@ first target @@ -123,7 +123,7 @@ vivado : # # Cleanup # -include $(RETROBASE)/rtl/make_viv/dontincdep.mk +include ${RETROBASE}/rtl/make_viv/dontincdep.mk # .PHONY : viv_clean viv_tmp_clean # diff --git a/rtl/make_viv/generic_xsim.mk b/rtl/make_viv/generic_xsim.mk new file mode 100644 index 00000000..02f5c228 --- /dev/null +++ b/rtl/make_viv/generic_xsim.mk @@ -0,0 +1,60 @@ +# $Id: generic_xsim.mk 733 2016-02-20 12:24:13Z mueller $ +# +# Copyright 2016- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# Revision History: +# Date Rev Version Comment +# 2016-02-06 727 1.0 Initial version +# +%_XSim : %.vbom + vbomconv -vsim_prj $< > $*_vsim.sh + chmod +x $*_vsim.sh + $*_vsim.sh + rm -rf $*_vsim.sh +# +# rule to build XSim ssim model from _ssim vbom +# +%_XSim_ssim : %_ssim.vbom + vbomconv -vsim_prj $< > $*_vsim.sh + chmod +x $*_vsim.sh + $*_vsim.sh + rm -rf $*_vsim.sh +# +# rule to build XSim osim model from _ssim vbom +# +%_XSim_osim : %_ssim.vbom + vbomconv -vsim_prj $*_osim.vbom > $*_vsim.sh + chmod +x $*_vsim.sh + $*_vsim.sh + rm -rf $*_vsim.sh +# +# rule to build XSim tsim model from _ssim vbom +# +%_XSim_tsim : %_ssim.vbom + vbomconv -vsim_prj $*_tsim.vbom > $*_vsim.sh + chmod +x $*_vsim.sh + $*_vsim.sh + rm -rf $*_vsim.sh +# +%.dep_vsim: %.vbom + vbomconv --dep_vsim $< > $@ +# +include ${RETROBASE}/rtl/make_ise/dontincdep.mk +# +.PHONY: xsim_clean xsim_tmp_clean +# +xsim_clean: xsim_tmp_clean + rm -f $(EXE_all:%=%_XSim) + rm -f $(EXE_all:%=%_XSim_ssim) + rm -f $(EXE_all:%=%_XSim_osim) + rm -f $(EXE_all:%=%_XSim_tsim) +# +xsim_tmp_clean: + rm -f isim.log isim.wdb + rm -f xsim.jou xsim.log + rm -f xsim_*.backup.jou xsim_*.backup.log + rm -f webtalk.jou webtalk.log + rm -f webtalk_*.backup.jou webtalk_*.backup.log + rm -rf xsim.dir +# diff --git a/rtl/make_viv/viv_default_arty.mk b/rtl/make_viv/viv_default_arty.mk new file mode 100644 index 00000000..611dc60f --- /dev/null +++ b/rtl/make_viv/viv_default_arty.mk @@ -0,0 +1,16 @@ +# $Id: viv_default_arty.mk 733 2016-02-20 12:24:13Z mueller $ +# +# Copyright 2016- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# Revision History: +# Date Rev Version Comment +# 2016-01-31 726 1.0 Initial version +#--- +# +# Setup for Digilent Arty +# +# setup default board and part +# +VIV_BOARD_SETUP = ${RETROBASE}/rtl/bplib/arty/arty_setup.tcl +# diff --git a/rtl/make_viv/viv_default_basys3.mk b/rtl/make_viv/viv_default_basys3.mk index 729305fb..d1a72676 100644 --- a/rtl/make_viv/viv_default_basys3.mk +++ b/rtl/make_viv/viv_default_basys3.mk @@ -1,4 +1,4 @@ -# $Id: viv_default_basys3.mk 637 2015-01-25 18:36:40Z mueller $ +# $Id: viv_default_basys3.mk 733 2016-02-20 12:24:13Z mueller $ # # Copyright 2015- by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory @@ -12,5 +12,5 @@ # # setup default board and part # -VIV_BOARD_SETUP = $(RETROBASE)/rtl/bplib/basys3/basys3_setup.tcl +VIV_BOARD_SETUP = ${RETROBASE}/rtl/bplib/basys3/basys3_setup.tcl # diff --git a/rtl/make_viv/viv_default_nexys4.mk b/rtl/make_viv/viv_default_nexys4.mk index 4c0637f8..2e822d93 100644 --- a/rtl/make_viv/viv_default_nexys4.mk +++ b/rtl/make_viv/viv_default_nexys4.mk @@ -1,4 +1,4 @@ -# $Id: viv_default_nexys4.mk 640 2015-02-01 09:56:53Z mueller $ +# $Id: viv_default_nexys4.mk 733 2016-02-20 12:24:13Z mueller $ # # Copyright 2015- by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory @@ -12,5 +12,5 @@ # # setup default board and part # -VIV_BOARD_SETUP = $(RETROBASE)/rtl/bplib/nexys4/nexys4_setup.tcl +VIV_BOARD_SETUP = ${RETROBASE}/rtl/bplib/nexys4/nexys4_setup.tcl # diff --git a/rtl/make_viv/viv_tools_build.tcl b/rtl/make_viv/viv_tools_build.tcl index 20552bea..cfe6a015 100644 --- a/rtl/make_viv/viv_tools_build.tcl +++ b/rtl/make_viv/viv_tools_build.tcl @@ -1,10 +1,11 @@ -# $Id: viv_tools_build.tcl 649 2015-02-21 21:10:16Z mueller $ +# $Id: viv_tools_build.tcl 738 2016-03-06 13:02:53Z mueller $ # # Copyright 2015- by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory # # Revision History: # Date Rev Version Comment +# 2016-02-28 649 1.1.1 add 2015.4 specific setups # 2015-02-21 649 1.1 add 2014.4 specific setups # 2015-02-14 646 1.0 Initial version # @@ -73,6 +74,11 @@ proc rvtb_default_build {stem step} { # set here to avoid messages during create_project set_msg_config -suppress -id {Board 49-26} } + "2015.4" { + # enable vhdl asserts, see http://www.xilinx.com/support/answers/65415.html + set_param synth.elaboration.rodinMoreOptions \ + {rt::set_parameter ignoreVhdlAssertStmts false} + } } # read setup diff --git a/rtl/sys_gen/tst_fx2loop/Makefile b/rtl/sys_gen/tst_fx2loop/Makefile index 4f42ea3d..1f6f9e1b 100644 --- a/rtl/sys_gen/tst_fx2loop/Makefile +++ b/rtl/sys_gen/tst_fx2loop/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -10,7 +10,7 @@ VBOM_all = $(wildcard *.vbom) NGC_all = $(VBOM_all:.vbom=.ngc) # -include $(RETROBASE)/rtl/make_ise/xflow_default_nexys2.mk +include ${RETROBASE}/rtl/make_ise/xflow_default_nexys2.mk # .PHONY : all clean distclean # @@ -33,7 +33,7 @@ tst_fx2loop_si : tst_fx2loop_si.c # #---- # -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_fx2loop/nexys2/ic/.cvsignore b/rtl/sys_gen/tst_fx2loop/nexys2/ic/.cvsignore index ba828daa..0445c0c1 100644 --- a/rtl/sys_gen/tst_fx2loop/nexys2/ic/.cvsignore +++ b/rtl/sys_gen/tst_fx2loop/nexys2/ic/.cvsignore @@ -1,4 +1 @@ -_impactbatch.log sys_tst_fx2loop_ic_n2.ucf -*.dep_ucf_cpp -*.svf diff --git a/rtl/sys_gen/tst_fx2loop/nexys2/ic/Makefile b/rtl/sys_gen/tst_fx2loop/nexys2/ic/Makefile index 301b7416..02d5983c 100644 --- a/rtl/sys_gen/tst_fx2loop/nexys2/ic/Makefile +++ b/rtl/sys_gen/tst_fx2loop/nexys2/ic/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -8,7 +8,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make_ise/xflow_default_nexys2.mk +include ${RETROBASE}/rtl/make_ise/xflow_default_nexys2.mk FX2_FILE = nexys2_jtag_2fifo_ic.ihx # .PHONY : all clean @@ -20,8 +20,8 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_fx2loop/nexys2/ic3/.cvsignore b/rtl/sys_gen/tst_fx2loop/nexys2/ic3/.cvsignore index c5d3aef3..58ee46ff 100644 --- a/rtl/sys_gen/tst_fx2loop/nexys2/ic3/.cvsignore +++ b/rtl/sys_gen/tst_fx2loop/nexys2/ic3/.cvsignore @@ -1,4 +1 @@ -_impactbatch.log sys_tst_fx2loop_ic3_n2.ucf -*.dep_ucf_cpp -*.svf diff --git a/rtl/sys_gen/tst_fx2loop/nexys2/ic3/Makefile b/rtl/sys_gen/tst_fx2loop/nexys2/ic3/Makefile index 5f150990..24aef271 100644 --- a/rtl/sys_gen/tst_fx2loop/nexys2/ic3/Makefile +++ b/rtl/sys_gen/tst_fx2loop/nexys2/ic3/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -8,7 +8,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make_ise/xflow_default_nexys2.mk +include ${RETROBASE}/rtl/make_ise/xflow_default_nexys2.mk FX2_FILE = nexys2_jtag_3fifo_ic.ihx # .PHONY : all clean @@ -20,8 +20,8 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_fx2loop/nexys2/sys_tst_fx2loop_n2.vbom b/rtl/sys_gen/tst_fx2loop/nexys2/sys_tst_fx2loop_n2.vbom index d2ca6442..ba88e02f 100644 --- a/rtl/sys_gen/tst_fx2loop/nexys2/sys_tst_fx2loop_n2.vbom +++ b/rtl/sys_gen/tst_fx2loop/nexys2/sys_tst_fx2loop_n2.vbom @@ -13,8 +13,8 @@ ../../../bplib/nxcramlib/nxcramlib.vhd ${sys_conf} # components -[xst,vsyn,isim,vsim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom -[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom +[xst,vsyn]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom +[ghdl,isim,vsim]../../../vlib/xlib/dcm_sfs_gsim.vbom ../../../vlib/genlib/clkdivce.vbom ../../../bplib/bpgen/sn_humanio.vbom ../tst_fx2loop_hiomap.vbom diff --git a/rtl/sys_gen/tst_fx2loop/nexys3/ic/.cvsignore b/rtl/sys_gen/tst_fx2loop/nexys3/ic/.cvsignore index 5b8e883f..06082257 100644 --- a/rtl/sys_gen/tst_fx2loop/nexys3/ic/.cvsignore +++ b/rtl/sys_gen/tst_fx2loop/nexys3/ic/.cvsignore @@ -1,4 +1 @@ -_impactbatch.log sys_tst_fx2loop_ic_n3.ucf -*.dep_ucf_cpp -*.svf diff --git a/rtl/sys_gen/tst_fx2loop/nexys3/ic/Makefile b/rtl/sys_gen/tst_fx2loop/nexys3/ic/Makefile index 65917696..4635374e 100644 --- a/rtl/sys_gen/tst_fx2loop/nexys3/ic/Makefile +++ b/rtl/sys_gen/tst_fx2loop/nexys3/ic/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -8,7 +8,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make_ise/xflow_default_nexys3.mk +include ${RETROBASE}/rtl/make_ise/xflow_default_nexys3.mk FX2_FILE = nexys3_jtag_2fifo_ic.ihx # .PHONY : all clean @@ -20,8 +20,8 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_fx2loop/nexys3/ic3/.cvsignore b/rtl/sys_gen/tst_fx2loop/nexys3/ic3/.cvsignore index 4e8c9810..ebe1a6e1 100644 --- a/rtl/sys_gen/tst_fx2loop/nexys3/ic3/.cvsignore +++ b/rtl/sys_gen/tst_fx2loop/nexys3/ic3/.cvsignore @@ -1,4 +1 @@ -_impactbatch.log sys_tst_fx2loop_ic3_n3.ucf -*.dep_ucf_cpp -*.svf diff --git a/rtl/sys_gen/tst_fx2loop/nexys3/ic3/Makefile b/rtl/sys_gen/tst_fx2loop/nexys3/ic3/Makefile index f0b179e8..24fae27a 100644 --- a/rtl/sys_gen/tst_fx2loop/nexys3/ic3/Makefile +++ b/rtl/sys_gen/tst_fx2loop/nexys3/ic3/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -8,7 +8,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make_ise/xflow_default_nexys3.mk +include ${RETROBASE}/rtl/make_ise/xflow_default_nexys3.mk FX2_FILE = nexys3_jtag_3fifo_ic.ihx # .PHONY : all clean @@ -20,8 +20,8 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_fx2loop/nexys3/sys_tst_fx2loop_n3.vbom b/rtl/sys_gen/tst_fx2loop/nexys3/sys_tst_fx2loop_n3.vbom index e6b7207c..8bc82ddc 100644 --- a/rtl/sys_gen/tst_fx2loop/nexys3/sys_tst_fx2loop_n3.vbom +++ b/rtl/sys_gen/tst_fx2loop/nexys3/sys_tst_fx2loop_n3.vbom @@ -13,8 +13,8 @@ ../../../bplib/nxcramlib/nxcramlib.vhd ${sys_conf} # components -[xst,vsyn,isim,vsim]../../../vlib/xlib/s6_cmt_sfs_unisim.vbom -[ghdl]../../../vlib/xlib/s6_cmt_sfs_gsim.vbom +[xst,vsyn]../../../vlib/xlib/s6_cmt_sfs_unisim.vbom +[ghdl,isim,vsim]../../../vlib/xlib/s6_cmt_sfs_gsim.vbom ../../../vlib/genlib/clkdivce.vbom ../../../bplib/bpgen/sn_humanio.vbom ../tst_fx2loop_hiomap.vbom diff --git a/rtl/sys_gen/tst_rlink/Makefile b/rtl/sys_gen/tst_rlink/Makefile index b8493396..99bcff32 100644 --- a/rtl/sys_gen/tst_rlink/Makefile +++ b/rtl/sys_gen/tst_rlink/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -7,7 +7,7 @@ VBOM_all = $(wildcard *.vbom) NGC_all = $(VBOM_all:.vbom=.ngc) # -include $(RETROBASE)/rtl/make_ise/xflow_default_s3board.mk +include ${RETROBASE}/rtl/make_ise/xflow_default_s3board.mk # .PHONY : all clean # @@ -18,7 +18,7 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_rlink/arty/Makefile b/rtl/sys_gen/tst_rlink/arty/Makefile new file mode 100644 index 00000000..5f42c88f --- /dev/null +++ b/rtl/sys_gen/tst_rlink/arty/Makefile @@ -0,0 +1,25 @@ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2016-02-14 731 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +include ${RETROBASE}/rtl/make_viv/viv_default_arty.mk +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : viv_clean +# +#---- +# +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +endif +# diff --git a/rtl/sys_gen/tst_rlink/arty/sys_conf.vhd b/rtl/sys_gen/tst_rlink/arty/sys_conf.vhd new file mode 100644 index 00000000..6c1b2a08 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/arty/sys_conf.vhd @@ -0,0 +1,57 @@ +-- $Id: sys_conf.vhd 743 2016-03-13 16:42:31Z mueller $ +-- +-- Copyright 2016- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_rlink_arty (for synthesis) +-- +-- Dependencies: - +-- Tool versions: viv 2015.4; ghdl 0.33 +-- Revision History: +-- Date Rev Version Comment +-- 2016-03-12 741 1.1 add sysmon_rbus +-- 2016-02-16 731 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + -- configure clocks -------------------------------------------------------- + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 1; -- dcm 100 MHz + constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + + -- configure rlink and hio interfaces -------------------------------------- + constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + + -- configure further units ------------------------------------------------- + constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC) + + -- derived constants ======================================================= + + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_ser2rri_cdinit : integer := + (sys_conf_clksys/sys_conf_ser2rri_defbaud)-1; + +end package sys_conf; + diff --git a/rtl/sys_gen/tst_rlink/arty/sys_tst_rlink_arty.vbom b/rtl/sys_gen/tst_rlink/arty/sys_tst_rlink_arty.vbom new file mode 100644 index 00000000..61f1f118 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/arty/sys_tst_rlink_arty.vbom @@ -0,0 +1,28 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/xlib/xlib.vhd +../../../vlib/genlib/genlib.vhd +../../../vlib/serport/serportlib.vbom +../../../vlib/rbus/rblib.vhd +../../../vlib/rlink/rlinklib.vbom +../../../bplib/bpgen/bpgenlib.vbom +../../../bplib/bpgen/bpgenrbuslib.vbom +../../../bplib/sysmon/sysmonrbuslib.vbom +${sys_conf := sys_conf.vhd} +# components +[xst,vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom +[ghdl,isim,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/bp_rs232_2line_iob.vbom +../../../bplib/bpgen/bp_swibtnled.vbom +../../../vlib/rlink/rlink_sp1c.vbom +../rbd_tst_rlink.vbom +../../../bplib/bpgen/rgbdrv_master.vbom +../../../bplib/bpgen/rgbdrv_analog_rbus.vbom +../../../bplib/sysmon/sysmonx_rbus_arty.vbom +../../../vlib/rbus/rb_sres_or_4.vbom +../../../vlib/rbus/rb_sres_or_3.vbom +# design +sys_tst_rlink_arty.vhd +@xdc:../../../bplib/arty/arty_pclk.xdc +@xdc:../../../bplib/arty/arty_pins.xdc diff --git a/rtl/sys_gen/tst_rlink/arty/sys_tst_rlink_arty.vhd b/rtl/sys_gen/tst_rlink/arty/sys_tst_rlink_arty.vhd new file mode 100644 index 00000000..b4df25bd --- /dev/null +++ b/rtl/sys_gen/tst_rlink/arty/sys_tst_rlink_arty.vhd @@ -0,0 +1,352 @@ +-- $Id: sys_tst_rlink_arty.vhd 743 2016-03-13 16:42:31Z mueller $ +-- +-- Copyright 2016- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_tst_rlink_arty - syn +-- Description: rlink tester design for arty board +-- +-- Dependencies: vlib/xlib/s7_cmt_sfs +-- vlib/genlib/clkdivce +-- bplib/bpgen/bp_rs232_2line_iob +-- bplib/bpgen/bp_swibtnled +-- vlib/rlink/rlink_sp1c +-- rbd_tst_rlink +-- bplib/bpgen/rgbdrv_master +-- bplib/bpgen/rgbdrv_analog_rbus +-- bplib/sysmon/sysmonx_rbus_arty +-- vlib/rbus/rb_sres_or_4 +-- vlib/rbus/rb_sres_or_3 +-- +-- Test bench: tb/tb_tst_rlink_arty +-- +-- Target Devices: generic +-- Tool versions: viv 2015.4; ghdl 0.33 +-- +-- Synthesized (xst): +-- Date Rev viv Target flop lutl lutm bram slic +-- 2016-03-13 743 2015.4 xc7a35t-1L 980 1390 64 4.5 514 +XADC +-- 2016-02-20 734 2015.4 xc7a35t-1L 941 1352 64 4.5 478 +-- 2016-02-14 731 2015.4 xc7a35t-1L 777 1313 64 4.5 399 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2016-03-13 743 1.1.3 hardwire XON=1, all SWI now unused +-- 2016-03-12 741 1.1.2 use sysmonx_rbus_arty now +-- 2016-03-06 740 1.1.1 add A_VPWRN/P to baseline config +-- 2016-03-06 738 1.1 add xadc_rbus +-- 2016-02-20 734 1.0.1 add rgbdrv_analog_rbus for four rgb leds +-- 2016-02-14 731 1.0 Initial version (derived from sys_tst_rlink_b3) +------------------------------------------------------------------------------ +-- Usage of Arty Switches, Buttons, LEDs: +-- +-- SWI(3:2): no function +-- SWI(1): -unused- +-- SWI(0): -unused- +-- +-- LED(3): not SER_MONI.txok (shows tx back preasure) +-- LED(2): SER_MONI.txact (shows tx activity) +-- LED(1): not SER_MONI.rxok (shows rx back preasure) +-- LED(0): SER_MONI.rxact (shows rx activity) +-- + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.genlib.all; +use work.serportlib.all; +use work.rblib.all; +use work.rlinklib.all; +use work.bpgenlib.all; +use work.bpgenrbuslib.all; +use work.sysmonrbuslib.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_tst_rlink_arty is -- top level + -- implements arty_aif + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv4; -- arty switches + I_BTN : in slv4; -- arty buttons + O_LED : out slv4; -- arty leds + O_RGBLED0 : out slv3; -- arty rgb-led 0 + O_RGBLED1 : out slv3; -- arty rgb-led 1 + O_RGBLED2 : out slv3; -- arty rgb-led 2 + O_RGBLED3 : out slv3; -- arty rgb-led 3 + A_VPWRP : in slv4; -- arty pwrmon (pos) + A_VPWRN : in slv4 -- arty pwrmon (neg) + ); +end sys_tst_rlink_arty; + +architecture syn of sys_tst_rlink_arty is + + signal CLK : slbit := '0'; + + signal RXD : slbit := '1'; + signal TXD : slbit := '0'; + + signal SWI : slv4 := (others=>'0'); + signal BTN : slv4 := (others=>'0'); + signal LED : slv4 := (others=>'0'); + + signal RESET : slbit := '0'; + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal RB_MREQ : rb_mreq_type := rb_mreq_init; + signal RB_SRES : rb_sres_type := rb_sres_init; + signal RB_SRES_TST : rb_sres_type := rb_sres_init; + signal RB_SRES_RGB : rb_sres_type := rb_sres_init; + signal RB_SRES_RGB0 : rb_sres_type := rb_sres_init; + signal RB_SRES_RGB1 : rb_sres_type := rb_sres_init; + signal RB_SRES_RGB2 : rb_sres_type := rb_sres_init; + signal RB_SRES_RGB3 : rb_sres_type := rb_sres_init; + signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init; + + signal RB_LAM : slv16 := (others=>'0'); + signal RB_STAT : slv4 := (others=>'0'); + + signal SER_MONI : serport_moni_type := serport_moni_init; + signal STAT : slv8 := (others=>'0'); + + signal RGBCNTL : slv3 := (others=>'0'); + signal DIMCNTL : slv12 := (others=>'0'); + + constant rbaddr_rgb0 : slv16 := x"fc00"; -- fe00/0004: 1111 1100 0000 00xx + constant rbaddr_rgb1 : slv16 := x"fc04"; -- fe04/0004: 1111 1100 0000 01xx + constant rbaddr_rgb2 : slv16 := x"fc08"; -- fe08/0004: 1111 1100 0000 10xx + constant rbaddr_rgb3 : slv16 := x"fc0c"; -- fe0c/0004: 1111 1100 0000 11xx + constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx + +begin + + assert (sys_conf_clksys mod 1000000) = 0 + report "assert sys_conf_clksys on MHz grid" + severity failure; + + RESET <= '0'; -- so far not used + + GEN_CLKSYS : s7_cmt_sfs + generic map ( + VCO_DIVIDE => sys_conf_clksys_vcodivide, + VCO_MULTIPLY => sys_conf_clksys_vcomultiply, + OUT_DIVIDE => sys_conf_clksys_outdivide, + CLKIN_PERIOD => 10.0, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clksys_gentype) + port map ( + CLKIN => I_CLK100, + CLKFX => CLK, + LOCKED => open + ); + + CLKDIV : clkdivce + generic map ( + CDUWIDTH => 7, + USECDIV => sys_conf_clksys_mhz, + MSECDIV => 1000) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC + ); + + IOB_RS232 : bp_rs232_2line_iob + port map ( + CLK => CLK, + RXD => RXD, + TXD => TXD, + I_RXD => I_RXD, + O_TXD => O_TXD + ); + + HIO : bp_swibtnled + generic map ( + SWIDTH => I_SWI'length, + BWIDTH => I_BTN'length, + LWIDTH => O_LED'length, + DEBOUNCE => sys_conf_hio_debounce) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + SWI => SWI, + BTN => BTN, + LED => LED, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED + ); + + RLINK : rlink_sp1c + generic map ( + BTOWIDTH => 6, + RTAWIDTH => 12, + SYSID => (others=>'0'), + IFAWIDTH => 5, + OFAWIDTH => 5, + ENAPIN_RLMON => sbcntl_sbf_rlmon, + ENAPIN_RBMON => sbcntl_sbf_rbmon, + CDWIDTH => 15, + CDINIT => sys_conf_ser2rri_cdinit, + RBMON_AWIDTH => 0, -- must be 0, rbmon in rbd_tst_rlink + RBMON_RBADDR => (others=>'0')) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + CE_INT => CE_MSEC, + RESET => RESET, + ENAXON => '1', + ESCFILL => '0', + RXSD => RXD, + TXSD => TXD, + CTS_N => '0', + RTS_N => open, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT, + RL_MONI => open, + SER_MONI => SER_MONI + ); + + RBDTST : entity work.rbd_tst_rlink + port map ( + CLK => CLK, + RESET => RESET, + CE_USEC => CE_USEC, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_TST, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT, + RB_SRES_TOP => RB_SRES, + RXSD => RXD, + RXACT => SER_MONI.rxact, + STAT => STAT + ); + + RGBMSTR : rgbdrv_master + generic map ( + DWIDTH => DIMCNTL'length) + port map ( + CLK => CLK, + RESET => RESET, + CE_USEC => CE_USEC, + RGBCNTL => RGBCNTL, + DIMCNTL => DIMCNTL + ); + + RGB0 : rgbdrv_analog_rbus + generic map ( + DWIDTH => DIMCNTL'length, + RB_ADDR => rbaddr_rgb0) + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_RGB0, + RGBCNTL => RGBCNTL, + DIMCNTL => DIMCNTL, + O_RGBLED => O_RGBLED0 + ); + + RGB1 : rgbdrv_analog_rbus + generic map ( + DWIDTH => DIMCNTL'length, + RB_ADDR => rbaddr_rgb1) + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_RGB1, + RGBCNTL => RGBCNTL, + DIMCNTL => DIMCNTL, + O_RGBLED => O_RGBLED1 + ); + + RGB2 : rgbdrv_analog_rbus + generic map ( + DWIDTH => DIMCNTL'length, + RB_ADDR => rbaddr_rgb2) + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_RGB2, + RGBCNTL => RGBCNTL, + DIMCNTL => DIMCNTL, + O_RGBLED => O_RGBLED2 + ); + + RGB3 : rgbdrv_analog_rbus + generic map ( + DWIDTH => DIMCNTL'length, + RB_ADDR => rbaddr_rgb3) + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_RGB3, + RGBCNTL => RGBCNTL, + DIMCNTL => DIMCNTL, + O_RGBLED => O_RGBLED3 + ); + + SMRB : if sys_conf_rbd_sysmon generate + I0: sysmonx_rbus_arty + generic map ( -- use default INIT_ (LP: Vccint=0.95) + CLK_MHZ => sys_conf_clksys_mhz, + RB_ADDR => rbaddr_sysmon) + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_SYSMON, + ALM => open, + OT => open, + TEMP => open, + VPWRN => A_VPWRN, + VPWRP => A_VPWRP + ); + end generate SMRB; + + RB_SRES_ORRGB : rb_sres_or_4 + port map ( + RB_SRES_1 => RB_SRES_RGB0, + RB_SRES_2 => RB_SRES_RGB1, + RB_SRES_3 => RB_SRES_RGB2, + RB_SRES_4 => RB_SRES_RGB3, + RB_SRES_OR => RB_SRES_RGB + ); + + RB_SRES_OR1 : rb_sres_or_3 + port map ( + RB_SRES_1 => RB_SRES_TST, + RB_SRES_2 => RB_SRES_RGB, + RB_SRES_3 => RB_SRES_SYSMON, + RB_SRES_OR => RB_SRES + ); + + LED(3) <= not SER_MONI.txok; + LED(2) <= SER_MONI.txact; + LED(1) <= not SER_MONI.rxok; + LED(0) <= SER_MONI.rxact; + +end syn; diff --git a/rtl/sys_gen/tst_rlink/arty/tb/.cvsignore b/rtl/sys_gen/tst_rlink/arty/tb/.cvsignore new file mode 100644 index 00000000..a44ec91a --- /dev/null +++ b/rtl/sys_gen/tst_rlink/arty/tb/.cvsignore @@ -0,0 +1,2 @@ +tb_tst_rlink_arty +sysmon_stim diff --git a/rtl/sys_gen/tst_rlink/arty/tb/Makefile b/rtl/sys_gen/tst_rlink/arty/tb/Makefile new file mode 100644 index 00000000..7684277a --- /dev/null +++ b/rtl/sys_gen/tst_rlink/arty/tb/Makefile @@ -0,0 +1,30 @@ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2016-02-14 731 1.0 Initial version +# +EXE_all = tb_tst_rlink_arty +# +include ${RETROBASE}/rtl/make_viv/viv_default_arty.mk +# +.PHONY : all all_ssim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +# +clean : viv_clean ghdl_clean +# +#----- +# +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk +include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(wildcard *.o.dep_ghdl) +endif +# diff --git a/rtl/sys_gen/tst_rlink/arty/tb/sys_conf_sim.vhd b/rtl/sys_gen/tst_rlink/arty/tb/sys_conf_sim.vhd new file mode 100644 index 00000000..7ed15fda --- /dev/null +++ b/rtl/sys_gen/tst_rlink/arty/tb/sys_conf_sim.vhd @@ -0,0 +1,63 @@ +-- $Id: sys_conf_sim.vhd 743 2016-03-13 16:42:31Z mueller $ +-- +-- Copyright 2016- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_rlink_arty (for simulation) +-- +-- Dependencies: - +-- Tool versions: viv 2015.4; ghdl 0.33 +-- Revision History: +-- Date Rev Version Comment +-- 2016-03-12 741 1.1 add sysmon_rbus +-- 2016-02-14 731 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + -- configure clocks -------------------------------------------------------- + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 1; -- vco --- MHz + constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + -- single clock design, clkser = clksys + constant sys_conf_clkser_vcodivide : positive := sys_conf_clksys_vcodivide; + constant sys_conf_clkser_vcomultiply : positive := sys_conf_clksys_vcomultiply; + constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide; + constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype; + + -- configure rlink and hio interfaces -------------------------------------- + constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim + constant sys_conf_hio_debounce : boolean := false; -- no debouncers + + -- configure further units ------------------------------------------------- + constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC) + + -- derived constants ======================================================= + + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_clkser : integer := + ((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) / + sys_conf_clkser_outdivide; + constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000; + +end package sys_conf; diff --git a/rtl/sys_gen/tst_rlink/arty/tb/tb_tst_rlink_arty.vbom b/rtl/sys_gen/tst_rlink/arty/tb/tb_tst_rlink_arty.vbom new file mode 100644 index 00000000..b13664d9 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/arty/tb/tb_tst_rlink_arty.vbom @@ -0,0 +1,7 @@ +# configure tb_arty with sys_tst_rlink_arty target; +# use vhdl configure file (tb_tst_rlink_arty.vhd) to allow +# that all configurations will co-exist in work library +${arty_aif := ../sys_tst_rlink_arty.vbom} +sys_conf = sys_conf_sim.vhd +../../../../bplib/arty/tb/tb_arty.vbom +tb_tst_rlink_arty.vhd diff --git a/rtl/sys_gen/tst_rlink/arty/tb/tb_tst_rlink_arty.vhd b/rtl/sys_gen/tst_rlink/arty/tb/tb_tst_rlink_arty.vhd new file mode 100644 index 00000000..69ecae36 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/arty/tb/tb_tst_rlink_arty.vhd @@ -0,0 +1,35 @@ +-- $Id: tb_tst_rlink_arty.vhd 731 2016-02-14 21:07:14Z mueller $ +-- +-- Copyright 2016- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_tst_rlink_arty +-- Description: Configuration for tb_tst_rlink_arty for tb_arty +-- +-- Dependencies: sys_tst_rlink_arty +-- +-- To test: sys_tst_rlink_arty +-- +-- Revision History: +-- Date Rev Version Comment +-- 2016-02-14 731 1.0 Initial version +------------------------------------------------------------------------------ + +configuration tb_tst_rlink_arty of tb_arty is + + for sim + for all : arty_aif + use entity work.sys_tst_rlink_arty; + end for; + end for; + +end tb_tst_rlink_arty; diff --git a/rtl/sys_gen/tst_rlink/arty/tb/tb_tst_rlink_arty_ssim.vbom b/rtl/sys_gen/tst_rlink/arty/tb/tb_tst_rlink_arty_ssim.vbom new file mode 100644 index 00000000..9f0ba048 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/arty/tb/tb_tst_rlink_arty_ssim.vbom @@ -0,0 +1,6 @@ +# configure for _*sim case +# Note: this tb uses sys_tst_rlink_arty.vbom in local directory +# (not in .. as usual) to allow a tb specific configure !!! +arty_aif = sys_tst_rlink_arty_ssim.vhd +tb_tst_rlink_arty.vbom +@top:tb_tst_rlink_arty diff --git a/rtl/sys_gen/tst_rlink/arty/tb/tbw.dat b/rtl/sys_gen/tst_rlink/arty/tb/tbw.dat new file mode 100644 index 00000000..396a8561 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/arty/tb/tbw.dat @@ -0,0 +1,7 @@ +# $Id: tbw.dat 741 2016-03-12 23:49:03Z mueller $ +# +[tb_tst_rlink_arty] +rlink_cext_fifo_rx = +rlink_cext_fifo_tx = +rlink_cext_conf = +sysmon_stim = ../../../../bplib/sysmon/tb/sysmon_stim_arty.dat diff --git a/rtl/sys_gen/tst_rlink/basys3/.cvsignore b/rtl/sys_gen/tst_rlink/basys3/.cvsignore deleted file mode 100644 index bcfb2aa7..00000000 --- a/rtl/sys_gen/tst_rlink/basys3/.cvsignore +++ /dev/null @@ -1,7 +0,0 @@ -.Xil -project_mflow -*.jou -*.log -*.rpt -*.dcp -*.dep_* diff --git a/rtl/sys_gen/tst_rlink/basys3/Makefile b/rtl/sys_gen/tst_rlink/basys3/Makefile index 0262221e..1de72d1c 100644 --- a/rtl/sys_gen/tst_rlink/basys3/Makefile +++ b/rtl/sys_gen/tst_rlink/basys3/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 646 2015-02-15 12:04:55Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -7,7 +7,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make_viv/viv_default_basys3.mk +include ${RETROBASE}/rtl/make_viv/viv_default_basys3.mk # .PHONY : all clean # @@ -17,7 +17,7 @@ clean : viv_clean # #---- # -include $(RETROBASE)/rtl/make_viv/generic_vivado.mk +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_vsyn) diff --git a/rtl/sys_gen/tst_rlink/basys3/sys_conf.vhd b/rtl/sys_gen/tst_rlink/basys3/sys_conf.vhd index 16043b76..0321ae47 100644 --- a/rtl/sys_gen/tst_rlink/basys3/sys_conf.vhd +++ b/rtl/sys_gen/tst_rlink/basys3/sys_conf.vhd @@ -1,6 +1,6 @@ --- $Id: sys_conf.vhd 636 2015-01-16 22:22:25Z mueller $ +-- $Id: sys_conf.vhd 743 2016-03-13 16:42:31Z mueller $ -- --- Copyright 2015- by Walter F.J. Mueller +-- Copyright 2015-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,9 +16,11 @@ -- Description: Definitions for sys_tst_rlink_b3 (for synthesis) -- -- Dependencies: - --- Tool versions: viv 2014.4; ghdl 0.31 +-- Tool versions: viv 2014.4-2015.4; ghdl 0.31-0.33 -- Revision History: -- Date Rev Version Comment +-- 2016-03-12 741 1.1 add sysmon_rbus +-- 2016-02-26 735 1.0.2 use s7_cmt_sfs -- 2015-01-16 636 1.0 Initial version ------------------------------------------------------------------------------ @@ -29,16 +31,20 @@ use work.slvtypes.all; package sys_conf is + -- configure clocks -------------------------------------------------------- constant sys_conf_clksys_vcodivide : positive := 1; constant sys_conf_clksys_vcomultiply : positive := 1; -- dcm 100 MHz constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz - constant sys_conf_clksys_gentype : string := "DCM"; + constant sys_conf_clksys_gentype : string := "MMCM"; + -- configure rlink and hio interfaces -------------------------------------- constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud - constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers - -- derived constants + -- configure further units ------------------------------------------------- + constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC) + + -- derived constants ======================================================= constant sys_conf_clksys : integer := ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / diff --git a/rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vbom b/rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vbom index d7129b07..4d3054f6 100644 --- a/rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vbom +++ b/rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vbom @@ -7,16 +7,18 @@ ../../../vlib/rlink/rlinklib.vbom ../../../bplib/bpgen/bpgenlib.vbom ../../../bplib/bpgen/bpgenrbuslib.vbom +../../../bplib/sysmon/sysmonrbuslib.vbom ${sys_conf := sys_conf.vhd} # components -[xst,vsyn,isim,vsim]../../../vlib/xlib/s6_cmt_sfs_unisim.vbom -[ghdl]../../../vlib/xlib/s6_cmt_sfs_gsim.vbom +[xst,vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom +[ghdl,isim,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom ../../../vlib/genlib/clkdivce.vbom ../../../bplib/bpgen/bp_rs232_2line_iob.vbom ../../../bplib/bpgen/sn_humanio_rbus.vbom ../../../vlib/rlink/rlink_sp1c.vbom ../rbd_tst_rlink.vbom -../../../vlib/rbus/rb_sres_or_2.vbom +../../../bplib/sysmon/sysmonx_rbus_base.vbom +../../../vlib/rbus/rb_sres_or_3.vbom # design sys_tst_rlink_b3.vhd @xdc:../../../bplib/basys3/basys3_pclk.xdc diff --git a/rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vhd b/rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vhd index 496d8831..2fad1792 100644 --- a/rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vhd +++ b/rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vhd @@ -1,6 +1,6 @@ --- $Id: sys_tst_rlink_b3.vhd 672 2015-05-02 21:58:28Z mueller $ +-- $Id: sys_tst_rlink_b3.vhd 745 2016-03-18 22:10:34Z mueller $ -- --- Copyright 2015- by Walter F.J. Mueller +-- Copyright 2015-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -15,38 +15,43 @@ -- Module Name: sys_tst_rlink_b3 - syn -- Description: rlink tester design for basys3 -- --- Dependencies: vlib/xlib/s6_cmt_sfs +-- Dependencies: vlib/xlib/s7_cmt_sfs -- vlib/genlib/clkdivce -- bplib/bpgen/bp_rs232_2line_iob -- bplib/bpgen/sn_humanio_rbus -- vlib/rlink/rlink_sp1c -- rbd_tst_rlink --- vlib/rbus/rb_sres_or_2 +-- bplib/sysmon/sysmonx_rbus_base +-- vlib/rbus/rb_sres_or_3 -- -- Test bench: tb/tb_tst_rlink_b3 -- -- Target Devices: generic --- Tool versions: viv 2014.4; ghdl 0.31 +-- Tool versions: viv 2014.4-2015.4; ghdl 0.31-0.33 -- -- Synthesized (xst): -- Date Rev viv Target flop lutl lutm bram slic +-- 2016-03-13 743 2015.4 xc7a35t-1 988 1372 64 4.5 503 +XADC -- 2015-01-30 636 2014.4 xc7a35t-1 946 1319 64 4.5 476 -- -- Revision History: -- Date Rev Version Comment +-- 2016-03-18 745 1.1.1 hardwire XON=1 +-- 2016-03-12 741 1.1 add sysmon_rbus +-- 2016-02-26 735 1.0.2 use s7_cmt_sfs -- 2015-04-11 666 1.0.1 rearrange XON handling -- 2015-01-16 636 1.0 Initial version (derived from sys_tst_rlink_n3) ------------------------------------------------------------------------------ -- Usage of Basys 3 Switches, Buttons, LEDs: -- -- SWI(7:2): no function (only connected to sn_humanio_rbus) --- SWI(1): 1 enable XON +-- SWI(1): -unused- -- SWI(0): -unused- -- -- LED(7): SER_MONI.abact -- LED(6:2): no function (only connected to sn_humanio_rbus) --- LED(0): timer 0 busy -- LED(1): timer 1 busy +-- LED(0): timer 0 busy -- -- DSP: SER_MONI.clkdiv (from auto bauder) -- DP(3): not SER_MONI.txok (shows tx back preasure) @@ -66,6 +71,7 @@ use work.rblib.all; use work.rlinklib.all; use work.bpgenlib.all; use work.bpgenrbuslib.all; +use work.sysmonrbuslib.all; use work.sys_conf.all; -- ---------------------------------------------------------------------------- @@ -90,8 +96,6 @@ architecture syn of sys_tst_rlink_b3 is signal RXD : slbit := '1'; signal TXD : slbit := '0'; - signal RTS_N : slbit := '0'; - signal CTS_N : slbit := '0'; signal SWI : slv16 := (others=>'0'); signal BTN : slv5 := (others=>'0'); @@ -105,8 +109,9 @@ architecture syn of sys_tst_rlink_b3 is signal RB_MREQ : rb_mreq_type := rb_mreq_init; signal RB_SRES : rb_sres_type := rb_sres_init; - signal RB_SRES_HIO : rb_sres_type := rb_sres_init; - signal RB_SRES_TST : rb_sres_type := rb_sres_init; + signal RB_SRES_HIO : rb_sres_type := rb_sres_init; + signal RB_SRES_TST : rb_sres_type := rb_sres_init; + signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init; signal RB_LAM : slv16 := (others=>'0'); signal RB_STAT : slv4 := (others=>'0'); @@ -114,7 +119,8 @@ architecture syn of sys_tst_rlink_b3 is signal SER_MONI : serport_moni_type := serport_moni_init; signal STAT : slv8 := (others=>'0'); - constant rbaddr_hio : slv16 := x"fef0"; -- fef0/4: 1111 1110 1111 00xx + constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx + constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx begin @@ -124,7 +130,7 @@ begin RESET <= '0'; -- so far not used - GEN_CLKSYS : s6_cmt_sfs + GEN_CLKSYS : s7_cmt_sfs generic map ( VCO_DIVIDE => sys_conf_clksys_vcodivide, VCO_MULTIPLY => sys_conf_clksys_vcomultiply, @@ -195,15 +201,15 @@ begin ENAPIN_RBMON => sbcntl_sbf_rbmon, CDWIDTH => 15, CDINIT => sys_conf_ser2rri_cdinit, - RBMON_AWIDTH => 0, - RBMON_RBADDR => x"ffe8") + RBMON_AWIDTH => 0, -- must be 0, rbmon in rbd_tst_rlink + RBMON_RBADDR => (others=>'0')) port map ( CLK => CLK, CE_USEC => CE_USEC, CE_MSEC => CE_MSEC, CE_INT => CE_MSEC, RESET => RESET, - ENAXON => SWI(1), + ENAXON => '1', ESCFILL => '0', RXSD => RXD, TXSD => TXD, @@ -232,10 +238,27 @@ begin STAT => STAT ); - RB_SRES_OR1 : rb_sres_or_2 + SMRB : if sys_conf_rbd_sysmon generate + I0: sysmonx_rbus_base + generic map ( -- use default INIT_ (Vccint=1.00) + CLK_MHZ => sys_conf_clksys_mhz, + RB_ADDR => rbaddr_sysmon) + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_SYSMON, + ALM => open, + OT => open, + TEMP => open + ); + end generate SMRB; + + RB_SRES_OR1 : rb_sres_or_3 port map ( RB_SRES_1 => RB_SRES_HIO, RB_SRES_2 => RB_SRES_TST, + RB_SRES_3 => RB_SRES_SYSMON, RB_SRES_OR => RB_SRES ); diff --git a/rtl/sys_gen/tst_rlink/basys3/tb/.cvsignore b/rtl/sys_gen/tst_rlink/basys3/tb/.cvsignore index 68d85658..3a5e91bc 100644 --- a/rtl/sys_gen/tst_rlink/basys3/tb/.cvsignore +++ b/rtl/sys_gen/tst_rlink/basys3/tb/.cvsignore @@ -1,6 +1,2 @@ tb_tst_rlink_b3 -tb_tst_rlink_b3_[so]sim -rlink_cext_fifo_rx -rlink_cext_fifo_tx -rlink_cext_conf -*.dep_* +sysmon_stim diff --git a/rtl/sys_gen/tst_rlink/basys3/tb/Makefile b/rtl/sys_gen/tst_rlink/basys3/tb/Makefile index ab01f372..20ad50e3 100644 --- a/rtl/sys_gen/tst_rlink/basys3/tb/Makefile +++ b/rtl/sys_gen/tst_rlink/basys3/tb/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 648 2015-02-20 20:16:21Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -6,7 +6,7 @@ # EXE_all = tb_tst_rlink_b3 # -include $(RETROBASE)/rtl/make_viv/viv_default_basys3.mk +include ${RETROBASE}/rtl/make_viv/viv_default_basys3.mk # .PHONY : all all_ssim clean # @@ -17,8 +17,8 @@ clean : viv_clean ghdl_clean # #----- # -include $(RETROBASE)/rtl/make_viv/generic_vivado.mk -include $(RETROBASE)/rtl/make_viv/generic_ghdl.mk +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk +include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/sys_gen/tst_rlink/basys3/tb/sys_conf_sim.vhd b/rtl/sys_gen/tst_rlink/basys3/tb/sys_conf_sim.vhd index 92362dc6..ec64eed0 100644 --- a/rtl/sys_gen/tst_rlink/basys3/tb/sys_conf_sim.vhd +++ b/rtl/sys_gen/tst_rlink/basys3/tb/sys_conf_sim.vhd @@ -1,6 +1,6 @@ --- $Id: sys_conf_sim.vhd 648 2015-02-20 20:16:21Z mueller $ +-- $Id: sys_conf_sim.vhd 743 2016-03-13 16:42:31Z mueller $ -- --- Copyright 2015- by Walter F.J. Mueller +-- Copyright 2015-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,9 +16,10 @@ -- Description: Definitions for sys_tst_rlink_b3 (for simulation) -- -- Dependencies: - --- Tool versions: viv 2014.4; ghdl 0.31 +-- Tool versions: viv 2014.4-2015.4; ghdl 0.31-0.33 -- Revision History: -- Date Rev Version Comment +-- 2016-03-12 741 1.1 add sysmon_rbus -- 2015-02-18 648 1.0 Initial version ------------------------------------------------------------------------------ @@ -29,6 +30,7 @@ use work.slvtypes.all; package sys_conf is + -- configure clocks -------------------------------------------------------- constant sys_conf_clksys_vcodivide : positive := 1; constant sys_conf_clksys_vcomultiply : positive := 1; -- vco --- MHz constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz @@ -39,11 +41,14 @@ package sys_conf is constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide; constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype; + -- configure rlink and hio interfaces -------------------------------------- constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim - constant sys_conf_hio_debounce : boolean := false; -- no debouncers - -- derived constants + -- configure further units ------------------------------------------------- + constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC) + + -- derived constants ======================================================= constant sys_conf_clksys : integer := ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / diff --git a/rtl/sys_gen/tst_rlink/basys3/tb/tbw.dat b/rtl/sys_gen/tst_rlink/basys3/tb/tbw.dat index bb2e936b..146779b1 100644 --- a/rtl/sys_gen/tst_rlink/basys3/tb/tbw.dat +++ b/rtl/sys_gen/tst_rlink/basys3/tb/tbw.dat @@ -1,6 +1,7 @@ -# $Id: tbw.dat 648 2015-02-20 20:16:21Z mueller $ +# $Id: tbw.dat 741 2016-03-12 23:49:03Z mueller $ # [tb_tst_rlink_b3] rlink_cext_fifo_rx = rlink_cext_fifo_tx = rlink_cext_conf = +sysmon_stim = ../../../../bplib/sysmon/tb/sysmon_stim_n4.dat diff --git a/rtl/sys_gen/tst_rlink/nexys2/.cvsignore b/rtl/sys_gen/tst_rlink/nexys2/.cvsignore index 484b4545..11ea64d5 100644 --- a/rtl/sys_gen/tst_rlink/nexys2/.cvsignore +++ b/rtl/sys_gen/tst_rlink/nexys2/.cvsignore @@ -1,4 +1 @@ -_impactbatch.log sys_tst_rlink_n2.ucf -*.dep_ucf_cpp -*.svf diff --git a/rtl/sys_gen/tst_rlink/nexys2/Makefile b/rtl/sys_gen/tst_rlink/nexys2/Makefile index 94ca8134..f5b66427 100644 --- a/rtl/sys_gen/tst_rlink/nexys2/Makefile +++ b/rtl/sys_gen/tst_rlink/nexys2/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -8,7 +8,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make_ise/xflow_default_nexys2.mk +include ${RETROBASE}/rtl/make_ise/xflow_default_nexys2.mk # .PHONY : all clean # @@ -19,8 +19,8 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_rlink/nexys2/sys_conf.vhd b/rtl/sys_gen/tst_rlink/nexys2/sys_conf.vhd index 398190dd..fd90c9ac 100644 --- a/rtl/sys_gen/tst_rlink/nexys2/sys_conf.vhd +++ b/rtl/sys_gen/tst_rlink/nexys2/sys_conf.vhd @@ -1,6 +1,6 @@ --- $Id: sys_conf.vhd 649 2015-02-21 21:10:16Z mueller $ +-- $Id: sys_conf.vhd 743 2016-03-13 16:42:31Z mueller $ -- --- Copyright 2010- by Walter F.J. Mueller +-- Copyright 2010-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,7 +16,7 @@ -- Description: Definitions for sys_tst_rlink_n2 (for synthesis) -- -- Dependencies: - --- Tool versions: xst 12.1-14.7; ghdl 0.29-0.31 +-- Tool versions: xst 12.1-14.7; ghdl 0.29-0.33 -- Revision History: -- Date Rev Version Comment -- 2010-12-29 351 1.0 Initial version @@ -29,14 +29,15 @@ use work.slvtypes.all; package sys_conf is + -- configure clocks -------------------------------------------------------- constant sys_conf_clkfx_divide : positive := 1; constant sys_conf_clkfx_multiply : positive := 1; -- + -- configure rlink and hio interfaces -------------------------------------- constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud - constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers - -- derived constants + -- derived constants ======================================================= constant sys_conf_clksys : integer := (50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply; diff --git a/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vbom b/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vbom index 7c7f7502..3e1506e3 100644 --- a/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vbom +++ b/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vbom @@ -10,8 +10,8 @@ ../../../bplib/nxcramlib/nxcramlib.vhd ${sys_conf := sys_conf.vhd} # components -[xst,vsyn,isim,vsim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom -[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom +[xst,vsyn]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom +[ghdl,isim,vsim]../../../vlib/xlib/dcm_sfs_gsim.vbom ../../../vlib/genlib/clkdivce.vbom ../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom ../../../bplib/bpgen/sn_humanio_rbus.vbom diff --git a/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd b/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd index f758791e..4ac65eb9 100644 --- a/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd +++ b/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd @@ -1,6 +1,6 @@ --- $Id: sys_tst_rlink_n2.vhd 672 2015-05-02 21:58:28Z mueller $ +-- $Id: sys_tst_rlink_n2.vhd 743 2016-03-13 16:42:31Z mueller $ -- --- Copyright 2010-2015 by Walter F.J. Mueller +-- Copyright 2010-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -27,10 +27,11 @@ -- Test bench: tb/tb_tst_rlink_n2 -- -- Target Devices: generic --- Tool versions: xst 12.1-14.7; ghdl 0.29-0.31 +-- Tool versions: xst 12.1-14.7; ghdl 0.29-0.33 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri +-- 2016-03-06 743 14.7 131013 xc3s1200e-4 933 2007 128 1348 -- 2014-12-20 614 14.7 131013 xc3s1200e-4 914 1951 128 1321 t 15.7 -- 2012-12-27 453 13.3 O76d xc3s1200e-4 754 1605 96 1057 t 14.5 -- 2011-12-18 440 13.1 O40d xc3s1200e-4 754 1605 96 1057 t 16.8 @@ -62,8 +63,8 @@ -- -- LED(7) SER_MONI.abact -- (6:2) no function (only connected to sn_humanio_rbus) --- (0) timer 0 busy -- (1) timer 1 busy +-- (0) timer 0 busy -- -- DSP: SER_MONI.clkdiv (from auto bauder) -- DP(3) not SER_MONI.txok (shows tx back preasure) @@ -147,7 +148,7 @@ architecture syn of sys_tst_rlink_n2 is signal SER_MONI : serport_moni_type := serport_moni_init; signal STAT : slv8 := (others=>'0'); - constant rbaddr_hio : slv16 := x"fef0"; -- fef0/4: 1111 1110 1111 00xx + constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx begin @@ -229,8 +230,8 @@ begin ENAPIN_RBMON => sbcntl_sbf_rbmon, CDWIDTH => 15, CDINIT => sys_conf_ser2rri_cdinit, - RBMON_AWIDTH => 0, - RBMON_RBADDR => x"ffe8") + RBMON_AWIDTH => 0, -- must be 0, rbmon in rbd_tst_rlink + RBMON_RBADDR => (others=>'0')) port map ( CLK => CLK, CE_USEC => CE_USEC, diff --git a/rtl/sys_gen/tst_rlink/nexys2/tb/.cvsignore b/rtl/sys_gen/tst_rlink/nexys2/tb/.cvsignore index af2c07f0..a5315705 100644 --- a/rtl/sys_gen/tst_rlink/nexys2/tb/.cvsignore +++ b/rtl/sys_gen/tst_rlink/nexys2/tb/.cvsignore @@ -1,7 +1,2 @@ tb_tst_rlink_n2 -tb_tst_rlink_n2_[sft]sim -rlink_cext_fifo_rx -rlink_cext_fifo_tx -rlink_cext_conf sys_tst_rlink_n2.ucf -*.dep_ucf_cpp diff --git a/rtl/sys_gen/tst_rlink/nexys2/tb/Makefile b/rtl/sys_gen/tst_rlink/nexys2/tb/Makefile index ea4f8ba3..cbd029ba 100644 --- a/rtl/sys_gen/tst_rlink/nexys2/tb/Makefile +++ b/rtl/sys_gen/tst_rlink/nexys2/tb/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -7,7 +7,7 @@ # EXE_all = tb_tst_rlink_n2 # -include $(RETROBASE)/rtl/make_ise/xflow_default_nexys2.mk +include ${RETROBASE}/rtl/make_ise/xflow_default_nexys2.mk # .PHONY : all all_ssim all_tsim clean # @@ -20,8 +20,8 @@ clean : ise_clean ghdl_clean # #----- # -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/sys_gen/tst_rlink/nexys2/tb/sys_conf_sim.vhd b/rtl/sys_gen/tst_rlink/nexys2/tb/sys_conf_sim.vhd index ea7a4d67..bef9f566 100644 --- a/rtl/sys_gen/tst_rlink/nexys2/tb/sys_conf_sim.vhd +++ b/rtl/sys_gen/tst_rlink/nexys2/tb/sys_conf_sim.vhd @@ -1,6 +1,6 @@ --- $Id: sys_conf_sim.vhd 649 2015-02-21 21:10:16Z mueller $ +-- $Id: sys_conf_sim.vhd 743 2016-03-13 16:42:31Z mueller $ -- --- Copyright 2010- by Walter F.J. Mueller +-- Copyright 2010-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,7 +16,7 @@ -- Description: Definitions for sys_tst_rlink_n2 (for simulation) -- -- Dependencies: - --- Tool versions: xst 12.1-14.7; ghdl 0.29-0.31 +-- Tool versions: xst 12.1-14.7; ghdl 0.29-0.33 -- Revision History: -- Date Rev Version Comment -- 2010-12-29 351 1.0 Initial version @@ -29,14 +29,15 @@ use work.slvtypes.all; package sys_conf is + -- configure clocks -------------------------------------------------------- constant sys_conf_clkfx_divide : positive := 1; constant sys_conf_clkfx_multiply : positive := 1; + -- configure rlink and hio interfaces -------------------------------------- constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim - constant sys_conf_hio_debounce : boolean := false; -- no debouncers - -- derived constants + -- derived constants ======================================================= constant sys_conf_clksys : integer := (50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply; diff --git a/rtl/sys_gen/tst_rlink/nexys3/.cvsignore b/rtl/sys_gen/tst_rlink/nexys3/.cvsignore index 563446fc..76ab4dc9 100644 --- a/rtl/sys_gen/tst_rlink/nexys3/.cvsignore +++ b/rtl/sys_gen/tst_rlink/nexys3/.cvsignore @@ -1,4 +1 @@ -_impactbatch.log sys_tst_rlink_n3.ucf -*.dep_ucf_cpp -*.svf diff --git a/rtl/sys_gen/tst_rlink/nexys3/Makefile b/rtl/sys_gen/tst_rlink/nexys3/Makefile index dc768ad8..5e4e9a71 100644 --- a/rtl/sys_gen/tst_rlink/nexys3/Makefile +++ b/rtl/sys_gen/tst_rlink/nexys3/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -7,7 +7,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make_ise/xflow_default_nexys3.mk +include ${RETROBASE}/rtl/make_ise/xflow_default_nexys3.mk # .PHONY : all clean # @@ -18,8 +18,8 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_rlink/nexys3/sys_conf.vhd b/rtl/sys_gen/tst_rlink/nexys3/sys_conf.vhd index 909fae62..671c45f3 100644 --- a/rtl/sys_gen/tst_rlink/nexys3/sys_conf.vhd +++ b/rtl/sys_gen/tst_rlink/nexys3/sys_conf.vhd @@ -1,6 +1,6 @@ --- $Id: sys_conf.vhd 649 2015-02-21 21:10:16Z mueller $ +-- $Id: sys_conf.vhd 743 2016-03-13 16:42:31Z mueller $ -- --- Copyright 2011-2013 by Walter F.J. Mueller +-- Copyright 2011-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -30,16 +30,17 @@ use work.slvtypes.all; package sys_conf is + -- configure clocks -------------------------------------------------------- constant sys_conf_clksys_vcodivide : positive := 1; constant sys_conf_clksys_vcomultiply : positive := 1; -- dcm 100 MHz constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz constant sys_conf_clksys_gentype : string := "DCM"; + -- configure rlink and hio interfaces -------------------------------------- constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud - constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers - -- derived constants + -- derived constants ======================================================= constant sys_conf_clksys : integer := ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / diff --git a/rtl/sys_gen/tst_rlink/nexys3/sys_tst_rlink_n3.vbom b/rtl/sys_gen/tst_rlink/nexys3/sys_tst_rlink_n3.vbom index 06674d1d..2212a889 100644 --- a/rtl/sys_gen/tst_rlink/nexys3/sys_tst_rlink_n3.vbom +++ b/rtl/sys_gen/tst_rlink/nexys3/sys_tst_rlink_n3.vbom @@ -10,8 +10,8 @@ ../../../bplib/nxcramlib/nxcramlib.vhd ${sys_conf := sys_conf.vhd} # components -[xst,vsyn,isim,vsim]../../../vlib/xlib/s6_cmt_sfs_unisim.vbom -[ghdl]../../../vlib/xlib/s6_cmt_sfs_gsim.vbom +[xst,vsyn]../../../vlib/xlib/s6_cmt_sfs_unisim.vbom +[ghdl,isim,vsim]../../../vlib/xlib/s6_cmt_sfs_gsim.vbom ../../../vlib/genlib/clkdivce.vbom ../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom ../../../bplib/bpgen/sn_humanio_rbus.vbom diff --git a/rtl/sys_gen/tst_rlink/nexys3/sys_tst_rlink_n3.vhd b/rtl/sys_gen/tst_rlink/nexys3/sys_tst_rlink_n3.vhd index 23100b77..19dec502 100644 --- a/rtl/sys_gen/tst_rlink/nexys3/sys_tst_rlink_n3.vhd +++ b/rtl/sys_gen/tst_rlink/nexys3/sys_tst_rlink_n3.vhd @@ -1,6 +1,6 @@ --- $Id: sys_tst_rlink_n3.vhd 672 2015-05-02 21:58:28Z mueller $ +-- $Id: sys_tst_rlink_n3.vhd 743 2016-03-13 16:42:31Z mueller $ -- --- Copyright 2011-2015 by Walter F.J. Mueller +-- Copyright 2011-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -27,11 +27,12 @@ -- Test bench: tb/tb_tst_rlink_n3 -- -- Target Devices: generic --- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 +-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.33 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri --- 2014-12-20 614 13.1 131013 xc6slx16-2 917 1379 64 513 t 8.9 +-- 2016-03-13 743 14.7 131013 xc6slx16-2 950 1380 70 504 +-- 2014-12-20 614 14.7 131013 xc6slx16-2 917 1379 64 513 t 8.9 -- 2011-12-18 440 13.1 O40d xc6slx16-2 752 1258 48 439 t 7.9 -- 2011-11-26 433 13.1 O40d xc6slx16-2 722 1199 36 423 t 9.7 -- @@ -54,8 +55,8 @@ -- -- LED(7): SER_MONI.abact -- LED(6:2): no function (only connected to sn_humanio_rbus) --- LED(0): timer 0 busy -- LED(1): timer 1 busy +-- LED(0): timer 0 busy -- -- DSP: SER_MONI.clkdiv (from auto bauder) -- DP(3): not SER_MONI.txok (shows tx back preasure) @@ -140,7 +141,7 @@ architecture syn of sys_tst_rlink_n3 is signal SER_MONI : serport_moni_type := serport_moni_init; signal STAT : slv8 := (others=>'0'); - constant rbaddr_hio : slv16 := x"fef0"; -- fef0/4: 1111 1110 1111 00xx + constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx begin @@ -227,8 +228,8 @@ begin ENAPIN_RBMON => sbcntl_sbf_rbmon, CDWIDTH => 15, CDINIT => sys_conf_ser2rri_cdinit, - RBMON_AWIDTH => 0, - RBMON_RBADDR => x"ffe8") + RBMON_AWIDTH => 0, -- must be 0, rbmon in rbd_tst_rlink + RBMON_RBADDR => (others=>'0')) port map ( CLK => CLK, CE_USEC => CE_USEC, diff --git a/rtl/sys_gen/tst_rlink/nexys3/tb/.cvsignore b/rtl/sys_gen/tst_rlink/nexys3/tb/.cvsignore index ca4bcbfe..befc321f 100644 --- a/rtl/sys_gen/tst_rlink/nexys3/tb/.cvsignore +++ b/rtl/sys_gen/tst_rlink/nexys3/tb/.cvsignore @@ -1,7 +1,2 @@ tb_tst_rlink_n3 -tb_tst_rlink_n3_[sft]sim -rlink_cext_fifo_rx -rlink_cext_fifo_tx -rlink_cext_conf sys_tst_rlink_n3.ucf -*.dep_ucf_cpp diff --git a/rtl/sys_gen/tst_rlink/nexys3/tb/Makefile b/rtl/sys_gen/tst_rlink/nexys3/tb/Makefile index 2ac11ecc..c2b57005 100644 --- a/rtl/sys_gen/tst_rlink/nexys3/tb/Makefile +++ b/rtl/sys_gen/tst_rlink/nexys3/tb/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -6,7 +6,7 @@ # EXE_all = tb_tst_rlink_n3 # -include $(RETROBASE)/rtl/make_ise/xflow_default_nexys3.mk +include ${RETROBASE}/rtl/make_ise/xflow_default_nexys3.mk # .PHONY : all all_ssim all_tsim clean # @@ -19,8 +19,8 @@ clean : ise_clean ghdl_clean # #----- # -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/sys_gen/tst_rlink/nexys3/tb/sys_conf_sim.vhd b/rtl/sys_gen/tst_rlink/nexys3/tb/sys_conf_sim.vhd index 7fc35a1b..2a238c66 100644 --- a/rtl/sys_gen/tst_rlink/nexys3/tb/sys_conf_sim.vhd +++ b/rtl/sys_gen/tst_rlink/nexys3/tb/sys_conf_sim.vhd @@ -1,6 +1,6 @@ --- $Id: sys_conf_sim.vhd 649 2015-02-21 21:10:16Z mueller $ +-- $Id: sys_conf_sim.vhd 743 2016-03-13 16:42:31Z mueller $ -- --- Copyright 2011-2013 by Walter F.J. Mueller +-- Copyright 2011-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,7 +16,7 @@ -- Description: Definitions for sys_tst_rlink_n3 (for simulation) -- -- Dependencies: - --- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 +-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.33 -- Revision History: -- Date Rev Version Comment -- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect @@ -30,16 +30,17 @@ use work.slvtypes.all; package sys_conf is + -- configure clocks -------------------------------------------------------- constant sys_conf_clksys_vcodivide : positive := 1; constant sys_conf_clksys_vcomultiply : positive := 1; -- dcm 100 MHz constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz constant sys_conf_clksys_gentype : string := "DCM"; + -- configure rlink and hio interfaces -------------------------------------- constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim - constant sys_conf_hio_debounce : boolean := false; -- no debouncers - -- derived constants + -- derived constants ======================================================= constant sys_conf_clksys : integer := ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / diff --git a/rtl/sys_gen/tst_rlink/nexys4/.cvsignore b/rtl/sys_gen/tst_rlink/nexys4/.cvsignore index 9a32754a..3a9a0cce 100644 --- a/rtl/sys_gen/tst_rlink/nexys4/.cvsignore +++ b/rtl/sys_gen/tst_rlink/nexys4/.cvsignore @@ -1,11 +1 @@ -_impactbatch.log sys_tst_rlink_n4.ucf -*.dep_ucf_cpp -*.svf -.Xil -project_mflow -*.jou -*.log -*.rpt -*.dcp -*.dep_* diff --git a/rtl/sys_gen/tst_rlink/nexys4/Makefile b/rtl/sys_gen/tst_rlink/nexys4/Makefile index c2b6b663..31f766a3 100644 --- a/rtl/sys_gen/tst_rlink/nexys4/Makefile +++ b/rtl/sys_gen/tst_rlink/nexys4/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 646 2015-02-15 12:04:55Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -7,7 +7,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make_viv/viv_default_nexys4.mk +include ${RETROBASE}/rtl/make_viv/viv_default_nexys4.mk # .PHONY : all clean # @@ -17,7 +17,7 @@ clean : viv_clean # #---- # -include $(RETROBASE)/rtl/make_viv/generic_vivado.mk +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_vsyn) diff --git a/rtl/sys_gen/tst_rlink/nexys4/Makefile.ise b/rtl/sys_gen/tst_rlink/nexys4/Makefile.ise index 5d849476..652d526e 100644 --- a/rtl/sys_gen/tst_rlink/nexys4/Makefile.ise +++ b/rtl/sys_gen/tst_rlink/nexys4/Makefile.ise @@ -1,5 +1,5 @@ # -*- makefile-gmake -*- -# $Id: Makefile.ise 646 2015-02-15 12:04:55Z mueller $ +# $Id: Makefile.ise 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -8,7 +8,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make_ise/xflow_default_nexys4.mk +include ${RETROBASE}/rtl/make_ise/xflow_default_nexys4.mk # .PHONY : all clean # @@ -19,8 +19,8 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_rlink/nexys4/sys_conf.vhd b/rtl/sys_gen/tst_rlink/nexys4/sys_conf.vhd index 16bd9fbb..90a40b07 100644 --- a/rtl/sys_gen/tst_rlink/nexys4/sys_conf.vhd +++ b/rtl/sys_gen/tst_rlink/nexys4/sys_conf.vhd @@ -1,6 +1,6 @@ --- $Id: sys_conf.vhd 640 2015-02-01 09:56:53Z mueller $ +-- $Id: sys_conf.vhd 743 2016-03-13 16:42:31Z mueller $ -- --- Copyright 2013- by Walter F.J. Mueller +-- Copyright 2013-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,9 +16,10 @@ -- Description: Definitions for sys_tst_rlink_n4 (for synthesis) -- -- Dependencies: - --- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31 +-- Tool versions: ise 14.5-14.7; viv 2014.42015.4; ghdl 0.29-0.33 -- Revision History: -- Date Rev Version Comment +-- 2016-03-12 741 1.1 add sysmon_rbus -- 2013-09-28 535 1.0 Initial version ------------------------------------------------------------------------------ @@ -29,6 +30,7 @@ use work.slvtypes.all; package sys_conf is + -- configure clocks -------------------------------------------------------- constant sys_conf_clksys_vcodivide : positive := 1; constant sys_conf_clksys_vcomultiply : positive := 12; -- vco 1200 MHz constant sys_conf_clksys_outdivide : positive := 10; -- sys 120 MHz @@ -39,11 +41,14 @@ package sys_conf is constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide; constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype; + -- configure rlink and hio interfaces -------------------------------------- constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud - constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers - -- derived constants + -- configure further units ------------------------------------------------- + constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC) + + -- derived constants ======================================================= constant sys_conf_clksys : integer := ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / diff --git a/rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vbom b/rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vbom index 26773c66..b2df0549 100644 --- a/rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vbom +++ b/rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vbom @@ -7,16 +7,21 @@ ../../../vlib/rlink/rlinklib.vbom ../../../bplib/bpgen/bpgenlib.vbom ../../../bplib/bpgen/bpgenrbuslib.vbom +../../../bplib/sysmon/sysmonrbuslib.vbom ${sys_conf := sys_conf.vhd} # components -[xst,vsyn,isim,vsim]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom -[ghdl]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom +[xst,vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom +[ghdl,isim,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom ../../../vlib/genlib/clkdivce.vbom ../../../bplib/bpgen/bp_rs232_4line_iob.vbom ../../../bplib/bpgen/sn_humanio_rbus.vbom ../../../vlib/rlink/rlink_sp1c.vbom ../rbd_tst_rlink.vbom +../../../bplib/bpgen/rgbdrv_master.vbom +../../../bplib/bpgen/rgbdrv_analog_rbus.vbom +../../../bplib/sysmon/sysmonx_rbus_base.vbom ../../../vlib/rbus/rb_sres_or_2.vbom +../../../vlib/rbus/rb_sres_or_4.vbom # design sys_tst_rlink_n4.vhd @ucf_cpp: sys_tst_rlink_n4.ucf diff --git a/rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vhd b/rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vhd index ea386283..6afac52e 100644 --- a/rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vhd +++ b/rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vhd @@ -1,6 +1,6 @@ --- $Id: sys_tst_rlink_n4.vhd 672 2015-05-02 21:58:28Z mueller $ +-- $Id: sys_tst_rlink_n4.vhd 743 2016-03-13 16:42:31Z mueller $ -- --- Copyright 2013-2015 by Walter F.J. Mueller +-- Copyright 2013-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -21,19 +21,27 @@ -- bplib/bpgen/sn_humanio_rbus -- vlib/rlink/rlink_sp1c -- rbd_tst_rlink +-- bplib/bpgen/rgbdrv_master +-- bplib/bpgen/rgbdrv_analog_rbus +-- bplib/sysmon/sysmonx_rbus_base -- vlib/rbus/rb_sres_or_2 +-- vlib/rbus/rb_sres_or_4 -- -- Test bench: tb/tb_tst_rlink_n4 -- -- Target Devices: generic --- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31 +-- Tool versions: ise 14.5-14.7; viv 2014.4-2015.4; ghdl 0.29-0.33 -- -- Synthesized: -- Date Rev viv Target flop lutl lutm bram slic --- 2015-01-31 640 2014.4 xc7a100t-1 990 1360 64 0 495 +-- 2016-03-13 743 2015.4 xc7a100t-1 1124 1463 64 4.5 567 +XADC +-- 2016-02-20 734 2015.4 xc7a100t-1 1080 1424 64 4.5 502 +RGB +-- 2015-01-31 640 2014.4 xc7a100t-1 990 1360 64 4.5 495 -- -- Revision History: -- Date Rev Version Comment +-- 2016-03-12 741 1.5 add sysmon_rbus +-- 2016-02-20 734 1.4.2 add rgbdrv_analog_rbus for two rgb leds -- 2015-04-11 666 1.4.1 rearrange XON handling -- 2015-02-06 643 1.4 factor out memory -- 2015-02-01 641 1.3.1 separate I_BTNRST_N; autobaud on msb of display @@ -50,8 +58,8 @@ -- -- LED(7): SER_MONI.abact -- LED(6:2): no function (only connected to sn_humanio_rbus) --- LED(0): timer 0 busy -- LED(1): timer 1 busy +-- LED(0): timer 0 busy -- -- DSP: SER_MONI.clkdiv (from auto bauder) -- DP(3): not SER_MONI.txok (shows tx back preasure) @@ -71,6 +79,7 @@ use work.rblib.all; use work.rlinklib.all; use work.bpgenlib.all; use work.bpgenrbuslib.all; +use work.sysmonrbuslib.all; use work.sys_conf.all; -- ---------------------------------------------------------------------------- @@ -115,8 +124,12 @@ architecture syn of sys_tst_rlink_n4 is signal RB_MREQ : rb_mreq_type := rb_mreq_init; signal RB_SRES : rb_sres_type := rb_sres_init; - signal RB_SRES_HIO : rb_sres_type := rb_sres_init; - signal RB_SRES_TST : rb_sres_type := rb_sres_init; + signal RB_SRES_HIO : rb_sres_type := rb_sres_init; + signal RB_SRES_TST : rb_sres_type := rb_sres_init; + signal RB_SRES_RGB0 : rb_sres_type := rb_sres_init; + signal RB_SRES_RGB1 : rb_sres_type := rb_sres_init; + signal RB_SRES_RGB : rb_sres_type := rb_sres_init; + signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init; signal RB_LAM : slv16 := (others=>'0'); signal RB_STAT : slv4 := (others=>'0'); @@ -124,7 +137,13 @@ architecture syn of sys_tst_rlink_n4 is signal SER_MONI : serport_moni_type := serport_moni_init; signal STAT : slv8 := (others=>'0'); - constant rbaddr_hio : slv16 := x"fef0"; -- fef0/4: 1111 1110 1111 0xxx + signal RGBCNTL : slv3 := (others=>'0'); + signal DIMCNTL : slv12 := (others=>'0'); + + constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx + constant rbaddr_rgb0 : slv16 := x"fc00"; -- fe00/0004: 1111 1100 0000 00xx + constant rbaddr_rgb1 : slv16 := x"fc04"; -- fe04/0004: 1111 1100 0000 01xx + constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx begin @@ -210,8 +229,8 @@ begin ENAPIN_RBMON => sbcntl_sbf_rbmon, CDWIDTH => 15, CDINIT => sys_conf_ser2rri_cdinit, - RBMON_AWIDTH => 0, - RBMON_RBADDR => x"ffe8") + RBMON_AWIDTH => 0, -- must be 0, rbmon in rbd_tst_rlink + RBMON_RBADDR => (others=>'0')) port map ( CLK => CLK, CE_USEC => CE_USEC, @@ -247,10 +266,75 @@ begin STAT => STAT ); - RB_SRES_OR1 : rb_sres_or_2 + RGBMSTR : rgbdrv_master + generic map ( + DWIDTH => DIMCNTL'length) + port map ( + CLK => CLK, + RESET => RESET, + CE_USEC => CE_USEC, + RGBCNTL => RGBCNTL, + DIMCNTL => DIMCNTL + ); + + RGB0 : rgbdrv_analog_rbus + generic map ( + DWIDTH => DIMCNTL'length, + RB_ADDR => rbaddr_rgb0) + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_RGB0, + RGBCNTL => RGBCNTL, + DIMCNTL => DIMCNTL, + O_RGBLED => O_RGBLED0 + ); + + RGB1 : rgbdrv_analog_rbus + generic map ( + DWIDTH => DIMCNTL'length, + RB_ADDR => rbaddr_rgb1) + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_RGB1, + RGBCNTL => RGBCNTL, + DIMCNTL => DIMCNTL, + O_RGBLED => O_RGBLED1 + ); + + + SMRB : if sys_conf_rbd_sysmon generate + I0: sysmonx_rbus_base + generic map ( -- use default INIT_ (Vccint=1.00) + CLK_MHZ => sys_conf_clksys_mhz, + RB_ADDR => rbaddr_sysmon) + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_SYSMON, + ALM => open, + OT => open, + TEMP => open + ); + end generate SMRB; + + RB_SRES_ORRGB : rb_sres_or_2 + port map ( + RB_SRES_1 => RB_SRES_RGB0, + RB_SRES_2 => RB_SRES_RGB1, + RB_SRES_OR => RB_SRES_RGB + ); + + RB_SRES_OR1 : rb_sres_or_4 port map ( RB_SRES_1 => RB_SRES_HIO, RB_SRES_2 => RB_SRES_TST, + RB_SRES_3 => RB_SRES_RGB, + RB_SRES_4 => RB_SRES_SYSMON, RB_SRES_OR => RB_SRES ); @@ -270,10 +354,6 @@ begin LED(7) <= SER_MONI.abact; LED(6 downto 2) <= (others=>'0'); LED(1) <= STAT(1); - LED(0) <= STAT(0); - - -- setup unused outputs in nexys4 - O_RGBLED0 <= (others=>'0'); - O_RGBLED1 <= (others=>not I_BTNRST_N); + LED(0) <= STAT(0); end syn; diff --git a/rtl/sys_gen/tst_rlink/nexys4/tb/.cvsignore b/rtl/sys_gen/tst_rlink/nexys4/tb/.cvsignore index 8912e778..facde239 100644 --- a/rtl/sys_gen/tst_rlink/nexys4/tb/.cvsignore +++ b/rtl/sys_gen/tst_rlink/nexys4/tb/.cvsignore @@ -1,8 +1,3 @@ tb_tst_rlink_n4 -tb_tst_rlink_n4_[sft]sim -rlink_cext_fifo_rx -rlink_cext_fifo_tx -rlink_cext_conf sys_tst_rlink_n4.ucf -*.dep_ucf_cpp -*.dep_* +sysmon_stim diff --git a/rtl/sys_gen/tst_rlink/nexys4/tb/Makefile b/rtl/sys_gen/tst_rlink/nexys4/tb/Makefile index c149294a..130aa9da 100644 --- a/rtl/sys_gen/tst_rlink/nexys4/tb/Makefile +++ b/rtl/sys_gen/tst_rlink/nexys4/tb/Makefile @@ -1,24 +1,32 @@ -# $Id: Makefile 648 2015-02-20 20:16:21Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment +# 2016-02-07 729 1.0.1 add generic_xsim.mk # 2015-02-18 648 1.0 Initial version # EXE_all = tb_tst_rlink_n4 # -include $(RETROBASE)/rtl/make_viv/viv_default_nexys4.mk +include ${RETROBASE}/rtl/make_viv/viv_default_nexys4.mk # .PHONY : all all_ssim clean # all : $(EXE_all) all_ssim : $(EXE_all:=_ssim) +all_osim : $(EXE_all:=_osim) +# +all_XSim : $(EXE_all:=_XSim) +all_XSim_ssim : $(EXE_all:=_XSim_ssim) +all_XSim_osim : $(EXE_all:=_XSim_osim) +all_XSim_tsim : $(EXE_all:=_XSim_tsim) # clean : viv_clean ghdl_clean # #----- # -include $(RETROBASE)/rtl/make_viv/generic_vivado.mk -include $(RETROBASE)/rtl/make_viv/generic_ghdl.mk +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk +include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk +include ${RETROBASE}/rtl/make_viv/generic_xsim.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/sys_gen/tst_rlink/nexys4/tb/Makefile.ise b/rtl/sys_gen/tst_rlink/nexys4/tb/Makefile.ise index 98ab374d..d683fc5b 100644 --- a/rtl/sys_gen/tst_rlink/nexys4/tb/Makefile.ise +++ b/rtl/sys_gen/tst_rlink/nexys4/tb/Makefile.ise @@ -1,5 +1,5 @@ # -*- makefile-gmake -*- -# $Id: Makefile.ise 646 2015-02-15 12:04:55Z mueller $ +# $Id: Makefile.ise 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -7,7 +7,7 @@ # EXE_all = tb_tst_rlink_n4 # -include $(RETROBASE)/rtl/make_ise/xflow_default_nexys4.mk +include ${RETROBASE}/rtl/make_ise/xflow_default_nexys4.mk # .PHONY : all all_ssim all_tsim clean # @@ -20,8 +20,8 @@ clean : ise_clean ghdl_clean # #----- # -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/sys_gen/tst_rlink/nexys4/tb/sys_conf_sim.vhd b/rtl/sys_gen/tst_rlink/nexys4/tb/sys_conf_sim.vhd index 9a9cdda1..41c52ff8 100644 --- a/rtl/sys_gen/tst_rlink/nexys4/tb/sys_conf_sim.vhd +++ b/rtl/sys_gen/tst_rlink/nexys4/tb/sys_conf_sim.vhd @@ -1,6 +1,6 @@ --- $Id: sys_conf_sim.vhd 648 2015-02-20 20:16:21Z mueller $ +-- $Id: sys_conf_sim.vhd 743 2016-03-13 16:42:31Z mueller $ -- --- Copyright 2013- by Walter F.J. Mueller +-- Copyright 2013-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,9 +16,10 @@ -- Description: Definitions for sys_tst_rlink_n4 (for simulation) -- -- Dependencies: - --- Tool versions: xst 14.5-14.7; viv 2014.4; ghdl 0.29-0.31 +-- Tool versions: xst 14.5-14.7; viv 2014.4-2015.4; ghdl 0.29-0.33 -- Revision History: -- Date Rev Version Comment +-- 2016-03-12 741 1.1 add sysmon_rbus -- 2013-09-28 535 1.0 Initial version ------------------------------------------------------------------------------ @@ -29,6 +30,7 @@ use work.slvtypes.all; package sys_conf is + -- configure clocks -------------------------------------------------------- constant sys_conf_clksys_vcodivide : positive := 1; constant sys_conf_clksys_vcomultiply : positive := 1; -- vco --- MHz constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz @@ -39,11 +41,14 @@ package sys_conf is constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide; constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype; + -- configure rlink and hio interfaces -------------------------------------- constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim - constant sys_conf_hio_debounce : boolean := false; -- no debouncers - -- derived constants + -- configure further units ------------------------------------------------- + constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC) + + -- derived constants ======================================================= constant sys_conf_clksys : integer := ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / diff --git a/rtl/sys_gen/tst_rlink/nexys4/tb/tbw.dat b/rtl/sys_gen/tst_rlink/nexys4/tb/tbw.dat index f91d9984..89b57c45 100644 --- a/rtl/sys_gen/tst_rlink/nexys4/tb/tbw.dat +++ b/rtl/sys_gen/tst_rlink/nexys4/tb/tbw.dat @@ -1,6 +1,7 @@ -# $Id: tbw.dat 535 2013-09-29 11:46:25Z mueller $ +# $Id: tbw.dat 741 2016-03-12 23:49:03Z mueller $ # [tb_tst_rlink_n4] rlink_cext_fifo_rx = rlink_cext_fifo_tx = rlink_cext_conf = +sysmon_stim = ../../../../bplib/sysmon/tb/sysmon_stim_n4.dat diff --git a/rtl/sys_gen/tst_rlink/s3board/.cvsignore b/rtl/sys_gen/tst_rlink/s3board/.cvsignore index bc7b0264..5233003a 100644 --- a/rtl/sys_gen/tst_rlink/s3board/.cvsignore +++ b/rtl/sys_gen/tst_rlink/s3board/.cvsignore @@ -1,4 +1 @@ -_impactbatch.log sys_tst_rlink_s3.ucf -*.dep_ucf_cpp -*.svf diff --git a/rtl/sys_gen/tst_rlink/s3board/Makefile b/rtl/sys_gen/tst_rlink/s3board/Makefile index c97d6392..d0ea75bf 100644 --- a/rtl/sys_gen/tst_rlink/s3board/Makefile +++ b/rtl/sys_gen/tst_rlink/s3board/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -7,7 +7,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make_ise/xflow_default_s3board.mk +include ${RETROBASE}/rtl/make_ise/xflow_default_s3board.mk # .PHONY : all clean # @@ -18,8 +18,8 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_rlink/s3board/sys_conf.vhd b/rtl/sys_gen/tst_rlink/s3board/sys_conf.vhd index 234e1c61..b53c33c6 100644 --- a/rtl/sys_gen/tst_rlink/s3board/sys_conf.vhd +++ b/rtl/sys_gen/tst_rlink/s3board/sys_conf.vhd @@ -1,6 +1,6 @@ --- $Id: sys_conf.vhd 649 2015-02-21 21:10:16Z mueller $ +-- $Id: sys_conf.vhd 743 2016-03-13 16:42:31Z mueller $ -- --- Copyright 2011- by Walter F.J. Mueller +-- Copyright 2011-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,7 +16,7 @@ -- Description: Definitions for sys_tst_rlink_s3 (for synthesis) -- -- Dependencies: - --- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 +-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.33 -- Revision History: -- Date Rev Version Comment -- 2011-12-22 442 1.0 Initial version @@ -29,11 +29,11 @@ use work.slvtypes.all; package sys_conf is + -- configure rlink and hio interfaces -------------------------------------- constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud - constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers - -- derived constants + -- derived constants ======================================================= constant sys_conf_clksys : integer := 50000000; constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; diff --git a/rtl/sys_gen/tst_rlink/s3board/sys_tst_rlink_s3.vhd b/rtl/sys_gen/tst_rlink/s3board/sys_tst_rlink_s3.vhd index 020daf2d..09a6d9d8 100644 --- a/rtl/sys_gen/tst_rlink/s3board/sys_tst_rlink_s3.vhd +++ b/rtl/sys_gen/tst_rlink/s3board/sys_tst_rlink_s3.vhd @@ -1,6 +1,6 @@ --- $Id: sys_tst_rlink_s3.vhd 672 2015-05-02 21:58:28Z mueller $ +-- $Id: sys_tst_rlink_s3.vhd 743 2016-03-13 16:42:31Z mueller $ -- --- Copyright 2011-2015 by Walter F.J. Mueller +-- Copyright 2011-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -26,10 +26,11 @@ -- Test bench: tb/tb_tst_rlink_s3 -- -- Target Devices: generic --- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 +-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.33 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri +-- 2016-03-12 743 14.7 131013 xc3s1000e-4 931 2078 128 1383 -- 2014-12-20 614 14.7 131013 xc3s1000e-4 916 1973 128 1316 t 15.9 -- 2011-12-22 442 13.1 O40d xc3s1000e-4 765 1672 96 1088 t 12.6 -- @@ -49,8 +50,8 @@ -- -- LED(7): SER_MONI.abact -- LED(6:2): no function (only connected to sn_humanio_rbus) --- LED(0): timer 0 busy -- LED(1): timer 1 busy +-- LED(0): timer 0 busy -- -- DSP: SER_MONI.clkdiv (from auto bauder) -- DP(3): not SER_MONI.txok (shows tx back preasure) @@ -128,7 +129,7 @@ architecture syn of sys_tst_rlink_s3 is signal SER_MONI : serport_moni_type := serport_moni_init; signal STAT : slv8 := (others=>'0'); - constant rbaddr_hio : slv16 := x"fef0"; -- fef0/4: 1111 1110 1111 00xx + constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx begin @@ -200,8 +201,8 @@ begin ENAPIN_RBMON => sbcntl_sbf_rbmon, CDWIDTH => 15, CDINIT => sys_conf_ser2rri_cdinit, - RBMON_AWIDTH => 0, - RBMON_RBADDR => x"ffe8") + RBMON_AWIDTH => 0, -- must be 0, rbmon in rbd_tst_rlink + RBMON_RBADDR => (others=>'0')) port map ( CLK => CLK, CE_USEC => CE_USEC, diff --git a/rtl/sys_gen/tst_rlink/s3board/tb/.cvsignore b/rtl/sys_gen/tst_rlink/s3board/tb/.cvsignore index e809654e..a65a1673 100644 --- a/rtl/sys_gen/tst_rlink/s3board/tb/.cvsignore +++ b/rtl/sys_gen/tst_rlink/s3board/tb/.cvsignore @@ -1,7 +1,2 @@ tb_tst_rlink_s3 -tb_tst_rlink_s3_[sft]sim -rlink_cext_fifo_rx -rlink_cext_fifo_tx -rlink_cext_conf sys_tst_rlink_s3.ucf -*.dep_ucf_cpp diff --git a/rtl/sys_gen/tst_rlink/s3board/tb/Makefile b/rtl/sys_gen/tst_rlink/s3board/tb/Makefile index 7b9d801f..6cf8a017 100644 --- a/rtl/sys_gen/tst_rlink/s3board/tb/Makefile +++ b/rtl/sys_gen/tst_rlink/s3board/tb/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -6,7 +6,7 @@ # EXE_all = tb_tst_rlink_s3 # -include $(RETROBASE)/rtl/make_ise/xflow_default_s3board.mk +include ${RETROBASE}/rtl/make_ise/xflow_default_s3board.mk # .PHONY : all all_ssim all_tsim clean # @@ -19,8 +19,8 @@ clean : ise_clean ghdl_clean # #----- # -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/sys_gen/tst_rlink/s3board/tb/sys_conf_sim.vhd b/rtl/sys_gen/tst_rlink/s3board/tb/sys_conf_sim.vhd index 64c18cf7..87204a76 100644 --- a/rtl/sys_gen/tst_rlink/s3board/tb/sys_conf_sim.vhd +++ b/rtl/sys_gen/tst_rlink/s3board/tb/sys_conf_sim.vhd @@ -1,6 +1,6 @@ --- $Id: sys_conf_sim.vhd 649 2015-02-21 21:10:16Z mueller $ +-- $Id: sys_conf_sim.vhd 743 2016-03-13 16:42:31Z mueller $ -- --- Copyright 2011- by Walter F.J. Mueller +-- Copyright 2011-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,7 +16,7 @@ -- Description: Definitions for sys_tst_rlink_s3 (for simulation) -- -- Dependencies: - --- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 +-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.33 -- Revision History: -- Date Rev Version Comment -- 2011-12-22 442 1.0 Initial version @@ -29,11 +29,11 @@ use work.slvtypes.all; package sys_conf is + -- configure rlink and hio interfaces -------------------------------------- constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim - constant sys_conf_hio_debounce : boolean := false; -- no debouncers - -- derived constants + -- derived constants ======================================================= constant sys_conf_clksys : integer := 50000000; constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; diff --git a/rtl/sys_gen/tst_rlink_cuff/Makefile b/rtl/sys_gen/tst_rlink_cuff/Makefile index a769a652..1580d1e9 100644 --- a/rtl/sys_gen/tst_rlink_cuff/Makefile +++ b/rtl/sys_gen/tst_rlink_cuff/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -7,7 +7,7 @@ VBOM_all = $(wildcard *.vbom) NGC_all = $(VBOM_all:.vbom=.ngc) # -include $(RETROBASE)/rtl/make_ise/xflow_default_nexys2.mk +include ${RETROBASE}/rtl/make_ise/xflow_default_nexys2.mk # .PHONY : all clean # @@ -18,7 +18,7 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_rlink_cuff/atlys/ic/.cvsignore b/rtl/sys_gen/tst_rlink_cuff/atlys/ic/.cvsignore index 0b95d230..8fc6e05c 100644 --- a/rtl/sys_gen/tst_rlink_cuff/atlys/ic/.cvsignore +++ b/rtl/sys_gen/tst_rlink_cuff/atlys/ic/.cvsignore @@ -1,4 +1 @@ -_impactbatch.log sys_tst_rlink_cuff_ic_atlys.ucf -*.dep_ucf_cpp -*.svf diff --git a/rtl/sys_gen/tst_rlink_cuff/atlys/ic/Makefile b/rtl/sys_gen/tst_rlink_cuff/atlys/ic/Makefile index e1235342..681582af 100644 --- a/rtl/sys_gen/tst_rlink_cuff/atlys/ic/Makefile +++ b/rtl/sys_gen/tst_rlink_cuff/atlys/ic/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -8,7 +8,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make_ise/xflow_default_atlys.mk +include ${RETROBASE}/rtl/make_ise/xflow_default_atlys.mk FX2_FILE = nexys3_jtag_2fifo_ic.ihx # .PHONY : all clean @@ -20,8 +20,8 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_rlink_cuff/atlys/sys_tst_rlink_cuff_atlys.vbom b/rtl/sys_gen/tst_rlink_cuff/atlys/sys_tst_rlink_cuff_atlys.vbom index dd3d7625..e0caadb7 100644 --- a/rtl/sys_gen/tst_rlink_cuff/atlys/sys_tst_rlink_cuff_atlys.vbom +++ b/rtl/sys_gen/tst_rlink_cuff/atlys/sys_tst_rlink_cuff_atlys.vbom @@ -13,8 +13,8 @@ ../../../bplib/fx2lib/fx2lib.vhd ${sys_conf} # components -[xst,vsyn,isim,vsim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom -[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom +[xst,vsyn]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom +[ghdl,isim,vsim]../../../vlib/xlib/dcm_sfs_gsim.vbom ../../../vlib/genlib/clkdivce.vbom ../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom ../../../bplib/bpgen/sn_humanio_demu_rbus.vbom diff --git a/rtl/sys_gen/tst_rlink_cuff/atlys/sys_tst_rlink_cuff_atlys.vhd b/rtl/sys_gen/tst_rlink_cuff/atlys/sys_tst_rlink_cuff_atlys.vhd index 711865aa..f1b45f93 100644 --- a/rtl/sys_gen/tst_rlink_cuff/atlys/sys_tst_rlink_cuff_atlys.vhd +++ b/rtl/sys_gen/tst_rlink_cuff/atlys/sys_tst_rlink_cuff_atlys.vhd @@ -1,4 +1,4 @@ --- $Id: sys_tst_rlink_cuff_atlys.vhd 638 2015-01-25 22:01:38Z mueller $ +-- $Id: sys_tst_rlink_cuff_atlys.vhd 734 2016-02-20 22:43:20Z mueller $ -- -- Copyright 2013-2015 by Walter F.J. Mueller -- @@ -51,8 +51,8 @@ -- -- LED(7) SER_MONI.abact -- (6:2) no function (only connected to sn_humanio_demu_rbus) --- (0) timer 0 busy -- (1) timer 1 busy +-- (0) timer 0 busy -- -- DSP: SER_MONI.clkdiv (from auto bauder) -- for SWI(2)='0' (serport) @@ -142,7 +142,7 @@ architecture syn of sys_tst_rlink_cuff_atlys is signal FX2_TX2AFULL : slbit := '0'; signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init; - constant rbaddr_hio : slv16 := x"fef0"; -- fef0/4: 1111 1110 1111 00xx + constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx begin diff --git a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/.cvsignore b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/.cvsignore index 51c87eba..11608ab0 100644 --- a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/.cvsignore +++ b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/.cvsignore @@ -1,4 +1 @@ -_impactbatch.log sys_tst_rlink_cuff_ic_n2.ucf -*.dep_ucf_cpp -*.svf diff --git a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/Makefile b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/Makefile index 71130bca..619425f6 100644 --- a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/Makefile +++ b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -8,7 +8,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make_ise/xflow_default_nexys2.mk +include ${RETROBASE}/rtl/make_ise/xflow_default_nexys2.mk FX2_FILE = nexys2_jtag_2fifo_ic.ihx # .PHONY : all clean @@ -20,8 +20,8 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/.cvsignore b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/.cvsignore index bb211711..dd63195b 100644 --- a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/.cvsignore +++ b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/.cvsignore @@ -1,6 +1 @@ tb_tst_rlink_cuff_ic_n2 -tb_tst_rlink_cuff_ic_n2_[sft]sim -rlink_cext_fifo_rx -rlink_cext_fifo_tx -rlink_cext_conf -*.dep_ucf_cpp diff --git a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/Makefile b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/Makefile index 5c56d3ea..9b0086ba 100644 --- a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/Makefile +++ b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -6,7 +6,7 @@ # EXE_all = tb_tst_rlink_cuff_ic_n2 # -include $(RETROBASE)/rtl/make_ise/xflow_default_nexys2.mk +include ${RETROBASE}/rtl/make_ise/xflow_default_nexys2.mk # .PHONY : all all_ssim all_tsim clean # @@ -19,8 +19,8 @@ clean : ise_clean ghdl_clean # #----- # -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/.cvsignore b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/.cvsignore index 114283c4..b988e8c2 100644 --- a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/.cvsignore +++ b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/.cvsignore @@ -1,4 +1 @@ -_impactbatch.log sys_tst_rlink_cuff_ic3_n2.ucf -*.dep_ucf_cpp -*.svf diff --git a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/Makefile b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/Makefile index 986e6338..3e0833f5 100644 --- a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/Makefile +++ b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -8,7 +8,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make_ise/xflow_default_nexys2.mk +include ${RETROBASE}/rtl/make_ise/xflow_default_nexys2.mk FX2_FILE = nexys2_jtag_3fifo_ic.ihx # .PHONY : all clean @@ -20,8 +20,8 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_rlink_cuff/nexys2/sys_tst_rlink_cuff_n2.vbom b/rtl/sys_gen/tst_rlink_cuff/nexys2/sys_tst_rlink_cuff_n2.vbom index 34daca9d..52844056 100644 --- a/rtl/sys_gen/tst_rlink_cuff/nexys2/sys_tst_rlink_cuff_n2.vbom +++ b/rtl/sys_gen/tst_rlink_cuff/nexys2/sys_tst_rlink_cuff_n2.vbom @@ -14,8 +14,8 @@ ../../../bplib/nxcramlib/nxcramlib.vhd ${sys_conf} # components -[xst,vsyn,isim,vsim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom -[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom +[xst,vsyn]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom +[ghdl,isim,vsim]../../../vlib/xlib/dcm_sfs_gsim.vbom ../../../vlib/genlib/clkdivce.vbom ../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom ../../../bplib/bpgen/sn_humanio_rbus.vbom diff --git a/rtl/sys_gen/tst_rlink_cuff/nexys2/sys_tst_rlink_cuff_n2.vhd b/rtl/sys_gen/tst_rlink_cuff/nexys2/sys_tst_rlink_cuff_n2.vhd index f033ab32..dbd5d403 100644 --- a/rtl/sys_gen/tst_rlink_cuff/nexys2/sys_tst_rlink_cuff_n2.vhd +++ b/rtl/sys_gen/tst_rlink_cuff/nexys2/sys_tst_rlink_cuff_n2.vhd @@ -1,4 +1,4 @@ --- $Id: sys_tst_rlink_cuff_n2.vhd 638 2015-01-25 22:01:38Z mueller $ +-- $Id: sys_tst_rlink_cuff_n2.vhd 734 2016-02-20 22:43:20Z mueller $ -- -- Copyright 2012-2015 by Walter F.J. Mueller -- @@ -56,8 +56,8 @@ -- -- LED(7) SER_MONI.abact -- (6:2) no function (only connected to sn_humanio_rbus) --- (0) timer 0 busy -- (1) timer 1 busy +-- (0) timer 0 busy -- -- DSP: SER_MONI.clkdiv (from auto bauder) -- for SWI(2)='0' (serport) @@ -161,7 +161,7 @@ architecture syn of sys_tst_rlink_cuff_n2 is signal FX2_TX2AFULL : slbit := '0'; signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init; - constant rbaddr_hio : slv16 := x"fef0"; -- fef0/4: 1111 1110 1111 00xx + constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx begin diff --git a/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/.cvsignore b/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/.cvsignore index c4333f66..f03a2a72 100644 --- a/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/.cvsignore +++ b/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/.cvsignore @@ -1,4 +1 @@ -_impactbatch.log sys_tst_rlink_cuff_ic_n3.ucf -*.dep_ucf_cpp -*.svf diff --git a/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/Makefile b/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/Makefile index 215884ab..3f4664bd 100644 --- a/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/Makefile +++ b/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -8,7 +8,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make_ise/xflow_default_nexys3.mk +include ${RETROBASE}/rtl/make_ise/xflow_default_nexys3.mk FX2_FILE = nexys3_jtag_2fifo_ic.ihx # .PHONY : all clean @@ -20,8 +20,8 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/tb/.cvsignore b/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/tb/.cvsignore index 5b93b2e6..ef198f8d 100644 --- a/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/tb/.cvsignore +++ b/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/tb/.cvsignore @@ -1,6 +1 @@ tb_tst_rlink_cuff_ic_n3 -tb_tst_rlink_cuff_ic_n3_[sft]sim -rlink_cext_fifo_rx -rlink_cext_fifo_tx -rlink_cext_conf -*.dep_ucf_cpp diff --git a/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/tb/Makefile b/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/tb/Makefile index 30c79884..690f83fb 100644 --- a/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/tb/Makefile +++ b/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/tb/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -6,7 +6,7 @@ # EXE_all = tb_tst_rlink_cuff_ic_n3 # -include $(RETROBASE)/rtl/make_ise/xflow_default_nexys3.mk +include ${RETROBASE}/rtl/make_ise/xflow_default_nexys3.mk # .PHONY : all all_ssim all_tsim clean # @@ -19,8 +19,8 @@ clean : ise_clean ghdl_clean # #----- # -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/sys_gen/tst_rlink_cuff/nexys3/sys_tst_rlink_cuff_n3.vbom b/rtl/sys_gen/tst_rlink_cuff/nexys3/sys_tst_rlink_cuff_n3.vbom index ffee41a2..139d6c97 100644 --- a/rtl/sys_gen/tst_rlink_cuff/nexys3/sys_tst_rlink_cuff_n3.vbom +++ b/rtl/sys_gen/tst_rlink_cuff/nexys3/sys_tst_rlink_cuff_n3.vbom @@ -14,8 +14,8 @@ ../../../bplib/nxcramlib/nxcramlib.vhd ${sys_conf} # components -[xst,vsyn,isim,vsim]../../../vlib/xlib/s6_cmt_sfs_unisim.vbom -[ghdl]../../../vlib/xlib/s6_cmt_sfs_gsim.vbom +[xst,vsyn]../../../vlib/xlib/s6_cmt_sfs_unisim.vbom +[ghdl,isim,vsim]../../../vlib/xlib/s6_cmt_sfs_gsim.vbom ../../../vlib/genlib/clkdivce.vbom ../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom ../../../bplib/bpgen/sn_humanio_rbus.vbom diff --git a/rtl/sys_gen/tst_rlink_cuff/nexys3/sys_tst_rlink_cuff_n3.vhd b/rtl/sys_gen/tst_rlink_cuff/nexys3/sys_tst_rlink_cuff_n3.vhd index 1b89c719..22436184 100644 --- a/rtl/sys_gen/tst_rlink_cuff/nexys3/sys_tst_rlink_cuff_n3.vhd +++ b/rtl/sys_gen/tst_rlink_cuff/nexys3/sys_tst_rlink_cuff_n3.vhd @@ -1,4 +1,4 @@ --- $Id: sys_tst_rlink_cuff_n3.vhd 638 2015-01-25 22:01:38Z mueller $ +-- $Id: sys_tst_rlink_cuff_n3.vhd 734 2016-02-20 22:43:20Z mueller $ -- -- Copyright 2013-2015 by Walter F.J. Mueller -- @@ -53,8 +53,8 @@ -- -- LED(7) SER_MONI.abact -- (6:2) no function (only connected to sn_humanio_rbus) --- (0) timer 0 busy -- (1) timer 1 busy +-- (0) timer 0 busy -- -- DSP: SER_MONI.clkdiv (from auto bauder) -- for SWI(2)='0' (serport) @@ -159,7 +159,7 @@ architecture syn of sys_tst_rlink_cuff_n3 is signal FX2_TX2AFULL : slbit := '0'; signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init; - constant rbaddr_hio : slv16 := x"fef0"; -- fef0/4: 1111 1110 1111 00xx + constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx begin diff --git a/rtl/sys_gen/tst_serloop/Makefile b/rtl/sys_gen/tst_serloop/Makefile index d649f158..230ada60 100644 --- a/rtl/sys_gen/tst_serloop/Makefile +++ b/rtl/sys_gen/tst_serloop/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -8,7 +8,7 @@ VBOM_all = $(wildcard *.vbom) NGC_all = $(VBOM_all:.vbom=.ngc) # -include $(RETROBASE)/rtl/make_ise/xflow_default_s3board.mk +include ${RETROBASE}/rtl/make_ise/xflow_default_s3board.mk # .PHONY : all clean distclean # @@ -21,7 +21,7 @@ distclean : # #---- # -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_serloop/nexys2/.cvsignore b/rtl/sys_gen/tst_serloop/nexys2/.cvsignore index b8842bab..dc398daf 100644 --- a/rtl/sys_gen/tst_serloop/nexys2/.cvsignore +++ b/rtl/sys_gen/tst_serloop/nexys2/.cvsignore @@ -1,5 +1,2 @@ -_impactbatch.log sys_tst_serloop1_n2.ucf sys_tst_serloop2_n2.ucf -*.dep_ucf_cpp -*.svf diff --git a/rtl/sys_gen/tst_serloop/nexys2/Makefile b/rtl/sys_gen/tst_serloop/nexys2/Makefile index b08e216d..86af5de7 100644 --- a/rtl/sys_gen/tst_serloop/nexys2/Makefile +++ b/rtl/sys_gen/tst_serloop/nexys2/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -7,7 +7,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make_ise/xflow_default_nexys2.mk +include ${RETROBASE}/rtl/make_ise/xflow_default_nexys2.mk # .PHONY : all clean # @@ -18,8 +18,8 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop2_n2.vbom b/rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop2_n2.vbom index 37490503..888b03fe 100644 --- a/rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop2_n2.vbom +++ b/rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop2_n2.vbom @@ -8,8 +8,8 @@ ../../../bplib/nxcramlib/nxcramlib.vhd ${sys_conf := sys_conf2.vhd} # components -[xst,vsyn,isim,vsim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom -[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom +[xst,vsyn]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom +[ghdl,isim,vsim]../../../vlib/xlib/dcm_sfs_gsim.vbom ../../../vlib/genlib/clkdivce.vbom ../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom ../../../bplib/bpgen/sn_humanio.vbom diff --git a/rtl/sys_gen/tst_serloop/nexys2/tb/.cvsignore b/rtl/sys_gen/tst_serloop/nexys2/tb/.cvsignore index bead3e30..08565a07 100644 --- a/rtl/sys_gen/tst_serloop/nexys2/tb/.cvsignore +++ b/rtl/sys_gen/tst_serloop/nexys2/tb/.cvsignore @@ -1,10 +1,3 @@ tb_tst_serloop1_n2 -tb_tst_serloop1_n2_[sft]sim -tb_tst_serloop1_n2_ISim -tb_tst_serloop1_n2_ISim_[sft]sim tb_tst_serloop2_n2 -tb_tst_serloop2_n2_[sft]sim -tb_tst_serloop2_n2_ISim -tb_tst_serloop2_n2_ISim_[sft]sim tb_tst_serloop_stim -*.dep_ucf_cpp diff --git a/rtl/sys_gen/tst_serloop/nexys2/tb/Makefile b/rtl/sys_gen/tst_serloop/nexys2/tb/Makefile index 941e677b..f3a8041c 100644 --- a/rtl/sys_gen/tst_serloop/nexys2/tb/Makefile +++ b/rtl/sys_gen/tst_serloop/nexys2/tb/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -7,7 +7,7 @@ EXE_all = tb_tst_serloop1_n2 EXE_all += tb_tst_serloop2_n2 # -include $(RETROBASE)/rtl/make_ise/xflow_default_nexys2.mk +include ${RETROBASE}/rtl/make_ise/xflow_default_nexys2.mk # .PHONY : all all_ssim all_tsim clean # @@ -19,9 +19,9 @@ clean : ise_clean ghdl_clean isim_clean # #----- # -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk -include $(RETROBASE)/rtl/make_ise/generic_isim.mk -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_isim.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop1_n2.vbom b/rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop1_n2.vbom index 3faa651a..ee6a2f7f 100644 --- a/rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop1_n2.vbom +++ b/rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop1_n2.vbom @@ -5,7 +5,7 @@ sys_conf = sys_conf1_sim.vhd ../../../../vlib/simlib/simlib.vhd # components ../../../../vlib/simlib/simclk.vbom -../sys_tst_serloop1_n2.vbom +@uut: ../sys_tst_serloop1_n2.vbom ../../tb/tb_tst_serloop.vbom # design tb_tst_serloop1_n2.vhd diff --git a/rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop2_n2.vbom b/rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop2_n2.vbom index 59cebce1..22e18d0d 100644 --- a/rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop2_n2.vbom +++ b/rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop2_n2.vbom @@ -7,7 +7,7 @@ sys_conf = sys_conf2_sim.vhd # components ../../../../vlib/simlib/simclk.vbom ../../../../vlib/xlib/dcm_sfs_gsim.vbom -../sys_tst_serloop2_n2.vbom +@uut: ../sys_tst_serloop2_n2.vbom ../../tb/tb_tst_serloop.vbom # design tb_tst_serloop2_n2.vhd diff --git a/rtl/sys_gen/tst_serloop/nexys3/.cvsignore b/rtl/sys_gen/tst_serloop/nexys3/.cvsignore index b298a397..395c926b 100644 --- a/rtl/sys_gen/tst_serloop/nexys3/.cvsignore +++ b/rtl/sys_gen/tst_serloop/nexys3/.cvsignore @@ -1,5 +1,2 @@ -_impactbatch.log sys_tst_serloop1_n3.ucf sys_tst_serloop2_n3.ucf -*.dep_ucf_cpp -*.svf diff --git a/rtl/sys_gen/tst_serloop/nexys3/Makefile b/rtl/sys_gen/tst_serloop/nexys3/Makefile index 1b75a211..edf6389e 100644 --- a/rtl/sys_gen/tst_serloop/nexys3/Makefile +++ b/rtl/sys_gen/tst_serloop/nexys3/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -7,7 +7,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make_ise/xflow_default_nexys3.mk +include ${RETROBASE}/rtl/make_ise/xflow_default_nexys3.mk # .PHONY : all clean # @@ -18,8 +18,8 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_serloop/nexys3/tb/.cvsignore b/rtl/sys_gen/tst_serloop/nexys3/tb/.cvsignore index d01b09a0..4bdd830e 100644 --- a/rtl/sys_gen/tst_serloop/nexys3/tb/.cvsignore +++ b/rtl/sys_gen/tst_serloop/nexys3/tb/.cvsignore @@ -1,10 +1,3 @@ tb_tst_serloop1_n3 -tb_tst_serloop1_n3_[sft]sim -tb_tst_serloop1_n3_ISim -tb_tst_serloop1_n3_ISim_[sft]sim tb_tst_serloop2_n3 -tb_tst_serloop2_n3_[sft]sim -tb_tst_serloop2_n3_ISim -tb_tst_serloop2_n3_ISim_[sft]sim tb_tst_serloop_stim -*.dep_ucf_cpp diff --git a/rtl/sys_gen/tst_serloop/nexys3/tb/Makefile b/rtl/sys_gen/tst_serloop/nexys3/tb/Makefile index 2eeca478..b9927c68 100644 --- a/rtl/sys_gen/tst_serloop/nexys3/tb/Makefile +++ b/rtl/sys_gen/tst_serloop/nexys3/tb/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -7,7 +7,7 @@ # EXE_all = tb_tst_serloop1_n3 # -include $(RETROBASE)/rtl/make_ise/xflow_default_nexys3.mk +include ${RETROBASE}/rtl/make_ise/xflow_default_nexys3.mk # .PHONY : all all_ssim all_tsim clean # @@ -19,9 +19,9 @@ clean : ise_clean ghdl_clean isim_clean # #----- # -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk -include $(RETROBASE)/rtl/make_ise/generic_isim.mk -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_isim.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/sys_gen/tst_serloop/nexys3/tb/tb_tst_serloop1_n3.vbom b/rtl/sys_gen/tst_serloop/nexys3/tb/tb_tst_serloop1_n3.vbom index f3d7cf19..bd9d4d16 100644 --- a/rtl/sys_gen/tst_serloop/nexys3/tb/tb_tst_serloop1_n3.vbom +++ b/rtl/sys_gen/tst_serloop/nexys3/tb/tb_tst_serloop1_n3.vbom @@ -5,7 +5,7 @@ sys_conf = sys_conf1_sim.vhd ../../../../vlib/simlib/simlib.vhd # components ../../../../vlib/simlib/simclk.vbom -../sys_tst_serloop1_n3.vbom +@uut: ../sys_tst_serloop1_n3.vbom ../../tb/tb_tst_serloop.vbom # design tb_tst_serloop1_n3.vhd diff --git a/rtl/sys_gen/tst_serloop/nexys4/.cvsignore b/rtl/sys_gen/tst_serloop/nexys4/.cvsignore deleted file mode 100644 index bcfb2aa7..00000000 --- a/rtl/sys_gen/tst_serloop/nexys4/.cvsignore +++ /dev/null @@ -1,7 +0,0 @@ -.Xil -project_mflow -*.jou -*.log -*.rpt -*.dcp -*.dep_* diff --git a/rtl/sys_gen/tst_serloop/nexys4/Makefile b/rtl/sys_gen/tst_serloop/nexys4/Makefile index 4835aa3c..6d75c538 100644 --- a/rtl/sys_gen/tst_serloop/nexys4/Makefile +++ b/rtl/sys_gen/tst_serloop/nexys4/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 646 2015-02-15 12:04:55Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -7,7 +7,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make_viv/viv_default_nexys4.mk +include ${RETROBASE}/rtl/make_viv/viv_default_nexys4.mk # .PHONY : all clean # @@ -17,7 +17,7 @@ clean : viv_clean # #---- # -include $(RETROBASE)/rtl/make_viv/generic_vivado.mk +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_vsyn) diff --git a/rtl/sys_gen/tst_serloop/nexys4/tb/.cvsignore b/rtl/sys_gen/tst_serloop/nexys4/tb/.cvsignore index e1cd7d9a..e89da9a6 100644 --- a/rtl/sys_gen/tst_serloop/nexys4/tb/.cvsignore +++ b/rtl/sys_gen/tst_serloop/nexys4/tb/.cvsignore @@ -1,4 +1,2 @@ tb_tst_serloop1_n4 -tb_tst_serloop1_n4_[so]sim tb_tst_serloop_stim -*.dep_* diff --git a/rtl/sys_gen/tst_serloop/nexys4/tb/Makefile b/rtl/sys_gen/tst_serloop/nexys4/tb/Makefile index f1516384..ca75862a 100644 --- a/rtl/sys_gen/tst_serloop/nexys4/tb/Makefile +++ b/rtl/sys_gen/tst_serloop/nexys4/tb/Makefile @@ -1,24 +1,32 @@ -# $Id: Makefile 649 2015-02-21 21:10:16Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment +# 2016-02-07 729 1.0.1 add generic_xsim.mk # 2015-02-21 649 1.0 Initial version # EXE_all = tb_tst_serloop1_n4 # -include $(RETROBASE)/rtl/make_viv/viv_default_nexys4.mk +include ${RETROBASE}/rtl/make_viv/viv_default_nexys4.mk # .PHONY : all all_ssim clean # all : $(EXE_all) all_ssim : $(EXE_all:=_ssim) +all_osim : $(EXE_all:=_osim) +# +all_XSim : $(EXE_all:=_XSim) +all_XSim_ssim : $(EXE_all:=_XSim_ssim) +all_XSim_osim : $(EXE_all:=_XSim_osim) +all_XSim_tsim : $(EXE_all:=_XSim_tsim) # clean : viv_clean ghdl_clean # #----- # -include $(RETROBASE)/rtl/make_viv/generic_vivado.mk -include $(RETROBASE)/rtl/make_viv/generic_ghdl.mk +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk +include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk +include ${RETROBASE}/rtl/make_viv/generic_xsim.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/sys_gen/tst_serloop/nexys4/tb/tb_tst_serloop1_n4.vbom b/rtl/sys_gen/tst_serloop/nexys4/tb/tb_tst_serloop1_n4.vbom index 4653012a..7ebf92bd 100644 --- a/rtl/sys_gen/tst_serloop/nexys4/tb/tb_tst_serloop1_n4.vbom +++ b/rtl/sys_gen/tst_serloop/nexys4/tb/tb_tst_serloop1_n4.vbom @@ -5,7 +5,7 @@ sys_conf = sys_conf1_sim.vhd ../../../../vlib/simlib/simlib.vhd # components ../../../../vlib/simlib/simclk.vbom -../sys_tst_serloop1_n4.vbom +@uut: ../sys_tst_serloop1_n4.vbom ../../tb/tb_tst_serloop.vbom # design tb_tst_serloop1_n4.vhd diff --git a/rtl/sys_gen/tst_serloop/s3board/.cvsignore b/rtl/sys_gen/tst_serloop/s3board/.cvsignore index 9a5b8e3b..3b6ca789 100644 --- a/rtl/sys_gen/tst_serloop/s3board/.cvsignore +++ b/rtl/sys_gen/tst_serloop/s3board/.cvsignore @@ -1,4 +1 @@ -_impactbatch.log sys_tst_serloop_s3.ucf -*.dep_ucf_cpp -*.svf diff --git a/rtl/sys_gen/tst_serloop/s3board/Makefile b/rtl/sys_gen/tst_serloop/s3board/Makefile index 70d13b25..32810fb7 100644 --- a/rtl/sys_gen/tst_serloop/s3board/Makefile +++ b/rtl/sys_gen/tst_serloop/s3board/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -7,7 +7,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make_ise/xflow_default_s3board.mk +include ${RETROBASE}/rtl/make_ise/xflow_default_s3board.mk # .PHONY : all clean # @@ -18,8 +18,8 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_serloop/s3board/sys_tst_serloop_s3.vbom b/rtl/sys_gen/tst_serloop/s3board/sys_tst_serloop_s3.vbom index faa1b30d..b5009668 100644 --- a/rtl/sys_gen/tst_serloop/s3board/sys_tst_serloop_s3.vbom +++ b/rtl/sys_gen/tst_serloop/s3board/sys_tst_serloop_s3.vbom @@ -8,8 +8,8 @@ ../../../bplib/s3board/s3boardlib.vbom ${sys_conf := sys_conf.vhd} # components -[xst,vsyn,isim,vsim]../../../vlib/xlib/dcm_sfs_unisim_s3.vbom -[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom +[xst,vsyn]../../../vlib/xlib/dcm_sfs_unisim_s3.vbom +[ghdl,isim,vsim]../../../vlib/xlib/dcm_sfs_gsim.vbom ../../../vlib/genlib/clkdivce.vbom ../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom ../../../bplib/bpgen/sn_humanio.vbom diff --git a/rtl/sys_gen/tst_serloop/s3board/tb/.cvsignore b/rtl/sys_gen/tst_serloop/s3board/tb/.cvsignore index 84045df2..20b38ab8 100644 --- a/rtl/sys_gen/tst_serloop/s3board/tb/.cvsignore +++ b/rtl/sys_gen/tst_serloop/s3board/tb/.cvsignore @@ -1,6 +1,2 @@ tb_tst_serloop_s3 -tb_tst_serloop_s3_[sft]sim -tb_tst_serloop_s3_ISim -tb_tst_serloop_s3_ISim_[sft]sim tb_tst_serloop_stim -*.dep_ucf_cpp diff --git a/rtl/sys_gen/tst_serloop/s3board/tb/Makefile b/rtl/sys_gen/tst_serloop/s3board/tb/Makefile index 384af1b2..857ee03c 100644 --- a/rtl/sys_gen/tst_serloop/s3board/tb/Makefile +++ b/rtl/sys_gen/tst_serloop/s3board/tb/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -6,7 +6,7 @@ # EXE_all = tb_tst_serloop_s3 # -include $(RETROBASE)/rtl/make_ise/xflow_default_s3board.mk +include ${RETROBASE}/rtl/make_ise/xflow_default_s3board.mk # .PHONY : all all_ssim all_tsim clean # @@ -18,9 +18,9 @@ clean : ise_clean ghdl_clean isim_clean # #----- # -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk -include $(RETROBASE)/rtl/make_ise/generic_isim.mk -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_isim.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/sys_gen/tst_serloop/s3board/tb/tb_tst_serloop_s3.vbom b/rtl/sys_gen/tst_serloop/s3board/tb/tb_tst_serloop_s3.vbom index 96a1db32..b8f8dea5 100644 --- a/rtl/sys_gen/tst_serloop/s3board/tb/tb_tst_serloop_s3.vbom +++ b/rtl/sys_gen/tst_serloop/s3board/tb/tb_tst_serloop_s3.vbom @@ -7,7 +7,7 @@ sys_conf = sys_conf_sim.vhd # components ../../../../vlib/simlib/simclk.vbom ../../../../vlib/xlib/dcm_sfs_gsim.vbom -../sys_tst_serloop_s3.vbom +@uut: ../sys_tst_serloop_s3.vbom ../../tb/tb_tst_serloop.vbom # design tb_tst_serloop_s3.vhd diff --git a/rtl/sys_gen/tst_snhumanio/Makefile b/rtl/sys_gen/tst_snhumanio/Makefile index d413b6a3..a91b61e9 100644 --- a/rtl/sys_gen/tst_snhumanio/Makefile +++ b/rtl/sys_gen/tst_snhumanio/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -7,7 +7,7 @@ VBOM_all = $(wildcard *.vbom) NGC_all = $(VBOM_all:.vbom=.ngc) # -include $(RETROBASE)/rtl/make_ise/xflow_default_s3board.mk +include ${RETROBASE}/rtl/make_ise/xflow_default_s3board.mk # .PHONY : all clean # @@ -17,7 +17,7 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_snhumanio/atlys/.cvsignore b/rtl/sys_gen/tst_snhumanio/atlys/.cvsignore index 2249f17e..e08e64ff 100644 --- a/rtl/sys_gen/tst_snhumanio/atlys/.cvsignore +++ b/rtl/sys_gen/tst_snhumanio/atlys/.cvsignore @@ -1,4 +1 @@ -_impactbatch.log sys_tst_snhumanio_atlys.ucf -*.dep_ucf_cpp -*.svf diff --git a/rtl/sys_gen/tst_snhumanio/atlys/Makefile b/rtl/sys_gen/tst_snhumanio/atlys/Makefile index 1c31f539..0b7e42e6 100644 --- a/rtl/sys_gen/tst_snhumanio/atlys/Makefile +++ b/rtl/sys_gen/tst_snhumanio/atlys/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -7,7 +7,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make_ise/xflow_default_atlys.mk +include ${RETROBASE}/rtl/make_ise/xflow_default_atlys.mk # .PHONY : all clean # @@ -18,8 +18,8 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_snhumanio/basys3/.cvsignore b/rtl/sys_gen/tst_snhumanio/basys3/.cvsignore deleted file mode 100644 index bcfb2aa7..00000000 --- a/rtl/sys_gen/tst_snhumanio/basys3/.cvsignore +++ /dev/null @@ -1,7 +0,0 @@ -.Xil -project_mflow -*.jou -*.log -*.rpt -*.dcp -*.dep_* diff --git a/rtl/sys_gen/tst_snhumanio/basys3/Makefile b/rtl/sys_gen/tst_snhumanio/basys3/Makefile index 540f0167..4da352fb 100644 --- a/rtl/sys_gen/tst_snhumanio/basys3/Makefile +++ b/rtl/sys_gen/tst_snhumanio/basys3/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 646 2015-02-15 12:04:55Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -7,7 +7,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make_viv/viv_default_basys3.mk +include ${RETROBASE}/rtl/make_viv/viv_default_basys3.mk # .PHONY : all clean # @@ -18,7 +18,7 @@ clean : viv_clean # #---- # -include $(RETROBASE)/rtl/make_viv/generic_vivado.mk +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_vsyn) diff --git a/rtl/sys_gen/tst_snhumanio/nexys2/.cvsignore b/rtl/sys_gen/tst_snhumanio/nexys2/.cvsignore index 827dbbf7..cb18cbc9 100644 --- a/rtl/sys_gen/tst_snhumanio/nexys2/.cvsignore +++ b/rtl/sys_gen/tst_snhumanio/nexys2/.cvsignore @@ -1,4 +1 @@ -_impactbatch.log sys_tst_snhumanio_n2.ucf -*.dep_ucf_cpp -*.svf diff --git a/rtl/sys_gen/tst_snhumanio/nexys2/Makefile b/rtl/sys_gen/tst_snhumanio/nexys2/Makefile index 25c1ed7d..1c0cd73d 100644 --- a/rtl/sys_gen/tst_snhumanio/nexys2/Makefile +++ b/rtl/sys_gen/tst_snhumanio/nexys2/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -7,7 +7,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make_ise/xflow_default_nexys2.mk +include ${RETROBASE}/rtl/make_ise/xflow_default_nexys2.mk # .PHONY : all clean # @@ -18,8 +18,8 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_snhumanio/nexys3/.cvsignore b/rtl/sys_gen/tst_snhumanio/nexys3/.cvsignore index bd754501..6fc8ab9f 100644 --- a/rtl/sys_gen/tst_snhumanio/nexys3/.cvsignore +++ b/rtl/sys_gen/tst_snhumanio/nexys3/.cvsignore @@ -1,5 +1,2 @@ -_impactbatch.log sys_tst_snhumanio_n3.ucf -*.dep_ucf_cpp _impact* -*.svf diff --git a/rtl/sys_gen/tst_snhumanio/nexys3/Makefile b/rtl/sys_gen/tst_snhumanio/nexys3/Makefile index 1b75a211..edf6389e 100644 --- a/rtl/sys_gen/tst_snhumanio/nexys3/Makefile +++ b/rtl/sys_gen/tst_snhumanio/nexys3/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -7,7 +7,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make_ise/xflow_default_nexys3.mk +include ${RETROBASE}/rtl/make_ise/xflow_default_nexys3.mk # .PHONY : all clean # @@ -18,8 +18,8 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_snhumanio/nexys4/.cvsignore b/rtl/sys_gen/tst_snhumanio/nexys4/.cvsignore deleted file mode 100644 index bcfb2aa7..00000000 --- a/rtl/sys_gen/tst_snhumanio/nexys4/.cvsignore +++ /dev/null @@ -1,7 +0,0 @@ -.Xil -project_mflow -*.jou -*.log -*.rpt -*.dcp -*.dep_* diff --git a/rtl/sys_gen/tst_snhumanio/nexys4/Makefile b/rtl/sys_gen/tst_snhumanio/nexys4/Makefile index c5741c41..cded854e 100644 --- a/rtl/sys_gen/tst_snhumanio/nexys4/Makefile +++ b/rtl/sys_gen/tst_snhumanio/nexys4/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 646 2015-02-15 12:04:55Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -7,7 +7,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make_viv/viv_default_nexys4.mk +include ${RETROBASE}/rtl/make_viv/viv_default_nexys4.mk # .PHONY : all clean # @@ -18,7 +18,7 @@ clean : viv_clean # #---- # -include $(RETROBASE)/rtl/make_viv/generic_vivado.mk +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_vsyn) diff --git a/rtl/sys_gen/tst_snhumanio/s3board/.cvsignore b/rtl/sys_gen/tst_snhumanio/s3board/.cvsignore index 4a12f23d..9f223846 100644 --- a/rtl/sys_gen/tst_snhumanio/s3board/.cvsignore +++ b/rtl/sys_gen/tst_snhumanio/s3board/.cvsignore @@ -1,4 +1 @@ -_impactbatch.log sys_tst_snhumanio_s3.ucf -*.dep_ucf_cpp -*.svf diff --git a/rtl/sys_gen/tst_snhumanio/s3board/Makefile b/rtl/sys_gen/tst_snhumanio/s3board/Makefile index 39047041..fbf58f65 100644 --- a/rtl/sys_gen/tst_snhumanio/s3board/Makefile +++ b/rtl/sys_gen/tst_snhumanio/s3board/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -7,7 +7,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make_ise/xflow_default_s3board.mk +include ${RETROBASE}/rtl/make_ise/xflow_default_s3board.mk # .PHONY : all clean # @@ -18,8 +18,8 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/w11a/arty_bram/Makefile b/rtl/sys_gen/w11a/arty_bram/Makefile new file mode 100644 index 00000000..b12fd285 --- /dev/null +++ b/rtl/sys_gen/w11a/arty_bram/Makefile @@ -0,0 +1,25 @@ +# $Id: Makefile 737 2016-02-28 09:07:18Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2016-02-27 736 1.0 Initial version +# +VBOM_all = sys_w11a_br_arty.vbom +BIT_all = $(VBOM_all:.vbom=.bit) +# +include ${RETROBASE}/rtl/make_viv/viv_default_arty.mk +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : viv_clean +# +#---- +# +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +endif +# diff --git a/rtl/sys_gen/w11a/arty_bram/pdp11_hio70_arty.vbom b/rtl/sys_gen/w11a/arty_bram/pdp11_hio70_arty.vbom new file mode 100644 index 00000000..5a0444d8 --- /dev/null +++ b/rtl/sys_gen/w11a/arty_bram/pdp11_hio70_arty.vbom @@ -0,0 +1,6 @@ +# libs +../../../vlib/slvtypes.vhd +../../../w11a/pdp11.vbom +# components +# design +pdp11_hio70_arty.vhd diff --git a/rtl/sys_gen/w11a/arty_bram/pdp11_hio70_arty.vhd b/rtl/sys_gen/w11a/arty_bram/pdp11_hio70_arty.vhd new file mode 100644 index 00000000..953931e1 --- /dev/null +++ b/rtl/sys_gen/w11a/arty_bram/pdp11_hio70_arty.vhd @@ -0,0 +1,186 @@ +-- $Id: pdp11_hio70_arty.vhd 737 2016-02-28 09:07:18Z mueller $ +-- +-- Copyright 2016- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: pdp11_hio70_arty - syn +-- Description: pdp11: hio led and rgb for sys70 for arty +-- +-- Dependencies: - +-- Test bench: - +-- Target Devices: generic +-- Tool versions: viv 2015.4; ghdl 0.31 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2016-02-27 737 1.0 Initial version +------------------------------------------------------------------------------ +-- +-- collects the output for LED and RGB leds +-- MODE = 00xy +-- LED IO activity +-- (3) not SER_MONI.txok (shows tx back preasure) +-- (2) SER_MONI.txact (shows tx activity) +-- (1) not SER_MONI.rxok (shows rx back preasure) +-- (0) SER_MONI.rxact (shows rx activity) +-- RGB_G CPU busy (active cpugo=1, enabled with y=1) +-- (3) kernel mode, non-wait, pri>0 +-- (2) kernel mode, non-wait, pri=0 +-- (1) supervisor mode +-- (0) user mode +-- RGB_R CPU rust (active cpugo=0, enabled with y=1) +-- (3:0) cpurust code +-- RGB_B MEM/cmd busy (enabled with x=1) +-- (3) MEM_ACT_W +-- (2) MEM_ACT_R +-- (1) cmdbusy (all rlink access, mostly rdma) +-- (0) not cpugo +-- +-- MODE = 0100 (DR emulation) +-- LED DR(15:12) +-- RGB_B DR(11:08) +-- RGB_G DR( 7:04) +-- RGB_R DR( 3:00) +-- +-- MODE = 1xyy (show lsb or msb of 16 bit register) +-- LED show upper, RGB_G lower nibble; x=0 shows lsb and x=1 shows msb +-- yy = 00: abclkdiv & abclkdiv_f +-- 01: PC +-- 10: DISPREG +-- 11: DR emulation +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.pdp11.all; + +-- ---------------------------------------------------------------------------- + +entity pdp11_hio70_arty is -- hio led+rgb for sys70 for arty + port ( + CLK : in slbit; -- clock + MODE : in slv4; -- mode select + MEM_ACT_R : in slbit; -- memory active read + MEM_ACT_W : in slbit; -- memory active write + CP_STAT : in cp_stat_type; -- console port status + DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status + DISPREG : in slv16; -- display register + IOLEDS : in slv4; -- serport ioleds + ABCLKDIV : in slv16; -- serport clock divider + LED : out slv4; -- hio leds + RGB_R : out slv4; -- hio rgb leds - red + RGB_G : out slv4; -- hio rgb leds - green + RGB_B : out slv4 -- hio rgb leds - blue + ); +end pdp11_hio70_arty; + +architecture syn of pdp11_hio70_arty is + + signal R_LED : slv4 := (others=>'0'); + signal R_RGB_R : slv4 := (others=>'0'); + signal R_RGB_G : slv4 := (others=>'0'); + signal R_RGB_B : slv4 := (others=>'0'); + +begin + + proc_regs : process (CLK) + variable idat16 : slv16 := (others=>'0'); + variable idat8 : slv8 := (others=>'0'); + variable iled : slv4 := (others=>'0'); + variable irgb_r : slv4 := (others=>'0'); + variable irgb_g : slv4 := (others=>'0'); + variable irgb_b : slv4 := (others=>'0'); + begin + if rising_edge(CLK) then + + idat16 := (others=>'0'); + case MODE(1 downto 0) is + when "00" => idat16 := ABCLKDIV; + when "01" => idat16 := DM_STAT_DP.pc; + when "10" => idat16 := DISPREG; + when "11" => idat16 := DM_STAT_DP.dsrc; + when others => null; + end case; + + if MODE(2) = '0' then + idat8 := idat16( 7 downto 0); + else + idat8 := idat16(15 downto 8); + end if; + + iled := (others=>'0'); + irgb_r := (others=>'0'); + irgb_g := (others=>'0'); + irgb_b := (others=>'0'); + + if MODE(3) = '0' then + if MODE(2) = '0' then -- LED shows IO; RGB shows CPU/MEM + iled := IOLEDS; + + if MODE(0) = '1' then + if CP_STAT.cpugo = '1' then + case DM_STAT_DP.psw.cmode is + when c_psw_kmode => + if CP_STAT.cpuwait = '0' then + if unsigned(DM_STAT_DP.psw.pri) = 0 then + irgb_g(2) := '1'; + else + irgb_g(3) := '1'; + end if; + end if; + when c_psw_smode => + irgb_g(1) := '1'; + when c_psw_umode => + irgb_g(0) := '1'; + when others => null; + end case; + else + irgb_r(3 downto 0) := CP_STAT.cpurust; + end if; + end if; -- MODE(0) = '1' + + if MODE(1) = '1' then + irgb_b(3) := MEM_ACT_W; + irgb_b(2) := MEM_ACT_R; + irgb_b(1) := CP_STAT.cmdbusy; + irgb_b(0) := not CP_STAT.cpugo; + end if; + + else -- LED+RGB show DR emulation + iled := DM_STAT_DP.dsrc(15 downto 12); + irgb_b := DM_STAT_DP.dsrc(11 downto 8); + irgb_g := DM_STAT_DP.dsrc( 7 downto 4); + irgb_r := DM_STAT_DP.dsrc( 3 downto 0); + end if; -- MODE(2) = '0' + + else -- LED+RGB show one of four regs + iled := idat8(7 downto 4); + irgb_g := idat8(3 downto 0); + end if; -- MODE(3) = '0' + + R_LED <= iled; + R_RGB_R <= irgb_r; + R_RGB_G <= irgb_g; + R_RGB_B <= irgb_b; + end if; + + end process proc_regs; + + LED <= R_LED; + RGB_R <= R_RGB_R; + RGB_G <= R_RGB_G; + RGB_B <= R_RGB_B; + +end syn; diff --git a/rtl/sys_gen/w11a/arty_bram/sys_conf.vhd b/rtl/sys_gen/w11a/arty_bram/sys_conf.vhd new file mode 100644 index 00000000..573a3c46 --- /dev/null +++ b/rtl/sys_gen/w11a/arty_bram/sys_conf.vhd @@ -0,0 +1,96 @@ +-- $Id: sys_conf.vhd 742 2016-03-13 14:40:19Z mueller $ +-- +-- Copyright 2016- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_w11a_br_arty (for synthesis) +-- +-- Dependencies: - +-- Tool versions: viv 2015.4; ghdl 0.33 +-- Revision History: +-- Date Rev Version Comment +-- 2016-03-13 742 1.1 add sysmon_bus +-- 2016-02-27 736 1.0 Initial version (derived from _b3 version) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + -- configure clocks -------------------------------------------------------- + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz + constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + -- single clock design, clkser = clksys + constant sys_conf_clkser_vcodivide : positive := sys_conf_clksys_vcodivide; + constant sys_conf_clkser_vcomultiply : positive := sys_conf_clksys_vcomultiply; + constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide; + constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype; + + -- configure rlink and hio interfaces -------------------------------------- + constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + + -- configure memory controller --------------------------------------------- + constant sys_conf_memctl_mawidth : positive := 4; + constant sys_conf_memctl_nblock : positive := 11; + + -- configure debug and monitoring units ------------------------------------ + constant sys_conf_rbmon_awidth : integer := 0; -- no rbmon to save BRAMs + constant sys_conf_ibmon_awidth : integer := 0; -- no ibmon to save BRAMs + constant sys_conf_dmscnt : boolean := true; + constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable + constant sys_conf_dmcmon_awidth : integer := 0; -- no dmcmon to save BRAMs + constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC) + + -- configure w11 cpu core -------------------------------------------------- + -- sys_conf_mem_losize is highest 64 byte MMU block number + -- the bram_memcnt uses 4*4kB memory blocks => 1 MEM block = 256 MMU blocks + constant sys_conf_mem_losize : integer := 256*sys_conf_memctl_nblock-1; + + constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled + + -- configure w11 system devices -------------------------------------------- + -- configure character and communication devices + constant sys_conf_ibd_dl11_1 : boolean := true; -- 2nd DL11 + constant sys_conf_ibd_pc11 : boolean := true; -- PC11 + constant sys_conf_ibd_lp11 : boolean := true; -- LP11 + + -- configure mass storage devices + constant sys_conf_ibd_rk11 : boolean := true; -- RK11 + constant sys_conf_ibd_rl11 : boolean := true; -- RL11 + constant sys_conf_ibd_rhrp : boolean := true; -- RHRP + constant sys_conf_ibd_tm11 : boolean := true; -- TM11 + + -- configure other devices + constant sys_conf_ibd_iist : boolean := true; -- IIST + + -- derived constants ======================================================= + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_clkser : integer := + ((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) / + sys_conf_clkser_outdivide; + constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000; + + constant sys_conf_ser2rri_cdinit : integer := + (sys_conf_clkser/sys_conf_ser2rri_defbaud)-1; + +end package sys_conf; diff --git a/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vbom b/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vbom new file mode 100644 index 00000000..d3c7ea0a --- /dev/null +++ b/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vbom @@ -0,0 +1,32 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/xlib/xlib.vhd +../../../vlib/genlib/genlib.vhd +../../../vlib/serport/serportlib.vbom +../../../vlib/rbus/rblib.vhd +../../../vlib/rlink/rlinklib.vbom +../../../bplib/bpgen/bpgenlib.vbom +../../../bplib/sysmon/sysmonrbuslib.vbom +../../../ibus/iblib.vhd +../../../ibus/ibdlib.vhd +../../../w11a/pdp11.vhd +sys_conf = sys_conf.vhd +# components +[xst,vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom +[ghdl,isim,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/bp_rs232_2line_iob.vbom +../../../vlib/rlink/rlink_sp1c.vbom +../../../w11a/pdp11_sys70.vbom +../../../ibus/ibdr_maxisys.vbom +../../../w11a/pdp11_bram_memctl.vbom +../../../vlib/rlink/ioleds_sp1c.vbom +pdp11_hio70_arty.vbom +../../../bplib/bpgen/bp_swibtnled.vbom +../../../bplib/bpgen/rgbdrv_3x4mux.vbom +../../../bplib/sysmon/sysmonx_rbus_arty.vbom +../../../vlib/rbus/rb_sres_or_2.vbom +# design +sys_w11a_br_arty.vhd +@xdc:../../../bplib/arty/arty_pclk.xdc +@xdc:../../../bplib/arty/arty_pins.xdc diff --git a/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vhd b/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vhd new file mode 100644 index 00000000..add02693 --- /dev/null +++ b/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vhd @@ -0,0 +1,414 @@ +-- $Id: sys_w11a_br_arty.vhd 742 2016-03-13 14:40:19Z mueller $ +-- +-- Copyright 2016- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_w11a_br_arty - syn +-- Description: w11a test design for arty +-- +-- Dependencies: vlib/xlib/s7_cmt_sfs +-- vlib/genlib/clkdivce +-- bplib/bpgen/bp_rs232_2line_iob +-- vlib/rlink/rlink_sp1c +-- w11a/pdp11_sys70 +-- ibus/ibdr_maxisys +-- w11a/pdp11_bram_memctl +-- vlib/rlink/ioleds_sp1c +-- pdp11_hio70_arty +-- bplib/bpgen/bp_swibtnled +-- bplib/bpgen/rgbdrv_3x4mux +-- bplib/sysmon/sysmonx_rbus_arty +-- vlib/rbus/rb_sres_or_2 +-- +-- Test bench: tb/tb_sys_w11a_br_arty +-- +-- Target Devices: generic +-- Tool versions: viv 2015.4; ghdl 0.33 +-- +-- Synthesized: +-- Date Rev viv Target flop lutl lutm bram slic +-- 2016-03-13 742 2015.4 xc7a35t-1 1996 4309 162 48.5 1333 +XADC +-- 2016-02-27 737 2015.4 xc7a35t-1 1952 4246 162 48.5 1316 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2016-03-13 742 1.1.1 add sysmon_rbus +-- 2016-03-06 740 1.1 add A_VPWRN/P to baseline config +-- 2016-02-27 736 1.0 Initial version (derived from sys_w11a_b3) +------------------------------------------------------------------------------ +-- +-- w11a test design for arty (using BRAM as memory) +-- w11a + rlink + serport +-- +-- Usage of Arty switches, Buttons, LEDs +-- +-- SWI(3:0): determine what is displayed in the LEDs and RGBLEDs +-- 00xy LED shows IO +-- y=1 enables CPU activities on RGB_G,RGB_R +-- x=1 enables MEM activities on RGB_B +-- 0100 LED+RGB give DR emulation 'light show' +-- 1xyy LED+RGB show low (x=0) or high (x=1) byte of +-- yy = 00: abclkdiv & abclkdiv_f +-- 01: PC +-- 10: DISPREG +-- 11: DR emulation +-- LED shows upper, RGB low nibble of the byte selected by x +-- +-- LED and RGB assignment for SWI=00xy +-- LED IO activity +-- (3) not SER_MONI.txok (shows tx back preasure) +-- (2) SER_MONI.txact (shows tx activity) +-- (1) not SER_MONI.rxok (shows rx back preasure) +-- (0) SER_MONI.rxact (shows rx activity) +-- RGB_G CPU busy (active cpugo=1, enabled with SWI(0)) +-- (3) kernel mode, non-wait, pri>0 +-- (2) kernel mode, non-wait, pri=0 +-- (1) supervisor mode +-- (0) user mode +-- RGB_R CPU rust (active cpugo=0, enabled with SWI(0)) +-- (3:0) cpurust code +-- RGB_B MEM/cmd busy (enabled with SWI(1)) +-- (3) MEM_ACT_W +-- (2) MEM_ACT_R +-- (1) cmdbusy (all rlink access, mostly rdma) +-- (0) not cpugo +-- +-- LED and RGB assignment for SWI=0100 (DR emulation) +-- LED DR(15:12) +-- RGB_B DR(11:08) +-- RGB_G DR( 7:04) +-- RGB_R DR( 3:00) +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.genlib.all; +use work.serportlib.all; +use work.rblib.all; +use work.rlinklib.all; +use work.bpgenlib.all; +use work.sysmonrbuslib.all; +use work.iblib.all; +use work.ibdlib.all; +use work.pdp11.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_w11a_br_arty is -- top level + -- implements arty_aif + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv4; -- arty switches + I_BTN : in slv4; -- arty buttons + O_LED : out slv4; -- arty leds + O_RGBLED0 : out slv3; -- arty rgb-led 0 + O_RGBLED1 : out slv3; -- arty rgb-led 1 + O_RGBLED2 : out slv3; -- arty rgb-led 2 + O_RGBLED3 : out slv3; -- arty rgb-led 3 + A_VPWRN : in slv4; -- arty pwrmon (neg) + A_VPWRP : in slv4 -- arty pwrmon (pos) + ); +end sys_w11a_br_arty; + +architecture syn of sys_w11a_br_arty is + + signal CLK : slbit := '0'; + + signal RESET : slbit := '0'; + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal RXD : slbit := '1'; + signal TXD : slbit := '0'; + + signal RB_MREQ : rb_mreq_type := rb_mreq_init; + signal RB_SRES : rb_sres_type := rb_sres_init; + signal RB_SRES_CPU : rb_sres_type := rb_sres_init; + signal RB_SRES_HIO : rb_sres_type := rb_sres_init; + signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init; + + signal RB_LAM : slv16 := (others=>'0'); + signal RB_STAT : slv4 := (others=>'0'); + + signal SER_MONI : serport_moni_type := serport_moni_init; + + signal GRESET : slbit := '0'; -- general reset (from rbus) + signal CRESET : slbit := '0'; -- cpu reset (from cp) + signal BRESET : slbit := '0'; -- bus reset (from cp or cpu) + signal ITIMER : slbit := '0'; + + signal EI_PRI : slv3 := (others=>'0'); + signal EI_VECT : slv9_2 := (others=>'0'); + signal EI_ACKM : slbit := '0'; + signal CP_STAT : cp_stat_type := cp_stat_init; + signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init; + + signal MEM_REQ : slbit := '0'; + signal MEM_WE : slbit := '0'; + signal MEM_BUSY : slbit := '0'; + signal MEM_ACK_R : slbit := '0'; + signal MEM_ACT_R : slbit := '0'; + signal MEM_ACT_W : slbit := '0'; + signal MEM_ADDR : slv20 := (others=>'0'); + signal MEM_BE : slv4 := (others=>'0'); + signal MEM_DI : slv32 := (others=>'0'); + signal MEM_DO : slv32 := (others=>'0'); + + signal IB_MREQ : ib_mreq_type := ib_mreq_init; + signal IB_SRES_IBDR : ib_sres_type := ib_sres_init; + + signal DISPREG : slv16 := (others=>'0'); + signal ABCLKDIV : slv16 := (others=>'0'); + signal IOLEDS : slv4 := (others=>'0'); + + signal SWI : slv4 := (others=>'0'); + signal BTN : slv4 := (others=>'0'); + signal LED : slv4 := (others=>'0'); + signal RGB_R : slv4 := (others=>'0'); + signal RGB_G : slv4 := (others=>'0'); + signal RGB_B : slv4 := (others=>'0'); + + constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx + constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx + +begin + + assert (sys_conf_clksys mod 1000000) = 0 + report "assert sys_conf_clksys on MHz grid" + severity failure; + + GEN_CLKSYS : s7_cmt_sfs -- clock generator ------------------- + generic map ( + VCO_DIVIDE => sys_conf_clksys_vcodivide, + VCO_MULTIPLY => sys_conf_clksys_vcomultiply, + OUT_DIVIDE => sys_conf_clksys_outdivide, + CLKIN_PERIOD => 10.0, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clksys_gentype) + port map ( + CLKIN => I_CLK100, + CLKFX => CLK, + LOCKED => open + ); + + CLKDIV : clkdivce -- usec/msec clock divider ----------- + generic map ( + CDUWIDTH => 7, + USECDIV => sys_conf_clksys_mhz, + MSECDIV => 1000) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC + ); + + IOB_RS232 : bp_rs232_2line_iob -- serport iob ---------------------- + port map ( + CLK => CLK, + RXD => RXD, + TXD => TXD, + I_RXD => I_RXD, + O_TXD => O_TXD + ); + + RLINK : rlink_sp1c -- rlink for serport ----------------- + generic map ( + BTOWIDTH => 7, -- 128 cycles access timeout + RTAWIDTH => 12, + SYSID => (others=>'0'), + IFAWIDTH => 5, -- 32 word input fifo + OFAWIDTH => 5, -- 32 word output fifo + ENAPIN_RLMON => sbcntl_sbf_rlmon, + ENAPIN_RBMON => sbcntl_sbf_rbmon, + CDWIDTH => 13, + CDINIT => sys_conf_ser2rri_cdinit, + RBMON_AWIDTH => sys_conf_rbmon_awidth, + RBMON_RBADDR => rbaddr_rbmon) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + CE_INT => CE_MSEC, + RESET => RESET, + ENAXON => '1', -- XON statically enabled ! + ESCFILL => '0', + RXSD => RXD, + TXSD => TXD, + CTS_N => '0', + RTS_N => open, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT, + RL_MONI => open, + SER_MONI => SER_MONI + ); + + SYS70 : pdp11_sys70 -- 1 cpu system ---------------------- + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_CPU, + RB_STAT => RB_STAT, + RB_LAM_CPU => RB_LAM(0), + GRESET => GRESET, + CRESET => CRESET, + BRESET => BRESET, + CP_STAT => CP_STAT, + EI_PRI => EI_PRI, + EI_VECT => EI_VECT, + EI_ACKM => EI_ACKM, + ITIMER => ITIMER, + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_IBDR, + MEM_REQ => MEM_REQ, + MEM_WE => MEM_WE, + MEM_BUSY => MEM_BUSY, + MEM_ACK_R => MEM_ACK_R, + MEM_ADDR => MEM_ADDR, + MEM_BE => MEM_BE, + MEM_DI => MEM_DI, + MEM_DO => MEM_DO, + DM_STAT_DP => DM_STAT_DP + ); + + + IBDR_SYS : ibdr_maxisys -- IO system ------------------------- + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + RESET => GRESET, + BRESET => BRESET, + ITIMER => ITIMER, + CPUSUSP => CP_STAT.cpususp, + RB_LAM => RB_LAM(15 downto 1), + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_IBDR, + EI_ACKM => EI_ACKM, + EI_PRI => EI_PRI, + EI_VECT => EI_VECT, + DISPREG => DISPREG + ); + + BRAM_CTL: pdp11_bram_memctl -- memory controller ----------------- + generic map ( + MAWIDTH => sys_conf_memctl_mawidth, + NBLOCK => sys_conf_memctl_nblock) + port map ( + CLK => CLK, + RESET => GRESET, + REQ => MEM_REQ, + WE => MEM_WE, + BUSY => MEM_BUSY, + ACK_R => MEM_ACK_R, + ACK_W => open, + ACT_R => MEM_ACT_R, + ACT_W => MEM_ACT_W, + ADDR => MEM_ADDR, + BE => MEM_BE, + DI => MEM_DI, + DO => MEM_DO + ); + + LED_IO : ioleds_sp1c -- hio leds from serport ------------- + port map ( + SER_MONI => SER_MONI, + IOLEDS => IOLEDS + ); + + ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f; + + HIO70 : entity work.pdp11_hio70_arty -- hio from sys70 -------------------- + port map ( + CLK => CLK, + MODE => SWI, + MEM_ACT_R => MEM_ACT_R, + MEM_ACT_W => MEM_ACT_W, + CP_STAT => CP_STAT, + DM_STAT_DP => DM_STAT_DP, + DISPREG => DISPREG, + IOLEDS => IOLEDS, + ABCLKDIV => ABCLKDIV, + LED => LED, + RGB_R => RGB_R, + RGB_G => RGB_G, + RGB_B => RGB_B + ); + + HIO : bp_swibtnled + generic map ( + SWIDTH => I_SWI'length, + BWIDTH => I_BTN'length, + LWIDTH => O_LED'length, + DEBOUNCE => sys_conf_hio_debounce) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + SWI => SWI, + BTN => BTN, + LED => LED, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED + ); + + HIORGB : rgbdrv_3x4mux + port map ( + CLK => CLK, + RESET => RESET, + CE_USEC => CE_USEC, + DATR => RGB_R, + DATG => RGB_G, + DATB => RGB_B, + O_RGBLED0 => O_RGBLED0, + O_RGBLED1 => O_RGBLED1, + O_RGBLED2 => O_RGBLED2, + O_RGBLED3 => O_RGBLED3 + ); + + SMRB : if sys_conf_rbd_sysmon generate + I0: sysmonx_rbus_arty + generic map ( -- use default INIT_ (LP: Vccint=0.95) + CLK_MHZ => sys_conf_clksys_mhz, + RB_ADDR => rbaddr_sysmon) + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_SYSMON, + ALM => open, + OT => open, + TEMP => open, + VPWRN => A_VPWRN, + VPWRP => A_VPWRP + ); + end generate SMRB; + + RB_SRES_OR : rb_sres_or_2 -- rbus or --------------------------- + port map ( + RB_SRES_1 => RB_SRES_CPU, + RB_SRES_2 => RB_SRES_SYSMON, + RB_SRES_OR => RB_SRES + ); + +end syn; diff --git a/rtl/sys_gen/w11a/arty_bram/tb/.cvsignore b/rtl/sys_gen/w11a/arty_bram/tb/.cvsignore new file mode 100644 index 00000000..1414d4aa --- /dev/null +++ b/rtl/sys_gen/w11a/arty_bram/tb/.cvsignore @@ -0,0 +1,2 @@ +tb_w11a_br_arty +sysmon_stim diff --git a/rtl/sys_gen/w11a/arty_bram/tb/Makefile b/rtl/sys_gen/w11a/arty_bram/tb/Makefile new file mode 100644 index 00000000..3ac5026a --- /dev/null +++ b/rtl/sys_gen/w11a/arty_bram/tb/Makefile @@ -0,0 +1,30 @@ +# $Id: Makefile 736 2016-02-27 12:33:40Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2016-02-27 736 1.0 Initial version +# +EXE_all = tb_w11a_br_arty +# +include ${RETROBASE}/rtl/make_viv/viv_default_arty.mk +# +.PHONY : all all_ssim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +# +clean : viv_clean ghdl_clean +# +#----- +# +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk +include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(wildcard *.o.dep_ghdl) +endif +# diff --git a/rtl/sys_gen/w11a/arty_bram/tb/sys_conf_sim.vhd b/rtl/sys_gen/w11a/arty_bram/tb/sys_conf_sim.vhd new file mode 100644 index 00000000..8864e5e6 --- /dev/null +++ b/rtl/sys_gen/w11a/arty_bram/tb/sys_conf_sim.vhd @@ -0,0 +1,93 @@ +-- $Id: sys_conf_sim.vhd 742 2016-03-13 14:40:19Z mueller $ +-- +-- Copyright 2016- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_w11a_br_arty (for simulation) +-- +-- Dependencies: - +-- Tool versions: viv 2015.4; ghdl 0.33 +-- Revision History: +-- Date Rev Version Comment +-- 2016-03-13 742 1.1 add sysmon_bus +-- 2016-02-27 736 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + -- configure clocks -------------------------------------------------------- + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 1; -- vco --- MHz + constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + -- single clock design, clkser = clksys + constant sys_conf_clkser_vcodivide : positive := sys_conf_clksys_vcodivide; + constant sys_conf_clkser_vcomultiply : positive := sys_conf_clksys_vcomultiply; + constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide; + constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype; + + -- configure rlink and hio interfaces -------------------------------------- + constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim + constant sys_conf_hio_debounce : boolean := false; -- no debouncers + + -- configure memory controller --------------------------------------------- + constant sys_conf_memctl_mawidth : positive := 4; + constant sys_conf_memctl_nblock : positive := 11; + + -- configure debug and monitoring units ------------------------------------ + constant sys_conf_rbmon_awidth : integer := 0; -- no rbmon to save BRAMs + constant sys_conf_ibmon_awidth : integer := 0; -- no ibmon to save BRAMs + constant sys_conf_dmscnt : boolean := true; + constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable + constant sys_conf_dmcmon_awidth : integer := 0; -- no dmcmon to save BRAMs + constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC) + + -- configure w11 cpu core -------------------------------------------------- + -- sys_conf_mem_losize is highest 64 byte MMU block number + -- the bram_memcnt uses 4*4kB memory blocks => 1 MEM block = 256 MMU blocks + constant sys_conf_mem_losize : integer := 256*sys_conf_memctl_nblock-1; + + constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled + + -- configure w11 system devices -------------------------------------------- + -- configure character and communication devices + constant sys_conf_ibd_dl11_1 : boolean := true; -- 2nd DL11 + constant sys_conf_ibd_pc11 : boolean := true; -- PC11 + constant sys_conf_ibd_lp11 : boolean := true; -- LP11 + + -- configure mass storage devices + constant sys_conf_ibd_rk11 : boolean := true; -- RK11 + constant sys_conf_ibd_rl11 : boolean := true; -- RL11 + constant sys_conf_ibd_rhrp : boolean := true; -- RHRP + constant sys_conf_ibd_tm11 : boolean := true; -- TM11 + + -- configure other devices + constant sys_conf_ibd_iist : boolean := true; -- IIST + + -- derived constants ======================================================= + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_clkser : integer := + ((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) / + sys_conf_clkser_outdivide; + constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000; + +end package sys_conf; diff --git a/rtl/sys_gen/w11a/arty_bram/tb/tb_w11a_br_arty.vbom b/rtl/sys_gen/w11a/arty_bram/tb/tb_w11a_br_arty.vbom new file mode 100644 index 00000000..2c3dbd3e --- /dev/null +++ b/rtl/sys_gen/w11a/arty_bram/tb/tb_w11a_br_arty.vbom @@ -0,0 +1,7 @@ +# configure tb_arty with sys_w11a_br_arty target; +# use vhdl configure file (tb_w11a_br_arty.vhd) to allow +# that all configurations will co-exist in work library +${basys3_aif := ../sys_w11a_br_arty.vbom} +sys_conf = sys_conf_sim.vhd +../../../../bplib/arty/tb/tb_arty.vbom +tb_w11a_br_arty.vhd diff --git a/rtl/sys_gen/w11a/arty_bram/tb/tb_w11a_br_arty.vhd b/rtl/sys_gen/w11a/arty_bram/tb/tb_w11a_br_arty.vhd new file mode 100644 index 00000000..0752cd63 --- /dev/null +++ b/rtl/sys_gen/w11a/arty_bram/tb/tb_w11a_br_arty.vhd @@ -0,0 +1,35 @@ +-- $Id: tb_w11a_br_arty.vhd 736 2016-02-27 12:33:40Z mueller $ +-- +-- Copyright 2016- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_w11a_br_arty +-- Description: Configuration for tb_w11a_br_arty for tb_arty +-- +-- Dependencies: sys_w11a_br_arty +-- +-- To test: sys_w11a_br_arty +-- +-- Revision History: +-- Date Rev Version Comment +-- 2016-02-27 736 1.0 Initial version +------------------------------------------------------------------------------ + +configuration tb_w11a_br_arty of tb_arty is + + for sim + for all : arty_aif + use entity work.sys_w11a_br_arty; + end for; + end for; + +end tb_w11a_br_arty; diff --git a/rtl/sys_gen/w11a/arty_bram/tb/tb_w11a_br_arty_ssim.vbom b/rtl/sys_gen/w11a/arty_bram/tb/tb_w11a_br_arty_ssim.vbom new file mode 100644 index 00000000..0423e4ea --- /dev/null +++ b/rtl/sys_gen/w11a/arty_bram/tb/tb_w11a_br_arty_ssim.vbom @@ -0,0 +1,6 @@ +# configure for _*sim case +# Note: this tb uses sys_w11a_br_arty.vbom in local directory +# (not in .. as usual) to allow a tb specific configure !!! +basys3_aif = sys_w11a_br_arty_ssim.vhd +tb_w11a_br_arty.vbom +@top:tb_w11a_br_arty diff --git a/rtl/sys_gen/w11a/arty_bram/tb/tbw.dat b/rtl/sys_gen/w11a/arty_bram/tb/tbw.dat new file mode 100644 index 00000000..0e17f263 --- /dev/null +++ b/rtl/sys_gen/w11a/arty_bram/tb/tbw.dat @@ -0,0 +1,7 @@ +# $Id: tbw.dat 742 2016-03-13 14:40:19Z mueller $ +# +[tb_w11a_br_arty] +rlink_cext_fifo_rx = +rlink_cext_fifo_tx = +rlink_cext_conf = +sysmon_stim = ../../../../bplib/sysmon/tb/sysmon_stim_arty.dat diff --git a/rtl/sys_gen/w11a/basys3/.cvsignore b/rtl/sys_gen/w11a/basys3/.cvsignore deleted file mode 100644 index bcfb2aa7..00000000 --- a/rtl/sys_gen/w11a/basys3/.cvsignore +++ /dev/null @@ -1,7 +0,0 @@ -.Xil -project_mflow -*.jou -*.log -*.rpt -*.dcp -*.dep_* diff --git a/rtl/sys_gen/w11a/basys3/Makefile b/rtl/sys_gen/w11a/basys3/Makefile index 13065b8e..6e7321fa 100644 --- a/rtl/sys_gen/w11a/basys3/Makefile +++ b/rtl/sys_gen/w11a/basys3/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 646 2015-02-15 12:04:55Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -7,7 +7,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make_viv/viv_default_basys3.mk +include ${RETROBASE}/rtl/make_viv/viv_default_basys3.mk # .PHONY : all clean # @@ -17,7 +17,7 @@ clean : viv_clean # #---- # -include $(RETROBASE)/rtl/make_viv/generic_vivado.mk +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_vsyn) diff --git a/rtl/sys_gen/w11a/basys3/sys_conf.vhd b/rtl/sys_gen/w11a/basys3/sys_conf.vhd index 1d36d8ea..6296413d 100644 --- a/rtl/sys_gen/w11a/basys3/sys_conf.vhd +++ b/rtl/sys_gen/w11a/basys3/sys_conf.vhd @@ -1,6 +1,6 @@ --- $Id: sys_conf.vhd 698 2015-07-05 21:20:18Z mueller $ +-- $Id: sys_conf.vhd 742 2016-03-13 14:40:19Z mueller $ -- --- Copyright 2015- by Walter F.J. Mueller +-- Copyright 2015-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,9 +16,10 @@ -- Description: Definitions for sys_w11a_b3 (for synthesis) -- -- Dependencies: - --- Tool versions: viv 2014.4; ghdl 0.31 +-- Tool versions: viv 2014.4-2015.4; ghdl 0.31-0.33 -- Revision History: -- Date Rev Version Comment +-- 2016-03-13 742 1.1.2 add sysmon_bus; use 72 MHz, no tc otherwise -- 2015-06-26 695 1.1.1 add sys_conf_(dmscnt|dmhbpt*|dmcmon*) -- 2015-03-14 658 1.1 add sys_conf_ibd_* definitions -- 2015-02-08 644 1.0 Initial version (derived from _n4 version) @@ -32,9 +33,9 @@ use work.slvtypes.all; package sys_conf is -- configure clocks -------------------------------------------------------- - constant sys_conf_clksys_vcodivide : positive := 1; - constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz - constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz + constant sys_conf_clksys_vcodivide : positive := 5; -- f 20 Mhz + constant sys_conf_clksys_vcomultiply : positive := 36; -- vco 720 MHz + constant sys_conf_clksys_outdivide : positive := 10; -- sys 72 MHz constant sys_conf_clksys_gentype : string := "MMCM"; -- single clock design, clkser = clksys constant sys_conf_clkser_vcodivide : positive := sys_conf_clksys_vcodivide; @@ -56,6 +57,7 @@ package sys_conf is constant sys_conf_dmscnt : boolean := true; constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable constant sys_conf_dmcmon_awidth : integer := 0; -- no dmcmon to save BRAMs + constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC) -- configure w11 cpu core -------------------------------------------------- -- sys_conf_mem_losize is highest 64 byte MMU block number diff --git a/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vbom b/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vbom index f219b34c..3cf758fc 100644 --- a/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vbom +++ b/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vbom @@ -7,13 +7,14 @@ ../../../vlib/rlink/rlinklib.vbom ../../../bplib/bpgen/bpgenlib.vbom ../../../bplib/bpgen/bpgenrbuslib.vbom +../../../bplib/sysmon/sysmonrbuslib.vbom ../../../ibus/iblib.vhd ../../../ibus/ibdlib.vhd ../../../w11a/pdp11.vhd sys_conf = sys_conf.vhd # components -[xst,vsyn,isim,vsim]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom -[ghdl]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom +[xst,vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom +[ghdl,isim,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom ../../../vlib/genlib/clkdivce.vbom ../../../bplib/bpgen/bp_rs232_2line_iob.vbom ../../../vlib/rlink/rlink_sp1c.vbom @@ -23,7 +24,8 @@ sys_conf = sys_conf.vhd ../../../vlib/rlink/ioleds_sp1c.vbom ../../../w11a/pdp11_hio70.vbom ../../../bplib/bpgen/sn_humanio_rbus.vbom -../../../vlib/rbus/rb_sres_or_2.vbom +../../../bplib/sysmon/sysmonx_rbus_base.vbom +../../../vlib/rbus/rb_sres_or_3.vbom # design sys_w11a_b3.vhd @xdc:../../../bplib/basys3/basys3_pclk.xdc diff --git a/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd b/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd index cded624c..943fb983 100644 --- a/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd +++ b/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd @@ -1,6 +1,6 @@ --- $Id: sys_w11a_b3.vhd 686 2015-06-04 21:08:08Z mueller $ +-- $Id: sys_w11a_b3.vhd 745 2016-03-18 22:10:34Z mueller $ -- --- Copyright 2015- by Walter F.J. Mueller +-- Copyright 2015-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -25,21 +25,25 @@ -- vlib/rlink/ioleds_sp1c -- w11a/pdp11_hio70 -- bplib/bpgen/sn_humanio_rbus --- vlib/rbus/rb_sres_or_2 +-- bplib/sysmon/sysmonx_rbus_base +-- vlib/rbus/rb_sres_or_3 -- -- Test bench: tb/tb_sys_w11a_b3 -- -- Target Devices: generic --- Tool versions: viv 2014.4; ghdl 0.31 +-- Tool versions: viv 2014.4-2015.4; ghdl 0.31-0.33 -- -- Synthesized: -- Date Rev viv Target flop lutl lutm bram slic +-- 2016-03-13 742 2015.4 xc7a35t-1 2135 4420 162 48.5 1396 +XADC -- 2015-06-04 686 2014.4 xc7a35t-1 1919 4372 162 47.5 1408 +TM11 17% -- 2015-05-14 680 2014.4 xc7a35t-1 1837 4304 162 47.5 1354 +RHRP 17% -- 2015-02-21 649 2014.4 xc7a35t-1 1637 3767 146 47.5 1195 -- -- Revision History: -- Date Rev Version Comment +-- 2016-03-18 745 2.2.1 hardwire XON=1 +-- 2016-03-13 742 2.2 add sysmon_rbus -- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul -- 2015-05-01 672 2.0 use pdp11_sys70 and pdp11_hio70 -- 2015-04-11 666 1.1.1 rearrange XON handling @@ -62,7 +66,7 @@ -- 0 overall status -- 1 DR emulation -- SWI(2): unused-reserved (USB port select) --- SWI(1): 1 enable XON +-- SWI(1): unused-reserved (XON, is hardwired to '1') -- SWI(0): unused-reserved (serial port select) -- -- LEDs if SWI(3) = 1 @@ -103,6 +107,7 @@ use work.rblib.all; use work.rlinklib.all; use work.bpgenlib.all; use work.bpgenrbuslib.all; +use work.sysmonrbuslib.all; use work.iblib.all; use work.ibdlib.all; use work.pdp11.all; @@ -135,10 +140,11 @@ architecture syn of sys_w11a_b3 is signal RXD : slbit := '1'; signal TXD : slbit := '0'; - signal RB_MREQ : rb_mreq_type := rb_mreq_init; - signal RB_SRES : rb_sres_type := rb_sres_init; - signal RB_SRES_CPU : rb_sres_type := rb_sres_init; - signal RB_SRES_HIO : rb_sres_type := rb_sres_init; + signal RB_MREQ : rb_mreq_type := rb_mreq_init; + signal RB_SRES : rb_sres_type := rb_sres_init; + signal RB_SRES_CPU : rb_sres_type := rb_sres_init; + signal RB_SRES_HIO : rb_sres_type := rb_sres_init; + signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init; signal RB_LAM : slv16 := (others=>'0'); signal RB_STAT : slv4 := (others=>'0'); @@ -181,7 +187,8 @@ architecture syn of sys_w11a_b3 is signal DSP_DP : slv4 := (others=>'0'); constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx - constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0004: 1111 1110 1111 00xx + constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx + constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx begin @@ -243,7 +250,7 @@ begin CE_MSEC => CE_MSEC, CE_INT => CE_MSEC, RESET => RESET, - ENAXON => SWI(1), + ENAXON => '1', ESCFILL => '0', RXSD => RXD, TXSD => TXD, @@ -376,10 +383,27 @@ begin O_SEG_N => O_SEG_N ); - RB_SRES_OR : rb_sres_or_2 -- rbus or --------------------------- + SMRB : if sys_conf_rbd_sysmon generate + I0: sysmonx_rbus_base + generic map ( -- use default INIT_ (Vccint=1.00) + CLK_MHZ => sys_conf_clksys_mhz, + RB_ADDR => rbaddr_sysmon) + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_SYSMON, + ALM => open, + OT => open, + TEMP => open + ); + end generate SMRB; + + RB_SRES_OR : rb_sres_or_3 -- rbus or --------------------------- port map ( RB_SRES_1 => RB_SRES_CPU, RB_SRES_2 => RB_SRES_HIO, + RB_SRES_3 => RB_SRES_SYSMON, RB_SRES_OR => RB_SRES ); diff --git a/rtl/sys_gen/w11a/basys3/tb/.cvsignore b/rtl/sys_gen/w11a/basys3/tb/.cvsignore index 9229a836..1861ba65 100644 --- a/rtl/sys_gen/w11a/basys3/tb/.cvsignore +++ b/rtl/sys_gen/w11a/basys3/tb/.cvsignore @@ -1,6 +1,2 @@ tb_w11a_b3 -tb_w11a_b3_[so]sim -rlink_cext_fifo_rx -rlink_cext_fifo_tx -rlink_cext_conf -*.dep_* +sysmon_stim diff --git a/rtl/sys_gen/w11a/basys3/tb/Makefile b/rtl/sys_gen/w11a/basys3/tb/Makefile index 77d5f2d1..4305605a 100644 --- a/rtl/sys_gen/w11a/basys3/tb/Makefile +++ b/rtl/sys_gen/w11a/basys3/tb/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 649 2015-02-21 21:10:16Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -6,7 +6,7 @@ # EXE_all = tb_w11a_b3 # -include $(RETROBASE)/rtl/make_viv/viv_default_basys3.mk +include ${RETROBASE}/rtl/make_viv/viv_default_basys3.mk # .PHONY : all all_ssim clean # @@ -17,8 +17,8 @@ clean : viv_clean ghdl_clean # #----- # -include $(RETROBASE)/rtl/make_viv/generic_vivado.mk -include $(RETROBASE)/rtl/make_viv/generic_ghdl.mk +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk +include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/sys_gen/w11a/basys3/tb/sys_conf_sim.vhd b/rtl/sys_gen/w11a/basys3/tb/sys_conf_sim.vhd index 13388820..6c07b756 100644 --- a/rtl/sys_gen/w11a/basys3/tb/sys_conf_sim.vhd +++ b/rtl/sys_gen/w11a/basys3/tb/sys_conf_sim.vhd @@ -1,6 +1,6 @@ --- $Id: sys_conf_sim.vhd 698 2015-07-05 21:20:18Z mueller $ +-- $Id: sys_conf_sim.vhd 742 2016-03-13 14:40:19Z mueller $ -- --- Copyright 2015- by Walter F.J. Mueller +-- Copyright 2015-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,9 +16,10 @@ -- Description: Definitions for sys_w11a_b3 (for simulation) -- -- Dependencies: - --- Tool versions: viv 2014.4; ghdl 0.31 +-- Tool versions: viv 2014.4-2015.4; ghdl 0.31-0.33 -- Revision History: -- Date Rev Version Comment +-- 2016-03-13 742 1.1.2 add sysmon_bus (but disabled like for fpga) -- 2015-06-26 695 1.1.1 add sys_conf_(dmscnt|dmhbpt*|dmcmon*) -- 2015-03-14 658 1.1 add sys_conf_ibd_* definitions -- 2015-02-21 649 1.0 Initial version @@ -56,6 +57,7 @@ package sys_conf is constant sys_conf_dmscnt : boolean := true; constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable constant sys_conf_dmcmon_awidth : integer := 0; -- no dmcmon to save BRAMs + constant sys_conf_rbd_sysmon : boolean := false; -- SYSMON(XADC) -- configure w11 cpu core -------------------------------------------------- -- sys_conf_mem_losize is highest 64 byte MMU block number diff --git a/rtl/sys_gen/w11a/basys3/tb/tbw.dat b/rtl/sys_gen/w11a/basys3/tb/tbw.dat index ed5fb2b8..6b9a4cdc 100644 --- a/rtl/sys_gen/w11a/basys3/tb/tbw.dat +++ b/rtl/sys_gen/w11a/basys3/tb/tbw.dat @@ -1,6 +1,7 @@ -# $Id: tbw.dat 649 2015-02-21 21:10:16Z mueller $ +# $Id: tbw.dat 742 2016-03-13 14:40:19Z mueller $ # [tb_w11a_b3] rlink_cext_fifo_rx = rlink_cext_fifo_tx = rlink_cext_conf = +sysmon_stim = ../../../../bplib/sysmon/tb/sysmon_stim_n4.dat diff --git a/rtl/sys_gen/w11a/nexys2/.cvsignore b/rtl/sys_gen/w11a/nexys2/.cvsignore index 0cee8088..9adde05b 100644 --- a/rtl/sys_gen/w11a/nexys2/.cvsignore +++ b/rtl/sys_gen/w11a/nexys2/.cvsignore @@ -1,5 +1,3 @@ sys_w11a_n2.ucf -*.dep_ucf_cpp log_* _impact* -*.svf diff --git a/rtl/sys_gen/w11a/nexys2/Makefile b/rtl/sys_gen/w11a/nexys2/Makefile index fc15f3a3..dedb0c16 100644 --- a/rtl/sys_gen/w11a/nexys2/Makefile +++ b/rtl/sys_gen/w11a/nexys2/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -9,7 +9,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make_ise/xflow_default_nexys2.mk +include ${RETROBASE}/rtl/make_ise/xflow_default_nexys2.mk FX2_FILE = nexys2_jtag_2fifo_ic.ihx # .PHONY : all clean @@ -26,8 +26,8 @@ sys_w11a_n2.mcs : sys_w11a_n2.bit # #---- # -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vbom b/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vbom index c571b924..9e22a656 100644 --- a/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vbom +++ b/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vbom @@ -15,8 +15,8 @@ ../../../w11a/pdp11.vhd sys_conf = sys_conf.vhd # components -[xst,vsyn,isim,vsim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom -[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom +[xst,vsyn]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom +[ghdl,isim,vsim]../../../vlib/xlib/dcm_sfs_gsim.vbom ../../../vlib/genlib/clkdivce.vbom ../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom ../../../bplib/fx2rlink/rlink_sp1c_fx2.vbom diff --git a/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd b/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd index 8b8a60c8..084665fe 100644 --- a/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd +++ b/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd @@ -1,4 +1,4 @@ --- $Id: sys_w11a_n2.vhd 692 2015-06-21 11:53:24Z mueller $ +-- $Id: sys_w11a_n2.vhd 734 2016-02-20 22:43:20Z mueller $ -- -- Copyright 2010-2015 by Walter F.J. Mueller -- @@ -277,7 +277,7 @@ architecture syn of sys_w11a_n2 is signal ABCLKDIV : slv16 := (others=>'0'); constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx - constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0004: 1111 1110 1111 00xx + constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx begin diff --git a/rtl/sys_gen/w11a/nexys2/tb/.cvsignore b/rtl/sys_gen/w11a/nexys2/tb/.cvsignore index 4f22b0cd..066e17a1 100644 --- a/rtl/sys_gen/w11a/nexys2/tb/.cvsignore +++ b/rtl/sys_gen/w11a/nexys2/tb/.cvsignore @@ -1,8 +1,2 @@ tb_w11a_n2 -tb_w11a_n2_[sft]sim -rlink_cext_fifo_rx -rlink_cext_fifo_tx -rlink_cext_conf -tmu_ofile sys_w11a_n2.ucf -*.dep_ucf_cpp diff --git a/rtl/sys_gen/w11a/nexys2/tb/Makefile b/rtl/sys_gen/w11a/nexys2/tb/Makefile index bcfa09a4..694fef65 100644 --- a/rtl/sys_gen/w11a/nexys2/tb/Makefile +++ b/rtl/sys_gen/w11a/nexys2/tb/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -7,7 +7,7 @@ # EXE_all = tb_w11a_n2 # -include $(RETROBASE)/rtl/make_ise/xflow_default_nexys2.mk +include ${RETROBASE}/rtl/make_ise/xflow_default_nexys2.mk # .PHONY : all all_ssim all_tsim clean # @@ -19,8 +19,8 @@ clean : ise_clean ghdl_clean # #----- # -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/sys_gen/w11a/nexys3/.cvsignore b/rtl/sys_gen/w11a/nexys3/.cvsignore index fc6cb454..40d1ab6c 100644 --- a/rtl/sys_gen/w11a/nexys3/.cvsignore +++ b/rtl/sys_gen/w11a/nexys3/.cvsignore @@ -1,5 +1,3 @@ sys_w11a_n3.ucf -*.dep_ucf_cpp log_* _impact* -*.svf diff --git a/rtl/sys_gen/w11a/nexys3/Makefile b/rtl/sys_gen/w11a/nexys3/Makefile index 25b8f9be..6eeae597 100644 --- a/rtl/sys_gen/w11a/nexys3/Makefile +++ b/rtl/sys_gen/w11a/nexys3/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -8,7 +8,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make_ise/xflow_default_nexys3.mk +include ${RETROBASE}/rtl/make_ise/xflow_default_nexys3.mk FX2_FILE = nexys3_jtag_2fifo_ic.ihx # .PHONY : all clean @@ -20,8 +20,8 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vbom b/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vbom index a65fa688..50b76ca0 100644 --- a/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vbom +++ b/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vbom @@ -15,8 +15,8 @@ ../../../w11a/pdp11.vhd sys_conf = sys_conf.vhd # components -[xst,vsyn,isim,vsim]../../../vlib/xlib/s6_cmt_sfs_unisim.vbom -[ghdl]../../../vlib/xlib/s6_cmt_sfs_gsim.vbom +[xst,vsyn]../../../vlib/xlib/s6_cmt_sfs_unisim.vbom +[ghdl,isim,vsim]../../../vlib/xlib/s6_cmt_sfs_gsim.vbom ../../../vlib/genlib/clkdivce.vbom ../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom ../../../bplib/fx2rlink/rlink_sp1c_fx2.vbom diff --git a/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd b/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd index cbc4ea07..03e8f5b0 100644 --- a/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd +++ b/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd @@ -1,4 +1,4 @@ --- $Id: sys_w11a_n3.vhd 698 2015-07-05 21:20:18Z mueller $ +-- $Id: sys_w11a_n3.vhd 734 2016-02-20 22:43:20Z mueller $ -- -- Copyright 2011-2015 by Walter F.J. Mueller -- @@ -245,7 +245,7 @@ architecture syn of sys_w11a_n3 is signal DSP_DP : slv4 := (others=>'0'); constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx - constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0004: 1111 1110 1111 00xx + constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx begin diff --git a/rtl/sys_gen/w11a/nexys3/tb/.cvsignore b/rtl/sys_gen/w11a/nexys3/tb/.cvsignore index 0926b500..b3cfa8b7 100644 --- a/rtl/sys_gen/w11a/nexys3/tb/.cvsignore +++ b/rtl/sys_gen/w11a/nexys3/tb/.cvsignore @@ -1,8 +1,2 @@ tb_w11a_n3 -tb_w11a_n3_[sft]sim -rlink_cext_fifo_rx -rlink_cext_fifo_tx -rlink_cext_conf -tmu_ofile sys_w11a_n3.ucf -*.dep_ucf_cpp diff --git a/rtl/sys_gen/w11a/nexys3/tb/Makefile b/rtl/sys_gen/w11a/nexys3/tb/Makefile index 80cc2e3d..3cfa3b13 100644 --- a/rtl/sys_gen/w11a/nexys3/tb/Makefile +++ b/rtl/sys_gen/w11a/nexys3/tb/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -6,7 +6,7 @@ # EXE_all = tb_w11a_n3 # -include $(RETROBASE)/rtl/make_ise/xflow_default_nexys3.mk +include ${RETROBASE}/rtl/make_ise/xflow_default_nexys3.mk # .PHONY : all all_ssim all_tsim clean # @@ -18,8 +18,8 @@ clean : ise_clean ghdl_clean # #----- # -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/sys_gen/w11a/nexys4/.cvsignore b/rtl/sys_gen/w11a/nexys4/.cvsignore index 1e3b6be4..af26316e 100644 --- a/rtl/sys_gen/w11a/nexys4/.cvsignore +++ b/rtl/sys_gen/w11a/nexys4/.cvsignore @@ -1,12 +1,3 @@ sys_w11a_n4.ucf -*.dep_ucf_cpp log_* _impact* -*.svf -.Xil -project_mflow -*.jou -*.log -*.rpt -*.dcp -*.dep_* diff --git a/rtl/sys_gen/w11a/nexys4/Makefile b/rtl/sys_gen/w11a/nexys4/Makefile index 208c9637..7db09708 100644 --- a/rtl/sys_gen/w11a/nexys4/Makefile +++ b/rtl/sys_gen/w11a/nexys4/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 646 2015-02-15 12:04:55Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -7,7 +7,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make_viv/viv_default_nexys4.mk +include ${RETROBASE}/rtl/make_viv/viv_default_nexys4.mk # .PHONY : all clean # @@ -17,7 +17,7 @@ clean : viv_clean # #---- # -include $(RETROBASE)/rtl/make_viv/generic_vivado.mk +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_vsyn) diff --git a/rtl/sys_gen/w11a/nexys4/Makefile.ise b/rtl/sys_gen/w11a/nexys4/Makefile.ise index 70f997f1..067fdebe 100644 --- a/rtl/sys_gen/w11a/nexys4/Makefile.ise +++ b/rtl/sys_gen/w11a/nexys4/Makefile.ise @@ -1,5 +1,5 @@ # -*- makefile-gmake -*- -# $Id: Makefile.ise 646 2015-02-15 12:04:55Z mueller $ +# $Id: Makefile.ise 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -8,7 +8,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make_ise/xflow_default_nexys4.mk +include ${RETROBASE}/rtl/make_ise/xflow_default_nexys4.mk # .PHONY : all clean # @@ -19,8 +19,8 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/w11a/nexys4/sys_conf.vhd b/rtl/sys_gen/w11a/nexys4/sys_conf.vhd index 658ed147..f835e5f8 100644 --- a/rtl/sys_gen/w11a/nexys4/sys_conf.vhd +++ b/rtl/sys_gen/w11a/nexys4/sys_conf.vhd @@ -1,6 +1,6 @@ --- $Id: sys_conf.vhd 698 2015-07-05 21:20:18Z mueller $ +-- $Id: sys_conf.vhd 742 2016-03-13 14:40:19Z mueller $ -- --- Copyright 2013-2015 by Walter F.J. Mueller +-- Copyright 2013-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,9 +16,10 @@ -- Description: Definitions for sys_w11a_n4 (for synthesis) -- -- Dependencies: - --- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31 +-- Tool versions: ise 14.5-14.7; viv 2014.4-2015.4; ghdl 0.29-0.33 -- Revision History: -- Date Rev Version Comment +-- 2016-03-13 742 1.2.2 add sysmon_bus -- 2015-06-26 695 1.2.1 add sys_conf_(dmscnt|dmhbpt*|dmcmon*) -- 2015-03-14 658 1.2 add sys_conf_ibd_* definitions -- 2015-02-07 643 1.1 drop bram and minisys options @@ -67,6 +68,7 @@ package sys_conf is constant sys_conf_dmscnt : boolean := true; constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable constant sys_conf_dmcmon_awidth : integer := 9; -- use 0 to disable + constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC) -- configure w11 cpu core -------------------------------------------------- constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte diff --git a/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vbom b/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vbom index 9c540220..187b650c 100644 --- a/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vbom +++ b/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vbom @@ -7,14 +7,15 @@ ../../../vlib/rlink/rlinklib.vbom ../../../bplib/bpgen/bpgenlib.vbom ../../../bplib/bpgen/bpgenrbuslib.vbom +../../../bplib/sysmon/sysmonrbuslib.vbom ../../../bplib/nxcramlib/nxcramlib.vhd ../../../ibus/iblib.vhd ../../../ibus/ibdlib.vhd ../../../w11a/pdp11.vhd sys_conf = sys_conf.vhd # components -[xst,vsyn,isim,vsim]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom -[ghdl]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom +[xst,vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom +[ghdl,isim,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom ../../../vlib/genlib/clkdivce.vbom ../../../bplib/bpgen/bp_rs232_4line_iob.vbom ../../../vlib/rlink/rlink_sp1c.vbom @@ -24,7 +25,8 @@ sys_conf = sys_conf.vhd ../../../vlib/rlink/ioleds_sp1c.vbom ../../../w11a/pdp11_hio70.vbom ../../../bplib/bpgen/sn_humanio_rbus.vbom -../../../ibus/ib_sres_or_2.vbom +../../../bplib/sysmon/sysmonx_rbus_base.vbom +../../../vlib/rbus/rb_sres_or_3.vbom # design sys_w11a_n4.vhd # constraints diff --git a/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vhd b/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vhd index 6d29e378..47ea0024 100644 --- a/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vhd +++ b/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vhd @@ -1,6 +1,6 @@ --- $Id: sys_w11a_n4.vhd 686 2015-06-04 21:08:08Z mueller $ +-- $Id: sys_w11a_n4.vhd 742 2016-03-13 14:40:19Z mueller $ -- --- Copyright 2013-2015 by Walter F.J. Mueller +-- Copyright 2013-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -25,15 +25,17 @@ -- bplib/fx2rlink/ioleds_sp1c -- w11a/pdp11_hio70 -- bplib/bpgen/sn_humanio_rbus --- vlib/rbus/rb_sres_or_2 +-- bplib/sysmon/sysmonx_rbus_base +-- vlib/rbus/rb_sres_or_3 -- -- Test bench: tb/tb_sys_w11a_n4 -- -- Target Devices: generic --- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31 +-- Tool versions: ise 14.5-14.7; viv 2014.4-2015.4; ghdl 0.29-0.33 -- -- Synthesized: -- Date Rev viv Target flop lutl lutm bram slic MHz +-- 2016-03-13 742 2015.4 xc7a100t-1 2536 4868 178 10.5 1542 80 +XADC -- 2015-06-04 686 2014.4 xc7a100t-1 2111 4541 162 7.5 1469 80 +TM11 -- 2015-05-14 680 2014.4 xc7a100t-1 2030 4459 162 7.5 1427 80 -- 2015-02-22 650 2014.4 xc7a100t-1 1606 3652 146 3.5 1158 80 @@ -41,6 +43,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2016-03-13 742 2.2 add sysmon_rbus -- 2015-05-09 677 2.1 start/stop/suspend overhaul; ; reset overhaul -- 2015-05-01 672 2.0 use pdp11_sys70 and pdp11_hio70 -- 2015-04-11 666 1.4.2 rearrange XON handling @@ -113,6 +116,7 @@ use work.rblib.all; use work.rlinklib.all; use work.bpgenlib.all; use work.bpgenrbuslib.all; +use work.sysmonrbuslib.all; use work.nxcramlib.all; use work.iblib.all; use work.ibdlib.all; @@ -163,10 +167,11 @@ architecture syn of sys_w11a_n4 is signal RTS_N : slbit := '0'; signal CTS_N : slbit := '0'; - signal RB_MREQ : rb_mreq_type := rb_mreq_init; - signal RB_SRES : rb_sres_type := rb_sres_init; - signal RB_SRES_CPU : rb_sres_type := rb_sres_init; - signal RB_SRES_HIO : rb_sres_type := rb_sres_init; + signal RB_MREQ : rb_mreq_type := rb_mreq_init; + signal RB_SRES : rb_sres_type := rb_sres_init; + signal RB_SRES_CPU : rb_sres_type := rb_sres_init; + signal RB_SRES_HIO : rb_sres_type := rb_sres_init; + signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init; signal RB_LAM : slv16 := (others=>'0'); signal RB_STAT : slv4 := (others=>'0'); @@ -212,7 +217,8 @@ architecture syn of sys_w11a_n4 is signal DSP_DP : slv8 := (others=>'0'); constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx - constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0004: 1111 1110 1111 00xx + constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx + constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx begin @@ -423,10 +429,27 @@ begin O_SEG_N => O_SEG_N ); - RB_SRES_OR : rb_sres_or_2 -- rbus or --------------------------- + SMRB : if sys_conf_rbd_sysmon generate + I0: sysmonx_rbus_base + generic map ( -- use default INIT_ (Vccint=1.00) + CLK_MHZ => sys_conf_clksys_mhz, + RB_ADDR => rbaddr_sysmon) + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_SYSMON, + ALM => open, + OT => open, + TEMP => open + ); + end generate SMRB; + + RB_SRES_OR : rb_sres_or_3 -- rbus or --------------------------- port map ( RB_SRES_1 => RB_SRES_CPU, RB_SRES_2 => RB_SRES_HIO, + RB_SRES_3 => RB_SRES_SYSMON, RB_SRES_OR => RB_SRES ); diff --git a/rtl/sys_gen/w11a/nexys4/tb/.cvsignore b/rtl/sys_gen/w11a/nexys4/tb/.cvsignore index eb0f2a2c..63955af6 100644 --- a/rtl/sys_gen/w11a/nexys4/tb/.cvsignore +++ b/rtl/sys_gen/w11a/nexys4/tb/.cvsignore @@ -1,9 +1,3 @@ tb_w11a_n4 -tb_w11a_n4_[sft]sim -rlink_cext_fifo_rx -rlink_cext_fifo_tx -rlink_cext_conf -tmu_ofile sys_w11a_n4.ucf -*.dep_ucf_cpp -*.dep_* +sysmon_stim diff --git a/rtl/sys_gen/w11a/nexys4/tb/Makefile b/rtl/sys_gen/w11a/nexys4/tb/Makefile index bdc3e6c7..c24486bf 100644 --- a/rtl/sys_gen/w11a/nexys4/tb/Makefile +++ b/rtl/sys_gen/w11a/nexys4/tb/Makefile @@ -1,25 +1,33 @@ -# $Id: Makefile 646 2015-02-15 12:04:55Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment +# 2016-02-07 729 1.0.1 add generic_xsim.mk # 2015-02-14 646 1.0 Initial version # 2015-02-01 640 0.1 First draft # EXE_all = tb_w11a_n4 # -include $(RETROBASE)/rtl/make_viv/viv_default_nexys4.mk +include ${RETROBASE}/rtl/make_viv/viv_default_nexys4.mk # .PHONY : all all_ssim clean # all : $(EXE_all) all_ssim : $(EXE_all:=_ssim) +all_osim : $(EXE_all:=_osim) +# +all_XSim : $(EXE_all:=_XSim) +all_XSim_ssim : $(EXE_all:=_XSim_ssim) +all_XSim_osim : $(EXE_all:=_XSim_osim) +all_XSim_tsim : $(EXE_all:=_XSim_tsim) # clean : viv_clean ghdl_clean # #----- # -include $(RETROBASE)/rtl/make_viv/generic_vivado.mk -include $(RETROBASE)/rtl/make_viv/generic_ghdl.mk +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk +include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk +include ${RETROBASE}/rtl/make_viv/generic_xsim.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/sys_gen/w11a/nexys4/tb/Makefile.ise b/rtl/sys_gen/w11a/nexys4/tb/Makefile.ise index 1ee8fa81..6902de78 100644 --- a/rtl/sys_gen/w11a/nexys4/tb/Makefile.ise +++ b/rtl/sys_gen/w11a/nexys4/tb/Makefile.ise @@ -1,5 +1,5 @@ # -*- makefile-gmake -*- -# $Id: Makefile.ise 646 2015-02-15 12:04:55Z mueller $ +# $Id: Makefile.ise 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -7,7 +7,7 @@ # EXE_all = tb_w11a_n4 # -include $(RETROBASE)/rtl/make_ise/xflow_default_nexys4.mk +include ${RETROBASE}/rtl/make_ise/xflow_default_nexys4.mk # .PHONY : all all_ssim all_tsim clean # @@ -19,8 +19,8 @@ clean : ise_clean ghdl_clean # #----- # -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/sys_gen/w11a/nexys4/tb/sys_conf_sim.vhd b/rtl/sys_gen/w11a/nexys4/tb/sys_conf_sim.vhd index 46c70edf..b79b0a07 100644 --- a/rtl/sys_gen/w11a/nexys4/tb/sys_conf_sim.vhd +++ b/rtl/sys_gen/w11a/nexys4/tb/sys_conf_sim.vhd @@ -1,6 +1,6 @@ --- $Id: sys_conf_sim.vhd 698 2015-07-05 21:20:18Z mueller $ +-- $Id: sys_conf_sim.vhd 742 2016-03-13 14:40:19Z mueller $ -- --- Copyright 2013-2015 by Walter F.J. Mueller +-- Copyright 2013-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,9 +16,10 @@ -- Description: Definitions for sys_w11a_n4 (for simulation) -- -- Dependencies: - --- Tool versions: xst 14.5-14.7; ghdl 0.29-0.31 +-- Tool versions: xst 14.5-14.7; ghdl 0.29-0.33 -- Revision History: -- Date Rev Version Comment +-- 2016-03-13 742 1.2.2 add sysmon_bus -- 2015-06-26 695 1.2.1 add sys_conf_(dmscnt|dmhbpt*|dmcmon*) -- 2015-03-14 658 1.2 add sys_conf_ibd_* definitions -- 2015-02-07 643 1.1 drop bram and minisys options @@ -58,6 +59,7 @@ package sys_conf is constant sys_conf_dmscnt : boolean := true; constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable constant sys_conf_dmcmon_awidth : integer := 9; -- use 0 to disable + constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC) -- configure w11 cpu core -------------------------------------------------- constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte diff --git a/rtl/sys_gen/w11a/nexys4/tb/tbw.dat b/rtl/sys_gen/w11a/nexys4/tb/tbw.dat index 60e323ef..79da0770 100644 --- a/rtl/sys_gen/w11a/nexys4/tb/tbw.dat +++ b/rtl/sys_gen/w11a/nexys4/tb/tbw.dat @@ -1,6 +1,7 @@ -# $Id: tbw.dat 535 2013-09-29 11:46:25Z mueller $ +# $Id: tbw.dat 742 2016-03-13 14:40:19Z mueller $ # [tb_w11a_n4] rlink_cext_fifo_rx = rlink_cext_fifo_tx = rlink_cext_conf = +sysmon_stim = ../../../../bplib/sysmon/tb/sysmon_stim_n4.dat diff --git a/rtl/sys_gen/w11a/s3board/.cvsignore b/rtl/sys_gen/w11a/s3board/.cvsignore index 969a4d21..14d5256d 100644 --- a/rtl/sys_gen/w11a/s3board/.cvsignore +++ b/rtl/sys_gen/w11a/s3board/.cvsignore @@ -1,5 +1,3 @@ sys_w11a_s3.ucf -*.dep_ucf_cpp log_* _impact* -*.svf diff --git a/rtl/sys_gen/w11a/s3board/Makefile b/rtl/sys_gen/w11a/s3board/Makefile index 2ed49bba..7bd16d45 100644 --- a/rtl/sys_gen/w11a/s3board/Makefile +++ b/rtl/sys_gen/w11a/s3board/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -7,13 +7,13 @@ # 2010-04-24 282 1.1.3 use %.impact rule, all=BIT_all now # 2009-11-20 251 1.1.2 add .mcs rule # 2009-07-26 236 1.1.1 add program: rule -# 2007-11-26 98 1.1 include $(RETROBASE)/vlib/Makefile.(ghdl|xflow) +# 2007-11-26 98 1.1 include ${RETROBASE}/vlib/Makefile.(ghdl|xflow) # 2007-07-08 65 1.0 Initial version # VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make_ise/xflow_default_s3board.mk +include ${RETROBASE}/rtl/make_ise/xflow_default_s3board.mk # .PHONY : all clean # @@ -29,8 +29,8 @@ sys_w11a_s3.mcs : sys_w11a_s3.bit # #---- # -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd b/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd index 32234671..4819eed9 100644 --- a/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd +++ b/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd @@ -1,4 +1,4 @@ --- $Id: sys_w11a_s3.vhd 686 2015-06-04 21:08:08Z mueller $ +-- $Id: sys_w11a_s3.vhd 734 2016-02-20 22:43:20Z mueller $ -- -- Copyright 2007-2015 by Walter F.J. Mueller -- @@ -275,7 +275,7 @@ architecture syn of sys_w11a_s3 is signal ABCLKDIV : slv16 := (others=>'0'); constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx - constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0004: 1111 1110 1111 00xx + constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx begin diff --git a/rtl/sys_gen/w11a/s3board/tb/.cvsignore b/rtl/sys_gen/w11a/s3board/tb/.cvsignore index f9e04eed..73d9229a 100644 --- a/rtl/sys_gen/w11a/s3board/tb/.cvsignore +++ b/rtl/sys_gen/w11a/s3board/tb/.cvsignore @@ -1,8 +1,2 @@ tb_w11a_s3 -tb_w11a_s3_[sft]sim -rlink_cext_fifo_rx -rlink_cext_fifo_tx -rlink_cext_conf -tmu_ofile sys_w11a_s3.ucf -*.dep_ucf_cpp diff --git a/rtl/sys_gen/w11a/s3board/tb/Makefile b/rtl/sys_gen/w11a/s3board/tb/Makefile index 8812136b..42b4a046 100644 --- a/rtl/sys_gen/w11a/s3board/tb/Makefile +++ b/rtl/sys_gen/w11a/s3board/tb/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -9,7 +9,7 @@ # EXE_all = tb_w11a_s3 # -include $(RETROBASE)/rtl/make_ise/xflow_default_s3board.mk +include ${RETROBASE}/rtl/make_ise/xflow_default_s3board.mk # .PHONY : all all_ssim all_tsim clean # @@ -21,8 +21,8 @@ clean : ise_clean ghdl_clean # #----- # -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/sys_gen/w11a/tb/.cvsignore b/rtl/sys_gen/w11a/tb/.cvsignore index 0ab0e7ce..740a5d03 100644 --- a/rtl/sys_gen/w11a/tb/.cvsignore +++ b/rtl/sys_gen/w11a/tb/.cvsignore @@ -1,13 +1,5 @@ -rlink_cext_fifo_rx -rlink_cext_fifo_tx -rlink_cext_conf to_ptp to_lda -tmu_ofile -*.dsk -*.log -*.log.gz -*.lst *.lda lpt.dat ptp.dat diff --git a/rtl/vlib/comlib/Makefile b/rtl/vlib/comlib/Makefile index e485ad29..7b7bde7b 100644 --- a/rtl/vlib/comlib/Makefile +++ b/rtl/vlib/comlib/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -14,7 +14,7 @@ NGC_all = $(VBOM_all:.vbom=.ngc) ifndef XTW_BOARD XTW_BOARD=nexys3 endif -include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk +include ${RETROBASE}/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # .PHONY : all clean # @@ -24,7 +24,7 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/vlib/comlib/comlib.vhd b/rtl/vlib/comlib/comlib.vhd index 7bae519e..ae18d016 100644 --- a/rtl/vlib/comlib/comlib.vhd +++ b/rtl/vlib/comlib/comlib.vhd @@ -1,6 +1,6 @@ --- $Id: comlib.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: comlib.vhd 746 2016-03-19 13:08:36Z mueller $ -- --- Copyright 2007-2014 by Walter F.J. Mueller +-- Copyright 2007-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,9 +16,10 @@ -- Description: communication components -- -- Dependencies: - --- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 +-- Tool versions: ise 8.2-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33 -- Revision History: -- Date Rev Version Comment +-- 2016-03-13 744 1.6.1 crc16_update_tbl: work around XSim 2015.4 issue -- 2014-09-27 595 1.6 add crc16 (using CRC-CCITT polynomial) -- 2014-09-14 593 1.5 new iface for cdata2byte and byte2cdata -- 2011-09-17 410 1.4 now numeric_std clean; use for crc8 'A6' polynomial @@ -287,6 +288,7 @@ package body comlib is ); variable ch : slv16 := (others=>'0'); + variable cu : slv16 := (others=>'0'); variable t : slv8 := (others=>'0'); variable td : integer := 0; @@ -296,7 +298,13 @@ package body comlib is ch := crc(7 downto 0) & "00000000"; t := data xor crc(15 downto 8); td := crc16_tbl(to_integer(unsigned(t))); - return ch xor slv(to_unsigned(td, 16)); + cu := slv(to_unsigned(td, 16)); + ch := ch xor cu; + return ch; + +-- original code was simply +-- return ch xor slv(to_unsigned(td, 16)); +-- vivado 2015.4 xsim failed on this, issue worked around by equivalent code end function crc16_update_tbl; diff --git a/rtl/vlib/comlib/misc/Makefile b/rtl/vlib/comlib/misc/Makefile index 39d27be3..83d011d3 100644 --- a/rtl/vlib/comlib/misc/Makefile +++ b/rtl/vlib/comlib/misc/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -17,7 +17,7 @@ clean : ghdl_clean # #----- # -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/vlib/comlib/tb/.cvsignore b/rtl/vlib/comlib/tb/.cvsignore index e8880ab3..25e52ee6 100644 --- a/rtl/vlib/comlib/tb/.cvsignore +++ b/rtl/vlib/comlib/tb/.cvsignore @@ -1,5 +1,2 @@ tb_cdata2byte tb_cdata2byte_stim -tb_cdata2byte_[sft]sim -tb_cdata2byte_ISim -tb_cdata2byte_ISim_[sft]sim diff --git a/rtl/vlib/comlib/tb/Makefile b/rtl/vlib/comlib/tb/Makefile index 19553ccb..e0293a0e 100644 --- a/rtl/vlib/comlib/tb/Makefile +++ b/rtl/vlib/comlib/tb/Makefile @@ -1,36 +1,43 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 744 2016-03-13 20:28:25Z mueller $ # # Revision History: # Date Rev Version Comment -# 2014-10-17 596 1.0 Initial version +# 2016-03-13 744 1.0 Initial version # EXE_all = tb_cdata2byte + # -# reference board for test synthesis is Spartan-6 based Nexys3 +# reference board for test synthesis is Artix-7 based Nexys4 ifndef XTW_BOARD - XTW_BOARD=nexys3 + XTW_BOARD=nexys4 endif -include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk +include ${RETROBASE}/rtl/make_viv/viv_default_$(XTW_BOARD).mk # -.PHONY : all all_ssim all_tsim clean +.PHONY : all all_ssim all_osim clean +.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim # all : $(EXE_all) all_ssim : $(EXE_all:=_ssim) -all_tsim : $(EXE_all:=_tsim) +all_osim : $(EXE_all:=_osim) # -clean : ise_clean ghdl_clean isim_clean +all_XSim : $(EXE_all:=_XSim) +all_XSim_ssim : $(EXE_all:=_XSim_ssim) +all_XSim_osim : $(EXE_all:=_XSim_osim) +all_XSim_tsim : $(EXE_all:=_XSim_tsim) +# +clean : viv_clean ghdl_clean xsim_clean # #----- # -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk -include $(RETROBASE)/rtl/make_ise/generic_isim.mk -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk +include ${RETROBASE}/rtl/make_viv/generic_xsim.mk +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk # VBOM_all = $(wildcard *.vbom) # ifndef DONTINCDEP -include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_vsyn) include $(VBOM_all:.vbom=.dep_ghdl) -include $(VBOM_all:.vbom=.dep_isim) +include $(VBOM_all:.vbom=.dep_vsim) endif # diff --git a/rtl/vlib/comlib/tb/Makefile.ise b/rtl/vlib/comlib/tb/Makefile.ise new file mode 100644 index 00000000..ef6f4070 --- /dev/null +++ b/rtl/vlib/comlib/tb/Makefile.ise @@ -0,0 +1,36 @@ +# $Id: Makefile.ise 744 2016-03-13 20:28:25Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2014-10-17 596 1.0 Initial version +# +EXE_all = tb_cdata2byte +# +# reference board for test synthesis is Spartan-6 based Nexys3 +ifndef XTW_BOARD + XTW_BOARD=nexys3 +endif +include ${RETROBASE}/rtl/make_ise/xflow_default_$(XTW_BOARD).mk +# +.PHONY : all all_ssim all_tsim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_tsim : $(EXE_all:=_tsim) +# +clean : ise_clean ghdl_clean isim_clean +# +#----- +# +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_isim.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(VBOM_all:.vbom=.dep_isim) +endif +# diff --git a/rtl/vlib/comlib/tb/tb_cdata2byte.vbom b/rtl/vlib/comlib/tb/tb_cdata2byte.vbom index 9ce038e2..c8cc3151 100644 --- a/rtl/vlib/comlib/tb/tb_cdata2byte.vbom +++ b/rtl/vlib/comlib/tb/tb_cdata2byte.vbom @@ -5,6 +5,6 @@ # components ../../simlib/simclk.vbom ../../simlib/simclkcnt.vbom -${tbd_cdata2byte := tbd_cdata2byte.vbom} +@uut: ${uut := tbd_cdata2byte.vbom} # design tb_cdata2byte.vhd diff --git a/rtl/vlib/comlib/tb/tb_cdata2byte_ssim.vbom b/rtl/vlib/comlib/tb/tb_cdata2byte_ssim.vbom index f56950ff..51ae3f0e 100644 --- a/rtl/vlib/comlib/tb/tb_cdata2byte_ssim.vbom +++ b/rtl/vlib/comlib/tb/tb_cdata2byte_ssim.vbom @@ -1,4 +1,4 @@ # configure for _*sim case -tbd_cdata2byte = tbd_cdata2byte_ssim.vhd +uut = tbd_cdata2byte_ssim.vhd tb_cdata2byte.vbom @top:tb_cdata2byte diff --git a/rtl/vlib/genlib/Makefile b/rtl/vlib/genlib/Makefile index 43a3a7c2..4986c9e2 100644 --- a/rtl/vlib/genlib/Makefile +++ b/rtl/vlib/genlib/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -15,7 +15,7 @@ NGC_all = $(VBOM_all:.vbom=.ngc) ifndef XTW_BOARD XTW_BOARD=nexys3 endif -include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk +include ${RETROBASE}/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # .PHONY : all clean # @@ -25,7 +25,7 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/vlib/memlib/Makefile b/rtl/vlib/memlib/Makefile index 40e69a25..5c6dccb5 100644 --- a/rtl/vlib/memlib/Makefile +++ b/rtl/vlib/memlib/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -14,7 +14,7 @@ NGC_all = $(VBOM_all:.vbom=.ngc) ifndef XTW_BOARD XTW_BOARD=nexys3 endif -include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk +include ${RETROBASE}/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # .PHONY : all clean # @@ -24,7 +24,7 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/vlib/rbus/Makefile b/rtl/vlib/rbus/Makefile index c9425e0e..e439cce4 100644 --- a/rtl/vlib/rbus/Makefile +++ b/rtl/vlib/rbus/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -14,7 +14,7 @@ NGC_all = $(VBOM_all:.vbom=.ngc) ifndef XTW_BOARD XTW_BOARD=nexys3 endif -include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk +include ${RETROBASE}/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # .PHONY : all clean # @@ -24,7 +24,7 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/vlib/rbus/rb_sres_or_2.vhd b/rtl/vlib/rbus/rb_sres_or_2.vhd index ee2c4ed8..897c60e4 100644 --- a/rtl/vlib/rbus/rb_sres_or_2.vhd +++ b/rtl/vlib/rbus/rb_sres_or_2.vhd @@ -1,4 +1,4 @@ --- $Id: rb_sres_or_2.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: rb_sres_or_2.vhd 741 2016-03-12 23:49:03Z mueller $ -- -- Copyright 2008-2010 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: rb_sres_or_mon [sim only] -- Test bench: - -- Target Devices: generic --- Tool versions: ise 8.114.7; viv 2014.4; ghdl 0.18-0.31 +-- Tool versions: ise 8.1-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/vlib/rbus/rb_sres_or_3.vhd b/rtl/vlib/rbus/rb_sres_or_3.vhd index f45ba645..6046aa80 100644 --- a/rtl/vlib/rbus/rb_sres_or_3.vhd +++ b/rtl/vlib/rbus/rb_sres_or_3.vhd @@ -1,4 +1,4 @@ --- $Id: rb_sres_or_3.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: rb_sres_or_3.vhd 741 2016-03-12 23:49:03Z mueller $ -- -- Copyright 2008-2010 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: rb_sres_or_mon [sim only] -- Test bench: - -- Target Devices: generic --- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31 +-- Tool versions: ise 8.1-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/vlib/rbus/rb_sres_or_4.vhd b/rtl/vlib/rbus/rb_sres_or_4.vhd index 4e8a79ae..8adaeb55 100644 --- a/rtl/vlib/rbus/rb_sres_or_4.vhd +++ b/rtl/vlib/rbus/rb_sres_or_4.vhd @@ -1,4 +1,4 @@ --- $Id: rb_sres_or_4.vhd 649 2015-02-21 21:10:16Z mueller $ +-- $Id: rb_sres_or_4.vhd 741 2016-03-12 23:49:03Z mueller $ -- -- Copyright 2008-2010 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: rb_sres_or_mon [sim only] -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.114.7; ghdl 0.18-0.31 +-- Tool versions: xst 8.1-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/vlib/rbus/rb_sres_or_mon.vhd b/rtl/vlib/rbus/rb_sres_or_mon.vhd index 0159de83..2f366311 100644 --- a/rtl/vlib/rbus/rb_sres_or_mon.vhd +++ b/rtl/vlib/rbus/rb_sres_or_mon.vhd @@ -1,6 +1,6 @@ --- $Id: rb_sres_or_mon.vhd 649 2015-02-21 21:10:16Z mueller $ +-- $Id: rb_sres_or_mon.vhd 743 2016-03-13 16:42:31Z mueller $ -- --- Copyright 2010- by Walter F.J. Mueller +-- Copyright 2010-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -17,10 +17,11 @@ -- -- Dependencies: - -- Test bench: - --- Tool versions: ghdl 0.29-0.31 +-- Tool versions: viv 2014.4-2015.4; ghdl 0.29-0.33 -- -- Revision History: -- Date Rev Version Comment +-- 2016-03-13 743 3.1 now with 6 inputs; add RB_SRES_OR_MON_FAIL marker -- 2010-12-23 347 3.0 rename rritb_sres_or_mon->rb_sres_or_mon -- 2010-10-28 336 1.0.1 log errors only if now>0ns (drop startup glitches) -- 2010-06-26 309 1.0 Initial version @@ -41,11 +42,15 @@ entity rb_sres_or_mon is -- rbus result or monitor RB_SRES_1 : in rb_sres_type; -- rb_sres input 1 RB_SRES_2 : in rb_sres_type; -- rb_sres input 2 RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3 - RB_SRES_4 : in rb_sres_type := rb_sres_init -- rb_sres input 4 + RB_SRES_4 : in rb_sres_type := rb_sres_init; -- rb_sres input 4 + RB_SRES_5 : in rb_sres_type := rb_sres_init; -- rb_sres input 5 + RB_SRES_6 : in rb_sres_type := rb_sres_init -- rb_sres input 6 ); end rb_sres_or_mon; architecture sim of rb_sres_or_mon is + + signal RB_SRES_OR_MON_FAIL : slbit := '0'; begin @@ -67,23 +72,33 @@ begin if RB_SRES_2.ack /= '0' then nack := nack + 1; end if; if RB_SRES_3.ack /= '0' then nack := nack + 1; end if; if RB_SRES_4.ack /= '0' then nack := nack + 1; end if; + if RB_SRES_5.ack /= '0' then nack := nack + 1; end if; + if RB_SRES_6.ack /= '0' then nack := nack + 1; end if; if RB_SRES_1.busy /= '0' then nbusy := nbusy + 1; end if; if RB_SRES_2.busy /= '0' then nbusy := nbusy + 1; end if; if RB_SRES_3.busy /= '0' then nbusy := nbusy + 1; end if; if RB_SRES_4.busy /= '0' then nbusy := nbusy + 1; end if; + if RB_SRES_5.busy /= '0' then nbusy := nbusy + 1; end if; + if RB_SRES_6.busy /= '0' then nbusy := nbusy + 1; end if; if RB_SRES_1.err /= '0' then nerr := nerr + 1; end if; if RB_SRES_2.err /= '0' then nerr := nerr + 1; end if; if RB_SRES_3.err /= '0' then nerr := nerr + 1; end if; if RB_SRES_4.err /= '0' then nerr := nerr + 1; end if; + if RB_SRES_5.err /= '0' then nerr := nerr + 1; end if; + if RB_SRES_6.err /= '0' then nerr := nerr + 1; end if; if RB_SRES_1.dout /= dzero then ndout := ndout + 1; end if; if RB_SRES_2.dout /= dzero then ndout := ndout + 1; end if; if RB_SRES_3.dout /= dzero then ndout := ndout + 1; end if; if RB_SRES_4.dout /= dzero then ndout := ndout + 1; end if; + if RB_SRES_5.dout /= dzero then ndout := ndout + 1; end if; + if RB_SRES_6.dout /= dzero then ndout := ndout + 1; end if; + RB_SRES_OR_MON_FAIL <= '0'; if now > 0 ns and (nack>1 or nbusy>1 or nerr>1 or ndout>1) then + RB_SRES_OR_MON_FAIL <= '1'; write(oline, now, right, 12); if nack > 1 then write(oline, string'(" #ack=")); diff --git a/rtl/vlib/rbus/rblib.vhd b/rtl/vlib/rbus/rblib.vhd index dda567fb..05f0fab0 100644 --- a/rtl/vlib/rbus/rblib.vhd +++ b/rtl/vlib/rbus/rblib.vhd @@ -1,6 +1,6 @@ --- $Id: rblib.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: rblib.vhd 741 2016-03-12 23:49:03Z mueller $ -- --- Copyright 2007-2014 by Walter F.J. Mueller +-- Copyright 2007-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,10 +16,11 @@ -- Description: Definitions for rbus interface and bus entities -- -- Dependencies: - --- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 +-- Tool versions: ise 8.2-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33 -- -- Revision History: -- Date Rev Version Comment +-- 2016-03-12 741 4.1 add rb_sres_6 -- 2014-09-14 593 4.0 use new rlink v4 iface and 4 bit STAT -- 2014-08-15 583 3.5 rb_mreq addr now 16 bit -- 2011-12-23 444 3.1 CLK_CYCLE now integer @@ -99,6 +100,17 @@ component rb_sres_or_4 is -- rbus result or, 4 input RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output ); end component; +component rb_sres_or_6 is -- rbus result or, 6 input + port ( + RB_SRES_1 : in rb_sres_type; -- rb_sres input 1 + RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2 + RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3 + RB_SRES_4 : in rb_sres_type := rb_sres_init; -- rb_sres input 4 + RB_SRES_5 : in rb_sres_type := rb_sres_init; -- rb_sres input 5 + RB_SRES_6 : in rb_sres_type := rb_sres_init; -- rb_sres input 6 + RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output + ); +end component; component rbus_aif is -- rbus, abstract interface port ( @@ -156,10 +168,12 @@ end component; component rb_sres_or_mon is -- rbus result or monitor port ( - RB_SRES_1 : in rb_sres_type; -- rb_sres input 1 - RB_SRES_2 : in rb_sres_type; -- rb_sres input 2 + RB_SRES_1 : in rb_sres_type; -- rb_sres input 1 + RB_SRES_2 : in rb_sres_type; -- rb_sres input 2 RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3 - RB_SRES_4 : in rb_sres_type := rb_sres_init -- rb_sres input 4 + RB_SRES_4 : in rb_sres_type := rb_sres_init; -- rb_sres input 4 + RB_SRES_5 : in rb_sres_type := rb_sres_init; -- rb_sres input 5 + RB_SRES_6 : in rb_sres_type := rb_sres_init -- rb_sres input 6 ); end component; diff --git a/rtl/vlib/rlink/Makefile b/rtl/vlib/rlink/Makefile index c9425e0e..e439cce4 100644 --- a/rtl/vlib/rlink/Makefile +++ b/rtl/vlib/rlink/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -14,7 +14,7 @@ NGC_all = $(VBOM_all:.vbom=.ngc) ifndef XTW_BOARD XTW_BOARD=nexys3 endif -include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk +include ${RETROBASE}/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # .PHONY : all clean # @@ -24,7 +24,7 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/vlib/rlink/tb/.cvsignore b/rtl/vlib/rlink/tb/.cvsignore index 33054629..4ffcf6e7 100644 --- a/rtl/vlib/rlink/tb/.cvsignore +++ b/rtl/vlib/rlink/tb/.cvsignore @@ -1,18 +1,6 @@ tb_rlink_stim tb_rlink_direct -tb_rlink_direct_[sft]sim -tb_rlink_direct_ISim -tb_rlink_direct_ISim_[sft]sim tb_rlink_sp1c -tb_rlink_sp1c_[sft]sim -tb_rlink_sp1c_ISim -tb_rlink_sp1c_ISim_[sft]sim tb_rlink_tba_stim tb_rlink_tba_ttcombo -tb_rlink_tba_ttcombo_[sft]sim -tb_rlink_tba_ttcombo_ISim -tb_rlink_tba_ttcombo_ISim_[sft]sim tb_rlink_tba_eyemon -tb_rlink_tba_eyemon_[sft]sim -tb_rlink_tba_eyemon_ISim -tb_rlink_tba_eyemon_ISim_[sft]sim diff --git a/rtl/vlib/rlink/tb/Makefile b/rtl/vlib/rlink/tb/Makefile index a42dfe3a..f045cd2d 100644 --- a/rtl/vlib/rlink/tb/Makefile +++ b/rtl/vlib/rlink/tb/Makefile @@ -1,45 +1,44 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 744 2016-03-13 20:28:25Z mueller $ # # Revision History: # Date Rev Version Comment -# 2014-07-27 545 1.4.1 make reference board configurable via XTW_BOARD -# 2011-08-13 405 1.4 use includes from rtl/make -# 2010-12-05 343 1.3 rri->rlink renames -# 2009-11-21 252 1.2 add ISim support -# 2007-11-03 95 1.1.2 use .log rather .dat output in check_dsim -# 2007-09-16 83 1.1.1 add include *.o.dep_ghdl -# 2007-06-29 61 1.1 add clean and all -# 2007-06-10 51 1.0 Initial version +# 2016-03-13 744 1.0 Initial version # EXE_all = tb_rlink_direct EXE_all += tb_rlink_sp1c + # -# reference board for test synthesis is Spartan-6 based Nexys3 +# reference board for test synthesis is Artix-7 based Nexys4 ifndef XTW_BOARD - XTW_BOARD=nexys3 + XTW_BOARD=nexys4 endif -include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk +include ${RETROBASE}/rtl/make_viv/viv_default_$(XTW_BOARD).mk # -.PHONY : all all_ssim all_tsim clean +.PHONY : all all_ssim all_osim clean +.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim # all : $(EXE_all) all_ssim : $(EXE_all:=_ssim) -all_tsim : $(EXE_all:=_tsim) +all_osim : $(EXE_all:=_osim) # -clean : ise_clean ghdl_clean isim_clean +all_XSim : $(EXE_all:=_XSim) +all_XSim_ssim : $(EXE_all:=_XSim_ssim) +all_XSim_osim : $(EXE_all:=_XSim_osim) +all_XSim_tsim : $(EXE_all:=_XSim_tsim) +# +clean : viv_clean ghdl_clean xsim_clean # #----- # -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk -include $(RETROBASE)/rtl/make_ise/generic_isim.mk -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk +include ${RETROBASE}/rtl/make_viv/generic_xsim.mk +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk # VBOM_all = $(wildcard *.vbom) # ifndef DONTINCDEP -include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_vsyn) include $(VBOM_all:.vbom=.dep_ghdl) -include $(VBOM_all:.vbom=.dep_isim) -include $(wildcard *.o.dep_ghdl) +include $(VBOM_all:.vbom=.dep_vsim) endif # diff --git a/rtl/vlib/rlink/tb/Makefile.ise b/rtl/vlib/rlink/tb/Makefile.ise new file mode 100644 index 00000000..9ce67720 --- /dev/null +++ b/rtl/vlib/rlink/tb/Makefile.ise @@ -0,0 +1,48 @@ +# $Id: Makefile.ise 744 2016-03-13 20:28:25Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2014-07-27 545 1.4.1 make reference board configurable via XTW_BOARD +# 2011-08-13 405 1.4 use includes from rtl/make +# 2010-12-28 349 1.3.1 add tb_rlink_tba_eyemon +# 2010-12-05 343 1.3 rri->rlink renames +# 2009-11-21 252 1.2 add ISim support +# 2007-11-03 95 1.1.2 use .log rather .dat output in check_dsim +# 2007-09-16 83 1.1.1 add include *.o.dep_ghdl +# 2007-06-29 61 1.1 add clean and all +# 2007-06-10 51 1.0 Initial version +# +EXE_all = tb_rlink_direct +EXE_all += tb_rlink_sp1c +EXE_all += tb_rlink_tba_ttcombo +EXE_all += tb_rlink_tba_eyemon +# +# reference board for test synthesis is Spartan-6 based Nexys3 +ifndef XTW_BOARD + XTW_BOARD=nexys3 +endif +include ${RETROBASE}/rtl/make_ise/xflow_default_$(XTW_BOARD).mk +# +.PHONY : all all_ssim all_tsim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_tsim : $(EXE_all:=_tsim) +# +clean : ise_clean ghdl_clean isim_clean +# +#----- +# +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_isim.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(VBOM_all:.vbom=.dep_isim) +include $(wildcard *.o.dep_ghdl) +endif +# diff --git a/rtl/vlib/rlink/tb/tb_rlink.vbom b/rtl/vlib/rlink/tb/tb_rlink.vbom index 33595170..e1afed26 100644 --- a/rtl/vlib/rlink/tb/tb_rlink.vbom +++ b/rtl/vlib/rlink/tb/tb_rlink.vbom @@ -16,7 +16,7 @@ ../../simlib/simclkcnt.vbom ../../genlib/clkdivce.vbom ../../rbus/rbd_tester.vbom -${tbd_rlink_gen := tbd_rlink_direct.vbom} +@uut: ${uut := tbd_rlink_direct.vbom} # design tb_rlink.vhd @top:tb_rlink diff --git a/rtl/vlib/rlink/tb/tb_rlink_direct.vbom b/rtl/vlib/rlink/tb/tb_rlink_direct.vbom index 76587270..ff0cfb66 100644 --- a/rtl/vlib/rlink/tb/tb_rlink_direct.vbom +++ b/rtl/vlib/rlink/tb/tb_rlink_direct.vbom @@ -1,6 +1,6 @@ # configure tb_rlink with tbd_rlink_direct wrapper # use vhdl configure file (tb_rlink_direct.vhd) at allow # that all configurations will co-exist in work library -tbd_rlink_gen = tbd_rlink_direct.vbom +uut = tbd_rlink_direct.vbom tb_rlink.vbom tb_rlink_direct.vhd diff --git a/rtl/vlib/rlink/tb/tb_rlink_direct_ssim.vbom b/rtl/vlib/rlink/tb/tb_rlink_direct_ssim.vbom index e21b443f..644535bd 100644 --- a/rtl/vlib/rlink/tb/tb_rlink_direct_ssim.vbom +++ b/rtl/vlib/rlink/tb/tb_rlink_direct_ssim.vbom @@ -1,4 +1,4 @@ # configure tb_rlink with tbd_rlink_direct wrapper; _*sim case -tbd_rlink_gen = tbd_rlink_direct_ssim.vhd +uut = tbd_rlink_direct_ssim.vhd tb_rlink_direct.vbom @top : tb_rlink_direct diff --git a/rtl/vlib/rlink/tb/tb_rlink_sp1c.vbom b/rtl/vlib/rlink/tb/tb_rlink_sp1c.vbom index b4c85c73..3e446732 100644 --- a/rtl/vlib/rlink/tb/tb_rlink_sp1c.vbom +++ b/rtl/vlib/rlink/tb/tb_rlink_sp1c.vbom @@ -1,6 +1,6 @@ # configure tb_rlink with tbd_rlink_sp1c wrapper; # use vhdl configure file (tb_rlink_sp1c.vhd) to allow # that all configurations will co-exist in work library -tbd_rlink_gen = tbd_rlink_sp1c.vbom +uut = tbd_rlink_sp1c.vbom tb_rlink.vbom tb_rlink_sp1c.vhd diff --git a/rtl/vlib/rlink/tb/rlink_cext.c b/rtl/vlib/rlink/tbcore/rlink_cext.c similarity index 95% rename from rtl/vlib/rlink/tb/rlink_cext.c rename to rtl/vlib/rlink/tbcore/rlink_cext.c index af797fca..fce27f2d 100644 --- a/rtl/vlib/rlink/tb/rlink_cext.c +++ b/rtl/vlib/rlink/tbcore/rlink_cext.c @@ -1,6 +1,6 @@ -/* $Id: rlink_cext.c 602 2014-11-08 21:42:47Z mueller $ +/* $Id: rlink_cext.c 730 2016-02-13 16:22:03Z mueller $ * - * Copyright 2007-2014 by Walter F.J. Mueller + * Copyright 2007-2016 by Walter F.J. Mueller * * This program is free software; you may redistribute and/or modify it under * the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ * * Revision History: * Date Rev Vers Comment + * 2016-02-07 728 2.1 emit only one 'schedule clock stop' message * 2014-11-02 602 2.0 sideband handling for rlink v4; count EAGAINs * 2014-07-27 575 1.3.2 add ssize_t -> int casts to avoid warnings * add fflush(stdout) after standart open/close msgs @@ -124,6 +125,7 @@ int rlink_cext_getbyte(int clk) static int nidle = 0; static int ncesc = 0; static int nside = -1; + static int exitdone = 0; if (fd_rx < 0) { /* fifo's not yet opened */ fd_rx = open("rlink_cext_fifo_rx", O_RDONLY|O_NONBLOCK); @@ -183,7 +185,10 @@ int rlink_cext_getbyte(int clk) return 0x100; /* return idle, will reconnect */ } - printf("rlink_cext-I: seen EOF, schedule clock stop and exit\n"); + if (exitdone == 0) { + printf("rlink_cext-I: seen EOF, schedule clock stop and exit\n"); + exitdone = 1; + } fflush(stdout); return -1; /* signal EOF seen */ diff --git a/rtl/vlib/rlink/tbcore/rlink_cext_dpi.c b/rtl/vlib/rlink/tbcore/rlink_cext_dpi.c new file mode 100644 index 00000000..3941c500 --- /dev/null +++ b/rtl/vlib/rlink/tbcore/rlink_cext_dpi.c @@ -0,0 +1,33 @@ +/* $Id: rlink_cext_dpi.c 730 2016-02-13 16:22:03Z mueller $ + * + * Copyright 2016- by Walter F.J. Mueller + * + * This program is free software; you may redistribute and/or modify it under + * the terms of the GNU General Public License as published by the Free + * Software Foundation, either version 2, or at your option any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for complete details. + * + * Revision History: + * Date Rev Vers Comment + * 2016-02-07 729 1.0 Initial version + */ + +#include "svdpi.h" + +/* simple forwarders to call the old VHPI interface from DPI */ + +DPI_DLLESPEC +int rlink_cext_getbyte_dpi(int clk) +{ + return rlink_cext_getbyte(clk); +} + +DPI_DLLESPEC +int rlink_cext_putbyte_dpi(int dat) +{ + return rlink_cext_putbyte(dat); +} diff --git a/rtl/vlib/rlink/tbcore/rlink_cext_iface_dpi.sv b/rtl/vlib/rlink/tbcore/rlink_cext_iface_dpi.sv new file mode 100644 index 00000000..c8e500b7 --- /dev/null +++ b/rtl/vlib/rlink/tbcore/rlink_cext_iface_dpi.sv @@ -0,0 +1,78 @@ +// $Id: rlink_cext_iface_dpi.sv 731 2016-02-14 21:07:14Z mueller $ +// +// Copyright 2016- by Walter F.J. Mueller +// +// This program is free software; you may redistribute and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation, either version 2, or at your option any later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for complete details. +// +//---------------------------------------------------------------------------- +// Module Name: rlink_cext_iface - sim +// Description: Interface to external C code for tbcore_rlink - DPI version +// +// Dependencies: - +// +// To test: - +// +// Target Devices: generic +// Tool versions: viv 2015.4 +// Revision History: +// Date Rev Version Comment +// 2016-02-07 729 0.1 First draft +//---------------------------------------------------------------------------- + +`default_nettype none + +package rlink_cext_dpi; + import "DPI-C" function int rlink_cext_getbyte_dpi(input int clk); + import "DPI-C" function int rlink_cext_putbyte_dpi(input int dat); +endpackage // rlink_cext_dpi + +module rlink_cext_iface(input wire clk, + input wire [31:0] clk_cycle, + output reg [31:0] rx_data, + output reg rx_val, + input wire rx_hold, + input wire [7:0] tx_data, + input wire tx_ena + ); + + int itxdata = 0; + int itxrc = 0; + int icycle = 0; + int irxdata = 0; + reg r_rxval = 1'b0; + int r_rxdata = 0; + + initial rx_data = 8'b00000000; + initial rx_val = 1'b0; + + always @ (posedge clk) begin + if (tx_ena) begin + itxdata = tx_data; + itxrc = rlink_cext_dpi::rlink_cext_putbyte_dpi(itxdata); + if (itxrc != 0) begin + $display("rlink_cext_putbyte error: ", itxrc); + $finish; + end + end + end + + always @ (posedge clk) begin + if (~rx_hold | ~r_rxval ) begin + icycle = clk_cycle; + irxdata = rlink_cext_dpi::rlink_cext_getbyte_dpi(icycle); + rx_data <= irxdata; + rx_val <= irxdata >= 0; + end + end + + +endmodule // rlink_cext_iface + +`default_nettype wire diff --git a/rtl/vlib/rlink/tbcore/rlink_cext_iface_dpi.vbom b/rtl/vlib/rlink/tbcore/rlink_cext_iface_dpi.vbom new file mode 100644 index 00000000..a0181ede --- /dev/null +++ b/rtl/vlib/rlink/tbcore/rlink_cext_iface_dpi.vbom @@ -0,0 +1,7 @@ +# libs +# components +# dpi +rlink_cext_dpi.c +rlink_cext.c +# design +rlink_cext_iface_dpi.sv diff --git a/rtl/vlib/rlink/tbcore/rlink_cext_iface_vhpi.vbom b/rtl/vlib/rlink/tbcore/rlink_cext_iface_vhpi.vbom new file mode 100644 index 00000000..e2185291 --- /dev/null +++ b/rtl/vlib/rlink/tbcore/rlink_cext_iface_vhpi.vbom @@ -0,0 +1,8 @@ +# libs +../../slvtypes.vhd +rlink_cext_vhpi.vhd +# components +# vhpi +rlink_cext.c +# design +rlink_cext_iface_vhpi.vhd diff --git a/rtl/vlib/rlink/tbcore/rlink_cext_iface_vhpi.vhd b/rtl/vlib/rlink/tbcore/rlink_cext_iface_vhpi.vhd new file mode 100644 index 00000000..c7a4a100 --- /dev/null +++ b/rtl/vlib/rlink/tbcore/rlink_cext_iface_vhpi.vhd @@ -0,0 +1,90 @@ +-- $Id: rlink_cext_iface_vhpi.vhd 730 2016-02-13 16:22:03Z mueller $ +-- +-- Copyright 2016- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: rlink_cext_iface - sim +-- Description: Interface to external C code for tbcore_rlink - VHPI version +-- +-- Dependencies: - +-- +-- To test: - +-- +-- Target Devices: generic +-- Tool versions: ghdl 0.31 +-- Revision History: +-- Date Rev Version Comment +-- 2016-02-07 729 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.rlink_cext_vhpi.all; + +entity rlink_cext_iface is -- interface to external C code - VHPI + port ( + CLK : in slbit; -- clock + CLK_CYCLE : in slv32; -- clock cycle number + RX_DATA : out slv32; -- read data (data ext->tb) + RX_VAL : out slbit; -- read data valid (data ext->tb) + RX_HOLD : in slbit; -- read data hold (data ext->tb) + TX_DATA : in slv8; -- write data (data tb->ext) + TX_ENA : in slbit -- write data enable (data tb->ext) + ); +end rlink_cext_iface; + +architecture sim of rlink_cext_iface is + signal R_RXDATA : slv32 := (others=>'1'); + signal R_RXVAL : slbit := '0'; +begin + + proc_put: process (CLK) + variable itxrc : integer := 0; + begin + if rising_edge(CLK) then + if TX_ENA = '1' then + itxrc := rlink_cext_putbyte(to_integer(unsigned(TX_DATA))); + assert itxrc=0 + report "rlink_cext_putbyte error: " & integer'image(itxrc) + severity failure; + end if; + + end if; + + end process proc_put; + + proc_get: process (CLK) + variable irxint : integer := 0; + begin + if rising_edge(CLK) then + if RX_HOLD = '0' or R_RXVAL = '0' then + irxint := rlink_cext_getbyte(to_integer(signed(CLK_CYCLE))); + R_RXDATA <= slv(to_signed(irxint, 32)); + if irxint >= 0 then + R_RXVAL <= '1'; + else + R_RXVAL <= '0'; + end if; + end if; + end if; + + end process proc_get; + + RX_DATA <= R_RXDATA; + RX_VAL <= R_RXVAL; + +end sim; diff --git a/rtl/vlib/rlink/tb/rlink_cext_vhpi.vhd b/rtl/vlib/rlink/tbcore/rlink_cext_vhpi.vhd similarity index 94% rename from rtl/vlib/rlink/tb/rlink_cext_vhpi.vhd rename to rtl/vlib/rlink/tbcore/rlink_cext_vhpi.vhd index f8a6a787..1e19c96d 100644 --- a/rtl/vlib/rlink/tb/rlink_cext_vhpi.vhd +++ b/rtl/vlib/rlink/tbcore/rlink_cext_vhpi.vhd @@ -1,4 +1,4 @@ --- $Id: rlink_cext_vhpi.vhd 649 2015-02-21 21:10:16Z mueller $ +-- $Id: rlink_cext_vhpi.vhd 730 2016-02-13 16:22:03Z mueller $ -- -- Copyright 2007-2010 by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: VHDL procedural interface: VHDL declaration side -- -- Dependencies: - --- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31 +-- Tool versions: ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2010-12-29 351 1.1 rename vhpi_rriext->rlink_cext_vhpi; new rbv3 names diff --git a/rtl/vlib/rlink/tb/tbcore_rlink.vbom b/rtl/vlib/rlink/tbcore/tbcore_rlink.vbom similarity index 73% rename from rtl/vlib/rlink/tb/tbcore_rlink.vbom rename to rtl/vlib/rlink/tbcore/tbcore_rlink.vbom index 4bd79b79..38870b9d 100644 --- a/rtl/vlib/rlink/tb/tbcore_rlink.vbom +++ b/rtl/vlib/rlink/tbcore/tbcore_rlink.vbom @@ -4,11 +4,9 @@ ../../simlib/simbus.vhd ../../rbus/rblib.vhd ../rlinklib.vbom -rlinktblib.vhd -rlink_cext_vhpi.vhd # components ../../simlib/simclkcnt.vbom -# vhpi -rlink_cext.c +[ghdl]rlink_cext_iface_vhpi.vbom +[viv]rlink_cext_iface_dpi.vbom # design tbcore_rlink.vhd diff --git a/rtl/vlib/rlink/tb/tbcore_rlink.vhd b/rtl/vlib/rlink/tbcore/tbcore_rlink.vhd similarity index 87% rename from rtl/vlib/rlink/tb/tbcore_rlink.vhd rename to rtl/vlib/rlink/tbcore/tbcore_rlink.vhd index 0496ecb3..68ef49df 100644 --- a/rtl/vlib/rlink/tb/tbcore_rlink.vhd +++ b/rtl/vlib/rlink/tbcore/tbcore_rlink.vhd @@ -1,6 +1,6 @@ --- $Id: tbcore_rlink.vhd 712 2015-11-01 22:53:45Z mueller $ +-- $Id: tbcore_rlink.vhd 731 2016-02-14 21:07:14Z mueller $ -- --- Copyright 2010-2015 by Walter F.J. Mueller +-- Copyright 2010-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,13 +16,15 @@ -- Description: Core for a rlink_cext based test bench -- -- Dependencies: simlib/simclkcnt +-- rlink_cext_iface -- -- To test: generic, any rlink_cext based target -- -- Target Devices: generic --- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31 +-- Tool versions: ghdl 0.26-0.31 -- Revision History: -- Date Rev Version Comment +-- 2016-02-07 729 3.2 use rlink_cext_iface (allow VHPI and DPI backend) -- 2015-11-01 712 3.1.3 proc_stim: drive SB_CNTL from start to avoid 'U' -- 2013-01-04 469 3.1.2 use 1ns wait for .sinit to allow simbus debugging -- 2011-12-25 445 3.1.1 add SB_ init drivers to avoid SB_VAL='U' at start @@ -47,8 +49,6 @@ use work.simlib.all; use work.simbus.all; use work.rblib.all; use work.rlinklib.all; -use work.rlinktblib.all; -use work.rlink_cext_vhpi.all; entity tbcore_rlink is -- core of rlink_cext based test bench port ( @@ -64,12 +64,29 @@ end tbcore_rlink; architecture sim of tbcore_rlink is - signal CLK_CYCLE : integer := 0; + signal CLK_CYCLE : integer := 0; + signal CEXT_CYCLE : slv32 := (others=>'0'); + signal CEXT_RXDATA : slv32 := (others=>'0'); + signal CEXT_RXVAL : slbit := '0'; + signal CEXT_RXHOLD : slbit := '1'; begin CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE); + CEXT_IFACE : entity work.rlink_cext_iface + port map ( + CLK => CLK, + CLK_CYCLE => CEXT_CYCLE, + RX_DATA => CEXT_RXDATA, + RX_VAL => CEXT_RXVAL, + RX_HOLD => CEXT_RXHOLD, + TX_DATA => TX_DATA, + TX_ENA => TX_ENA + ); + + CEXT_CYCLE <= slv(to_signed(CLK_CYCLE,32)); + proc_conf: process file fconf : text open read_mode is "rlink_cext_conf"; variable iline : line; @@ -178,12 +195,17 @@ begin SB_ADDR <= (others=>'Z'); SB_DATA <= (others=>'Z'); SB_CNTL <= (others=>'Z'); - + + CEXT_RXHOLD <= '1'; + -- wait for 10 clock cycles (design run up) for i in 0 to 9 loop wait until rising_edge(CLK); end loop; -- i - + + writetimestamp(oline, CLK_CYCLE, ": START"); + writeline(output, oline); + stim_loop: loop wait until falling_edge(CLK); @@ -193,9 +215,11 @@ begin RX_VAL <= '0'; + CEXT_RXHOLD <= RX_HOLD; + if RX_HOLD = '0' then - irxint := rlink_cext_getbyte(CLK_CYCLE); - if irxint >= 0 then + irxint := to_integer(signed(CEXT_RXDATA)); + if CEXT_RXVAL = '1' then if irxint <= 16#ff# then -- normal data byte RX_DATA <= slv(to_unsigned(irxint, 8)); RX_VAL <= '1'; @@ -228,8 +252,9 @@ begin else report "rlink_cext_getbyte error: " & integer'image(-irxint) severity failure; - end if; - end if; + end if; -- CEXT_RXVAL = '1' + + end if; -- RX_HOLD = '0' SB_CNTL <= r_sb_cntl; @@ -250,24 +275,4 @@ begin end process proc_stim; - proc_moni: process - variable itxdata : integer := 0; - variable itxrc : integer := 0; - variable oline : line; - begin - - loop - wait until rising_edge(CLK); - if TX_ENA = '1' then - itxdata := to_integer(unsigned(TX_DATA)); - itxrc := rlink_cext_putbyte(itxdata); - assert itxrc=0 - report "rlink_cext_putbyte error: " & integer'image(itxrc) - severity failure; - end if; - - end loop; - - end process proc_moni; - end sim; diff --git a/rtl/vlib/serport/Makefile b/rtl/vlib/serport/Makefile index bd2bb47c..674d3367 100644 --- a/rtl/vlib/serport/Makefile +++ b/rtl/vlib/serport/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -14,7 +14,7 @@ NGC_all = $(VBOM_all:.vbom=.ngc) ifndef XTW_BOARD XTW_BOARD=nexys3 endif -include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk +include ${RETROBASE}/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # .PHONY : all clean # @@ -24,7 +24,7 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/vlib/serport/serport_master.vbom b/rtl/vlib/serport/serport_master.vbom deleted file mode 100644 index f508a528..00000000 --- a/rtl/vlib/serport/serport_master.vbom +++ /dev/null @@ -1,9 +0,0 @@ -# libs -../slvtypes.vhd -serportlib.vbom -# components -serport_uart_rxtx.vbom -serport_xonrx.vbom -serport_xontx.vbom -# design -serport_master.vhd diff --git a/rtl/vlib/serport/serport_uart_autobaud.vhd b/rtl/vlib/serport/serport_uart_autobaud.vhd index f07895b7..2abe3497 100644 --- a/rtl/vlib/serport/serport_uart_autobaud.vhd +++ b/rtl/vlib/serport/serport_uart_autobaud.vhd @@ -1,6 +1,6 @@ --- $Id: serport_uart_autobaud.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: serport_uart_autobaud.vhd 734 2016-02-20 22:43:20Z mueller $ -- --- Copyright 2007-2015 by Walter F.J. Mueller +-- Copyright 2007-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -28,6 +28,9 @@ -- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned -- 2007-06-30 62 1.0 Initial version ------------------------------------------------------------------------------ +-- Note: for test bench usage a copy of all serport_* entities, with _tb +-- appended to the name, has been created in the /tb sub folder. +-- Ensure to update the copy when this file is changed !! library ieee; use ieee.std_logic_1164.all; diff --git a/rtl/vlib/serport/serport_uart_rx.vhd b/rtl/vlib/serport/serport_uart_rx.vhd index 8adb456c..d5219d63 100644 --- a/rtl/vlib/serport/serport_uart_rx.vhd +++ b/rtl/vlib/serport/serport_uart_rx.vhd @@ -1,6 +1,6 @@ --- $Id: serport_uart_rx.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: serport_uart_rx.vhd 734 2016-02-20 22:43:20Z mueller $ -- --- Copyright 2007-2011 by Walter F.J. Mueller +-- Copyright 2007-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -41,6 +41,9 @@ -- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned -- 2007-06-30 62 1.0 Initial version ------------------------------------------------------------------------------ +-- Note: for test bench usage a copy of all serport_* entities, with _tb +-- appended to the name, has been created in the /tb sub folder. +-- Ensure to update the copy when this file is changed !! library ieee; use ieee.std_logic_1164.all; diff --git a/rtl/vlib/serport/serport_uart_rxtx.vhd b/rtl/vlib/serport/serport_uart_rxtx.vhd index 8facfbff..8282d9aa 100644 --- a/rtl/vlib/serport/serport_uart_rxtx.vhd +++ b/rtl/vlib/serport/serport_uart_rxtx.vhd @@ -1,6 +1,6 @@ --- $Id: serport_uart_rxtx.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: serport_uart_rxtx.vhd 734 2016-02-20 22:43:20Z mueller $ -- --- Copyright 2007-2011 by Walter F.J. Mueller +-- Copyright 2007-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -24,6 +24,9 @@ -- Date Rev Version Comment -- 2007-06-24 60 1.0 Initial version ------------------------------------------------------------------------------ +-- Note: for test bench usage a copy of all serport_* entities, with _tb +-- appended to the name, has been created in the /tb sub folder. +-- Ensure to update the copy when this file is changed !! library ieee; use ieee.std_logic_1164.all; diff --git a/rtl/vlib/serport/serport_uart_rxtx_ab.vhd b/rtl/vlib/serport/serport_uart_rxtx_ab.vhd index 04f7f25b..63d80cd5 100644 --- a/rtl/vlib/serport/serport_uart_rxtx_ab.vhd +++ b/rtl/vlib/serport/serport_uart_rxtx_ab.vhd @@ -1,6 +1,6 @@ --- $Id: serport_uart_rxtx_ab.vhd 666 2015-04-12 21:17:54Z mueller $ +-- $Id: serport_uart_rxtx_ab.vhd 734 2016-02-20 22:43:20Z mueller $ -- --- Copyright 2007-2015 by Walter F.J. Mueller +-- Copyright 2007-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -33,6 +33,9 @@ -- 2010-12-26 348 1.1 add ABCLKDIV port for clock divider setting -- 2007-06-24 60 1.0 Initial version ------------------------------------------------------------------------------ +-- Note: for test bench usage a copy of all serport_* entities, with _tb +-- appended to the name, has been created in the /tb sub folder. +-- Ensure to update the copy when this file is changed !! library ieee; use ieee.std_logic_1164.all; diff --git a/rtl/vlib/serport/serport_uart_tx.vhd b/rtl/vlib/serport/serport_uart_tx.vhd index 5daeafac..1ec37e12 100644 --- a/rtl/vlib/serport/serport_uart_tx.vhd +++ b/rtl/vlib/serport/serport_uart_tx.vhd @@ -1,6 +1,6 @@ --- $Id: serport_uart_tx.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: serport_uart_tx.vhd 734 2016-02-20 22:43:20Z mueller $ -- --- Copyright 2007-2011 by Walter F.J. Mueller +-- Copyright 2007-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -27,6 +27,9 @@ -- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned -- 2007-06-30 62 1.0 Initial version ------------------------------------------------------------------------------ +-- Note: for test bench usage a copy of all serport_* entities, with _tb +-- appended to the name, has been created in the /tb sub folder. +-- Ensure to update the copy when this file is changed !! library ieee; use ieee.std_logic_1164.all; diff --git a/rtl/vlib/serport/serport_xonrx.vhd b/rtl/vlib/serport/serport_xonrx.vhd index f2412b25..f8832deb 100644 --- a/rtl/vlib/serport/serport_xonrx.vhd +++ b/rtl/vlib/serport/serport_xonrx.vhd @@ -1,6 +1,6 @@ --- $Id: serport_xonrx.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: serport_xonrx.vhd 734 2016-02-20 22:43:20Z mueller $ -- --- Copyright 2011- by Walter F.J. Mueller +-- Copyright 2011-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -23,6 +23,9 @@ -- Date Rev Version Comment -- 2011-10-22 417 1.0 Initial version ------------------------------------------------------------------------------ +-- Note: for test bench usage a copy of all serport_* entities, with _tb +-- appended to the name, has been created in the /tb sub folder. +-- Ensure to update the copy when this file is changed !! library ieee; use ieee.std_logic_1164.all; diff --git a/rtl/vlib/serport/serport_xontx.vhd b/rtl/vlib/serport/serport_xontx.vhd index 980e1c17..3d014f50 100644 --- a/rtl/vlib/serport/serport_xontx.vhd +++ b/rtl/vlib/serport/serport_xontx.vhd @@ -1,6 +1,6 @@ --- $Id: serport_xontx.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: serport_xontx.vhd 734 2016-02-20 22:43:20Z mueller $ -- --- Copyright 2011- by Walter F.J. Mueller +-- Copyright 2011-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -24,6 +24,9 @@ -- 2011-11-13 425 1.0 Initial version -- 2011-10-22 417 0.5 First draft ------------------------------------------------------------------------------ +-- Note: for test bench usage a copy of all serport_* entities, with _tb +-- appended to the name, has been created in the /tb sub folder. +-- Ensure to update the copy when this file is changed !! library ieee; use ieee.std_logic_1164.all; diff --git a/rtl/vlib/serport/serportlib.vhd b/rtl/vlib/serport/serportlib.vhd index 3bfc5e52..127c9b76 100644 --- a/rtl/vlib/serport/serportlib.vhd +++ b/rtl/vlib/serport/serportlib.vhd @@ -1,6 +1,6 @@ --- $Id: serportlib.vhd 666 2015-04-12 21:17:54Z mueller $ +-- $Id: serportlib.vhd 724 2016-01-03 22:53:53Z mueller $ -- --- Copyright 2007-2015 by Walter F.J. Mueller +-- Copyright 2007-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -32,6 +32,9 @@ -- 2007-10-22 88 1.1 renames (in prev revs); remove std_logic_unsigned -- 2007-06-03 45 1.0 Initial version ------------------------------------------------------------------------------ +-- Note: for test bench usage a copy of all serport_* entities, with -tb +-- appended to the name, has been created in the /tb sub folder. +-- Ensure to update the copy when this file is changed !! library ieee; use ieee.std_logic_1164.all; diff --git a/rtl/vlib/serport/tb/.cvsignore b/rtl/vlib/serport/tb/.cvsignore index cfec62b6..6ef5b60b 100644 --- a/rtl/vlib/serport/tb/.cvsignore +++ b/rtl/vlib/serport/tb/.cvsignore @@ -1,15 +1,6 @@ tb_serport_autobaud tb_serport_autobaud_stim -tb_serport_autobaud_[sft]sim -tb_serport_autobaud_ISim -tb_serport_autobaud_ISim_[sft]sim tb_serport_uart_rx tb_serport_uart_rx_stim -tb_serport_uart_rx_[sft]sim -tb_serport_uart_rx_ISim -tb_serport_uart_rx_ISim_[sft]sim tb_serport_uart_rxtx tb_serport_uart_rxtx_stim -tb_serport_uart_rxtx_[sft]sim -tb_serport_uart_rxtx_ISim -tb_serport_uart_rxtx_ISim_[sft]sim diff --git a/rtl/vlib/serport/tb/Makefile b/rtl/vlib/serport/tb/Makefile.ise similarity index 76% rename from rtl/vlib/serport/tb/Makefile rename to rtl/vlib/serport/tb/Makefile.ise index f403fdd7..5b4b7b07 100644 --- a/rtl/vlib/serport/tb/Makefile +++ b/rtl/vlib/serport/tb/Makefile.ise @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile.ise 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -16,7 +16,7 @@ EXE_all += tb_serport_autobaud ifndef XTW_BOARD XTW_BOARD=nexys3 endif -include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk +include ${RETROBASE}/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # .PHONY : all all_ssim all_tsim clean # @@ -28,9 +28,9 @@ clean : ise_clean ghdl_clean isim_clean # #----- # -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk -include $(RETROBASE)/rtl/make_ise/generic_isim.mk -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_isim.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/vlib/serport/tb/serport_master_tb.vbom b/rtl/vlib/serport/tb/serport_master_tb.vbom new file mode 100644 index 00000000..52d61bb7 --- /dev/null +++ b/rtl/vlib/serport/tb/serport_master_tb.vbom @@ -0,0 +1,8 @@ +# libs +../../slvtypes.vhd +# components +serport_uart_rxtx_tb.vbom +serport_xonrx_tb.vbom +serport_xontx_tb.vbom +# design +serport_master_tb.vhd diff --git a/rtl/vlib/serport/serport_master.vhd b/rtl/vlib/serport/tb/serport_master_tb.vhd similarity index 79% rename from rtl/vlib/serport/serport_master.vhd rename to rtl/vlib/serport/tb/serport_master_tb.vhd index c21776b6..ac833797 100644 --- a/rtl/vlib/serport/serport_master.vhd +++ b/rtl/vlib/serport/tb/serport_master_tb.vhd @@ -1,6 +1,6 @@ --- $Id: serport_master.vhd 666 2015-04-12 21:17:54Z mueller $ +-- $Id: serport_master_tb.vhd 724 2016-01-03 22:53:53Z mueller $ -- --- Copyright 2015- by Walter F.J. Mueller +-- Copyright 2015-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -12,23 +12,20 @@ -- for complete details. -- ------------------------------------------------------------------------------ --- Module Name: serport_master - syn --- Description: serial port: serial port module, master side +-- Module Name: serport_master_tb - sim +-- Description: serial port: serial port module, master side (SIM only!) -- --- Dependencies: serport_uart_rxtx_ab --- serport_xonrx --- serport_xontx +-- Dependencies: serport_uart_rxtx_ab_tb +-- serport_xonrx_tb +-- serport_xontx_tb -- Test bench: - -- Target Devices: generic --- Tool versions: ise 14.7; viv 2014.4; ghdl 0.31 --- --- Synthesized (xst): --- Date Rev ise Target flop lutl lutm slic t peri --- 2015-04-12 666 14.7 131013 xc6slx16-2 104 171 0 63 s 6.4 +-- Tool versions: ghdl 0.31 -- -- Revision History: -- Date Rev Version Comment --- 2015-04-12 666 1.0 Initial version +-- 2016-01-03 724 1.0 Initial version (copied from serport_master) + ------------------------------------------------------------------------------ library ieee; @@ -36,9 +33,8 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.slvtypes.all; -use work.serportlib.all; -entity serport_master is -- serial port module, 1 clock domain +entity serport_master_tb is -- serial port module, 1 clock domain generic ( CDWIDTH : positive := 13); -- clk divider width port ( @@ -59,10 +55,10 @@ entity serport_master is -- serial port module, 1 clock domain RXRTS_N : out slbit; -- receive rts (uart view, act.low) TXCTS_N : in slbit := '0' -- transmit cts (uart view, act.low) ); -end serport_master; +end serport_master_tb; -architecture syn of serport_master is +architecture sim of serport_master_tb is signal UART_RXDATA : slv8 := (others=>'0'); signal UART_RXVAL : slbit := '0'; @@ -77,7 +73,7 @@ architecture syn of serport_master is begin - UART : serport_uart_rxtx -- uart, rx+tx combo + UART : entity work.serport_uart_rxtx_tb -- uart, rx+tx combo generic map ( CDWIDTH => CDWIDTH) port map ( @@ -95,7 +91,7 @@ begin TXBUSY => UART_TXBUSY ); - XONRX : serport_xonrx -- xon/xoff logic rx path + XONRX : entity work.serport_xonrx_tb -- xon/xoff logic rx path port map ( CLK => CLK, RESET => RESET, @@ -110,7 +106,7 @@ begin TXOK => TXOK ); - XONTX : serport_xontx -- xon/xoff logic tx path + XONTX : entity work.serport_xontx_tb -- xon/xoff logic tx path port map ( CLK => CLK, RESET => RESET, @@ -139,4 +135,4 @@ begin end if; end process proc_cts; -end syn; +end sim; diff --git a/rtl/vlib/serport/tb/serport_uart_rx_tb.vbom b/rtl/vlib/serport/tb/serport_uart_rx_tb.vbom new file mode 100644 index 00000000..c52aba3c --- /dev/null +++ b/rtl/vlib/serport/tb/serport_uart_rx_tb.vbom @@ -0,0 +1,4 @@ +# libs +../../slvtypes.vhd +# design +serport_uart_rx_tb.vhd diff --git a/rtl/vlib/serport/tb/serport_uart_rx_tb.vhd b/rtl/vlib/serport/tb/serport_uart_rx_tb.vhd new file mode 100644 index 00000000..8a89f1ad --- /dev/null +++ b/rtl/vlib/serport/tb/serport_uart_rx_tb.vhd @@ -0,0 +1,295 @@ +-- $Id: serport_uart_rx_tb.vhd 724 2016-01-03 22:53:53Z mueller $ +-- +-- Copyright 2007-2016 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +-- The uart expects CLKDIV+1 wide input bit symbols. +-- This implementation counts the number of 1's in the first CLKDIV clock +-- cycles, and checks in the last cycle of the symbol time whether the +-- number of 1's was > CLKDIV/2. This supresses short glitches nicely, +-- especially for larger clock dividers. +-- +------------------------------------------------------------------------------ +-- Module Name: serport_uart_rx_tb - sim +-- Description: serial port UART - receiver (SIM only!) +-- +-- Dependencies: - +-- Target Devices: generic +-- Tool versions: ghdl 0.18-0.31 +-- Revision History: +-- Date Rev Version Comment +-- 2016-01-03 724 1.0 Initial version (copied from serport_uart_rx) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; + +entity serport_uart_rx_tb is -- serial port uart: receive part + generic ( + CDWIDTH : positive := 13); -- clk divider width + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting + RXSD : in slbit; -- receive serial data (uart view) + RXDATA : out slv8; -- receiver data out + RXVAL : out slbit; -- receiver data valid + RXERR : out slbit; -- receiver data error (frame error) + RXACT : out slbit -- receiver active + ); +end serport_uart_rx_tb; + + +architecture sim of serport_uart_rx_tb is + + type state_type is ( + s_idle, -- s_idle: idle + s_colb0, -- s_colb0: collect b0 (start bit) + s_endb0, -- s_endb0: finish b0 (start bit) + s_colbx, -- s_colbx: collect bx + s_endbx, -- s_endbx: finish bx + s_colb9, -- s_colb9: collect bx (stop bit) + s_endb9 -- s_endb9: finish bx (stop bit) + ); + + type regs_type is record + state : state_type; -- state + ccnt : slv(CDWIDTH-1 downto 0); -- clock divider counter + dcnt : slv(CDWIDTH downto 0); -- data '1' counter + bcnt : slv4; -- bit counter + sreg : slv8; -- input shift register + end record regs_type; + + constant ccntzero : slv(CDWIDTH-1 downto 0) := (others=>'0'); + constant dcntzero : slv(CDWIDTH downto 0) := (others=>'0'); + constant regs_init : regs_type := ( + s_idle, -- state + ccntzero, -- ccnt + dcntzero, -- dcnt + (others=>'0'), -- bcnt + (others=>'0') -- sreg + ); + + signal R_REGS : regs_type := regs_init; -- state registers + signal N_REGS : regs_type := regs_init; -- next value state regs + +begin + + proc_regs: process (CLK) + begin + + if rising_edge(CLK) then + R_REGS <= N_REGS; + end if; + + end process proc_regs; + + proc_next: process (R_REGS, RESET, CLKDIV, RXSD) + + variable r : regs_type := regs_init; + variable n : regs_type := regs_init; + + variable dbit : slbit := '0'; + variable ld_ccnt : slbit := '0'; + variable tc_ccnt : slbit := '0'; + variable tc_bcnt : slbit := '0'; + variable ld_dcnt : slbit := '0'; + variable ld_bcnt : slbit := '0'; + variable ce_bcnt : slbit := '0'; + variable iact : slbit := '0'; + variable ival : slbit := '0'; + variable ierr : slbit := '0'; + + begin + + r := R_REGS; + n := R_REGS; + + dbit := '0'; + ld_ccnt := '0'; + tc_ccnt := '0'; + tc_bcnt := '0'; + ld_dcnt := '0'; + ld_bcnt := '0'; + ce_bcnt := '0'; + iact := '1'; + ival := '0'; + ierr := '0'; + + if unsigned(r.ccnt) = 0 then + tc_ccnt := '1'; + end if; + if unsigned(r.bcnt) = 9 then + tc_bcnt := '1'; + end if; + + if unsigned(r.dcnt) > unsigned("00" & CLKDIV(CDWIDTH-1 downto 1)) then + dbit := '1'; + end if; + + case r.state is + + when s_idle => -- s_idle: idle ---------------------- + iact := '0'; + ld_dcnt := '1'; -- always keep dcnt in reset + if RXSD = '0' then -- if start bit seen + if tc_ccnt = '1' then + n.state := s_endb0; -- finish b0 + ld_ccnt := '1'; -- start next bit + ce_bcnt := '1'; + else + n.state := s_colb0; -- collect b0 + end if; + else -- otherwise + ld_ccnt := '1'; -- keep all counters in reset + ld_bcnt := '1'; + end if; + + when s_colb0 => -- s_colb0: collect b0 (start bit) --- + if tc_ccnt = '1' then -- last cycle of b0 ? + n.state := s_endb0; -- finish b0 + ld_ccnt := '1'; -- " + ce_bcnt := '1'; + else -- continue in b0 ? + if dbit='1' and RXSD='1' then -- too many 1's ? + n.state := s_idle; -- abort to idle + ld_dcnt := '1'; -- put counters in reset + ld_ccnt := '1'; + ld_bcnt := '1'; + end if; + end if; + + when s_endb0 => -- s_endb0: finish b0 (start bit) --- + ld_dcnt := '1'; -- start next bit + if dbit = '1' then -- was it a 1 ? + n.state := s_idle; -- abort to idle + ld_ccnt := '1'; -- put counters in reset + ld_bcnt := '1'; + else + if tc_ccnt = '1' then -- last cycle of bx ? + n.state := s_endbx; -- finish bx + ld_ccnt := '1'; + ce_bcnt := '1'; + else -- continue in b0 ? + n.state := s_colbx; -- collect bx + end if; + end if; + + when s_colbx => -- s_colbx: collect bx --------------- + if tc_ccnt = '1' then -- last cycle of bx ? + n.state := s_endbx; -- finish bx + ld_ccnt := '1'; + ce_bcnt := '1'; + end if; + + when s_endbx => -- s_endbx: finish bx --------------- + ld_dcnt := '1'; -- start next bit + n.sreg := dbit & r.sreg(7 downto 1); + if tc_ccnt = '1' then -- last cycle of bx ? + if tc_bcnt = '1' then + n.state := s_endb9; -- finish b9 + ld_bcnt := '1'; -- and wrap bcnt + else + n.state := s_endbx; -- finish bx + ce_bcnt := '1'; + end if; + ld_ccnt := '1'; + else -- continue in bx ? + if tc_bcnt = '1' then + n.state := s_colb9; -- collect b9 + else + n.state := s_colbx; -- collect bx + end if; + end if; + + when s_colb9 => -- s_colb9: collect bx (stop bit) ---- + if tc_ccnt = '1' then -- last cycle of b9 ? + n.state := s_endb9; -- finish b9 + ld_ccnt := '1'; -- " + ld_bcnt := '1'; -- and wrap bcnt + else -- continue in b9 ? + if dbit='1' and RXSD='1' then -- already enough 1's ? + n.state := s_idle; -- finish to idle + ld_dcnt := '1'; -- put counters in reset + ld_ccnt := '1'; + ld_bcnt := '1'; + ival := '1'; + end if; + end if; + + when s_endb9 => -- s_endb9: finish bx (stop bit) ---- + ld_dcnt := '1'; -- start next bit + if dbit = '1' then -- was it a valid stop bit ? + ival := '1'; + else + ierr := '1'; + end if; + if RXSD = '1' then -- line in idle state ? + n.state := s_idle; -- finish to idle state + ld_ccnt := '1'; -- and put counters in reset + ld_bcnt := '1'; -- " + else + if tc_ccnt = '1' then -- last cycle of b9 ? + n.state := s_endb0; -- finish b0 + ld_ccnt := '1'; -- " + ce_bcnt := '1'; + else -- continue in b0 ? + n.state := s_colb0; -- collect bx + end if; + end if; + + when others => null; -- ----------------------------------- + + end case; + + if RESET = '1' then -- RESET seen + ld_ccnt := '1'; -- keep all counters in reset + ld_dcnt := '1'; + ld_bcnt := '1'; + n.state := s_idle; + end if; + + if ld_ccnt = '1' then -- implement ccnt + n.ccnt := CLKDIV; + else + n.ccnt := slv(unsigned(r.ccnt) - 1); + end if; + + if ld_dcnt = '1' then -- implement dcnt + n.dcnt(CDWIDTH downto 1) := (others=>'0'); + n.dcnt(0) := RXSD; + else + if RXSD = '1' then + n.dcnt := slv(unsigned(r.dcnt) + 1); + end if; + end if; + + if ld_bcnt = '1' then -- implement bcnt + n.bcnt := (others=>'0'); + else + if ce_bcnt = '1' then + n.bcnt := slv(unsigned(r.bcnt) + 1); + end if; + end if; + + N_REGS <= n; + + RXDATA <= r.sreg; + RXACT <= iact; + RXVAL <= ival; + RXERR <= ierr; + + end process proc_next; + +end sim; diff --git a/rtl/vlib/serport/tb/serport_uart_rxtx_tb.vbom b/rtl/vlib/serport/tb/serport_uart_rxtx_tb.vbom new file mode 100644 index 00000000..85074324 --- /dev/null +++ b/rtl/vlib/serport/tb/serport_uart_rxtx_tb.vbom @@ -0,0 +1,7 @@ +# libs +../../slvtypes.vhd +# components +serport_uart_rx_tb.vbom +serport_uart_tx_tb.vbom +# design +serport_uart_rxtx_tb.vhd diff --git a/rtl/vlib/serport/tb/serport_uart_rxtx_tb.vhd b/rtl/vlib/serport/tb/serport_uart_rxtx_tb.vhd new file mode 100644 index 00000000..18346b7f --- /dev/null +++ b/rtl/vlib/serport/tb/serport_uart_rxtx_tb.vhd @@ -0,0 +1,83 @@ +-- $Id: serport_uart_rxtx_tb.vhd 724 2016-01-03 22:53:53Z mueller $ +-- +-- Copyright 2007-2016 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: serport_uart_rxtx_tb - syn +-- Description: serial port UART - transmitter + receiver (SIM only!) +-- +-- Dependencies: serport_uart_rx_tb +-- serport_uart_tx_tb +-- Target Devices: generic +-- Tool versions: ghdl 0.18-0.31 +-- Revision History: +-- Date Rev Version Comment +-- 2016-01-03 724 1.0 Initial version (copied from serport_uart_rxtx) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; + +entity serport_uart_rxtx_tb is -- serial port uart: rx+tx combo + generic ( + CDWIDTH : positive := 13); -- clk divider width + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting + RXSD : in slbit; -- receive serial data (uart view) + RXDATA : out slv8; -- receiver data out + RXVAL : out slbit; -- receiver data valid + RXERR : out slbit; -- receiver data error (frame error) + RXACT : out slbit; -- receiver active + TXSD : out slbit; -- transmit serial data (uart view) + TXDATA : in slv8; -- transmit data in + TXENA : in slbit; -- transmit data enable + TXBUSY : out slbit -- transmit busy + ); +end serport_uart_rxtx_tb; + +architecture sim of serport_uart_rxtx_tb is + +begin + + RX : entity work.serport_uart_rx_tb + generic map ( + CDWIDTH => CDWIDTH) + port map ( + CLK => CLK, + RESET => RESET, + CLKDIV => CLKDIV, + RXSD => RXSD, + RXDATA => RXDATA, + RXVAL => RXVAL, + RXERR => RXERR, + RXACT => RXACT + ); + + TX : entity work.serport_uart_tx_tb + generic map ( + CDWIDTH => CDWIDTH) + port map ( + CLK => CLK, + RESET => RESET, + CLKDIV => CLKDIV, + TXSD => TXSD, + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY + ); + +end sim; diff --git a/rtl/vlib/serport/tb/serport_uart_tx_tb.vbom b/rtl/vlib/serport/tb/serport_uart_tx_tb.vbom new file mode 100644 index 00000000..50acf3ec --- /dev/null +++ b/rtl/vlib/serport/tb/serport_uart_tx_tb.vbom @@ -0,0 +1,4 @@ +# libs +../../slvtypes.vhd +# design +serport_uart_tx_tb.vhd diff --git a/rtl/vlib/serport/tb/serport_uart_tx_tb.vhd b/rtl/vlib/serport/tb/serport_uart_tx_tb.vhd new file mode 100644 index 00000000..4846fc8a --- /dev/null +++ b/rtl/vlib/serport/tb/serport_uart_tx_tb.vhd @@ -0,0 +1,128 @@ +-- $Id: serport_uart_tx_tb.vhd 724 2016-01-03 22:53:53Z mueller $ +-- +-- Copyright 2007-2016 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: serport_uart_tx_tb - sim +-- Description: serial port UART - transmitter (SIM only!) +-- +-- Dependencies: - +-- Target Devices: generic +-- Tool versions: ghdl 0.18-0.31 +-- Revision History: +-- Date Rev Version Comment +-- 2016-01-03 724 1.0 Initial version (copied from serport_uart_tx) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; + +entity serport_uart_tx_tb is -- serial port uart: transmit part + generic ( + CDWIDTH : positive := 13); -- clk divider width + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting + TXSD : out slbit; -- transmit serial data (uart view) + TXDATA : in slv8; -- transmit data in + TXENA : in slbit; -- transmit data enable + TXBUSY : out slbit -- transmit busy + ); +end serport_uart_tx_tb; + + +architecture sim of serport_uart_tx_tb is + + type regs_type is record + ccnt : slv(CDWIDTH-1 downto 0); -- clock divider counter + bcnt : slv4; -- bit counter + sreg : slv9; -- output shift register + busy : slbit; + end record regs_type; + + constant cntzero : slv(CDWIDTH-1 downto 0) := (others=>'0'); + constant regs_init : regs_type := ( + cntzero, + (others=>'0'), + (others=>'1'), -- sreg to all 1 !! + '0' + ); + + signal R_REGS : regs_type := regs_init; -- state registers + signal N_REGS : regs_type := regs_init; -- next value state regs + +begin + + proc_regs: process (CLK) + begin + + if rising_edge(CLK) then + R_REGS <= N_REGS; + end if; + + end process proc_regs; + + proc_next: process (R_REGS, RESET, CLKDIV, TXDATA, TXENA) + + variable r : regs_type := regs_init; + variable n : regs_type := regs_init; + variable ld_ccnt : slbit := '0'; + + begin + + r := R_REGS; + n := R_REGS; + ld_ccnt := '0'; + + if r.busy = '0' then + ld_ccnt := '1'; + n.bcnt := (others=>'0'); + if TXENA = '1' then + n.sreg := TXDATA & '0'; -- add start (0) bit + n.busy := '1'; + end if; + + else + + if unsigned(r.ccnt) = 0 then + ld_ccnt := '1'; + n.sreg := '1' & r.sreg(8 downto 1); + n.bcnt := slv(unsigned(r.bcnt) + 1); + if unsigned(r.bcnt) = 9 then -- if 10 bits send + n.busy := '0'; -- declare all done + end if; + end if; + end if; + + if RESET = '1' then + ld_ccnt := '1'; + n.busy := '0'; + end if; + + if ld_ccnt = '1' then + n.ccnt := CLKDIV; + else + n.ccnt := slv(unsigned(r.ccnt) - 1); + end if; + + N_REGS <= n; + + TXBUSY <= r.busy; + TXSD <= r.sreg(0); + + end process proc_next; + +end sim; diff --git a/rtl/vlib/serport/tb/serport_xonrx_tb.vbom b/rtl/vlib/serport/tb/serport_xonrx_tb.vbom new file mode 100644 index 00000000..0917bb3f --- /dev/null +++ b/rtl/vlib/serport/tb/serport_xonrx_tb.vbom @@ -0,0 +1,5 @@ +# libs +../../slvtypes.vhd +serportlib_tb.vhd +# design +serport_xonrx_tb.vhd diff --git a/rtl/vlib/serport/tb/serport_xonrx_tb.vhd b/rtl/vlib/serport/tb/serport_xonrx_tb.vhd new file mode 100644 index 00000000..bf69fafa --- /dev/null +++ b/rtl/vlib/serport/tb/serport_xonrx_tb.vhd @@ -0,0 +1,144 @@ +-- $Id: serport_xonrx_tb.vhd 724 2016-01-03 22:53:53Z mueller $ +-- +-- Copyright 2011-2016 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: serport_xonrx_tb - sim +-- Description: serial port: xon/xoff logic rx path (SIM only!) +-- +-- Dependencies: - +-- Test bench: - +-- Target Devices: generic +-- Tool versions: ghdl 0.29-0.31 +-- Revision History: +-- Date Rev Version Comment +-- 2016-01-03 724 1.0 Initial version (copied from serport_xonrx) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.serportlib_tb.all; + +entity serport_xonrx_tb is -- serial port: xon/xoff logic rx path + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + ENAXON : in slbit; -- enable xon/xoff handling + ENAESC : in slbit; -- enable xon/xoff escaping + UART_RXDATA : in slv8; -- uart data out + UART_RXVAL : in slbit; -- uart data valid + RXDATA : out slv8; -- user data out + RXVAL : out slbit; -- user data valid + RXHOLD : in slbit; -- user data hold + RXOVR : out slbit; -- user data overrun + TXOK : out slbit -- tx channel ok + ); +end serport_xonrx_tb; + + +architecture sim of serport_xonrx_tb is + + type regs_type is record + txok : slbit; -- tx channel ok state + escseen : slbit; -- escape seen + rxdata : slv8; -- user rxdata + rxval : slbit; -- user rxval + rxovr : slbit; -- user rxovr + end record regs_type; + + constant regs_init : regs_type := ( + '1', -- txok (startup default is ok !!) + '0', -- escseen + (others=>'0'), -- rxdata + '0','0' -- rxval,rxovr + ); + + signal R_REGS : regs_type := regs_init; -- state registers + signal N_REGS : regs_type := regs_init; -- next value state regs + +begin + + proc_regs: process (CLK) + begin + + if rising_edge(CLK) then + if RESET = '1' then + R_REGS <= regs_init; + else + R_REGS <= N_REGS; + end if; + end if; + + end process proc_regs; + + proc_next: process (R_REGS, ENAXON, ENAESC, UART_RXDATA, UART_RXVAL, RXHOLD) + + variable r : regs_type := regs_init; + variable n : regs_type := regs_init; + + begin + + r := R_REGS; + n := R_REGS; + + if ENAXON = '0' then + n.txok := '1'; + end if; + if ENAESC = '0' then + n.escseen := '0'; + end if; + + n.rxovr := '0'; -- ensure single clock pulse + + if UART_RXVAL = '1' then + if ENAXON='1' and UART_RXDATA=c_serport_xon then + n.txok := '1'; + elsif ENAXON='1' and UART_RXDATA=c_serport_xoff then + n.txok := '0'; + elsif ENAESC='1' and UART_RXDATA=c_serport_xesc then + n.escseen := '1'; + + else + if r.escseen = '1' then + n.escseen := '0'; + end if; + + if r.rxval = '0' then + n.rxval := '1'; + if r.escseen = '1' then + n.rxdata := not UART_RXDATA; + else + n.rxdata := UART_RXDATA; + end if; + else + n.rxovr := '1'; + end if; + end if; + end if; + + if r.rxval='1' and RXHOLD='0' then + n.rxval := '0'; + end if; + + N_REGS <= n; + + RXDATA <= r.rxdata; + RXVAL <= r.rxval; + RXOVR <= r.rxovr; + TXOK <= r.txok; + + end process proc_next; + +end sim; diff --git a/rtl/vlib/serport/tb/serport_xontx_tb.vbom b/rtl/vlib/serport/tb/serport_xontx_tb.vbom new file mode 100644 index 00000000..d9153ddb --- /dev/null +++ b/rtl/vlib/serport/tb/serport_xontx_tb.vbom @@ -0,0 +1,5 @@ +# libs +../../slvtypes.vhd +serportlib_tb.vhd +# design +serport_xontx_tb.vhd diff --git a/rtl/vlib/serport/tb/serport_xontx_tb.vhd b/rtl/vlib/serport/tb/serport_xontx_tb.vhd new file mode 100644 index 00000000..b511cfdb --- /dev/null +++ b/rtl/vlib/serport/tb/serport_xontx_tb.vhd @@ -0,0 +1,156 @@ +-- $Id: serport_xontx_tb.vhd 724 2016-01-03 22:53:53Z mueller $ +-- +-- Copyright 2011-2016 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: serport_xontx_tb - sim +-- Description: serial port: xon/xoff logic tx path (SIM only!) +-- +-- Dependencies: - +-- Test bench: - +-- Target Devices: generic +-- Tool versions: ghdl 0.29-0.31 +-- Revision History: +-- Date Rev Version Comment +-- 2016-01-03 724 1.0 Initial version (copied from serport_xontx) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.serportlib_tb.all; + +entity serport_xontx_tb is -- serial port: xon/xoff logic tx path + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + ENAXON : in slbit; -- enable xon/xoff handling + ENAESC : in slbit; -- enable xon/xoff escaping + UART_TXDATA : out slv8; -- uart data in + UART_TXENA : out slbit; -- uart data enable + UART_TXBUSY : in slbit; -- uart data busy + TXDATA : in slv8; -- user data in + TXENA : in slbit; -- user data enable + TXBUSY : out slbit; -- user data busy + RXOK : in slbit; -- rx channel ok + TXOK : in slbit -- tx channel ok + ); +end serport_xontx_tb; + + +architecture sim of serport_xontx_tb is + + type regs_type is record + ibuf : slv8; -- input buffer + ival : slbit; -- ibuf has valid data + obuf : slv8; -- output buffer + oval : slbit; -- obuf has valid data + rxok : slbit; -- rx channel ok state + enaxon_1 : slbit; -- last enaxon + escpend : slbit; -- escape pending + end record regs_type; + + constant regs_init : regs_type := ( + (others=>'0'),'0', -- ibuf,ival + (others=>'0'),'0', -- obuf,oval + '1', -- rxok (startup default is ok !!) + '0', -- enaxon_1 + '0' -- escpend + ); + + signal R_REGS : regs_type := regs_init; -- state registers + signal N_REGS : regs_type := regs_init; -- next value state regs + +begin + + proc_regs: process (CLK) + begin + + if rising_edge(CLK) then + if RESET = '1' then + R_REGS <= regs_init; + else + R_REGS <= N_REGS; + end if; + end if; + + end process proc_regs; + + proc_next: process (R_REGS, ENAXON, ENAESC, UART_TXBUSY, + TXDATA, TXENA, RXOK, TXOK) + + variable r : regs_type := regs_init; + variable n : regs_type := regs_init; + + begin + + r := R_REGS; + n := R_REGS; + + if TXENA='1' and r.ival='0' then + n.ibuf := TXDATA; + n.ival := '1'; + end if; + + if r.oval = '0' then + if ENAXON='1' and r.rxok/=RXOK then + n.rxok := RXOK; + n.oval := '1'; + if r.rxok = '0' then + n.obuf := c_serport_xon; + else + n.obuf := c_serport_xoff; + end if; + elsif TXOK = '1' then + if r.escpend = '1' then + n.obuf := not r.ibuf; + n.oval := '1'; + n.escpend := '0'; + n.ival := '0'; + elsif r.ival = '1' then + if ENAESC='1' and (r.ibuf=c_serport_xon or + r.ibuf=c_serport_xoff or + r.ibuf=c_serport_xesc) + then + n.obuf := c_serport_xesc; + n.oval := '1'; + n.escpend := '1'; + else + n.obuf := r.ibuf; + n.oval := '1'; + n.ival := '0'; + end if; + end if; + end if; + end if; + + if r.oval='1' and UART_TXBUSY='0' then + n.oval := '0'; + end if; + + -- FIXME: document this hack + n.enaxon_1 := ENAXON; + if ENAXON='1' and r.enaxon_1='0' then + n.rxok := not RXOK; + end if; + + N_REGS <= n; + + TXBUSY <= r.ival; + UART_TXDATA <= r.obuf; + UART_TXENA <= r.oval; + + end process proc_next; + +end sim; diff --git a/rtl/vlib/serport/tb/serportlib_tb.vhd b/rtl/vlib/serport/tb/serportlib_tb.vhd new file mode 100644 index 00000000..da89f7f7 --- /dev/null +++ b/rtl/vlib/serport/tb/serportlib_tb.vhd @@ -0,0 +1,40 @@ +-- $Id: serportlib_tb.vhd 724 2016-01-03 22:53:53Z mueller $ +-- +-- Copyright 2007-2016 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: serportlib_tb +-- Description: serial port interface components (SIM only!) +-- +-- Dependencies: - +-- Tool versions: ghdl 0.18-0.31 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2016-01-03 724 1.0 Initial version (copied from serportlib) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package serportlib_tb is + + -- here only constant definitions + -- no component defintions, use direct instantiation ! + + constant c_serport_xon : slv8 := "00010001"; -- char xon: ^Q = hex 11 + constant c_serport_xoff : slv8 := "00010011"; -- char xoff ^S = hex 13 + constant c_serport_xesc : slv8 := "00011011"; -- char xesc ^[ = ESC = hex 1B + +end package serportlib_tb; diff --git a/rtl/vlib/serport/tb/tb_serport_autobaud.vbom b/rtl/vlib/serport/tb/tb_serport_autobaud.vbom index 069526b3..d0760d6a 100644 --- a/rtl/vlib/serport/tb/tb_serport_autobaud.vbom +++ b/rtl/vlib/serport/tb/tb_serport_autobaud.vbom @@ -5,6 +5,6 @@ # components ../../simlib/simclk.vbom ../../simlib/simclkcnt.vbom -${tbd_serport_autobaud := tbd_serport_autobaud.vbom} +@uut: ${uut := tbd_serport_autobaud.vbom} # design tb_serport_autobaud.vhd diff --git a/rtl/vlib/serport/tb/tb_serport_autobaud_ssim.vbom b/rtl/vlib/serport/tb/tb_serport_autobaud_ssim.vbom index c68eeb90..86a6bb84 100644 --- a/rtl/vlib/serport/tb/tb_serport_autobaud_ssim.vbom +++ b/rtl/vlib/serport/tb/tb_serport_autobaud_ssim.vbom @@ -1,4 +1,4 @@ # configure for _*sim case -tbd_serport_autobaud = tbd_serport_autobaud_ssim.vhd +uut = tbd_serport_autobaud_ssim.vhd tb_serport_autobaud.vbom @top:tb_serport_autobaud diff --git a/rtl/vlib/serport/tb/tb_serport_uart_rx.vbom b/rtl/vlib/serport/tb/tb_serport_uart_rx.vbom index 746e6439..9618919b 100644 --- a/rtl/vlib/serport/tb/tb_serport_uart_rx.vbom +++ b/rtl/vlib/serport/tb/tb_serport_uart_rx.vbom @@ -5,6 +5,6 @@ # components ../../simlib/simclk.vbom ../../simlib/simclkcnt.vbom -${tbd_serport_uart_rx := tbd_serport_uart_rx.vbom} +@uut: ${uut := tbd_serport_uart_rx.vbom} # design tb_serport_uart_rx.vhd diff --git a/rtl/vlib/serport/tb/tb_serport_uart_rx_ssim.vbom b/rtl/vlib/serport/tb/tb_serport_uart_rx_ssim.vbom index 75ec6933..c18f18f8 100644 --- a/rtl/vlib/serport/tb/tb_serport_uart_rx_ssim.vbom +++ b/rtl/vlib/serport/tb/tb_serport_uart_rx_ssim.vbom @@ -1,4 +1,4 @@ # configure for _*sim case -tbd_serport_uart_rx = tbd_serport_uart_rx_ssim.vhd +uut = tbd_serport_uart_rx_ssim.vhd tb_serport_uart_rx.vbom @top:tb_serport_uart_rx diff --git a/rtl/vlib/serport/tb/tb_serport_uart_rxtx.vbom b/rtl/vlib/serport/tb/tb_serport_uart_rxtx.vbom index 98c3fca1..d960e188 100644 --- a/rtl/vlib/serport/tb/tb_serport_uart_rxtx.vbom +++ b/rtl/vlib/serport/tb/tb_serport_uart_rxtx.vbom @@ -5,6 +5,6 @@ # components ../../simlib/simclk.vbom ../../simlib/simclkcnt.vbom -${tbd_serport_uart_rxtx := tbd_serport_uart_rxtx.vbom} +@uut: ${uut := tbd_serport_uart_rxtx.vbom} # design tb_serport_uart_rxtx.vhd diff --git a/rtl/vlib/serport/tb/tb_serport_uart_rxtx_ssim.vbom b/rtl/vlib/serport/tb/tb_serport_uart_rxtx_ssim.vbom index 02225ee8..3e8c2dc2 100644 --- a/rtl/vlib/serport/tb/tb_serport_uart_rxtx_ssim.vbom +++ b/rtl/vlib/serport/tb/tb_serport_uart_rxtx_ssim.vbom @@ -1,4 +1,4 @@ # configure for _*sim case -tbd_serport_uart_rxtx = tbd_serport_uart_rxtx_ssim.vhd +uut = tbd_serport_uart_rxtx_ssim.vhd tb_serport_uart_rxtx.vbom @top:tb_serport_uart_rxtx diff --git a/rtl/vlib/xlib/Makefile b/rtl/vlib/xlib/Makefile index 0e34fb72..fe839b03 100644 --- a/rtl/vlib/xlib/Makefile +++ b/rtl/vlib/xlib/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version omment @@ -13,7 +13,7 @@ NGC_all = $(VBOM_all:.vbom=.ngc) ifndef XTW_BOARD XTW_BOARD=nexys3 endif -include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk +include ${RETROBASE}/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # .PHONY : all clean # @@ -23,7 +23,7 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/vlib/xlib/s7_cmt_sfs_gsim.vhd b/rtl/vlib/xlib/s7_cmt_sfs_gsim.vhd index 7411e00a..e38a3e76 100644 --- a/rtl/vlib/xlib/s7_cmt_sfs_gsim.vhd +++ b/rtl/vlib/xlib/s7_cmt_sfs_gsim.vhd @@ -1,4 +1,4 @@ --- $Id: s7_cmt_sfs_gsim.vhd 675 2015-05-08 21:05:08Z mueller $ +-- $Id: s7_cmt_sfs_gsim.vhd 734 2016-02-20 22:43:20Z mueller $ -- -- Copyright 2013- by Walter F.J. Mueller -- @@ -19,12 +19,15 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic Series-7 --- Tool versions: xst 14.5; viv 2014.4; ghdl 0.29 +-- Tool versions: xst 14.5-14.7; viv 2014.4-2015.4; ghdl 0.29-0.31 -- -- Revision History: -- Date Rev Version Comment -- 2013-09-28 535 1.0 Initial version (derived from dcm_sfs_gsim) ------------------------------------------------------------------------------ +-- Note: for test bench usage a copy of s7_cmt_sfs_gsim, with _tb instead +-- of _gsim in file name, has been created in the /tb sub folder. +-- Ensure to update the copy when this file is changed !! library ieee; use ieee.std_logic_1164.all; diff --git a/rtl/vlib/xlib/tb/.cvsignore b/rtl/vlib/xlib/tb/.cvsignore new file mode 100644 index 00000000..88b78b4a --- /dev/null +++ b/rtl/vlib/xlib/tb/.cvsignore @@ -0,0 +1 @@ +tb_dcm_sfs diff --git a/rtl/vlib/xlib/tb/Makefile b/rtl/vlib/xlib/tb/Makefile new file mode 100644 index 00000000..c943bbd6 --- /dev/null +++ b/rtl/vlib/xlib/tb/Makefile @@ -0,0 +1,39 @@ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2014-07-27 545 1.1.1 make reference board configurable via XTW_BOARD +# 2011-08-13 405 1.1 use includes from rtl/make +# 2010-11-07 337 1.0 Initial version +# +EXE_all = tb_dcm_sfs +# +# reference board for test synthesis is Spartan-6 based Nexys3 +ifndef XTW_BOARD + XTW_BOARD=nexys3 +endif +include ${RETROBASE}/rtl/make_ise/xflow_default_$(XTW_BOARD).mk +# +.PHONY : all all_ssim all_tsim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_tsim : $(EXE_all:=_tsim) +# +clean : ise_clean ghdl_clean isim_clean +# +#----- +# +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_isim.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(VBOM_all:.vbom=.dep_isim) +include $(wildcard *.o.dep_ghdl) +endif +# diff --git a/rtl/vlib/xlib/tb/s7_cmt_sfs_tb.vbom b/rtl/vlib/xlib/tb/s7_cmt_sfs_tb.vbom new file mode 100644 index 00000000..5144e322 --- /dev/null +++ b/rtl/vlib/xlib/tb/s7_cmt_sfs_tb.vbom @@ -0,0 +1,4 @@ +# libs +../../slvtypes.vhd +# design +s7_cmt_sfs_tb.vhd diff --git a/rtl/vlib/xlib/tb/s7_cmt_sfs_tb.vhd b/rtl/vlib/xlib/tb/s7_cmt_sfs_tb.vhd new file mode 100644 index 00000000..cb20947b --- /dev/null +++ b/rtl/vlib/xlib/tb/s7_cmt_sfs_tb.vhd @@ -0,0 +1,213 @@ +-- $Id: s7_cmt_sfs_tb.vhd 734 2016-02-20 22:43:20Z mueller $ +-- +-- Copyright 2016- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: s7_cmt_sfs_tb - sim +-- Description: Series-7 CMT for simple frequency synthesis (SIM only!) +-- simple vhdl model, without Xilinx UNISIM primitives +-- +-- Dependencies: - +-- Test bench: - +-- Target Devices: generic Series-7 +-- Tool versions: xst 14.7; viv 2015.4; ghdl 0.31 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2016-02-20 734 1.0 Initial version (copied from s7_cmt_sfs_gsim) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +entity s7_cmt_sfs_tb is -- 7-Series CMT for simple freq. synth. + generic ( + VCO_DIVIDE : positive := 1; -- vco clock divide + VCO_MULTIPLY : positive := 1; -- vco clock multiply + OUT_DIVIDE : positive := 1; -- output divide + CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns) + CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps) + STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED + GEN_TYPE : string := "PLL"); -- PLL or MMCM + port ( + CLKIN : in slbit; -- clock input + CLKFX : out slbit; -- clock output (synthesized freq.) + LOCKED : out slbit -- pll/mmcm locked + ); +end s7_cmt_sfs_tb; + + +architecture sim of s7_cmt_sfs_tb is + + signal CLK_DIVPULSE : slbit := '0'; + signal CLKOUT_PERIOD : time := 0 ns; + signal R_CLKOUT : slbit := '0'; + signal R_LOCKED : slbit := '0'; + +begin + + proc_init : process + + -- currently frequency limits taken from Artix-7 speed grade -1 + constant f_vcomin_pll : integer := 800; + constant f_vcomax_pll : integer := 1600; + constant f_pdmin_pll : integer := 19; + constant f_pdmax_pll : integer := 450; + + constant f_vcomin_mmcm : integer := 600; + constant f_vcomax_mmcm : integer := 1200; + constant f_pdmin_mmcm : integer := 10; + constant f_pdmax_mmcm : integer := 450; + + variable t_vco : time := 0 ns; + variable t_vcomin : time := 0 ns; + variable t_vcomax : time := 0 ns; + variable t_pd : time := 0 ns; + variable t_pdmin : time := 0 ns; + variable t_pdmax : time := 0 ns; + + begin + -- validate generics + + + if not (GEN_TYPE = "PLL" or GEN_TYPE = "MMCM") then + assert false + report "assert(GEN_TYPE='PLL' or GEN_TYPE='MMCM')" + severity failure; + end if; + + if VCO_DIVIDE/=1 or VCO_MULTIPLY/=1 or OUT_DIVIDE/=1 then + + if GEN_TYPE = "PLL" then + -- check DIV/MULT parameter range + if VCO_DIVIDE<1 or VCO_DIVIDE>56 or + VCO_MULTIPLY<2 or VCO_MULTIPLY>64 or + OUT_DIVIDE<1 or OUT_DIVIDE>128 + then + assert false + report + "assert(VCO_DIVIDE in 1:56 VCO_MULTIPLY in 2:64 OUT_DIVIDE in 1:128)" + severity failure; + end if; + -- setup VCO and PD range check boundaries + t_vcomin := (1000 ns / f_vcomax_pll) - 1 ps; + t_vcomax := (1000 ns / f_vcomin_pll) + 1 ps; + t_pdmin := (1000 ns / f_pdmax_pll) - 1 ps; + t_pdmax := (1000 ns / f_pdmin_pll) + 1 ps; + + end if; -- GEN_TYPE = "PLL" + + if GEN_TYPE = "MMCM" then + -- check DIV/MULT parameter range + if VCO_DIVIDE<1 or VCO_DIVIDE>106 or + VCO_MULTIPLY<2 or VCO_MULTIPLY>64 or + OUT_DIVIDE<1 or OUT_DIVIDE>128 + then + assert false + report + "assert(VCO_DIVIDE in 1:106 VCO_MULTIPLY in 2:64 OUT_DIVIDE in 1:128)" + severity failure; + end if; + -- setup VCO and PD range check boundaries + t_vcomin := (1000 ns / f_vcomax_pll) - 1 ps; + t_vcomax := (1000 ns / f_vcomin_pll) + 1 ps; + t_pdmin := (1000 ns / f_pdmax_pll) - 1 ps; + t_pdmax := (1000 ns / f_pdmin_pll) + 1 ps; + + end if; -- GEN_TYPE = "MMCM" + + -- now common check whether VCO and PD frequency is in range + t_pd := (1 ps * (1000.0*CLKIN_PERIOD)) * VCO_DIVIDE; + t_vco := t_pd / VCO_MULTIPLY; + + if t_vcot_vcomax then + assert false + report "assert(VCO frequency out of range)" + severity failure; + end if; + + if t_pdt_pdmax then + assert FALSE + report "assert(PD frequency out of range)" + severity failure; + end if; + + end if; -- one factor /= 1 + + wait; + end process proc_init; + + proc_clkin : process (CLKIN) + variable t_lastclkin : time := 0 ns; + variable t_lastperiod : time := 0 ns; + variable t_period : time := 0 ns; + variable nclkin : integer := 1; + begin + + if CLKIN'event then + if CLKIN = '1' then -- if CLKIN rising edge + + if t_lastclkin > 0 ns then + t_lastperiod := t_period; + t_period := now - t_lastclkin; + CLKOUT_PERIOD <= (t_period * VCO_DIVIDE * OUT_DIVIDE) / VCO_MULTIPLY; + if t_lastperiod > 0 ns and abs(t_period-t_lastperiod) > 1 ps then + report "s7_cmt_sp_sfs: CLKIN unstable" severity warning; + end if; + end if; + t_lastclkin := now; + + if t_period > 0 ns then + nclkin := nclkin - 1; + if nclkin <= 0 then + nclkin := VCO_DIVIDE * OUT_DIVIDE; + CLK_DIVPULSE <= '1'; + R_LOCKED <= '1'; + end if; + end if; + + else -- if CLKIN falling edge + CLK_DIVPULSE <= '0'; + end if; + end if; + + end process proc_clkin; + + proc_clkout : process + variable t_lastclkin : time := 0 ns; + variable t_lastperiod : time := 0 ns; + variable t_period : time := 0 ns; + variable nclkin : integer := 1; + begin + + loop + wait until CLK_DIVPULSE = '1'; + + for i in 1 to VCO_MULTIPLY loop + R_CLKOUT <= '1'; + wait for CLKOUT_PERIOD/2; + R_CLKOUT <= '0'; + if i /= VCO_MULTIPLY then + wait for CLKOUT_PERIOD/2; + end if; + end loop; -- i + + end loop; + + end process proc_clkout; + + CLKFX <= R_CLKOUT; + LOCKED <= R_LOCKED; + +end sim; diff --git a/rtl/w11a/Makefile b/rtl/w11a/Makefile index dd701ff8..f51dc9d4 100644 --- a/rtl/w11a/Makefile +++ b/rtl/w11a/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -14,7 +14,7 @@ NGC_all = $(VBOM_all:.vbom=.ngc) ifndef XTW_BOARD XTW_BOARD=nexys3 endif -include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk +include ${RETROBASE}/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # .PHONY : all clean # @@ -24,7 +24,7 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/w11a/pdp11_hio70.vhd b/rtl/w11a/pdp11_hio70.vhd index 3f0db5c3..2e9c1781 100644 --- a/rtl/w11a/pdp11_hio70.vhd +++ b/rtl/w11a/pdp11_hio70.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11_hio70.vhd 672 2015-05-02 21:58:28Z mueller $ +-- $Id: pdp11_hio70.vhd 737 2016-02-28 09:07:18Z mueller $ -- -- Copyright 2015- by Walter F.J. Mueller -- @@ -15,10 +15,12 @@ -- Module Name: pdp11_hio70 - syn -- Description: pdp11: hio led and dsp for sys70 -- --- Dependencies: - +-- Dependencies: pdp11_statleds +-- pdp11_ledmux +-- pdp11_dspmux -- Test bench: - -- Target Devices: generic --- Tool versions: ise 14.7; viv 2014.4; ghdl 0.31 +-- Tool versions: ise 14.7; viv 2014.4-2015.4; ghdl 0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/w11a/tb/.cvsignore b/rtl/w11a/tb/.cvsignore index 9af5fe8e..4faae0b7 100644 --- a/rtl/w11a/tb/.cvsignore +++ b/rtl/w11a/tb/.cvsignore @@ -1,12 +1,5 @@ tb_pdp11core tb_pdp11core_stim -tb_pdp11core_[sft]sim -tb_pdp11core_ISim -tb_pdp11core_ISim_[sft]sim tb_rlink_tba_pdp11core -tb_rlink_tba_pdp11core_[sft]sim -tb_rlink_tba_pdp11core_ISim -tb_rlink_tba_pdp11core_ISim_[sft]sim tb_rlink_tba_stim tb_pdp11core_stim.scmd -tmu_ofile diff --git a/rtl/w11a/tb/Makefile b/rtl/w11a/tb/Makefile index 30048866..afe94c79 100644 --- a/rtl/w11a/tb/Makefile +++ b/rtl/w11a/tb/Makefile @@ -1,64 +1,43 @@ -# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# $Id: Makefile 744 2016-03-13 20:28:25Z mueller $ # # Revision History: # Date Rev Version Comment -# 2014_12_26 621 1.4.2 use tbrun_tbw for check_* targets -# 2014-07-27 545 1.4.1 make reference board configurable via XTW_BOARD -# 2011-08-13 405 1.4 use includes from rtl/make -# 2010-12-30 351 1.3 retire tb_rripdp_pdp11core tb_rriext_pdp11core -# 2009-11-22 252 1.2 add ISim support -# 2007-09-16 83 1.1.1 add include *.o.dep_ghdl -# 2007-07-06 64 1.1 use vbom's -# 2007-06-17 58 1.0 Initial version +# 2016-03-13 744 1.0 Initial version # EXE_all = tb_pdp11core -# -# default reference board for test synthesis is Spartan-6 based Nexys3 -ifndef XTW_BOARD - XTW_BOARD=nexys3 -endif -include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # -.PHONY : all all_ssim all_tsim clean +# reference board for test synthesis is Artix-7 based Nexys4 +ifndef XTW_BOARD + XTW_BOARD=nexys4 +endif +include ${RETROBASE}/rtl/make_viv/viv_default_$(XTW_BOARD).mk +# +.PHONY : all all_ssim all_osim clean +.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim # all : $(EXE_all) all_ssim : $(EXE_all:=_ssim) -all_tsim : $(EXE_all:=_tsim) +all_osim : $(EXE_all:=_osim) # -clean : ise_clean ghdl_clean isim_clean +all_XSim : $(EXE_all:=_XSim) +all_XSim_ssim : $(EXE_all:=_XSim_ssim) +all_XSim_osim : $(EXE_all:=_XSim_osim) +all_XSim_tsim : $(EXE_all:=_XSim_tsim) +# +clean : viv_clean ghdl_clean xsim_clean # #----- # -include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk -include $(RETROBASE)/rtl/make_ise/generic_isim.mk -include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk +include ${RETROBASE}/rtl/make_viv/generic_xsim.mk +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk # VBOM_all = $(wildcard *.vbom) # ifndef DONTINCDEP -include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_vsyn) include $(VBOM_all:.vbom=.dep_ghdl) -include $(VBOM_all:.vbom=.dep_isim) -include $(wildcard *.o.dep_ghdl) +include $(VBOM_all:.vbom=.dep_vsim) endif # -#----- -# time ~/misc_walter/p11_util/bin/pdp11 $*.scmd > $*.simh_raw_log -%.simh_log: %.dat - tbdat2simh $*.dat > $*.scmd - time pdp11 $*.scmd > $*.simh_raw_log - simdat_check $*.simh_raw_log > $*.simh_log - grep FAIL $*.simh_log - -check_dsim: tb_pdp11core tb_pdp11core_stim.dat - tbrun_tbw tb_pdp11core || true - @ echo "# diff to reference" - diff tb_pdp11core_out_ref.dat tb_pdp11core_dsim.log - -check_ssim: tb_pdp11core_ssim tb_pdp11core_stim.dat - tbrun_tbw tb_pdp11core_ssim || true - @ echo "# diff to reference" - diff tb_pdp11core_out_ref.dat tb_pdp11core_ssim.log - -check_simh: tb_pdp11core_stim.simh_log diff --git a/rtl/w11a/tb/Makefile.ise b/rtl/w11a/tb/Makefile.ise new file mode 100644 index 00000000..ea461c00 --- /dev/null +++ b/rtl/w11a/tb/Makefile.ise @@ -0,0 +1,65 @@ +# $Id: Makefile.ise 744 2016-03-13 20:28:25Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2014_12_26 621 1.4.2 use tbrun_tbw for check_* targets +# 2014-07-27 545 1.4.1 make reference board configurable via XTW_BOARD +# 2011-08-13 405 1.4 use includes from rtl/make +# 2010-12-30 351 1.3 retire tb_rripdp_pdp11core tb_rriext_pdp11core +# 2009-11-22 252 1.2 add ISim support +# 2007-09-16 83 1.1.1 add include *.o.dep_ghdl +# 2007-07-06 64 1.1 use vbom's +# 2007-06-17 58 1.0 Initial version +# +EXE_all = tb_pdp11core +EXE_all += tb_rlink_tba_pdp11core +# +# default reference board for test synthesis is Spartan-6 based Nexys3 +ifndef XTW_BOARD + XTW_BOARD=nexys3 +endif +include ${RETROBASE}/rtl/make_ise/xflow_default_$(XTW_BOARD).mk + +# +.PHONY : all all_ssim all_tsim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_tsim : $(EXE_all:=_tsim) +# +clean : ise_clean ghdl_clean isim_clean +# +#----- +# +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_isim.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(VBOM_all:.vbom=.dep_isim) +include $(wildcard *.o.dep_ghdl) +endif +# +#----- +# time ~/misc_walter/p11_util/bin/pdp11 $*.scmd > $*.simh_raw_log +%.simh_log: %.dat + tbdat2simh $*.dat > $*.scmd + time pdp11 $*.scmd > $*.simh_raw_log + simdat_check $*.simh_raw_log > $*.simh_log + grep FAIL $*.simh_log + +check_dsim: tb_pdp11core tb_pdp11core_stim.dat + tbrun_tbw tb_pdp11core || true + @ echo "# diff to reference" + diff tb_pdp11core_out_ref.dat tb_pdp11core_dsim.log + +check_ssim: tb_pdp11core_ssim tb_pdp11core_stim.dat + tbrun_tbw tb_pdp11core_ssim || true + @ echo "# diff to reference" + diff tb_pdp11core_out_ref.dat tb_pdp11core_ssim.log + +check_simh: tb_pdp11core_stim.simh_log diff --git a/rtl/w11a/tb/tb_pdp11core.vbom b/rtl/w11a/tb/tb_pdp11core.vbom index e0cad9db..b28b20b7 100644 --- a/rtl/w11a/tb/tb_pdp11core.vbom +++ b/rtl/w11a/tb/tb_pdp11core.vbom @@ -7,6 +7,6 @@ # components ../../vlib/simlib/simclk.vbom ../../vlib/simlib/simclkcnt.vbom -${tbd_pdp11core := tbd_pdp11core.vbom} +@uut: ${uut := tbd_pdp11core.vbom} # design tb_pdp11core.vhd diff --git a/rtl/w11a/tb/tb_pdp11core_ssim.vbom b/rtl/w11a/tb/tb_pdp11core_ssim.vbom index 8e56da84..c497039b 100644 --- a/rtl/w11a/tb/tb_pdp11core_ssim.vbom +++ b/rtl/w11a/tb/tb_pdp11core_ssim.vbom @@ -1,4 +1,4 @@ # configure for _*sim case -tbd_pdp11core = tbd_pdp11core_ssim.vhd +uut = tbd_pdp11core_ssim.vhd tb_pdp11core.vbom @top:tb_pdp11core diff --git a/tools/asm-11/tests-err/Makefile b/tools/asm-11/tests-err/Makefile index 01a099fd..c143c4ed 100644 --- a/tools/asm-11/tests-err/Makefile +++ b/tools/asm-11/tests-err/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 525 2013-07-06 12:19:39Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -10,7 +10,7 @@ LSTERR_all = $(MAC_all:.mac=.lsterr) LDART_all = $(MAC_all:.mac=.ldart) LSTRT_all = $(MAC_all:.mac=.lstrt) # -include $(RETROBASE)/tools/make/generic_asm11.mk +include ${RETROBASE}/tools/make/generic_asm11.mk # .PHONY : def alllst allrt allexp clean cleanrt # diff --git a/tools/asm-11/tests/.cvsignore b/tools/asm-11/tests/.cvsignore index f11c8fba..35c294cc 100644 --- a/tools/asm-11/tests/.cvsignore +++ b/tools/asm-11/tests/.cvsignore @@ -1,5 +1,3 @@ *.lda -*.cof -*.lst *.ldart *.lstrt diff --git a/tools/asm-11/tests/Makefile b/tools/asm-11/tests/Makefile index 68446d1b..cdb537af 100644 --- a/tools/asm-11/tests/Makefile +++ b/tools/asm-11/tests/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 525 2013-07-06 12:19:39Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -12,7 +12,7 @@ LST_all = $(MAC_all:.mac=.lst) LDART_all = $(MAC_all:.mac=.ldart) LSTRT_all = $(MAC_all:.mac=.lstrt) # -include $(RETROBASE)/tools/make/generic_asm11.mk +include ${RETROBASE}/tools/make/generic_asm11.mk # .PHONY : def alllda allcof alllst allrt allexp clean cleanrt # diff --git a/tools/asm-11/w11/sys/dl11/.cvsignore b/tools/asm-11/w11/sys/dl11/.cvsignore index f11c8fba..35c294cc 100644 --- a/tools/asm-11/w11/sys/dl11/.cvsignore +++ b/tools/asm-11/w11/sys/dl11/.cvsignore @@ -1,5 +1,3 @@ *.lda -*.cof -*.lst *.ldart *.lstrt diff --git a/tools/asm-11/w11/sys/dl11/Makefile b/tools/asm-11/w11/sys/dl11/Makefile index 6c871f05..91437749 100644 --- a/tools/asm-11/w11/sys/dl11/Makefile +++ b/tools/asm-11/w11/sys/dl11/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 525 2013-07-06 12:19:39Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -9,7 +9,7 @@ MAC_all = $(wildcard *.mac) LDA_all = $(MAC_all:.mac=.lda) COF_all = $(MAC_all:.mac=.cof) # -include $(RETROBASE)/tools/make/generic_asm11.mk +include ${RETROBASE}/tools/make/generic_asm11.mk # .PHONY : alllda allcof alllst clean # diff --git a/tools/bin/rm_dep b/tools/bin/rm_dep index 3f8f5072..058fa64b 100755 --- a/tools/bin/rm_dep +++ b/tools/bin/rm_dep @@ -1,17 +1,18 @@ #!/bin/sh -# $Id: rm_dep 646 2015-02-15 12:04:55Z mueller $ +# $Id: rm_dep 727 2016-02-07 13:58:47Z mueller $ # # Copyright 2010-2015 by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory # # Revision History: # Date Rev Version Comment +# 2016-02-06 727 1.2.1 add dep_vsim # 2015-02-14 646 1.2 add dep_vsyn # 2011-01-09 354 1.1.1 add *.dep for cpp depends # 2010-04-26 284 1.1 add xargs -r to prevent rm errors on empty lists # 2010-04-24 282 1.0 Initial version # -for ftype in dep dep_ghdl dep_xst dep_isim dep_ucf_cpp dep_vsyn +for ftype in dep dep_ghdl dep_xst dep_isim dep_ucf_cpp dep_vsyn dep_vsim do echo "---------- remove *.$ftype ----------------------------------------" find -name "*.$ftype" | xargs --no-run-if-empty rm -v diff --git a/tools/bin/tbrun_tbw b/tools/bin/tbrun_tbw index ad0dee57..fb868bff 100755 --- a/tools/bin/tbrun_tbw +++ b/tools/bin/tbrun_tbw @@ -1,11 +1,12 @@ #!/bin/bash -# $Id: tbrun_tbw 641 2015-02-01 22:12:15Z mueller $ +# $Id: tbrun_tbw 727 2016-02-07 13:58:47Z mueller $ # -# Copyright 2014- by Walter F.J. Mueller +# Copyright 2014-2016 by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory # # Revision History: # Date Rev Version Comment +# 2016-02-06 727 1.1 add vivado xsim support; Makefile.ise support # 2014-12-27 622 1.0.1 add --stack, --ghw, --tbw, --pcom # 2014-12-26 621 1.0 Initial version # @@ -54,22 +55,37 @@ if (( $# == 0 )) ; then exit 1 fi +# defaults +isghdl=true +makeopts="" + # check for ISim isisim="" if [[ $tbench =~ _ISim ]] ; then isisim=true + isghdl="" + if [[ -f "Makefile.ise" ]] ; then + makeopts="-f Makefile.ise" + fi fi -# check for ghdl with _ssim, _fsim, _tsim +# check for XSim +isxsim="" +if [[ $tbench =~ _XSim ]] ; then + isxsim=true + isghdl="" +fi + +# check for ghdl with _ssim, _fsim, _osim, _tsim isghdlxsim="" -if [[ "$isisim" == "" ]] && [[ $tbench =~ _[sft]sim$ ]] ; then +if [[ -n "$isghdl" ]] && [[ $tbench =~ _[sfot]sim$ ]] ; then isghdlxsim=true logsuff="" fi # issue makes if [[ -n "$isghdlxsim" ]] ; then docmd "make ghdl_tmp_clean"; fi -docmd "make $tbench" +docmd "make $makeopts $tbench" exitstat=$? if [[ -n "$isghdlxsim" ]] ; then docmd "make ghdl_tmp_clean"; fi @@ -77,7 +93,7 @@ if (( $exitstat > 0 )) ; then exit $exitstat; fi # determine logfile name logsuff="_dsim" -if [[ $tbench =~ _[sft]sim$ ]] ; then logsuff=""; fi +if [[ $tbench =~ _[sfot]sim$ ]] ; then logsuff=""; fi if [[ -n "$optlsuf" ]] ; then logsuff="_$optlsuf"; fi logfile="${tbench}${logsuff}.log" @@ -85,12 +101,13 @@ logfile="${tbench}${logsuff}.log" # now build actual test command (a tbw|filter|tee|egrep pipe) cmd="time tbw $tbench" if [[ -n "$isisim" ]] ; then cmd+=" -run"; fi +if [[ -n "$isxsim" ]] ; then cmd+=" -run"; fi if [[ -n "$stimfile" ]] ; then cmd+=" $stimfile"; fi if [[ -n "$opttbw" ]] ; then cmd+=" $opttbw"; fi if [[ -n "$optstack" ]] ; then cmd+=" --stack-max-size=$optstack"; fi if [[ -n "$optghw" ]] ; then cmd+=" --wave=$optghw.ghw"; fi cmd+=" 2>&1" -if [[ -z "$isisim" ]] ; then cmd+=" | ghdl_assert_filter"; fi +if [[ -n "$isghdl" ]] ; then cmd+=" | ghdl_assert_filter"; fi cmd+=" | tee $logfile" pcomtag="" diff --git a/tools/bin/tbrun_tbwrri b/tools/bin/tbrun_tbwrri index 666bc0f9..907b8315 100755 --- a/tools/bin/tbrun_tbwrri +++ b/tools/bin/tbrun_tbwrri @@ -1,11 +1,12 @@ #!/bin/bash -# $Id: tbrun_tbwrri 666 2015-04-12 21:17:54Z mueller $ +# $Id: tbrun_tbwrri 745 2016-03-18 22:10:34Z mueller $ # -# Copyright 2014-2015 by Walter F.J. Mueller +# Copyright 2014-2016 by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory # # Revision History: # Date Rev Version Comment +# 2016-03-18 745 1.2 use --sxon and --hxon instead of --xon # 2015-04-11 666 1.1 add --fusp,--xon # 2014-12-27 622 1.0 Initial version # @@ -36,7 +37,8 @@ optrri="" optpcom="" optcuff="" optfusp="" -optxon="" +optsxon="" +opthxon="" # handle options while (( $# > 0 )) ; do @@ -50,7 +52,8 @@ while (( $# > 0 )) ; do -rri|--rri) optrri=$2 ; chkval $2 ; shift 2 ;; -cuff|--cuff) optcuff=$1 ; shift 1 ;; -fusp|--fusp) optfusp=$1 ; shift 1 ;; - -xon|--xon) optxon=$1 ; shift 1 ;; + -sxon|--sxon) optsxon=$1 ; shift 1 ;; + -hxon|--hxon) opthxon=$1 ; shift 1 ;; -pcom|--pcom) optpcom=$1 ; shift 1 ;; -\?|-h*|--h*) opthelp=$1 ; shift 1 ;; -*) echo "tbrun_tbwrri-E: invalid option '$1'"; exit 1 ;; @@ -71,19 +74,21 @@ if [[ -n "$opthelp" || $# -eq 0 ]] ; then echo " --rri opts append to ti_rri command" echo " --cuff use cuff and not serport" echo " --fusp use 2nd serport" - echo " --xon use xon with 1st serport" + echo " --sxon use xon with 1st serport (via SWI(1))" + echo " --hxon use xon with 1st serport (hardwired)" echo " --pcom print test comments" exit 1 fi -# check that only one of --cuff --fusp or --xon given +# check that only one of --cuff --fusp or --?xon given ncfxcount=0 if [[ -n "$optcuff" ]] ; then ncfxcount=$(($ncfxcount+1)); fi if [[ -n "$optfusp" ]] ; then ncfxcount=$(($ncfxcount+1)); fi -if [[ -n "$optxon" ]] ; then ncfxcount=$(($ncfxcount+1)); fi +if [[ -n "$opthxon" ]] ; then ncfxcount=$(($ncfxcount+1)); fi +if [[ -n "$optsxon" ]] ; then ncfxcount=$(($ncfxcount+1)); fi if (( $ncfxcount > 1 )) ; then - echo "tbrun_tbwrri-E: only one of --cuff,-fusp,--xon allowed" + echo "tbrun_tbwrri-E: only one of --cuff,-fusp,--sxon,--hxon allowed" exit 1 fi @@ -125,10 +130,11 @@ if [[ -n "$optghw" ]] ; then fi cmd+=" 2>&1 | ghdl_assert_filter\"" -# Note: the following ensurs that we always have 'fifo=,' with an # empty first field (the default fifo name) fifoopts="" -if [[ -n "$optxon" ]] ; then fifoopts+=",xon"; fi +if [[ -n "$opthxon" ]] ; then fifoopts+=",xon"; fi +if [[ -n "$optsxon" ]] ; then fifoopts+=",xon"; fi if (( $ncfxcount > 0 )) ; then fifoopts+=",noinit"; fi if [[ -n "$fifoopts" ]] ; then @@ -154,7 +160,7 @@ if [[ -n "$optfusp" ]] ; then cmd+=" \"rlc oob -sbdata 16 0x1\"" # swi = 0001 -> 2nd ser fi -if [[ -n "$optxon" ]] ; then +if [[ -n "$optsxon" ]] ; then cmd+=" \"rlc oob -sbdata 8 0x2\"" # portsel = 0010 -> 1st ser XON cmd+=" \"rlc oob -sbdata 16 0x2\"" # swi = 0010 -> 1st ser XON fi diff --git a/tools/bin/tbw b/tools/bin/tbw index f5913617..fc5a3b61 100755 --- a/tools/bin/tbw +++ b/tools/bin/tbw @@ -1,7 +1,7 @@ #!/usr/bin/perl -w -# $Id: tbw 642 2015-02-06 18:53:12Z mueller $ +# $Id: tbw 727 2016-02-07 13:58:47Z mueller $ # -# Copyright 2007-2015 by Walter F.J. Mueller +# Copyright 2007-2016 by Walter F.J. Mueller # # This program is free software; you may redistribute and/or modify it under # the terms of the GNU General Public License as published by the Free @@ -14,6 +14,7 @@ # # Revision History: # Date Rev Version Comment +# 2016-02-06 727 1.3 add XSim support # 2015-01-04 629 1.2.6 BUGFIX: setup proper dsc values after -fifo # 2014-12-23 619 1.2.5 add -fifo and -verbose options # 2014-07-27 575 1.2.4 use xtwi to start ISim models @@ -46,6 +47,7 @@ use FileHandle; my $tb_code; my $is_isim; my $is_isim_run; +my $is_xsim; my $is_fifo; my $is_verbose; @@ -77,7 +79,7 @@ if ($tb_code =~ m|^(.*)/(.*)$|) { } my $tb_code_stem = $tb_code_name; -$tb_code_stem =~ s/_[fst]sim$//; # drop _ssim,_fsim, or _tsim +$tb_code_stem =~ s/_[fost]sim$//; # drop _ssim,_fsim, _osim, or _tsim if ($tb_code_stem =~ /_ISim$/) { # is it an ISim executable ? $is_isim = 1; @@ -88,6 +90,15 @@ if ($tb_code_stem =~ /_ISim$/) { # is it an ISim executable ? } } +if ($tb_code_stem =~ /_XSim$/) { # is it an XSim executable ? + $is_xsim = 1; + $tb_code_stem =~ s/_XSim$//; # drop _XSim + if (scalar(@ARGV) && $ARGV[0] eq "-run") { # map -run to '-R' + $ARGV[0] = "-R"; + } +} + + if (scalar(@ARGV) && $ARGV[0] eq "-fifo") { push @file_dsc, {tag=>'rlink_cext_fifo_rx', val=>''}; push @file_dsc, {tag=>'rlink_cext_fifo_tx', val=>''}; diff --git a/tools/bin/ti_w11 b/tools/bin/ti_w11 index ee350b86..e55a5ebb 100755 --- a/tools/bin/ti_w11 +++ b/tools/bin/ti_w11 @@ -1,11 +1,12 @@ #!/usr/bin/perl -w -# $Id: ti_w11 712 2015-11-01 22:53:45Z mueller $ +# $Id: ti_w11 745 2016-03-18 22:10:34Z mueller $ # -# Copyright 2013-2015 by Walter F.J. Mueller +# Copyright 2013-2016 by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory # # Revision History: # Date Rev Version Comment +# 2016-03-18 745 1.3.3 add arty support, add -fx # 2015-11-01 712 1.3.2 use sb_cntl pin 12 for tmu; add -ghw option # 2015-05-14 680 1.3.1 use now -f1,-f1e,-f2,-f2e (fx now f1e) # 2015-04-13 667 1.3 rename -fu->-fc, add -f2,-fx; setup good defaults @@ -29,7 +30,7 @@ my $sysbase = "$ENV{RETROBASE}/rtl/sys_gen/w11a"; my $opt_dry; my $opt_b; my $opt_io = ''; -my $opt_f = ''; +my $opt_f = ''; my $opt_tmu; my $opt_ghw; my $tirri; @@ -40,6 +41,7 @@ my $val_tb_n3 = "tbw $sysbase/nexys3/tb/tb_w11a_n3 -fifo"; my $val_tb_b3 = "tbw $sysbase/basys3/tb/tb_w11a_b3 -fifo"; my $val_tb_n4 = "tbw $sysbase/nexys4/tb/tb_w11a_n4 -fifo"; my $val_tb_bn4 = "tbw $sysbase/nexys4_bram/tb/tb_w11a_br_n4 -fifo"; +my $val_tb_bar = "tbw $sysbase/arty_bram/tb/tb_w11a_br_arty -fifo"; my $val_tb; my $val_e; @@ -85,9 +87,9 @@ while (scalar(@ARGV)) { $val_tb = $val_tb_n3; shift @ARGV; - } elsif ($curarg =~ m{^-b3$} ) { # -b3 (use -f1x by default) + } elsif ($curarg =~ m{^-b3$} ) { # -b3 (use -fx by default) $opt_io = 'f'; - $opt_f = '1x'; + $opt_f = 'x'; $val_tb = $val_tb_b3; shift @ARGV; @@ -103,7 +105,13 @@ while (scalar(@ARGV)) { $val_tb = $val_tb_bn4; shift @ARGV; - } elsif ($curarg =~ m{^-f(c|1|1x|2|2x)$} ) { # -f.. + } elsif ($curarg =~ m{^-bar$} ) { # -bar (use -fx by default) + $opt_io = 'f'; + $opt_f = 'x'; + $val_tb = $val_tb_bar; + shift @ARGV; + + } elsif ($curarg =~ m{^-f(c|x|1|1x|2|2x)$} ) { # -f.. $opt_f = $1; shift @ARGV; @@ -176,7 +184,7 @@ while (scalar(@ARGV)) { if ($opt_io eq 'f') { my $fifoopts = ",noinit"; # fifo always with deferred init - $fifoopts .= ",xon" if $opt_f eq 'x'; + $fifoopts .= ",xon" if $opt_f =~ m/x$/; push @arglist, "--fifo=$fifoopts"; my $run_opts = ""; if ($opt_ghw) { @@ -190,7 +198,7 @@ if ($opt_io eq 'f') { } elsif ($opt_io eq 'u') { push @arglist, '--cuff'; } else { - print STDERR "ti_w11-E: neither -(s3|n2|n3|b3|n4|bn4) nor -t,-u specified\n"; + print STDERR "ti_w11-E: neither -(s3|n2|...) nor -t,-u specified\n"; print_usage(); exit 1; } @@ -290,18 +298,20 @@ exit 1; sub print_usage { print "usage: ti_w11 ...\n"; print " setup options for ghdl simulation runs:\n"; - print " -b3 start tb_w11a_b3 simulation (default: -f1x)\n"; + print " -b3 start tb_w11a_b3 simulation (default: -fx)\n"; print " -n4 start tb_w11a_n4 simulation\n"; print " -bn4 start tb_w11a_br_n4 simulation\n"; + print " -bar start tb_w11a_br_arty simulation (default: -fx)\n"; print " -n3 start tb_w11a_n3 simulation (default: -fc)\n"; print " -n2 start tb_w11a_n2 simulation (default: -fc)\n"; print " -s3 start tb_w11a_s3 simulation (default: -f2)\n"; print " -f.. simulation communication options\n"; print " -fc use fx2 data path (cuff)\n"; + print " -fx use 1st serport with hardwired xon\n"; print " -f1 use 1st serport\n"; - print " -f1x use 1st serport with xon\n"; + print " -f1x use 1st serport with switched xon\n"; print " -f2 use 2nd serport (fusp)\n"; - print " -f2x use 2nd serport with xon\n"; + print " -f2x use 2nd serport with switched xon\n"; print " -tmu activate trace and monitoring unit\n"; print " setup options for FPGA connects:\n"; print " -u use --cuff connect\n"; diff --git a/tools/bin/vbomconv b/tools/bin/vbomconv index 2acc08d5..27158b39 100755 --- a/tools/bin/vbomconv +++ b/tools/bin/vbomconv @@ -1,7 +1,7 @@ #!/usr/bin/perl -w -# $Id: vbomconv 672 2015-05-02 21:58:28Z mueller $ +# $Id: vbomconv 734 2016-02-20 22:43:20Z mueller $ # -# Copyright 2007-2015 by Walter F.J. Mueller +# Copyright 2007-2016 by Walter F.J. Mueller # # This program is free software; you may redistribute and/or modify it under # the terms of the GNU General Public License as published by the Free @@ -14,6 +14,9 @@ # # Revision History: # Date Rev Version Comment +# 2016-02-20 734 1.14 add [ise,viv]; add preliminary --(vsyn|vsim)_export; +# 2016-02-14 731 1.13 add @uut tag handling; +# 2016-02-07 728 1.12 add vivado xsim support; protect for empty xdc set # 2015-02-15 646 1.11 add vivado support: add -xlpath, use instead # of XTWI_PATH; drop --ise_path; add @lib:unimacro; # drop --viv_vhdl; add --vsyn_prj, --dep_vsyn; @@ -61,21 +64,27 @@ use Getopt::Long; my %opts = (); GetOptions(\%opts, "help", "trace", "xlpath=s", - "dep_ghdl", "dep_xst", "dep_isim", "dep_vsyn", - "xst_prj", "isim_prj", - "vsyn_prj", + "dep_ghdl", + "dep_xst", "dep_isim", + "dep_vsyn", "dep_vsim", + "xst_prj", "isim_prj", + "vsyn_prj", "vsim_prj", "ghdl_a", "ghdl_a_cmd", "ghdl_i", "ghdl_i_cmd", "ghdl_m", "ghdl_m_cmd", "ghdl_export=s", "xst_export=s", "isim_export=s", + "vsyn_export=s", + "vsim_export=s", "get_top", "flist") || exit 1; sub print_help; sub read_vbom; sub scan_vbom; +sub do_synsim; +sub scan_synsim; sub copy_edir; sub write_vbomdep; sub canon_fname; @@ -83,11 +92,15 @@ sub canon_fname; my @vbom_queue; # list of pending vbom's my @srcfile_list; # list of sources in compile order my @xdcfile_list; # list of xdc files +my @srcfile_list_vhd; # all vhdl sources +my @srcfile_list_v; # all (system) verilog sources +my @srcfile_list_c; # all C sources my %vbom_files; # key=vbom; val=full file list my %vbom_xdc; # key=vbom; val=xdc spec list my %vbom_done; # key=vbom; val=done flags my %vbom_rank; # key=vbom; val=vbom ranks my %srcfile_rank; # key=source file; val=file rank +my %srcfile_synsim; # key=source file; val=syn or sim my %para_tbl; # substitution table my @ucf_cpp_list; my $is_ghdl = 0; # ghdl simulation target @@ -96,17 +109,22 @@ my $is_isim = 0; # ISim simulation target my $is_vsyn = 0; # vivado synthesis target my $is_vsim = 0; # vivado simulation target my $is_sim = 0; # simulation target (generic) +my $is_ise = 0; # ISE target +my $is_viv = 0; # vivado target my $is_any = 0; # ignore tags (for --flist) my $nactions = 0; # number of action commands my $top_vbom; # top level vbom (from argv) +my $eff_vbom; # effective vbom ([fot]sim->ssim map) my $stem; # stem of $top_vbom my $top; # top level entity name my $top_done = 0; # @top seen +my $uut; # uut level name my $has_unisim; # @lib:unisim seen or implied my $has_unimacro; # @lib:unimacro seen my $has_simprim; # @lib:simprim seen or implied my $is_ssim; my $is_fsim; +my $is_osim; my $is_tsim; my $do_trace = exists $opts{trace}; my $level = 0; # vbom nesting level @@ -133,22 +151,27 @@ if (scalar(@ARGV) != 1) { foreach (keys %opts) { $nactions += 1 unless ($_ eq "trace" || $_ eq "xlpath"); - $is_ghdl = 1 if ($_ eq "dep_ghdl"); - $is_ghdl = 1 if ($_ =~ /^ghdl_/); + $is_ghdl = 1 if $_ eq "dep_ghdl"; + $is_ghdl = 1 if $_ =~ /^ghdl_/; - $is_xst = 1 if ($_ eq "dep_xst"); - $is_xst = 1 if ($_ =~ /^xst_/); + $is_xst = 1 if $_ eq "dep_xst"; + $is_xst = 1 if $_ =~ /^xst_/; - $is_isim = 1 if ($_ eq "dep_isim"); - $is_isim = 1 if ($_ =~ /^isim_/); + $is_isim = 1 if $_ eq "dep_isim"; + $is_isim = 1 if $_ =~ /^isim_/; - $is_vsyn = 1 if ($_ eq "dep_vsyn"); - $is_vsyn = 1 if ($_ =~ /^vsyn_/); + $is_vsyn = 1 if $_ eq "dep_vsyn"; + $is_vsyn = 1 if $_ =~ /^vsyn_/; - $is_any = 1 if ($_ eq "flist"); + $is_vsim = 1 if $_ eq "dep_vsim"; + $is_vsim = 1 if $_ =~ /^vsim_/; + + $is_any = 1 if $_ eq "flist"; } $is_sim = $is_ghdl | $is_isim | $is_vsim; +$is_ise = $is_xst | $is_isim; +$is_viv = $is_vsyn | $is_vsim; print STDERR "-- [ghdl] active\n" if $do_trace && $is_ghdl; print STDERR "-- [xst] active\n" if $do_trace && $is_xst; @@ -156,6 +179,8 @@ print STDERR "-- [isim] active\n" if $do_trace && $is_isim; print STDERR "-- [vsyn] active\n" if $do_trace && $is_vsyn; print STDERR "-- [vsim] active\n" if $do_trace && $is_vsim; print STDERR "-- [sim] active\n" if $do_trace && $is_sim; +print STDERR "-- [ise] active\n" if $do_trace && $is_ise; +print STDERR "-- [viv] active\n" if $do_trace && $is_viv; if ($nactions > 1) { print STDERR "vbomconv-E: only one action qualifier allowed\n\n"; @@ -173,24 +198,20 @@ $stem =~ s{\..*$}{}; $top = $stem; $top =~ s{^.*/}{}; -# now prepare virtual _fsim and _tsim vbom's +# now prepare virtual _fsim, _osim, and _tsim vbom's # they are inferred from the _ssim vbom's -if ($top_vbom =~ m{_ssim\.vbom$}) { # detect _ssim - $is_ssim = 1; -} -if ($top_vbom =~ m{_fsim\.vbom$}) { # map _fsim -> _ssim - $is_fsim = 1; - $top_vbom =~ s{_fsim\.vbom$}{_ssim.vbom}; -} -if ($top_vbom =~ m{_tsim\.vbom$}) { # map _tsim -> _ssim - $is_tsim = 1; - $top_vbom =~ s{_tsim\.vbom$}{_ssim.vbom}; -} +$is_ssim = 1 if $top_vbom =~ m{_ssim\.vbom$}; # detect _ssim +$is_fsim = 1 if $top_vbom =~ m{_fsim\.vbom$}; # detect _fsim +$is_osim = 1 if $top_vbom =~ m{_osim\.vbom$}; # detect _osim +$is_tsim = 1 if $top_vbom =~ m{_tsim\.vbom$}; # detect _tsim + +$eff_vbom = $top_vbom; +$eff_vbom =~ s{_[fot]sim\.vbom$}{_ssim.vbom}; # map [fot]sim -> ssim # traverse all vbom's start with command line argument -push @vbom_queue, $top_vbom; +push @vbom_queue, $eff_vbom; while (@vbom_queue) { my $cur_vbom = shift @vbom_queue; @@ -199,8 +220,11 @@ while (@vbom_queue) { # traverse internal vbom representation to build file table -$vbom_rank{$top_vbom} = {min=>1, max=>1}; -scan_vbom($top_vbom); +$vbom_rank{$eff_vbom} = {min=>1, max=>1}; +scan_vbom($eff_vbom); + +# separate sym (uut) and sim (tb) parts +do_synsim($uut); # sort file table, build file list (decreasing rank) # sort first by decreasing rank and second by filename @@ -229,6 +253,19 @@ foreach (@vbomfile_list_min) { push @xdcfile_list, @{$vbom_xdc{$_}} if exists $vbom_xdc{$_}; } +# now split source list according to languages +foreach (@srcfile_list) { + if (m/\.vhd$/) { + push @srcfile_list_vhd, $_; + } elsif (m/\.(v|sv)$/) { + push @srcfile_list_v, $_; + } elsif (m/\.c$/) { + push @srcfile_list_c, $_; +# } else { +# print STDERR "unknown file type $_\n"; + } +} + # now generate output and actions, depending on options given # --trace ------------------------------------------------------------ @@ -251,12 +288,13 @@ if ($do_trace) { print STDERR "\n"; print STDERR "final srcfile_rank table (sort by rank):\n"; foreach (sort {$b->[0] <=> $a->[0] || $a->[1] cmp $b->[1]} @srcpair_list) { - printf STDERR " %5d %s\n", $_->[0], $_->[1]; + printf STDERR " %5d %s %s\n", $_->[0], $srcfile_synsim{$_->[1]}, $_->[1]; } print STDERR "\n"; print STDERR "properties:\n"; print STDERR " \@top: $top\n"; + print STDERR " \@uut: $uut\n" if defined $uut; } # --ghdh_a -- ghdl analysis command ---------------------------------- @@ -363,7 +401,7 @@ if (exists $opts{ghdl_m} || exists $opts{ghdl_m_cmd} ) { $cmd .= " -P$xlpath/unimacro" if $has_unimacro; $cmd .= " -P$xlpath/simprim" if $has_simprim; $cmd .= " --ieee=synopsys"; - $cmd .= " --no-vital-checks" if $is_ssim or $is_fsim or $is_tsim; + $cmd .= " --no-vital-checks" if $is_ssim or $is_fsim or $is_osim or $is_tsim; foreach (@srcfile_list) { next unless /\.c$/; # C source ? @@ -431,25 +469,115 @@ if (exists $opts{vsyn_prj}) { print "}\n"; print "\n"; - print "set obj [get_filesets constrs_1]\n"; - print "add_files -norecurse -fileset \$obj \$xdc_files\n"; + # add_files does not allow adding an empty set, so protect + if (scalar @xdcfile_list) { + print "set obj [get_filesets constrs_1]\n"; + print "add_files -norecurse -fileset \$obj \$xdc_files\n"; + } print "\n"; } +# --vsim_prj --------------------------------------------------------- + +if (exists $opts{vsim_prj}) { + print "#!/bin/sh\n"; + print "#\n"; + print "# generated by vbomconv -vsim_prj $top_vbom\n"; + print "#\n"; + + # compile verilog before vhdl ! + # currently verilog only used for DPI interface code + # xvhdl relies in strict compilation order, also across languages, and fails + # when a not yet compiles module is instantiated via entiry work.... + + if (scalar @srcfile_list_v) { + print "# ---------- xvlog step\n"; + my $tfile_xvlog_prj = "tmp_${stem}_xvlog.prj"; + print "cat > $tfile_xvlog_prj <&1 |\\\n"; + print " tee xvlog_${stem}.log\n"; + print "rm -f $tfile_xvlog_prj\n"; + print "#\n"; + } + + if (scalar @srcfile_list_vhd) { + print "# ---------- xvhdl step\n"; + my $tfile_xvhdl_prj = "tmp_${stem}_xvhdl.prj"; + print "cat > $tfile_xvhdl_prj <&1 |\\\n"; + print " tee xvhdl_${stem}.log\n"; + print "rm -f $tfile_xvhdl_prj\n"; + print "#\n"; + } + + if (scalar @srcfile_list_c) { + print "# ---------- xsc step\n"; + print "xtwv xsc"; + foreach (@srcfile_list_c) { + print " \\\n $_"; + } + print "\n"; + print "#\n"; + } + + print "# ---------- xelab step\n"; + print "xtwv xelab --relax --debug typical --mt auto -m64 \\\n"; + print " -L work \\\n"; + if (scalar @srcfile_list_c) { + print " --sv_lib dpi \\\n"; + } + print " --snapshot $stem work.$top \\\n"; + print " -log xelab_${stem}.log\n"; + print "\n"; + + print "# ---------- create forwarder\n"; + my $fname_forwarder = "${stem}_XSim"; + $fname_forwarder =~ s/_([sot]sim)_XSim/_XSim_$1/; + print "if [ -x \"xsim.dir/${stem}/xsimk\" ]\n"; + print "then\n"; + print "#\n"; + print "cat > $fname_forwarder <$edir/$stem.tcl") or die "can't write open $edir/$stem.tcl: $!"; + + print TFILE "#\n"; + print TFILE "# setup file lists\n"; + print TFILE "#\n"; + + print TFILE "set syn_files {\n"; + foreach (@fl_syn) { + print TFILE " $_\n"; + } + print TFILE "}\n"; + print TFILE "\n"; + + print TFILE "set sim_files {\n"; + foreach (@fl_sim) { + print TFILE " $_\n"; + } + print TFILE "}\n"; + print TFILE "\n"; + + print TFILE "set xdc_files {\n"; + foreach (@fl_xdc) { + print TFILE " $_\n"; + } + print TFILE "}\n"; + print TFILE "\n"; + + print TFILE 'set obj [get_filesets sources_1]' . "\n"; + print TFILE 'add_files -norecurse -fileset $obj $syn_files' . "\n"; + printf TFILE 'set_property "top" "%s" $obj' . "\n", $top; + print TFILE "\n"; + + if (scalar @fl_sim) { + print TFILE 'set obj [get_filesets sim_1]' . "\n"; + print TFILE 'add_files -norecurse -fileset $obj $sim_files' . "\n"; + print TFILE "\n"; + } + + if (scalar @fl_xdc) { + print TFILE 'set obj [get_filesets constrs_1]' . "\n"; + print TFILE 'add_files -norecurse -fileset $obj $xdc_files' . "\n"; + print TFILE "\n"; + } + + close(TFILE); + + +} + # --get_top ---------------------------------------------------------- if (exists $opts{get_top}) { @@ -756,13 +1042,15 @@ sub read_vbom { my $keep = $is_any; ## print STDERR "+++1 |$qual|$name|$vbom|\n"; foreach my $pref (split /,/,$qual) { - if ($pref =~ /^(ghdl|xst|isim|vsyn|vsim|sim)$/) { + if ($pref =~ /^(ghdl|xst|isim|vsyn|vsim|sim|ise|viv)$/) { $keep = 1 if ($pref eq "ghdl" && $is_ghdl); $keep = 1 if ($pref eq "xst" && $is_xst); $keep = 1 if ($pref eq "isim" && $is_isim); $keep = 1 if ($pref eq "vsyn" && $is_vsyn); $keep = 1 if ($pref eq "vsim" && $is_vsim); $keep = 1 if ($pref eq "sim" && $is_sim); + $keep = 1 if ($pref eq "ise" && $is_ise); + $keep = 1 if ($pref eq "viv" && $is_viv); } else { print STDERR "vbomconv-W: unknown tag [$pref] in $vbom_file\n"; } @@ -776,6 +1064,7 @@ sub read_vbom { my $tag; my $val = $_; + my $uut_seen; # detect tag:val lines if (m{^\s*(.*?)\s*:\s*(.*?)\s*$}) { @@ -785,14 +1074,17 @@ sub read_vbom { # process @top: lines if ($tag eq '@top') { $top = $val unless $top_done; + next; # process @ucf_cpp: lines } elsif ($tag eq '@ucf_cpp') { push @ucf_cpp_list, $val; + next; # process @xdc: lines } elsif ($tag eq '@xdc') { push @{$vbom_xdc{$vbom}}, canon_fname($vbom_path, $val); + next; # process @lib: lines } elsif ($tag eq '@lib') { @@ -806,18 +1098,27 @@ sub read_vbom { print STDERR "vbomconv-E: invalid lib type \'$tag\' in $vbom_file\n"; exit 1; } + next; + + # process @uut: lines + } elsif ($tag eq '@uut') { + $uut_seen = 1; + # Note: fall through in this case, process as normal file name + # actual @uut tag handling later with canonized file names. # catch invalid @ tags } else { print STDERR "vbomconv-E: invalid \'$tag:\' line in $vbom_file\n"; exit 1; } - next; + } - # now do _fsim, _tsim mapping + # now do _fsim, _osim, _tsim mapping $val =~ s{_ssim\.vhd$}{_fsim.vhd} if $is_fsim; - $val =~ s{_ssim\.vhd$}{_tsim.vhd} if $is_tsim; + $val =~ s{_ssim\.vhd$}{_osim.vhd} if $is_osim; + $val =~ s{_ssim\.vhd$}{_tsim.vhd} if $is_tsim && $is_ise; # ISE + $val =~ s{_ssim\.vhd$}{_tsim.v} if $is_tsim && $is_viv; # Vivado # process normal .vhd or .vbom file lines # canonize file name unless not already done by filename substitution @@ -828,8 +1129,17 @@ sub read_vbom { $fullname = canon_fname($vbom_path, $val); } + # process @uut tag here, with canonized file names + if ($uut_seen) { + if (defined $uut) { + print STDERR "vbomconv-E: duplicate \@uut:, 1st '$uut' 2nd '$val'\n"; + exit 1; + } + $uut = $fullname; + } + # determine whether additional libs needed - if ($fullname =~ m{_ssim\.vhd$}) { # ends in _ssim.vhd + if ($fullname =~ m{_[so]sim\.vhd$}) { # ends in _ssim.vhd or _osim.vhd $has_unisim = 1; } if ($fullname =~ m{_[ft]sim\.vhd$}) { # ends in _fsim.vhd or _tsim.vhd @@ -871,10 +1181,9 @@ sub scan_vbom { $vbom_rank{$vbom} = {min=>$level, max=>$level}; } - foreach (@{$vbom_files{$vbom}}) { - my $file = $_; + foreach my $file (@{$vbom_files{$vbom}}) { $rank -= 1; - if (m{\.vbom$}) { + if ($file =~ m{\.vbom$}) { scan_vbom($file); } else { if (exists $srcfile_rank{$file}) { @@ -898,6 +1207,42 @@ sub scan_vbom { #------------------------------------------------------------------------------- +sub do_synsim { + my ($uut) = @_; + + # all is syn if no @uut defined; preset with sim when @uut defined + my $def = (defined $uut) ? 'sim' : 'syn'; + foreach my $file (keys %srcfile_rank) { + $srcfile_synsim{$file} = $def; + } + return unless defined $uut; + + # if @uut seen separate them + if (defined $uut) { + if ($uut =~ m{\.vbom}) { # uut is vbom (functional sim) + scan_synsim($uut); + } else { # uut is file (post syn sim) + $srcfile_synsim{$uut} = 'syn'; + } + } +} + +#------------------------------------------------------------------------------- + +sub scan_synsim { + my ($vbom) = @_; + + foreach my $file (@{$vbom_files{$vbom}}) { + if ($file =~ m{\.vbom$}) { + scan_synsim($file); + } else { + $srcfile_synsim{$file} = 'syn'; + } + } +} + +#------------------------------------------------------------------------------- + sub copy_edir { my ($file, $edir) = @_; print "cp -p $file $edir\n"; @@ -959,6 +1304,8 @@ sub print_help { print " --ghdl_export=s export all ghdl source files into directory s\n"; print " --xst_export=s export all xst source files into directory s\n"; print " --isim_export=s export all isim source files into directory s\n"; + print " --vsyn_export=s export all vsyn source files into directory s\n"; + print " --vsim_export=s export all vsim source files into directory s\n"; print " --get_top return top level entity name\n"; print " --flist list all files touched by vbom for all tags\n"; } diff --git a/tools/bin/xtwi b/tools/bin/xtwi index e5eace9e..83a62d62 100755 --- a/tools/bin/xtwi +++ b/tools/bin/xtwi @@ -1,7 +1,7 @@ #!/bin/bash -# $Id: xtwi 641 2015-02-01 22:12:15Z mueller $ +# $Id: xtwi 735 2016-02-26 22:17:42Z mueller $ # -# Copyright 2013- by Walter F.J. Mueller +# Copyright 2013-2016 by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory # # Xilinx Tool Wrapper script for ISE: @@ -10,6 +10,7 @@ # # Revision History: # Date Rev Version Comment +# 2016-02-21 735 1.1 use BARE_PATH ect to provide clean environment # 2013-10-12 539 1.0 Initial version # # Note: For Xilinx ISE installations with an install path holds @@ -31,6 +32,18 @@ then exit 1 fi + # provide clean environment when BARE_PATH ect defined + # add only $RETROBASE/tools/bin to path + if [ -n "$BARE_PATH" ] + then + export PATH=$BARE_PATH:$RETROBASE/tools/bin + unset LD_LIBRARY_PATH + if [ -n "$BARE_LD_LIBRARY_PATH" ] + then + export LD_LIBRARY_PATH=$BARE_LD_LIBRARY_PATH + fi + fi + # check whether 32 or 64 bit system (uname -m gives 'i686' or 'x86_64') if [ `uname -m` = "x86_64" ] then diff --git a/tools/bin/xtwv b/tools/bin/xtwv index 219e82d3..42769404 100755 --- a/tools/bin/xtwv +++ b/tools/bin/xtwv @@ -1,7 +1,7 @@ #!/bin/bash -# $Id: xtwv 641 2015-02-01 22:12:15Z mueller $ +# $Id: xtwv 735 2016-02-26 22:17:42Z mueller $ # -# Copyright 2013- by Walter F.J. Mueller +# Copyright 2013-2016 by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory # # Xilinx Tool Wrapper script for Vivado @@ -10,6 +10,7 @@ # # Revision History: # Date Rev Version Comment +# 2016-02-21 735 1.1 use BARE_PATH ect to provide clean environment # 2014-04-18 554 1.0.1 fake XILINX_VIVADO, 2014.1 doesn't define it anymore # 2013-10-12 539 1.0 Initial version (cloned from xtwi) # @@ -31,6 +32,18 @@ then exit 1 fi + # provide clean environment when BARE_PATH ect defined + # add only $RETROBASE/tools/bin to path + if [ -n "$BARE_PATH" ] + then + export PATH=$BARE_PATH:$RETROBASE/tools/bin + unset LD_LIBRARY_PATH + if [ -n "$BARE_LD_LIBRARY_PATH" ] + then + export LD_LIBRARY_PATH=$BARE_LD_LIBRARY_PATH + fi + fi + # check whether 32 or 64 bit system (uname -m gives 'i686' or 'x86_64') if [ `uname -m` = "x86_64" ] then diff --git a/tools/dox/w11_cpp.Doxyfile b/tools/dox/w11_cpp.Doxyfile index 07fefa43..e6237282 100644 --- a/tools/dox/w11_cpp.Doxyfile +++ b/tools/dox/w11_cpp.Doxyfile @@ -5,7 +5,7 @@ #--------------------------------------------------------------------------- DOXYFILE_ENCODING = UTF-8 PROJECT_NAME = "w11 - cpp" -PROJECT_NUMBER = 0.71 +PROJECT_NUMBER = 0.72 PROJECT_BRIEF = "Backend server for Rlink and w11" PROJECT_LOGO = OUTPUT_DIRECTORY = $(RETRODOXY)/w11/cpp diff --git a/tools/dox/w11_tcl.Doxyfile b/tools/dox/w11_tcl.Doxyfile index cc7bb546..d7d60adc 100644 --- a/tools/dox/w11_tcl.Doxyfile +++ b/tools/dox/w11_tcl.Doxyfile @@ -5,7 +5,7 @@ #--------------------------------------------------------------------------- DOXYFILE_ENCODING = UTF-8 PROJECT_NAME = "w11 - tcl" -PROJECT_NUMBER = 0.71 +PROJECT_NUMBER = 0.72 PROJECT_BRIEF = "Backend server for Rlink and w11" PROJECT_LOGO = OUTPUT_DIRECTORY = $(RETRODOXY)/w11/tcl diff --git a/tools/dox/w11_vhd_all.Doxyfile b/tools/dox/w11_vhd_all.Doxyfile index 2dcb2f34..d18b4fe0 100644 --- a/tools/dox/w11_vhd_all.Doxyfile +++ b/tools/dox/w11_vhd_all.Doxyfile @@ -5,7 +5,7 @@ #--------------------------------------------------------------------------- DOXYFILE_ENCODING = UTF-8 PROJECT_NAME = "w11 - vhd" -PROJECT_NUMBER = 0.71 +PROJECT_NUMBER = 0.72 PROJECT_BRIEF = "W11 CPU core and support modules" PROJECT_LOGO = OUTPUT_DIRECTORY = $(RETRODOXY)/w11/vhd diff --git a/tools/fx2/src/.cvsignore b/tools/fx2/src/.cvsignore index 885dad92..d9c355f0 100644 --- a/tools/fx2/src/.cvsignore +++ b/tools/fx2/src/.cvsignore @@ -1,7 +1,6 @@ *.asm *.ihx *.lnk -*.lst *.map *.mem *.rel diff --git a/tools/fx2/src/lib/.cvsignore b/tools/fx2/src/lib/.cvsignore index e02bc913..64d96c6b 100644 --- a/tools/fx2/src/lib/.cvsignore +++ b/tools/fx2/src/lib/.cvsignore @@ -1,7 +1,6 @@ *.asm *.ihx *.lnk -*.lst *.map *.mem *.rel diff --git a/tools/make/generic_so.mk b/tools/make/generic_so.mk index 18e04976..d58d9185 100644 --- a/tools/make/generic_so.mk +++ b/tools/make/generic_so.mk @@ -1,4 +1,4 @@ -# $Id: generic_so.mk 515 2013-05-04 17:28:59Z mueller $ +# $Id: generic_so.mk 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -15,7 +15,7 @@ # SOMINV minor version number # ifndef SOPATH -SOPATH = $(RETROBASE)/tools/lib +SOPATH = ${RETROBASE}/tools/lib endif # SOFILE = lib$(SONAME).so diff --git a/tools/make/generic_so_c.mk b/tools/make/generic_so_c.mk index 56c48198..84fc2d32 100644 --- a/tools/make/generic_so_c.mk +++ b/tools/make/generic_so_c.mk @@ -1,4 +1,4 @@ -# $Id: generic_so_c.mk 600 2014-11-02 22:33:02Z mueller $ +# $Id: generic_so_c.mk 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -16,7 +16,7 @@ # SOMINV minor version number # ifndef SOPATH -SOPATH = $(RETROBASE)/tools/lib +SOPATH = ${RETROBASE}/tools/lib endif # SOFILE = lib$(SONAME).so diff --git a/tools/oskit/211bsd_rk/.cvsignore b/tools/oskit/211bsd_rk/.cvsignore index e60dfe3f..24426de9 100644 --- a/tools/oskit/211bsd_rk/.cvsignore +++ b/tools/oskit/211bsd_rk/.cvsignore @@ -1,6 +1,4 @@ *.dat -*.dsk -*.log *hook.tcl *license.txt *license.pdf diff --git a/tools/oskit/211bsd_rl/.cvsignore b/tools/oskit/211bsd_rl/.cvsignore index e60dfe3f..24426de9 100644 --- a/tools/oskit/211bsd_rl/.cvsignore +++ b/tools/oskit/211bsd_rl/.cvsignore @@ -1,6 +1,4 @@ *.dat -*.dsk -*.log *hook.tcl *license.txt *license.pdf diff --git a/tools/oskit/211bsd_rp/.cvsignore b/tools/oskit/211bsd_rp/.cvsignore index 6c95b717..24426de9 100644 --- a/tools/oskit/211bsd_rp/.cvsignore +++ b/tools/oskit/211bsd_rp/.cvsignore @@ -1,7 +1,4 @@ *.dat -*.dsk -*.log -*.tgz *hook.tcl *license.txt *license.pdf diff --git a/tools/oskit/211bsd_tm/.cvsignore b/tools/oskit/211bsd_tm/.cvsignore index 809a0d32..24426de9 100644 --- a/tools/oskit/211bsd_tm/.cvsignore +++ b/tools/oskit/211bsd_tm/.cvsignore @@ -1,8 +1,4 @@ *.dat -*.dsk -*.log -*.tap -*.tgz *hook.tcl *license.txt *license.pdf diff --git a/tools/oskit/rsx11m-31_rk/.cvsignore b/tools/oskit/rsx11m-31_rk/.cvsignore index d1821140..dd9e902c 100644 --- a/tools/oskit/rsx11m-31_rk/.cvsignore +++ b/tools/oskit/rsx11m-31_rk/.cvsignore @@ -1,5 +1,3 @@ *.dat -*.dsk -*.log *hook.tcl *license.txt diff --git a/tools/oskit/rsx11m-40_rk/.cvsignore b/tools/oskit/rsx11m-40_rk/.cvsignore index d1821140..dd9e902c 100644 --- a/tools/oskit/rsx11m-40_rk/.cvsignore +++ b/tools/oskit/rsx11m-40_rk/.cvsignore @@ -1,5 +1,3 @@ *.dat -*.dsk -*.log *hook.tcl *license.txt diff --git a/tools/oskit/rsx11mp-30_rp/.cvsignore b/tools/oskit/rsx11mp-30_rp/.cvsignore index e60dfe3f..24426de9 100644 --- a/tools/oskit/rsx11mp-30_rp/.cvsignore +++ b/tools/oskit/rsx11mp-30_rp/.cvsignore @@ -1,6 +1,4 @@ *.dat -*.dsk -*.log *hook.tcl *license.txt *license.pdf diff --git a/tools/oskit/rt11-40_rk/.cvsignore b/tools/oskit/rt11-40_rk/.cvsignore index d1821140..dd9e902c 100644 --- a/tools/oskit/rt11-40_rk/.cvsignore +++ b/tools/oskit/rt11-40_rk/.cvsignore @@ -1,5 +1,3 @@ *.dat -*.dsk -*.log *hook.tcl *license.txt diff --git a/tools/oskit/rt11-53_rl/.cvsignore b/tools/oskit/rt11-53_rl/.cvsignore index d1821140..dd9e902c 100644 --- a/tools/oskit/rt11-53_rl/.cvsignore +++ b/tools/oskit/rt11-53_rl/.cvsignore @@ -1,5 +1,3 @@ *.dat -*.dsk -*.log *hook.tcl *license.txt diff --git a/tools/oskit/unix-v5_rk/.cvsignore b/tools/oskit/unix-v5_rk/.cvsignore index e60dfe3f..24426de9 100644 --- a/tools/oskit/unix-v5_rk/.cvsignore +++ b/tools/oskit/unix-v5_rk/.cvsignore @@ -1,6 +1,4 @@ *.dat -*.dsk -*.log *hook.tcl *license.txt *license.pdf diff --git a/tools/oskit/xxdp_rl/.cvsignore b/tools/oskit/xxdp_rl/.cvsignore index e4fdb970..ac9b659d 100644 --- a/tools/oskit/xxdp_rl/.cvsignore +++ b/tools/oskit/xxdp_rl/.cvsignore @@ -1,5 +1,2 @@ -*.gz *.dat -*.dsk -*.log *hook.tcl diff --git a/tools/src/librlink/Makefile b/tools/src/librlink/Makefile index 6956b82d..06b541b2 100644 --- a/tools/src/librlink/Makefile +++ b/tools/src/librlink/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 602 2014-11-08 21:42:47Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -43,10 +43,10 @@ SOFILE = lib$(SONAME).so SOFILEV = lib$(SONAME).so.$(SOMAJV) SOFILEVV = lib$(SONAME).so.$(SOMAJV).$(SOMINV) # -include $(RETROBASE)/tools/make/generic_cpp.mk -include $(RETROBASE)/tools/make/generic_dep.mk -include $(RETROBASE)/tools/make/generic_so.mk -include $(RETROBASE)/tools/make/dontincdep.mk +include ${RETROBASE}/tools/make/generic_cpp.mk +include ${RETROBASE}/tools/make/generic_dep.mk +include ${RETROBASE}/tools/make/generic_so.mk +include ${RETROBASE}/tools/make/dontincdep.mk # # The magic auto-dependency include # diff --git a/tools/src/librlinktpp/Makefile b/tools/src/librlinktpp/Makefile index acbb5fe3..c25f37fd 100644 --- a/tools/src/librlinktpp/Makefile +++ b/tools/src/librlinktpp/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 602 2014-11-08 21:42:47Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -23,7 +23,7 @@ SOMINV = 0 include ../checkpath_cpp.mk # INCLFLAGS = -I${RETROBASE}/tools/src -I${TCLINC} -I${BOOSTINC} -LDLIBS = -L$(TCLLIB) -l$(TCLLIBNAME) +LDLIBS = -L${TCLLIB} -l${TCLLIBNAME} LDLIBS += -L${RETROBASE}/tools/lib -lrtools -lrtcltools -lrlink # # Object files to be included @@ -39,10 +39,10 @@ SOFILE = lib$(SONAME).so SOFILEV = lib$(SONAME).so.$(SOMAJV) SOFILEVV = lib$(SONAME).so.$(SOMAJV).$(SOMINV) # -include $(RETROBASE)/tools/make/generic_cpp.mk -include $(RETROBASE)/tools/make/generic_dep.mk -include $(RETROBASE)/tools/make/generic_so.mk -include $(RETROBASE)/tools/make/dontincdep.mk +include ${RETROBASE}/tools/make/generic_cpp.mk +include ${RETROBASE}/tools/make/generic_dep.mk +include ${RETROBASE}/tools/make/generic_so.mk +include ${RETROBASE}/tools/make/dontincdep.mk # # The magic auto-dependency include # diff --git a/tools/src/librtcltools/Makefile b/tools/src/librtcltools/Makefile index 849b6fb1..cb1ee9b7 100644 --- a/tools/src/librtcltools/Makefile +++ b/tools/src/librtcltools/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 529 2013-08-02 17:15:43Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -36,10 +36,10 @@ SOFILE = lib$(SONAME).so SOFILEV = lib$(SONAME).so.$(SOMAJV) SOFILEVV = lib$(SONAME).so.$(SOMAJV).$(SOMINV) # -include $(RETROBASE)/tools/make/generic_cpp.mk -include $(RETROBASE)/tools/make/generic_dep.mk -include $(RETROBASE)/tools/make/generic_so.mk -include $(RETROBASE)/tools/make/dontincdep.mk +include ${RETROBASE}/tools/make/generic_cpp.mk +include ${RETROBASE}/tools/make/generic_dep.mk +include ${RETROBASE}/tools/make/generic_so.mk +include ${RETROBASE}/tools/make/dontincdep.mk # # The magic auto-dependency include # diff --git a/tools/src/librtools/Makefile b/tools/src/librtools/Makefile index adebc46d..a114c50e 100644 --- a/tools/src/librtools/Makefile +++ b/tools/src/librtools/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 600 2014-11-02 22:33:02Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -38,10 +38,10 @@ SOFILE = lib$(SONAME).so SOFILEV = lib$(SONAME).so.$(SOMAJV) SOFILEVV = lib$(SONAME).so.$(SOMAJV).$(SOMINV) # -include $(RETROBASE)/tools/make/generic_cpp.mk -include $(RETROBASE)/tools/make/generic_dep.mk -include $(RETROBASE)/tools/make/generic_so.mk -include $(RETROBASE)/tools/make/dontincdep.mk +include ${RETROBASE}/tools/make/generic_cpp.mk +include ${RETROBASE}/tools/make/generic_dep.mk +include ${RETROBASE}/tools/make/generic_so.mk +include ${RETROBASE}/tools/make/dontincdep.mk # # The magic auto-dependency include # diff --git a/tools/src/librutiltpp/Makefile b/tools/src/librutiltpp/Makefile index c6fd7f1b..a3d4c351 100644 --- a/tools/src/librutiltpp/Makefile +++ b/tools/src/librutiltpp/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 602 2014-11-08 21:42:47Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -23,7 +23,7 @@ include ../checkpath_cpp.mk # INCLFLAGS = -I${RETROBASE}/tools/src -I${TCLINC} -I${BOOSTINC} LDLIBS = -lpthread -LDLIBS += -L$(TCLLIB) -l$(TCLLIBNAME) +LDLIBS += -L${TCLLIB} -l${TCLLIBNAME} LDLIBS += -L${RETROBASE}/tools/lib -lrtcltools # # Object files to be included @@ -38,10 +38,10 @@ SOFILE = lib$(SONAME).so SOFILEV = lib$(SONAME).so.$(SOMAJV) SOFILEVV = lib$(SONAME).so.$(SOMAJV).$(SOMINV) # -include $(RETROBASE)/tools/make/generic_cpp.mk -include $(RETROBASE)/tools/make/generic_dep.mk -include $(RETROBASE)/tools/make/generic_so.mk -include $(RETROBASE)/tools/make/dontincdep.mk +include ${RETROBASE}/tools/make/generic_cpp.mk +include ${RETROBASE}/tools/make/generic_dep.mk +include ${RETROBASE}/tools/make/generic_so.mk +include ${RETROBASE}/tools/make/dontincdep.mk # # The magic auto-dependency include # diff --git a/tools/src/librw11/Makefile b/tools/src/librw11/Makefile index e34b3554..89f4f0e8 100644 --- a/tools/src/librw11/Makefile +++ b/tools/src/librw11/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 685 2015-05-25 12:18:36Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -50,10 +50,10 @@ SOFILE = lib$(SONAME).so SOFILEV = lib$(SONAME).so.$(SOMAJV) SOFILEVV = lib$(SONAME).so.$(SOMAJV).$(SOMINV) # -include $(RETROBASE)/tools/make/generic_cpp.mk -include $(RETROBASE)/tools/make/generic_dep.mk -include $(RETROBASE)/tools/make/generic_so.mk -include $(RETROBASE)/tools/make/dontincdep.mk +include ${RETROBASE}/tools/make/generic_cpp.mk +include ${RETROBASE}/tools/make/generic_dep.mk +include ${RETROBASE}/tools/make/generic_so.mk +include ${RETROBASE}/tools/make/dontincdep.mk # # The magic auto-dependency include # diff --git a/tools/src/librwxxtpp/Makefile b/tools/src/librwxxtpp/Makefile index 8837413e..9d67c745 100644 --- a/tools/src/librwxxtpp/Makefile +++ b/tools/src/librwxxtpp/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 683 2015-05-17 21:54:35Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -18,7 +18,7 @@ SOMINV = 0 include ../checkpath_cpp.mk # INCLFLAGS = -I${RETROBASE}/tools/src -I${TCLINC} -I${BOOSTINC} -LDLIBS = -L$(TCLLIB) -l$(TCLLIBNAME) +LDLIBS = -L${TCLLIB} -l${TCLLIBNAME} LDLIBS += -L${RETROBASE}/tools/lib -lrtools -lrtcltools LDLIBS += -lrlink -lrw11 LDLIBS += -lrlinktpp @@ -49,10 +49,10 @@ SOFILE = lib$(SONAME).so SOFILEV = lib$(SONAME).so.$(SOMAJV) SOFILEVV = lib$(SONAME).so.$(SOMAJV).$(SOMINV) # -include $(RETROBASE)/tools/make/generic_cpp.mk -include $(RETROBASE)/tools/make/generic_dep.mk -include $(RETROBASE)/tools/make/generic_so.mk -include $(RETROBASE)/tools/make/dontincdep.mk +include ${RETROBASE}/tools/make/generic_cpp.mk +include ${RETROBASE}/tools/make/generic_dep.mk +include ${RETROBASE}/tools/make/generic_so.mk +include ${RETROBASE}/tools/make/dontincdep.mk # # The magic auto-dependency include # diff --git a/tools/src/tclshcpp/Makefile b/tools/src/tclshcpp/Makefile index af2bb677..7037205f 100644 --- a/tools/src/tclshcpp/Makefile +++ b/tools/src/tclshcpp/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 601 2014-11-07 22:44:43Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # @@ -11,9 +11,9 @@ include ../checkpath_cpp.mk # INCLFLAGS = -I${TCLINC} -LDLIBS += -L$(TCLLIB) -l$(TCLLIBNAME) +LDLIBS += -L${TCLLIB} -l${TCLLIBNAME} # -BINPATH = $(RETROBASE)/tools/bin +BINPATH = ${RETROBASE}/tools/bin # # Object files to be included # @@ -28,9 +28,9 @@ $(BINPATH)/tclshcpp : $(OBJ_all) #- generic part ---------------------------------------------------------------- # -include $(RETROBASE)/tools/make/generic_cpp.mk -include $(RETROBASE)/tools/make/generic_dep.mk -include $(RETROBASE)/tools/make/dontincdep.mk +include ${RETROBASE}/tools/make/generic_cpp.mk +include ${RETROBASE}/tools/make/generic_dep.mk +include ${RETROBASE}/tools/make/dontincdep.mk # # The magic auto-dependency include # diff --git a/tools/src/testtclsh/Makefile b/tools/src/testtclsh/Makefile index b7230524..8192faec 100644 --- a/tools/src/testtclsh/Makefile +++ b/tools/src/testtclsh/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 601 2014-11-07 22:44:43Z mueller $ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ # # Revision History: # Date Rev Version Comment @@ -10,7 +10,7 @@ include ../checkpath_cpp.mk # INCLFLAGS = -I${TCLINC} -I${RETROBASE}/tools/src LDLIBS = -lreadline -LDLIBS += -L$(TCLLIB) -l$(TCLLIBNAME) -lreadline +LDLIBS += -L${TCLLIB} -l${TCLLIBNAME} -lreadline LDLIBS += -L${RETROBASE}/tools/lib -lrtcltools LDLIBS += -lrutiltpp -lrlinktpp -lrwxxtpp #LDLIBS += -lrusbtpp @@ -25,9 +25,9 @@ testtclsh : $(OBJ_all) #- generic part ---------------------------------------------------------------- # -include $(RETROBASE)/tools/make/generic_cpp.mk -include $(RETROBASE)/tools/make/generic_dep.mk -include $(RETROBASE)/tools/make/dontincdep.mk +include ${RETROBASE}/tools/make/generic_cpp.mk +include ${RETROBASE}/tools/make/generic_dep.mk +include ${RETROBASE}/tools/make/dontincdep.mk # # The magic auto-dependency include # diff --git a/tools/tbench/w11a_hbpt/test_hbpt_basics.tcl b/tools/tbench/w11a_hbpt/test_hbpt_basics.tcl index 522dd5ca..22a15709 100644 --- a/tools/tbench/w11a_hbpt/test_hbpt_basics.tcl +++ b/tools/tbench/w11a_hbpt/test_hbpt_basics.tcl @@ -1,10 +1,11 @@ -# $Id: test_hbpt_basics.tcl 722 2015-12-30 19:45:46Z mueller $ +# $Id: test_hbpt_basics.tcl 724 2016-01-03 22:53:53Z mueller $ # -# Copyright 2015- by Walter F.J. Mueller +# Copyright 2015-2016 by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory # # Revision History: # Date Rev Version Comment +# 2016-01-02 724 1.0.2 use s: defs for CP_STAT(rust) # 2015-12-30 721 1.0.1 BUGFIX: add missing wtcpu in mfpd/mtpd tests # 2015-07-11 700 1.0 Initial version # @@ -63,14 +64,14 @@ rw11::hb_set cpu0 0 i $sym(I1) rw11::asmrun $cpu sym $cpu wtcpu -reset $rw11::asmwait_tout $cpu cp -rreg "hb0.stat" -edata [regbld rw11::HB_STAT irseen] \ - -rstat -edata [regbld rw11::CP_STAT suspint {rust 06} susp go] \ + -rstat -edata [regbld rw11::CP_STAT suspint {rust hbpt} susp go] \ -rpc -edata $sym(I2) \ -rr0 -edata 1 rlc log " A2.2: step after ir break --------------------------" $cpu cp -step $cpu cp -rreg "hb0.stat" -edata [regbld rw11::HB_STAT irseen] \ - -rstat -edata [regbld rw11::CP_STAT suspint {rust 04} susp go] \ + -rstat -edata [regbld rw11::CP_STAT suspint {rust step} susp go] \ -rpc -edata $sym(I3) \ -rr0 -edata 2 @@ -85,14 +86,14 @@ rw11::hb_set cpu0 0 i $sym(I2) $sym(I3) rw11::asmrun $cpu sym $cpu wtcpu -reset $rw11::asmwait_tout $cpu cp -rreg "hb0.stat" -edata [regbld rw11::HB_STAT irseen] \ - -rstat -edata [regbld rw11::CP_STAT suspint {rust 06} susp go] \ + -rstat -edata [regbld rw11::CP_STAT suspint {rust hbpt} susp go] \ -rpc -edata $sym(I3) \ -rr0 -edata 2 rlc log " A3.2: resume, should re-break ----------------------" $cpu cp -resume $cpu wtcpu -reset $rw11::asmwait_tout -$cpu cp -rstat -edata [regbld rw11::CP_STAT suspint {rust 06} susp go] \ +$cpu cp -rstat -edata [regbld rw11::CP_STAT suspint {rust hbpt} susp go] \ -rpc -edata $sym(I4) \ -rr0 -edata 3 @@ -107,7 +108,7 @@ rw11::hb_set cpu0 0 r $sym(a) rw11::asmrun $cpu sym $cpu wtcpu -reset $rw11::asmwait_tout $cpu cp -rreg "hb0.stat" -edata [regbld rw11::HB_STAT drseen] \ - -rstat -edata [regbld rw11::CP_STAT suspint {rust 06} susp go] \ + -rstat -edata [regbld rw11::CP_STAT suspint {rust hbpt} susp go] \ -rpc -edata $sym(I5) \ -rr1 -edata 0123 @@ -117,7 +118,7 @@ rw11::hb_set cpu0 0 r $sym(pd) $cpu cp -resume $cpu wtcpu -reset $rw11::asmwait_tout $cpu cp -rreg "hb0.stat" -edata [regbld rw11::HB_STAT drseen] \ - -rstat -edata [regbld rw11::CP_STAT suspint {rust 06} susp go] \ + -rstat -edata [regbld rw11::CP_STAT suspint {rust hbpt} susp go] \ -rpc -edata $sym(I8) \ -rr2 -edata 0234 @@ -127,7 +128,7 @@ rw11::hb_set cpu0 0 w $sym(c) rw11::asmrun $cpu sym $cpu wtcpu -reset $rw11::asmwait_tout $cpu cp -rreg "hb0.stat" -edata [regbld rw11::HB_STAT dwseen] \ - -rstat -edata [regbld rw11::CP_STAT suspint {rust 06} susp go] \ + -rstat -edata [regbld rw11::CP_STAT suspint {rust hbpt} susp go] \ -rpc -edata $sym(I7) \ -rr2 -edata 0234 @@ -137,7 +138,7 @@ rw11::hb_set cpu0 0 w $sym(d) $cpu cp -resume $cpu wtcpu -reset $rw11::asmwait_tout $cpu cp -rreg "hb0.stat" -edata [regbld rw11::HB_STAT dwseen] \ - -rstat -edata [regbld rw11::CP_STAT suspint {rust 06} susp go] \ + -rstat -edata [regbld rw11::CP_STAT suspint {rust hbpt} susp go] \ -rpc -edata $sym(I8) \ -rr2 -edata 0234 @@ -242,7 +243,7 @@ rw11::asmrun $cpu sym $cpu wtcpu -reset $rw11::asmwait_tout $cpu cp -rreg "hb0.stat" -edata [regbld rw11::HB_STAT dwseen] \ - -rstat -edata [regbld rw11::CP_STAT suspint {rust 06} susp go] \ + -rstat -edata [regbld rw11::CP_STAT suspint {rust hbpt} susp go] \ -rpc -edata $sym(I3) rlc log " C3.1: kernel dr break on mfpd (pm=user) -> no bpt --" @@ -263,7 +264,7 @@ rw11::hb_set cpu0 0 ur [expr $sym(c)] rw11::asmrun $cpu sym $cpu wtcpu -reset $rw11::asmwait_tout $cpu cp -rreg "hb0.stat" -edata [regbld rw11::HB_STAT drseen] \ - -rstat -edata [regbld rw11::CP_STAT suspint {rust 06} susp go] \ + -rstat -edata [regbld rw11::CP_STAT suspint {rust hbpt} susp go] \ -rpc -edata $sym(I5) rlc log " C4.1: kernel dw break on mtpd (pm=user) -> no bpt --" @@ -284,6 +285,6 @@ rw11::hb_set cpu0 0 uw [expr $sym(d)] rw11::asmrun $cpu sym $cpu wtcpu -reset $rw11::asmwait_tout $cpu cp -rreg "hb0.stat" -edata [regbld rw11::HB_STAT dwseen] \ - -rstat -edata [regbld rw11::CP_STAT suspint {rust 06} susp go] \ + -rstat -edata [regbld rw11::CP_STAT suspint {rust hbpt} susp go] \ -rpc -edata $sym(I7) diff --git a/tools/tcl/rbsysmon/.cvsignore b/tools/tcl/rbsysmon/.cvsignore new file mode 100644 index 00000000..fc959ab2 --- /dev/null +++ b/tools/tcl/rbsysmon/.cvsignore @@ -0,0 +1 @@ +pkgIndex.tcl diff --git a/tools/tcl/rbsysmon/util.tcl b/tools/tcl/rbsysmon/util.tcl new file mode 100644 index 00000000..f8647d90 --- /dev/null +++ b/tools/tcl/rbsysmon/util.tcl @@ -0,0 +1,306 @@ +# $Id: util.tcl 742 2016-03-13 14:40:19Z mueller $ +# +# Copyright 2016- by Walter F.J. Mueller +# +# This program is free software; you may redistribute and/or modify it under +# the terms of the GNU General Public License as published by the Free +# Software Foundation, either version 2, or at your option any later version. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for complete details. +# +# Revision History: +# Date Rev Version Comment +# 2016-03-13 742 1.0 Initial version +# 2016-03-12 741 0.1 First draft +# + +package provide rbsysmon 1.0 + +package require rutil +package require rutiltpp + +namespace eval rbsysmon { + # + # setup register descriptions for sysmon_rbus + # + regdsc CNTL {reset 15} + regdsc STAT {jlock 3} {jmod 2} {jbusy 1} {ot 0} + regdsc ALM {vccddr 6} {vccpaux 5} {vccpint 4} \ + {vccbram 3} {vccaux 2} {vccint 1} {temp 0} + + # + # sysmon/xadc register definitions + # + variable regdef_current {} + # + variable regdef_xadc_base { + "0x00|sm.temp|t|cur temp" + "0x01|sm.vint|vs|cur Vccint" + "0x02|sm.vaux|vs|cur Vccaux" + "0x04|sm.vrefp|vs|cur Vrefp" + "0x05|sm.vrefn|vsb|cur Vrefn" + "0x06|sm.vbram|vs|cur Vccbram" + "0x08|sm.supaoff|v|supply A off" + "0x09|sm.adcaoff|vb|ADC A off" + "0x0a|sm.adcafac|g|ADC A gain" + "0x20|sm.tempma|t|max temp" + "0x21|sm.vintma|vs|max Vccint" + "0x22|sm.vauxma|vs|max Vccaux" + "0x23|sm.vbramma|vs|max Vccbram" + "0x24|sm.tempmi|t|min temp" + "0x25|sm.vintmi|vs|min Vccint" + "0x26|sm.vauxmi|vs|min Vccaux" + "0x27|sm.vbrammi|vs|min Vccbram" + "0x3f|sm.flag|b|flag reg" + "0x40|sm.conf0|b|conf 0" + "0x41|sm.conf1|b|conf 1" + "0x42|sm.conf2|b|conf 2" + "0x48|sm.seq00|b|select 0" + "0x49|sm.seq01|b|select 1" + "0x4a|sm.seq02|b|average 0" + "0x4b|sm.seq03|b|average 1" + "0x4c|sm.seq04|b|mode 0" + "0x4d|sm.seq05|b|mode 1" + "0x4e|sm.seq06|b|time 0" + "0x4f|sm.seq07|b|time 1" + "0x50|sm.alm00|t|temp up" + "0x51|sm.alm01|vs|ccint up" + "0x52|sm.alm02|vs|ccaux up" + "0x53|sm.alm03|t|ot limit" + "0x54|sm.alm04|t|temp low" + "0x55|sm.alm05|vs|ccint low" + "0x56|sm.alm06|vs|ccaux low" + "0x57|sm.alm07|t|ot reset" + "0x58|sm.alm08|vs|ccbram up" + "0x5c|sm.alm0c|vs|ccbram low" + "0x78|sm.rcntl|b|rbus cntl" + "0x79|sm.rstat|b|rbus stat" + "0x7a|sm.ralmh|b|rbus almh" + "0x7c|sm.rtemp|b|rbus temp" + "0x7d|sm.ralm|b|rbus aml" + "0x7f|sm.reos|d|rbus eos" + } + variable regdef_xadc_arty { + "0x11|sm.v01|v|cur Vaux[1]" + "0x12|sm.v02|v|cur Vaux[2]" + "0x19|sm.v09|v|cur Vaux[9]" + "0x1a|sm.v10|v|cur Vaux[10]" + } + + # + # setup_xadc + # + proc setup_xadc_base {{base 0xfb00}} { + variable regdef_current + set regdef_current $rbsysmon::regdef_xadc_base + setup_gen $base + } + + # + # setup_arty + # + proc setup_xadc_arty {{base 0xfb00}} { + variable regdef_current + set regdef_current [lsort [concat $rbsysmon::regdef_xadc_base \ + $rbsysmon::regdef_xadc_arty]] + setup_gen $base + } + + # + # setup_gen: amap definitions for sysmon_rbus + # + proc setup_gen {base} { + variable regdef_current + foreach def $regdef_current { + set defp [split $def "|"] + set off [lindex $defp 0] + set nam [lindex $defp 1] + rlc amap -insert $nam [expr {$base + $off}] + } + } + + # + # reset: reset xadc/sysmon + # + proc reset {} { + rlc exec -wreg sm.rcntl [regbld rbsysmon::CNTL reset] + } + + # + # print_raw: show all sysmon/xadc registers + # + proc print_raw {} { + variable regdef_current + set rval "name description : hex other" + foreach def $regdef_current { + set defp [split $def "|"] + set nam [lindex $defp 1] + set fmt [lindex $defp 2] + set txt [lindex $defp 3] + rlc exec -rreg $nam val + set line [format "%-10s %-20s: %4.4x " $nam $txt $val] + switch $fmt { + b { append line [pbvi b16 $val]} + d { append line [format "%6d" $val]} + t { append line [format "%6.1f deg" [conv_raw2t $val]]} + vs { append line [format "%8.3f V" [conv_raw2vs $val]]} + vsb { append line [format "%8.3f V" [conv_raw2vsb $val]]} + v { append line [format "%8.3f V" [conv_raw2v $val]]} + vb { append line [format "%8.3f V" [conv_raw2vb $val]]} + g { append line [format "%8.3f %%" [conv_raw2g $val]]} + default { append line "? $fmt ?" } + } + append rval "\n$line" + } + return $rval + } + + # + # print: nicely formatted summary + # + proc print {} { + rlc exec \ + -rreg sm.ralmh r_almh \ + -rreg sm.ralm r_alm + + set rval "Value cur val min val max val low lim high lim alarm" + rlc exec \ + -rreg sm.temp r_val \ + -rreg sm.tempma r_valma \ + -rreg sm.tempmi r_valmi \ + -rreg sm.alm00 r_valup \ + -rreg sm.alm04 r_vallo + append rval \ + [format "\ntemp %6.1f d %6.1f %6.1f %6.1f %6.1f %s" \ + [conv_raw2t $r_val] \ + [conv_raw2t $r_valmi] \ + [conv_raw2t $r_valma] \ + [conv_raw2t $r_vallo] \ + [conv_raw2t $r_valup] \ + [print_fmt_alm temp $r_alm $r_almh] ] + + rlc exec \ + -rreg sm.vint r_val \ + -rreg sm.vintma r_valma \ + -rreg sm.vintmi r_valmi \ + -rreg sm.alm01 r_valup \ + -rreg sm.alm05 r_vallo + append rval \ + [format "\nVccint %8.3f V %8.3f %8.3f %8.3f %8.3f %s" \ + [conv_raw2vs $r_val] \ + [conv_raw2vs $r_valmi] \ + [conv_raw2vs $r_valma] \ + [conv_raw2vs $r_vallo] \ + [conv_raw2vs $r_valup] \ + [print_fmt_alm vccint $r_alm $r_almh] ] + + rlc exec \ + -rreg sm.vaux r_val \ + -rreg sm.vauxma r_valma \ + -rreg sm.vauxmi r_valmi \ + -rreg sm.alm02 r_valup \ + -rreg sm.alm06 r_vallo + append rval \ + [format "\nVccaux %8.3f V %8.3f %8.3f %8.3f %8.3f %s" \ + [conv_raw2vs $r_val] \ + [conv_raw2vs $r_valmi] \ + [conv_raw2vs $r_valma] \ + [conv_raw2vs $r_vallo] \ + [conv_raw2vs $r_valup] \ + [print_fmt_alm vccaux $r_alm $r_almh] ] + + rlc exec \ + -rreg sm.vbram r_val \ + -rreg sm.vbramma r_valma \ + -rreg sm.vbrammi r_valmi \ + -rreg sm.alm08 r_valup \ + -rreg sm.alm0c r_vallo + append rval \ + [format "\nVccbram %8.3f V %8.3f %8.3f %8.3f %8.3f %s" \ + [conv_raw2vs $r_val] \ + [conv_raw2vs $r_valmi] \ + [conv_raw2vs $r_valma] \ + [conv_raw2vs $r_vallo] \ + [conv_raw2vs $r_valup] \ + [print_fmt_alm vccbram $r_alm $r_almh] ] + + if {[rlc amap -testname sm.v01]} { + rlc exec \ + -rreg sm.v01 r_v01 \ + -rreg sm.v02 r_v02 \ + -rreg sm.v09 r_v09 \ + -rreg sm.v10 r_10 + append rval \ + [format "\nV 5V0 %8.3f V" \ + [expr { 5.99 * [conv_raw2v $r_v01]} ] ] + append rval \ + [format "\nV VU %8.3f V" \ + [expr { 16.0 * [conv_raw2v $r_v02]} ] ] + append rval \ + [format "\nA 5V0 %8.3f A" \ + [expr { 4.0 * [conv_raw2v $r_v09]} ] ] + append rval \ + [format "\nA 0V95 %8.3f A" \ + [expr { 2.0 * [conv_raw2v $r_v09]} ] ] + } + + return $rval + } + + # + # helper for print + # + proc print_fmt_alm {chan alm almh} { + set cval [regget rbsysmon::ALM($chan) $alm] + set hval [regget rbsysmon::ALM($chan) $almh] + set cstr [expr {$cval ? "C!" : " "}] + set hstr [expr {$cval ? "H!" : " "}] + return "$cstr $hstr" + } + + # + # conversion procedures + # + proc conv_raw2t {val} { + return [expr {(($val / 65536.) * 503.975) - 273.14}] + } + proc conv_raw2vs {val} { + return [expr {($val / 65536.) * 3.}] + } + proc conv_raw2vsb {val} { + set val [rutil::sxt16 $val] + return [expr {($val / 65536.) * 3.}] + } + proc conv_raw2v {val} { + return [expr {$val / 65536.}] + } + proc conv_raw2vb {val} { + set val [rutil::sxt16 $val] + return [expr {$val / 65536.}] + } + proc conv_raw2g {val} { + set gmag [expr {$val & 0x3f}]; # get 6 lsbs + set gsig [expr {$val & 0x40}]; # get sign bit + set gain [expr {$gmag * 0.1}]; # unit is 0.1 % + if {$gsig == 0} {set gain [expr {-$gain}] } + return $gain + } + + # + # eosrate: returns eos rate (in Hz) + # + proc eosrate {} { + rlc exec -rreg sm.reos r_eosbeg + set tbeg [clock microseconds] + after 100 + rlc exec -rreg sm.reos r_eosend + set tend [clock microseconds] + set deos [expr {$r_eosend - $r_eosbeg}] + if {$deos < 0} {set deos [expr {$deos + 65536}]} + set dt [expr {($tend - $tbeg) * 1.e-6} ] + return [expr {$deos / $dt}] + } +} diff --git a/tools/tcl/rutil/regdsc.tcl b/tools/tcl/rutil/regdsc.tcl index bd9d06e1..ce8c8672 100644 --- a/tools/tcl/rutil/regdsc.tcl +++ b/tools/tcl/rutil/regdsc.tcl @@ -1,4 +1,4 @@ -# $Id: regdsc.tcl 705 2015-07-26 21:25:42Z mueller $ +# $Id: regdsc.tcl 724 2016-01-03 22:53:53Z mueller $ # # Copyright 2011-2015 by Walter F.J. Mueller # @@ -13,6 +13,7 @@ # # Revision History: # Date Rev Version Comment +# 2016-01-03 724 1.1.1 BUGFIX: regdsc: fix variable name in error msg # 2015-07-24 705 1.1 add regbldkv,reggetkv; regtxt: add {all 0} arg # add s:.. ptyp to support symbolic field values # 2015-06-26 695 1.0 Initial version (with reg* procs from util.tcl) @@ -56,7 +57,7 @@ namespace eval rutil { } foreach nam $popt { if {![string match {[A-Za-z]*} $nam]} { - error "regdsc-E: bad name \"$name\" for for \"$rdscName:$fnam\"" + error "regdsc-E: bad name \"$nam\" for for \"$rdscName:$fnam\"" } set nlen [string length $nam] if {$nlen > $plen} {set plen $nlen} diff --git a/tools/tcl/rw11/defs.tcl b/tools/tcl/rw11/defs.tcl index 84b8a28a..72207cd6 100644 --- a/tools/tcl/rw11/defs.tcl +++ b/tools/tcl/rw11/defs.tcl @@ -1,6 +1,6 @@ -# $Id: defs.tcl 719 2015-12-27 09:45:43Z mueller $ +# $Id: defs.tcl 724 2016-01-03 22:53:53Z mueller $ # -# Copyright 2014-2015 by Walter F.J. Mueller +# Copyright 2014-2016 by Walter F.J. Mueller # # This program is free software; you may redistribute and/or modify it under # the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ # # Revision History: # Date Rev Version Comment +# 2016-01-02 724 1.0.3 add s: defs for CP_STAT(rust) # 2015-12-26 719 1.0.2 add regmap_add defs; add CNTRL def # 2015-09-06 710 1.0.1 regdsc PSW: add silent n,z,v,c; *mode syms; fix tflag # 2014-03-07 553 1.0 Initial version (extracted from util.tcl) @@ -29,8 +30,23 @@ namespace eval rw11 { # setup cp interface register descriptions for w11a ----------------------- # regdsc CP_CNTL {func 3 0} - regdsc CP_STAT {suspext 9} {suspint 8} {rust 7 4} \ + + regdsc CP_STAT {suspext 9} {suspint 8} \ + {rust 7 4 "s:init:halt:reset:stop:step:susp:hbpt:runs:vecfet:recrsv:s1010:s1011:sfail:vfail:s1110:s1111"} \ {susp 3} {go 2} {merr 1} {err 0} + variable RUST_INIT [bvi b4 "0000"] + variable RUST_HALT [bvi b4 "0001"] + variable RUST_RESET [bvi b4 "0010"] + variable RUST_STOP [bvi b4 "0011"] + variable RUST_STEP [bvi b4 "0100"] + variable RUST_SUSP [bvi b4 "0101"] + variable RUST_HBPT [bvi b4 "0110"] + variable RUST_RUNS [bvi b4 "0111"] + variable RUST_VECFET [bvi b4 "1000"] + variable RUST_RECRSV [bvi b4 "1001"] + variable RUST_SFAIL [bvi b4 "1100"] + variable RUST_VFAIL [bvi b4 "1101"] + regdsc CP_AH {ubm 7} {p22 6} {addr 5 6} # # setup w11a register descriptions ----------------------------------------- diff --git a/tools/tcl/rw11/shell.tcl b/tools/tcl/rw11/shell.tcl index f1757d15..c94f309b 100644 --- a/tools/tcl/rw11/shell.tcl +++ b/tools/tcl/rw11/shell.tcl @@ -1,4 +1,4 @@ -# $Id: shell.tcl 717 2015-12-25 17:38:09Z mueller $ +# $Id: shell.tcl 724 2016-01-03 22:53:53Z mueller $ # # Copyright 2015- by Walter F.J. Mueller # @@ -198,7 +198,7 @@ namespace eval rw11 { if {$i > 0} {append rval "\n"} append rval [$shell_cpu show -pcps] $shell_cpu cp -rstat stat - if {[regget rw11::CP_STAT(rust) $stat] != 4} {break} + if {[regget rw11::CP_STAT(rust) $stat] != $rw11::RUST_STEP} {break} } return $rval } diff --git a/tools/tcl/setup_packages b/tools/tcl/setup_packages index 26feb8b0..37ec7c02 100755 --- a/tools/tcl/setup_packages +++ b/tools/tcl/setup_packages @@ -1,5 +1,5 @@ #! /usr/bin/env tclshcpp -# $Id: setup_packages 719 2015-12-27 09:45:43Z mueller $ +# $Id: setup_packages 741 2016-03-12 23:49:03Z mueller $ # pkg_mkIndex -verbose ../lib \ librlinktpp.so \ @@ -14,6 +14,7 @@ pkg_mkIndex -verbose rbmoni *.tcl pkg_mkIndex -verbose rbbram *.tcl pkg_mkIndex -verbose rbs3hio *.tcl pkg_mkIndex -verbose rbemon *.tcl +pkg_mkIndex -verbose rbsysmon *.tcl # pkg_mkIndex -verbose rw11 *.tcl pkg_mkIndex -verbose rw11util *.tcl