From e91847f8dbc18edf57c820394acb30b211e1f934 Mon Sep 17 00:00:00 2001 From: "Walter F.J. Mueller" Date: Mon, 9 Mar 2015 19:26:25 +0000 Subject: [PATCH] - added support for Vivado - added support for Nexys4 and Basys3 boards - added RL11 disk support - lots of documentation updated --- Makefile | 224 ++++-- doc/.cvsignore | 2 + doc/FILES.txt | 21 +- doc/INSTALL.txt | 364 ++------- doc/INSTALL_fx2_support.txt | 79 ++ doc/INSTALL_ghdl.txt | 22 +- doc/README.txt | 150 +++- doc/README_buildsystem_ISE.txt | 235 ++++++ doc/README_buildsystem_Vivado.txt | 190 +++++ doc/man/man1/config_wrapper.1 | 8 +- doc/man/man1/set_ftdi_lat.1 | 67 -- doc/man/man1/ti_rri.1 | 15 +- doc/man/man1/ti_w11.1 | 35 +- doc/man/man1/vbomconv.1 | 161 ++-- doc/man/man1/xilinx_ghdl_unisim.1 | 67 -- ...inx_ghdl_simprim.1 => xise_ghdl_simprim.1} | 37 +- doc/man/man1/xise_ghdl_unisim.1 | 68 ++ .../{isemsg_filter.1 => xise_msg_filter.1} | 22 +- doc/man/man1/xtwi.1 | 12 +- doc/man/man1/xtwv.1 | 17 +- doc/man/man1/xviv_ghdl_unisim.1 | 67 ++ doc/man/man5/vbom.5 | 34 +- doc/w11a_os_guide.txt | 170 ++-- doc/w11a_tb_guide.txt | 5 +- rtl/bplib/basys3/basys3_pclk.xdc | 14 + rtl/bplib/basys3/basys3_pins.xdc | 111 +++ rtl/bplib/basys3/basys3_setup.tcl | 4 + rtl/bplib/basys3/basys3lib.vhd | 46 ++ rtl/bplib/basys3/tb/tb_basys3.vbom | 25 + rtl/bplib/basys3/tb/tb_basys3.vhd | 175 ++++ rtl/bplib/basys3/tb/tb_basys3_core.vbom | 9 + rtl/bplib/basys3/tb/tb_basys3_core.vhd | 71 ++ rtl/bplib/bpgen/Makefile | 9 +- rtl/bplib/bpgen/bp_rs232_2l4l_iob.vhd | 4 +- rtl/bplib/bpgen/bp_rs232_2line_iob.vhd | 4 +- rtl/bplib/bpgen/bp_rs232_4line_iob.vhd | 4 +- rtl/bplib/bpgen/bp_swibtnled.vhd | 4 +- rtl/bplib/bpgen/bpgenlib.vhd | 37 +- rtl/bplib/bpgen/bpgenrbuslib.vhd | 32 +- .../{sn_4x7segctl.vbom => sn_7segctl.vbom} | 2 +- .../{sn_4x7segctl.vhd => sn_7segctl.vhd} | 79 +- rtl/bplib/bpgen/sn_humanio.vbom | 2 +- rtl/bplib/bpgen/sn_humanio.vhd | 44 +- rtl/bplib/bpgen/sn_humanio_demu.vhd | 4 +- rtl/bplib/bpgen/sn_humanio_demu_rbus.vhd | 4 +- rtl/bplib/bpgen/sn_humanio_rbus.vhd | 262 +++--- rtl/bplib/fx2lib/Makefile | 9 +- rtl/bplib/fx2lib/fx2_2fifoctl_as.vbom | 13 - rtl/bplib/fx2lib/fx2_2fifoctl_as.vhd | 647 --------------- rtl/bplib/fx2lib/fx2_2fifoctl_ic.vhd | 4 +- rtl/bplib/fx2lib/fx2_3fifoctl_ic.vhd | 4 +- rtl/bplib/fx2lib/fx2lib.vhd | 44 +- rtl/bplib/fx2lib/tb/fx2_2fifo_core.vhd | 4 +- rtl/bplib/fx2rlink/Makefile | 9 +- rtl/bplib/fx2rlink/ioleds_sp1c_fx2.vhd | 6 +- rtl/bplib/issi/Makefile | 4 +- rtl/bplib/issi/is61lv25616al.vhd | 4 +- rtl/bplib/micron/mt45w8mw16b.vhd | 4 +- rtl/bplib/nexys2/Makefile | 6 +- rtl/bplib/nexys2/nexys2lib.vhd | 4 +- rtl/bplib/nexys2/tb/Makefile | 10 +- rtl/bplib/nexys2/tb/tb_nexys2_core.vhd | 4 +- rtl/bplib/nexys2/tb/tb_nexys2_fusp.vhd | 4 +- rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vhd | 4 +- rtl/bplib/nexys3/nexys3lib.vhd | 4 +- rtl/bplib/nexys3/tb/Makefile | 10 +- rtl/bplib/nexys3/tb/tb_nexys3_core.vhd | 4 +- rtl/bplib/nexys3/tb/tb_nexys3_fusp.vhd | 4 +- rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vhd | 4 +- rtl/bplib/nexys4/nexys4_pclk.xdc | 13 + rtl/bplib/nexys4/nexys4_pins.xdc | 132 +++ rtl/bplib/nexys4/nexys4_pins_cram.xdc | 90 +++ rtl/bplib/nexys4/nexys4_setup.tcl | 4 + rtl/bplib/nexys4/nexys4lib.vhd | 81 ++ rtl/bplib/nexys4/tb/.cvsignore | 5 + rtl/bplib/nexys4/tb/Makefile.ise | 39 + rtl/bplib/nexys4/tb/tb_nexys4.vbom | 25 + rtl/bplib/nexys4/tb/tb_nexys4.vhd | 189 +++++ rtl/bplib/nexys4/tb/tb_nexys4_core.vbom | 9 + rtl/bplib/nexys4/tb/tb_nexys4_core.vhd | 77 ++ rtl/bplib/nexys4/tb/tb_nexys4_cram.vbom | 26 + rtl/bplib/nexys4/tb/tb_nexys4_cram.vhd | 224 ++++++ rtl/bplib/nxcramlib/Makefile | 9 +- rtl/bplib/nxcramlib/nx_cram_dummy.vhd | 4 +- rtl/bplib/nxcramlib/nx_cram_memctl_as.vhd | 6 +- rtl/bplib/nxcramlib/nxcramlib.vhd | 4 +- rtl/bplib/nxcramlib/tb/Makefile | 13 +- rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl.vhd | 4 +- .../nxcramlib/tb/tbd_nx_cram_memctl_as.vhd | 4 +- rtl/bplib/s3board/Makefile | 6 +- rtl/bplib/s3board/s3_sram_dummy.vhd | 4 +- rtl/bplib/s3board/s3_sram_memctl.vhd | 6 +- rtl/bplib/s3board/s3boardlib.vhd | 4 +- rtl/bplib/s3board/tb/Makefile | 10 +- rtl/bplib/s3board/tb/s3board_fusp_dummy.vhd | 4 +- rtl/bplib/s3board/tb/tb_s3_sram_memctl.vhd | 4 +- rtl/bplib/s3board/tb/tb_s3board_core.vhd | 4 +- rtl/bplib/s3board/tb/tb_s3board_fusp.vhd | 4 +- rtl/ibus/Makefile | 6 +- rtl/ibus/ib_intmap.vhd | 4 +- rtl/ibus/ib_sel.vhd | 4 +- rtl/ibus/ib_sres_or_2.vbom | 2 +- rtl/ibus/ib_sres_or_2.vhd | 4 +- rtl/ibus/ib_sres_or_3.vbom | 2 +- rtl/ibus/ib_sres_or_3.vhd | 4 +- rtl/ibus/ib_sres_or_4.vbom | 2 +- rtl/ibus/ib_sres_or_4.vhd | 4 +- rtl/ibus/ib_sres_or_mon.vhd | 4 +- rtl/ibus/ibd_iist.vhd | 4 +- rtl/ibus/ibd_kw11l.vhd | 4 +- rtl/ibus/ibdlib.vhd | 4 +- rtl/ibus/ibdr_dl11.vhd | 4 +- rtl/ibus/ibdr_lp11.vhd | 4 +- rtl/ibus/ibdr_maxisys.vbom | 2 +- rtl/ibus/ibdr_maxisys.vhd | 41 +- rtl/ibus/ibdr_minisys.vhd | 4 +- rtl/ibus/ibdr_pc11.vhd | 4 +- rtl/ibus/ibdr_rk11.vbom | 4 +- rtl/ibus/ibdr_rk11.vhd | 4 +- rtl/ibus/ibdr_rl11.vbom | 9 + rtl/ibus/ibdr_rl11.vhd | 660 +++++++++++++++ rtl/ibus/ibdr_sdreg.vhd | 4 +- rtl/ibus/iblib.vhd | 4 +- rtl/{make => make_ise}/dontincdep.mk | 5 +- rtl/{make => make_ise}/generic_ghdl.mk | 24 +- rtl/{make => make_ise}/generic_isim.mk | 7 +- rtl/{make => make_ise}/generic_xflow.mk | 47 +- rtl/{make => make_ise}/generic_xflow_cpld.mk | 5 +- rtl/{make => make_ise}/imp_7a_speed.opt | 0 rtl/{make => make_ise}/imp_s3_speed.opt | 0 rtl/{make => make_ise}/imp_s3_speed_maptd.opt | 0 rtl/{make => make_ise}/imp_s6_speed.opt | 0 .../imp_s6_speed_ise133.opt | 0 rtl/{make => make_ise}/syn_7a_speed.opt | 0 rtl/{make => make_ise}/syn_s3_speed.opt | 0 rtl/{make => make_ise}/syn_s6_speed.opt | 0 .../syn_s6_speed_ise133.opt | 0 rtl/{make => make_ise}/xflow_default_atlys.mk | 0 .../xflow_default_nexys2.mk | 0 .../xflow_default_nexys3.mk | 0 .../xflow_default_nexys4.mk | 0 .../xflow_default_s3board.mk | 0 .../xflow_default_s3board_200.mk | 0 rtl/make_viv/dontincdep.mk | 24 + rtl/make_viv/generic_ghdl.mk | 38 + rtl/make_viv/generic_vivado.mk | 142 ++++ rtl/make_viv/viv_default_basys3.mk | 16 + rtl/make_viv/viv_default_build.tcl | 12 + rtl/make_viv/viv_default_config.tcl | 12 + rtl/make_viv/viv_default_model.tcl | 11 + rtl/make_viv/viv_default_nexys4.mk | 16 + rtl/make_viv/viv_init.tcl | 13 + rtl/make_viv/viv_tools_build.tcl | 163 ++++ rtl/make_viv/viv_tools_config.tcl | 29 + rtl/make_viv/viv_tools_model.tcl | 38 + rtl/sys_gen/tst_fx2loop/Makefile | 7 +- rtl/sys_gen/tst_fx2loop/nexys2/ic/Makefile | 8 +- .../tst_fx2loop/nexys2/ic/sys_conf.vhd | 4 +- rtl/sys_gen/tst_fx2loop/nexys2/ic3/Makefile | 8 +- .../tst_fx2loop/nexys2/ic3/sys_conf.vhd | 4 +- .../nexys2/sys_tst_fx2loop_n2.vbom | 4 +- .../tst_fx2loop/nexys2/sys_tst_fx2loop_n2.vhd | 46 +- rtl/sys_gen/tst_fx2loop/nexys3/ic/Makefile | 8 +- .../tst_fx2loop/nexys3/ic/sys_conf.vhd | 4 +- rtl/sys_gen/tst_fx2loop/nexys3/ic3/Makefile | 8 +- .../tst_fx2loop/nexys3/ic3/sys_conf.vhd | 4 +- .../nexys3/sys_tst_fx2loop_n3.vbom | 4 +- .../tst_fx2loop/nexys3/sys_tst_fx2loop_n3.vhd | 45 +- rtl/sys_gen/tst_fx2loop/tst_fx2loop.vhd | 4 +- .../tst_fx2loop/tst_fx2loop_hiomap.vhd | 4 +- rtl/sys_gen/tst_fx2loop/tst_fx2looplib.vhd | 4 +- rtl/sys_gen/tst_rlink/Makefile | 7 +- rtl/sys_gen/tst_rlink/basys3/.cvsignore | 7 + rtl/sys_gen/tst_rlink/basys3/Makefile | 25 + rtl/sys_gen/tst_rlink/basys3/sys_conf.vhd | 52 ++ .../tst_rlink/basys3/sys_tst_rlink_b3.vbom | 23 + .../tst_rlink/basys3/sys_tst_rlink_b3.vhd | 252 ++++++ rtl/sys_gen/tst_rlink/basys3/tb/.cvsignore | 6 + rtl/sys_gen/tst_rlink/basys3/tb/Makefile | 30 + .../tst_rlink/basys3/tb/sys_conf_sim.vhd | 58 ++ .../tst_rlink/basys3/tb/tb_tst_rlink_b3.vbom | 7 + .../tst_rlink/basys3/tb/tb_tst_rlink_b3.vhd | 35 + .../basys3/tb/tb_tst_rlink_b3_ssim.vbom | 6 + rtl/sys_gen/tst_rlink/basys3/tb/tbw.dat | 6 + rtl/sys_gen/tst_rlink/nexys2/Makefile | 8 +- rtl/sys_gen/tst_rlink/nexys2/sys_conf.vhd | 4 +- .../tst_rlink/nexys2/sys_tst_rlink_n2.vbom | 2 +- rtl/sys_gen/tst_rlink/nexys2/tb/Makefile | 8 +- .../tst_rlink/nexys2/tb/sys_conf_sim.vhd | 4 +- rtl/sys_gen/tst_rlink/nexys3/Makefile | 8 +- rtl/sys_gen/tst_rlink/nexys3/sys_conf.vhd | 4 +- .../tst_rlink/nexys3/sys_tst_rlink_n3.vbom | 2 +- rtl/sys_gen/tst_rlink/nexys3/tb/Makefile | 8 +- .../tst_rlink/nexys3/tb/sys_conf_sim.vhd | 4 +- rtl/sys_gen/tst_rlink/nexys4/.cvsignore | 11 + rtl/sys_gen/tst_rlink/nexys4/Makefile | 26 + rtl/sys_gen/tst_rlink/nexys4/Makefile.ise | 29 + rtl/sys_gen/tst_rlink/nexys4/sys_conf.vhd | 62 ++ .../tst_rlink/nexys4/sys_tst_rlink_n4.ucf_cpp | 17 + .../tst_rlink/nexys4/sys_tst_rlink_n4.vbom | 24 + .../tst_rlink/nexys4/sys_tst_rlink_n4.vhd | 276 +++++++ rtl/sys_gen/tst_rlink/nexys4/tb/.cvsignore | 8 + rtl/sys_gen/tst_rlink/nexys4/tb/Makefile | 30 + rtl/sys_gen/tst_rlink/nexys4/tb/Makefile.ise | 33 + .../tst_rlink/nexys4/tb/sys_conf_sim.vhd | 58 ++ .../nexys4/tb/sys_tst_rlink_n4.ucf_cpp | 1 + .../tst_rlink/nexys4/tb/tb_tst_rlink_n4.vbom | 7 + .../tst_rlink/nexys4/tb/tb_tst_rlink_n4.vhd | 36 + .../nexys4/tb/tb_tst_rlink_n4_ssim.vbom | 6 + rtl/sys_gen/tst_rlink/nexys4/tb/tbw.dat | 6 + rtl/sys_gen/tst_rlink/s3board/Makefile | 8 +- rtl/sys_gen/tst_rlink/s3board/sys_conf.vhd | 4 +- rtl/sys_gen/tst_rlink/s3board/tb/Makefile | 8 +- .../tst_rlink/s3board/tb/sys_conf_sim.vhd | 4 +- rtl/sys_gen/tst_rlink_cuff/Makefile | 7 +- rtl/sys_gen/tst_rlink_cuff/atlys/ic/Makefile | 8 +- .../tst_rlink_cuff/atlys/ic/sys_conf.vhd | 4 +- .../atlys/sys_tst_rlink_cuff_atlys.vbom | 4 +- .../atlys/sys_tst_rlink_cuff_atlys.vhd | 44 +- rtl/sys_gen/tst_rlink_cuff/nexys2/ic/Makefile | 8 +- .../tst_rlink_cuff/nexys2/ic/sys_conf.vhd | 4 +- .../tst_rlink_cuff/nexys2/ic/tb/Makefile | 8 +- .../nexys2/ic/tb/sys_conf_sim.vhd | 4 +- .../tst_rlink_cuff/nexys2/ic3/Makefile | 8 +- .../tst_rlink_cuff/nexys2/ic3/sys_conf.vhd | 4 +- .../nexys2/sys_tst_rlink_cuff_n2.vbom | 4 +- .../nexys2/sys_tst_rlink_cuff_n2.vhd | 44 +- rtl/sys_gen/tst_rlink_cuff/nexys3/ic/Makefile | 8 +- .../tst_rlink_cuff/nexys3/ic/sys_conf.vhd | 4 +- .../tst_rlink_cuff/nexys3/ic/tb/Makefile | 8 +- .../nexys3/ic/tb/sys_conf_sim.vhd | 4 +- .../nexys3/sys_tst_rlink_cuff_n3.vbom | 4 +- .../nexys3/sys_tst_rlink_cuff_n3.vhd | 44 +- rtl/sys_gen/tst_serloop/Makefile | 7 +- rtl/sys_gen/tst_serloop/nexys2/Makefile | 8 +- rtl/sys_gen/tst_serloop/nexys2/sys_conf1.vhd | 4 +- rtl/sys_gen/tst_serloop/nexys2/sys_conf2.vhd | 4 +- .../nexys2/sys_tst_serloop1_n2.vhd | 4 +- .../nexys2/sys_tst_serloop2_n2.vbom | 2 +- .../nexys2/sys_tst_serloop2_n2.vhd | 4 +- rtl/sys_gen/tst_serloop/nexys2/tb/Makefile | 10 +- .../tst_serloop/nexys2/tb/sys_conf1_sim.vhd | 4 +- .../tst_serloop/nexys2/tb/sys_conf2_sim.vhd | 4 +- rtl/sys_gen/tst_serloop/nexys3/Makefile | 8 +- rtl/sys_gen/tst_serloop/nexys3/sys_conf1.vhd | 4 +- .../nexys3/sys_tst_serloop1_n3.vhd | 4 +- rtl/sys_gen/tst_serloop/nexys3/tb/Makefile | 10 +- .../tst_serloop/nexys3/tb/sys_conf1_sim.vhd | 4 +- rtl/sys_gen/tst_serloop/nexys4/.cvsignore | 7 + rtl/sys_gen/tst_serloop/nexys4/Makefile | 25 + rtl/sys_gen/tst_serloop/nexys4/sys_conf1.vhd | 37 + .../nexys4/sys_tst_serloop1_n4.vbom | 19 + .../nexys4/sys_tst_serloop1_n4.vhd | 223 ++++++ rtl/sys_gen/tst_serloop/nexys4/tb/.cvsignore | 4 + rtl/sys_gen/tst_serloop/nexys4/tb/Makefile | 30 + .../tst_serloop/nexys4/tb/sys_conf1_sim.vhd | 43 + .../nexys4/tb/tb_tst_serloop1_n4.vbom | 11 + .../nexys4/tb/tb_tst_serloop1_n4.vhd | 119 +++ rtl/sys_gen/tst_serloop/nexys4/tb/tbw.dat | 6 + rtl/sys_gen/tst_serloop/s3board/Makefile | 8 +- rtl/sys_gen/tst_serloop/s3board/sys_conf.vhd | 4 +- .../s3board/sys_tst_serloop_s3.vbom | 2 +- .../s3board/sys_tst_serloop_s3.vhd | 4 +- rtl/sys_gen/tst_serloop/s3board/tb/Makefile | 10 +- .../tst_serloop/s3board/tb/sys_conf_sim.vhd | 4 +- rtl/sys_gen/tst_serloop/tst_serloop.vhd | 4 +- .../tst_serloop/tst_serloop_hiomap.vhd | 4 +- rtl/sys_gen/tst_serloop/tst_serlooplib.vhd | 4 +- rtl/sys_gen/tst_snhumanio/Makefile | 6 +- rtl/sys_gen/tst_snhumanio/atlys/Makefile | 8 +- rtl/sys_gen/tst_snhumanio/atlys/sys_conf.vhd | 4 +- .../atlys/sys_tst_snhumanio_atlys.vhd | 4 +- rtl/sys_gen/tst_snhumanio/basys3/.cvsignore | 7 + rtl/sys_gen/tst_snhumanio/basys3/Makefile | 26 + rtl/sys_gen/tst_snhumanio/basys3/sys_conf.vhd | 35 + .../basys3/sys_tst_snhumanio_b3.vbom | 13 + .../basys3/sys_tst_snhumanio_b3.vhd | 129 +++ rtl/sys_gen/tst_snhumanio/nexys2/Makefile | 8 +- rtl/sys_gen/tst_snhumanio/nexys2/sys_conf.vhd | 4 +- .../nexys2/sys_tst_snhumanio_n2.vhd | 4 +- rtl/sys_gen/tst_snhumanio/nexys3/Makefile | 8 +- rtl/sys_gen/tst_snhumanio/nexys3/sys_conf.vhd | 4 +- .../nexys3/sys_tst_snhumanio_n3.vhd | 6 +- rtl/sys_gen/tst_snhumanio/nexys4/.cvsignore | 7 + rtl/sys_gen/tst_snhumanio/nexys4/Makefile | 26 + rtl/sys_gen/tst_snhumanio/nexys4/sys_conf.vhd | 35 + .../nexys4/sys_tst_snhumanio_n4.vbom | 13 + .../nexys4/sys_tst_snhumanio_n4.vhd | 142 ++++ rtl/sys_gen/tst_snhumanio/s3board/Makefile | 8 +- .../tst_snhumanio/s3board/sys_conf.vhd | 4 +- .../s3board/sys_tst_snhumanio_s3.vhd | 4 +- rtl/sys_gen/tst_snhumanio/tst_snhumanio.vhd | 4 +- rtl/sys_gen/w11a/basys3/.cvsignore | 7 + rtl/sys_gen/w11a/basys3/Makefile | 25 + rtl/sys_gen/w11a/basys3/sys_conf.vhd | 82 ++ rtl/sys_gen/w11a/basys3/sys_w11a_b3.vbom | 37 + rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd | 484 +++++++++++ rtl/sys_gen/w11a/basys3/tb/.cvsignore | 6 + rtl/sys_gen/w11a/basys3/tb/Makefile | 30 + rtl/sys_gen/w11a/basys3/tb/sys_conf_sim.vhd | 67 ++ rtl/sys_gen/w11a/basys3/tb/tb_w11a_b3.vbom | 7 + rtl/sys_gen/w11a/basys3/tb/tb_w11a_b3.vhd | 35 + .../w11a/basys3/tb/tb_w11a_b3_ssim.vbom | 6 + rtl/sys_gen/w11a/basys3/tb/tbw.dat | 6 + rtl/sys_gen/w11a/nexys2/Makefile | 8 +- rtl/sys_gen/w11a/nexys2/sys_conf.vhd | 14 +- rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vbom | 12 +- rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd | 334 ++++---- rtl/sys_gen/w11a/nexys2/tb/Makefile | 8 +- rtl/sys_gen/w11a/nexys2/tb/sys_conf_sim.vhd | 11 +- rtl/sys_gen/w11a/nexys3/Makefile | 8 +- rtl/sys_gen/w11a/nexys3/sys_conf.vhd | 11 +- rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vbom | 12 +- rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd | 339 ++++---- rtl/sys_gen/w11a/nexys3/tb/Makefile | 8 +- rtl/sys_gen/w11a/nexys3/tb/sys_conf_sim.vhd | 11 +- rtl/sys_gen/w11a/nexys4/.cvsignore | 12 + rtl/sys_gen/w11a/nexys4/Makefile | 25 + rtl/sys_gen/w11a/nexys4/Makefile.ise | 29 + rtl/sys_gen/w11a/nexys4/sys_conf.vhd | 92 +++ rtl/sys_gen/w11a/nexys4/sys_w11a_n4.ucf_cpp | 21 + rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vbom | 41 + rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vhd | 536 +++++++++++++ rtl/sys_gen/w11a/nexys4/tb/.cvsignore | 9 + rtl/sys_gen/w11a/nexys4/tb/Makefile | 31 + rtl/sys_gen/w11a/nexys4/tb/Makefile.ise | 32 + rtl/sys_gen/w11a/nexys4/tb/sys_conf_sim.vhd | 80 ++ .../w11a/nexys4/tb/sys_w11a_n4.ucf_cpp | 1 + rtl/sys_gen/w11a/nexys4/tb/tb_w11a_n4.vbom | 7 + rtl/sys_gen/w11a/nexys4/tb/tb_w11a_n4.vhd | 41 + .../w11a/nexys4/tb/tb_w11a_n4_ssim.vbom | 6 + rtl/sys_gen/w11a/nexys4/tb/tbw.dat | 6 + rtl/sys_gen/w11a/s3board/Makefile | 8 +- rtl/sys_gen/w11a/s3board/sys_w11a_s3.vbom | 6 +- rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd | 117 +-- rtl/sys_gen/w11a/s3board/tb/Makefile | 8 +- rtl/vlib/comlib/Makefile | 6 +- rtl/vlib/comlib/byte2cdata.vhd | 4 +- rtl/vlib/comlib/byte2word.vhd | 4 +- rtl/vlib/comlib/cdata2byte.vhd | 4 +- rtl/vlib/comlib/comlib.vhd | 4 +- rtl/vlib/comlib/crc16.vhd | 4 +- rtl/vlib/comlib/misc/Makefile | 4 +- rtl/vlib/comlib/tb/Makefile | 10 +- rtl/vlib/comlib/word2byte.vhd | 4 +- rtl/vlib/genlib/Makefile | 6 +- rtl/vlib/genlib/cdc_pulse.vhd | 4 +- rtl/vlib/genlib/clkdivce.vhd | 4 +- rtl/vlib/genlib/debounce_gen.vhd | 4 +- rtl/vlib/genlib/genlib.vhd | 4 +- rtl/vlib/genlib/gray2bin_gen.vhd | 4 +- rtl/vlib/genlib/gray_cnt_4.vhd | 4 +- rtl/vlib/genlib/gray_cnt_5.vhd | 4 +- rtl/vlib/genlib/gray_cnt_gen.vhd | 4 +- rtl/vlib/genlib/gray_cnt_n.vhd | 4 +- rtl/vlib/genlib/led_pulse_stretch.vhd | 4 +- rtl/vlib/memlib/Makefile | 6 +- rtl/vlib/memlib/fifo_1c_dram.vhd | 4 +- rtl/vlib/memlib/fifo_1c_dram_raw.vbom | 4 +- rtl/vlib/memlib/fifo_1c_dram_raw.vhd | 4 +- rtl/vlib/memlib/fifo_2c_dram.vbom | 4 +- rtl/vlib/memlib/fifo_2c_dram.vhd | 4 +- rtl/vlib/memlib/memlib.vhd | 4 +- rtl/vlib/memlib/ram_1swar_1ar_gen.vhd | 4 +- rtl/vlib/memlib/ram_1swar_1ar_gen_unisim.vhd | 4 +- rtl/vlib/memlib/ram_1swar_gen.vhd | 4 +- rtl/vlib/memlib/ram_1swar_gen_unisim.vhd | 4 +- rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd | 4 +- .../memlib/ram_1swsr_wfirst_gen_unisim.vhd | 4 +- .../memlib/ram_1swsr_xfirst_gen_unisim.vhd | 4 +- rtl/vlib/memlib/ram_2swsr_rfirst_gen.vhd | 4 +- .../memlib/ram_2swsr_rfirst_gen_unisim.vhd | 4 +- rtl/vlib/memlib/ram_2swsr_wfirst_gen.vhd | 4 +- .../memlib/ram_2swsr_wfirst_gen_unisim.vhd | 4 +- .../memlib/ram_2swsr_xfirst_gen_unisim.vhd | 4 +- rtl/vlib/rbus/Makefile | 6 +- rtl/vlib/rbus/rb_sel.vhd | 4 +- rtl/vlib/rbus/rb_sres_or_2.vbom | 2 +- rtl/vlib/rbus/rb_sres_or_2.vhd | 4 +- rtl/vlib/rbus/rb_sres_or_3.vbom | 2 +- rtl/vlib/rbus/rb_sres_or_3.vhd | 4 +- rtl/vlib/rbus/rb_sres_or_4.vbom | 2 +- rtl/vlib/rbus/rb_sres_or_4.vhd | 4 +- rtl/vlib/rbus/rb_sres_or_mon.vhd | 4 +- rtl/vlib/rbus/rbd_bram.vbom | 4 +- rtl/vlib/rbus/rbd_eyemon.vbom | 4 +- rtl/vlib/rbus/rbd_rbmon.vbom | 4 +- rtl/vlib/rbus/rblib.vhd | 4 +- rtl/vlib/rlink/Makefile | 6 +- rtl/vlib/rlink/ioleds_sp1c.vbom | 7 + rtl/vlib/rlink/ioleds_sp1c.vhd | 55 ++ rtl/vlib/rlink/rlink_core.vbom | 8 +- rtl/vlib/rlink/rlink_core.vhd | 4 +- rtl/vlib/rlink/rlink_core8.vbom | 2 +- rtl/vlib/rlink/rlink_core8.vhd | 4 +- rtl/vlib/rlink/rlink_mon_sb.vhd | 4 +- rtl/vlib/rlink/rlink_rlbmux.vhd | 4 +- rtl/vlib/rlink/rlink_sp1c.vhd | 4 +- rtl/vlib/rlink/rlinklib.vhd | 17 +- rtl/vlib/rlink/tb/Makefile | 10 +- rtl/vlib/rlink/tb/rlink_cext_vhpi.vhd | 4 +- rtl/vlib/rlink/tb/tbcore_rlink.vhd | 4 +- rtl/vlib/serport/Makefile | 6 +- rtl/vlib/serport/serport_1clock.vhd | 42 +- rtl/vlib/serport/serport_2clock.vhd | 38 +- rtl/vlib/serport/serport_uart_autobaud.vhd | 17 +- rtl/vlib/serport/serport_uart_rx.vhd | 4 +- rtl/vlib/serport/serport_uart_rxtx.vhd | 4 +- rtl/vlib/serport/serport_uart_rxtx_ab.vhd | 29 +- rtl/vlib/serport/serport_uart_tx.vhd | 4 +- rtl/vlib/serport/serport_xonrx.vhd | 4 +- rtl/vlib/serport/serport_xontx.vhd | 4 +- rtl/vlib/serport/serportlib.vhd | 13 +- rtl/vlib/serport/tb/Makefile | 10 +- rtl/vlib/serport/tb/tbd_serport_autobaud.vhd | 4 +- rtl/vlib/serport/tb/tbd_serport_uart_rx.vhd | 4 +- rtl/vlib/serport/tb/tbd_serport_uart_rxtx.vhd | 4 +- rtl/vlib/simlib/simbus.vhd | 4 +- rtl/vlib/simlib/simclk.vhd | 4 +- rtl/vlib/simlib/simclkcnt.vhd | 4 +- rtl/vlib/slvtypes.vhd | 4 +- rtl/vlib/xlib/Makefile | 6 +- rtl/vlib/xlib/dcm_sfs_gsim.vhd | 4 +- rtl/vlib/xlib/dcm_sfs_unisim_s3.vhd | 4 +- rtl/vlib/xlib/dcm_sfs_unisim_s3e.vhd | 4 +- rtl/vlib/xlib/iob_keeper_gen.vhd | 4 +- rtl/vlib/xlib/iob_reg_i.vhd | 4 +- rtl/vlib/xlib/iob_reg_i_gen.vhd | 4 +- rtl/vlib/xlib/iob_reg_io_gen.vbom | 2 +- rtl/vlib/xlib/iob_reg_io_gen.vhd | 4 +- rtl/vlib/xlib/iob_reg_o.vhd | 4 +- rtl/vlib/xlib/iob_reg_o_gen.vhd | 4 +- rtl/vlib/xlib/s6_cmt_sfs_gsim.vhd | 4 +- rtl/vlib/xlib/s6_cmt_sfs_unisim.vhd | 4 +- rtl/vlib/xlib/s7_cmt_sfs_gsim.vbom | 4 + rtl/vlib/xlib/s7_cmt_sfs_gsim.vhd | 213 +++++ rtl/vlib/xlib/s7_cmt_sfs_unisim.vbom | 5 + rtl/vlib/xlib/s7_cmt_sfs_unisim.vhd | 198 +++++ rtl/vlib/xlib/xlib.vhd | 4 +- rtl/w11a/Makefile | 6 +- rtl/w11a/pdp11.vhd | 60 +- rtl/w11a/pdp11_aunit.vhd | 4 +- rtl/w11a/pdp11_bram.vbom | 4 +- rtl/w11a/pdp11_bram.vhd | 4 +- rtl/w11a/pdp11_bram_memctl.vbom | 8 + rtl/w11a/pdp11_bram_memctl.vhd | 219 +++++ rtl/w11a/pdp11_cache.vbom | 4 +- rtl/w11a/pdp11_cache.vhd | 4 +- rtl/w11a/pdp11_core.vhd | 4 +- rtl/w11a/pdp11_core_rbus.vhd | 4 +- rtl/w11a/pdp11_decode.vhd | 4 +- rtl/w11a/pdp11_dpath.vhd | 4 +- rtl/w11a/pdp11_dspmux.vbom | 6 + rtl/w11a/pdp11_dspmux.vhd | 115 +++ rtl/w11a/pdp11_gpr.vbom | 4 +- rtl/w11a/pdp11_gpr.vhd | 4 +- rtl/w11a/pdp11_irq.vhd | 4 +- rtl/w11a/pdp11_ledmux.vbom | 6 + rtl/w11a/pdp11_ledmux.vhd | 76 ++ rtl/w11a/pdp11_lunit.vhd | 4 +- rtl/w11a/pdp11_mem70.vhd | 6 +- rtl/w11a/pdp11_mmu.vhd | 4 +- rtl/w11a/pdp11_mmu_sadr.vbom | 4 +- rtl/w11a/pdp11_mmu_sadr.vhd | 4 +- rtl/w11a/pdp11_mmu_ssr12.vhd | 4 +- rtl/w11a/pdp11_munit.vhd | 4 +- rtl/w11a/pdp11_ounit.vhd | 4 +- rtl/w11a/pdp11_psr.vhd | 4 +- rtl/w11a/pdp11_sequencer.vhd | 11 +- rtl/w11a/pdp11_sim.vhd | 4 +- rtl/w11a/pdp11_statleds.vbom | 6 + rtl/w11a/pdp11_statleds.vhd | 96 +++ rtl/w11a/pdp11_sys70.vhd | 4 +- rtl/w11a/pdp11_tmu.vhd | 4 +- rtl/w11a/pdp11_tmu_sb.vhd | 4 +- rtl/w11a/pdp11_ubmap.vbom | 4 +- rtl/w11a/pdp11_ubmap.vhd | 4 +- rtl/w11a/pdp11_vmbox.vhd | 4 +- rtl/w11a/sys_conf.vhd | 4 +- rtl/w11a/tb/Makefile | 10 +- rtl/w11a/tb/tbd_pdp11core.vbom | 2 +- rtl/w11a/tb/tbd_pdp11core.vhd | 4 +- tools/bin/rm_dep | 8 +- tools/bin/set_ftdi_lat | 34 - tools/bin/tbrun_tbw | 5 +- tools/bin/tbrun_tbwrri | 5 +- tools/bin/tbw | 4 +- tools/bin/ti_rri | 13 +- tools/bin/ti_w11 | 47 +- tools/bin/ticonv_pdpcp | 4 +- tools/bin/vbomconv | 400 +++++---- tools/bin/xilinx_ghdl_unisim | 74 -- tools/bin/xilinx_vhdl_chop | 40 - ...{xilinx_ghdl_simprim => xise_ghdl_simprim} | 52 +- tools/bin/xise_ghdl_unisim | 98 +++ tools/bin/{isemsg_filter => xise_msg_filter} | 17 +- tools/bin/xtwi | 5 +- tools/bin/xtwv | 5 +- tools/bin/xviv_ghdl_unisim | 127 +++ tools/dox/w11_cpp.Doxyfile | 2 +- tools/dox/w11_tcl.Doxyfile | 2 +- tools/dox/w11_vhd_all.Doxyfile | 2 +- tools/fx2/bin/nexys2_jtag_2fifo_as.ihx | 144 ---- tools/fx2/bin/nexys2_jtag_3fifo_as.ihx | 146 ---- tools/fx2/bin/nexys3_jtag_2fifo_as.ihx | 144 ---- tools/fx2/bin/nexys3_jtag_3fifo_as.ihx | 146 ---- tools/fx2/src/Makefile | 35 +- tools/make/generic_cpp.mk | 29 +- tools/oskit/211bsd_rl/.cvsignore | 5 + tools/oskit/211bsd_rl/211bsd_rl_boot.scmd | 16 + tools/oskit/211bsd_rl/211bsd_rl_boot.tcl | 26 + tools/oskit/211bsd_rl/README_211bsd_rlset.txt | 125 +++ tools/oskit/rt11-53_rl/.cvsignore | 4 + .../oskit/rt11-53_rl/README_rt11-53_rlset.txt | 70 ++ tools/oskit/rt11-53_rl/rt11-53_rl_boot.scmd | 16 + tools/oskit/rt11-53_rl/rt11-53_rl_boot.tcl | 25 + tools/oskit/xxdp_rl/.cvsignore | 4 + tools/oskit/xxdp_rl/README_license.txt | 9 + tools/oskit/xxdp_rl/README_xxdp_rlset.txt | 85 ++ tools/oskit/xxdp_rl/xxdp22_rl_boot.scmd | 13 + tools/oskit/xxdp_rl/xxdp22_rl_boot.tcl | 25 + tools/oskit/xxdp_rl/xxdp25_rl_boot.scmd | 13 + tools/oskit/xxdp_rl/xxdp25_rl_boot.tcl | 25 + tools/src/librlink/RlinkCommand.cpp | 22 +- tools/src/librlink/RlinkConnect.cpp | 140 +++- tools/src/librlink/RlinkConnect.hpp | 50 +- tools/src/librlink/RlinkConnect.ipp | 63 +- tools/src/librlink/RlinkPacketBufRcv.cpp | 6 +- tools/src/librlink/RlinkPort.cpp | 8 +- tools/src/librlink/RlinkPort.hpp | 5 +- tools/src/librlink/RlinkPortCuff.cpp | 26 +- tools/src/librlink/RlinkPortFactory.cpp | 6 +- tools/src/librlink/RlinkPortTerm.cpp | 56 +- tools/src/librlink/RlinkServer.cpp | 11 +- tools/src/librlink/RlinkServer.hpp | 13 +- tools/src/librlink/RlinkServer.ipp | 12 +- tools/src/librlinktpp/RtclAttnShuttle.cpp | 12 +- tools/src/librlinktpp/RtclRlinkConnect.cpp | 147 ++-- tools/src/librlinktpp/RtclRlinkConnect.hpp | 10 +- tools/src/librlinktpp/RtclRlinkPort.cpp | 103 ++- tools/src/librlinktpp/RtclRlinkPort.hpp | 21 +- tools/src/librlinktpp/RtclRlinkServer.cpp | 10 +- tools/src/librtcltools/Rtcl.cpp | 6 +- tools/src/librtcltools/RtclArgs.cpp | 16 +- tools/src/librtcltools/RtclGetList.cpp | 46 +- tools/src/librtcltools/RtclGetList.hpp | 11 +- tools/src/librtcltools/RtclSetList.cpp | 36 +- tools/src/librtcltools/RtclSetList.hpp | 11 +- tools/src/librtcltools/RtclStats.cpp | 6 +- tools/src/librtools/RlogFile.cpp | 44 +- tools/src/librtools/RlogFile.hpp | 12 +- tools/src/librtools/RlogFileCatalog.cpp | 8 +- tools/src/librutiltpp/RtclBvi.cpp | 6 +- tools/src/librutiltpp/RtclSignalAction.cpp | 10 +- tools/src/librutiltpp/RtclSystem.cpp | 8 +- tools/src/librw11/Makefile | 1 + tools/src/librw11/Rw11Cntl.cpp | 6 +- tools/src/librw11/Rw11CntlDL11.cpp | 7 +- tools/src/librw11/Rw11CntlRK11.cpp | 63 +- tools/src/librw11/Rw11CntlRK11.hpp | 23 +- tools/src/librw11/Rw11CntlRL11.cpp | 756 ++++++++++++++++++ tools/src/librw11/Rw11CntlRL11.hpp | 230 ++++++ tools/src/librw11/Rw11CntlRL11.ipp | 55 ++ tools/src/librw11/Rw11Cpu.cpp | 11 +- tools/src/librw11/Rw11Rdma.cpp | 30 +- tools/src/librw11/Rw11Rdma.hpp | 14 +- tools/src/librw11/Rw11RdmaDisk.cpp | 24 +- tools/src/librw11/Rw11RdmaDisk.hpp | 8 +- tools/src/librw11/Rw11UnitDisk.hpp | 8 +- tools/src/librw11/Rw11UnitDisk.ipp | 14 +- tools/src/librw11/Rw11UnitRL11.cpp | 102 +++ tools/src/librw11/Rw11UnitRL11.hpp | 58 ++ tools/src/librw11/Rw11UnitRL11.ipp | 69 ++ tools/src/librw11/Rw11VirtTermPty.cpp | 6 +- tools/src/librw11/Rw11VirtTermTcp.cpp | 6 +- tools/src/librwxxtpp/Makefile | 1 + tools/src/librwxxtpp/RtclRw11.cpp | 6 +- tools/src/librwxxtpp/RtclRw11CntlFactory.cpp | 17 +- tools/src/librwxxtpp/RtclRw11CntlRK11.cpp | 7 +- tools/src/librwxxtpp/RtclRw11CntlRL11.cpp | 112 +++ tools/src/librwxxtpp/RtclRw11CntlRL11.hpp | 50 ++ tools/src/librwxxtpp/RtclRw11Cpu.cpp | 12 +- tools/src/librwxxtpp/RtclRw11UnitRL11.cpp | 55 ++ tools/src/librwxxtpp/RtclRw11UnitRL11.hpp | 52 ++ tools/tcl/rbbram/perf.tcl | 8 +- tools/tcl/rbemon/util.tcl | 24 +- tools/tcl/rbs3hio/util.tcl | 107 ++- tools/tcl/rw11/util.tcl | 11 +- 588 files changed, 13843 insertions(+), 4540 deletions(-) create mode 100644 doc/.cvsignore create mode 100644 doc/INSTALL_fx2_support.txt create mode 100644 doc/README_buildsystem_ISE.txt create mode 100644 doc/README_buildsystem_Vivado.txt delete mode 100644 doc/man/man1/set_ftdi_lat.1 delete mode 100644 doc/man/man1/xilinx_ghdl_unisim.1 rename doc/man/man1/{xilinx_ghdl_simprim.1 => xise_ghdl_simprim.1} (65%) create mode 100644 doc/man/man1/xise_ghdl_unisim.1 rename doc/man/man1/{isemsg_filter.1 => xise_msg_filter.1} (81%) create mode 100644 doc/man/man1/xviv_ghdl_unisim.1 create mode 100644 rtl/bplib/basys3/basys3_pclk.xdc create mode 100644 rtl/bplib/basys3/basys3_pins.xdc create mode 100644 rtl/bplib/basys3/basys3_setup.tcl create mode 100644 rtl/bplib/basys3/basys3lib.vhd create mode 100644 rtl/bplib/basys3/tb/tb_basys3.vbom create mode 100644 rtl/bplib/basys3/tb/tb_basys3.vhd create mode 100644 rtl/bplib/basys3/tb/tb_basys3_core.vbom create mode 100644 rtl/bplib/basys3/tb/tb_basys3_core.vhd rename rtl/bplib/bpgen/{sn_4x7segctl.vbom => sn_7segctl.vbom} (75%) rename rtl/bplib/bpgen/{sn_4x7segctl.vhd => sn_7segctl.vhd} (64%) delete mode 100644 rtl/bplib/fx2lib/fx2_2fifoctl_as.vbom delete mode 100644 rtl/bplib/fx2lib/fx2_2fifoctl_as.vhd create mode 100644 rtl/bplib/nexys4/nexys4_pclk.xdc create mode 100644 rtl/bplib/nexys4/nexys4_pins.xdc create mode 100644 rtl/bplib/nexys4/nexys4_pins_cram.xdc create mode 100644 rtl/bplib/nexys4/nexys4_setup.tcl create mode 100644 rtl/bplib/nexys4/nexys4lib.vhd create mode 100644 rtl/bplib/nexys4/tb/.cvsignore create mode 100644 rtl/bplib/nexys4/tb/Makefile.ise create mode 100644 rtl/bplib/nexys4/tb/tb_nexys4.vbom create mode 100644 rtl/bplib/nexys4/tb/tb_nexys4.vhd create mode 100644 rtl/bplib/nexys4/tb/tb_nexys4_core.vbom create mode 100644 rtl/bplib/nexys4/tb/tb_nexys4_core.vhd create mode 100644 rtl/bplib/nexys4/tb/tb_nexys4_cram.vbom create mode 100644 rtl/bplib/nexys4/tb/tb_nexys4_cram.vhd create mode 100644 rtl/ibus/ibdr_rl11.vbom create mode 100644 rtl/ibus/ibdr_rl11.vhd rename rtl/{make => make_ise}/dontincdep.mk (72%) rename rtl/{make => make_ise}/generic_ghdl.mk (66%) rename rtl/{make => make_ise}/generic_isim.mk (85%) rename rtl/{make => make_ise}/generic_xflow.mk (89%) rename rtl/{make => make_ise}/generic_xflow_cpld.mk (95%) rename rtl/{make => make_ise}/imp_7a_speed.opt (100%) rename rtl/{make => make_ise}/imp_s3_speed.opt (100%) rename rtl/{make => make_ise}/imp_s3_speed_maptd.opt (100%) rename rtl/{make => make_ise}/imp_s6_speed.opt (100%) rename rtl/{make => make_ise}/imp_s6_speed_ise133.opt (100%) rename rtl/{make => make_ise}/syn_7a_speed.opt (100%) rename rtl/{make => make_ise}/syn_s3_speed.opt (100%) rename rtl/{make => make_ise}/syn_s6_speed.opt (100%) rename rtl/{make => make_ise}/syn_s6_speed_ise133.opt (100%) rename rtl/{make => make_ise}/xflow_default_atlys.mk (100%) rename rtl/{make => make_ise}/xflow_default_nexys2.mk (100%) rename rtl/{make => make_ise}/xflow_default_nexys3.mk (100%) rename rtl/{make => make_ise}/xflow_default_nexys4.mk (100%) rename rtl/{make => make_ise}/xflow_default_s3board.mk (100%) rename rtl/{make => make_ise}/xflow_default_s3board_200.mk (100%) create mode 100644 rtl/make_viv/dontincdep.mk create mode 100644 rtl/make_viv/generic_ghdl.mk create mode 100644 rtl/make_viv/generic_vivado.mk create mode 100644 rtl/make_viv/viv_default_basys3.mk create mode 100644 rtl/make_viv/viv_default_build.tcl create mode 100644 rtl/make_viv/viv_default_config.tcl create mode 100644 rtl/make_viv/viv_default_model.tcl create mode 100644 rtl/make_viv/viv_default_nexys4.mk create mode 100644 rtl/make_viv/viv_init.tcl create mode 100644 rtl/make_viv/viv_tools_build.tcl create mode 100644 rtl/make_viv/viv_tools_config.tcl create mode 100644 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mode 100644 rtl/sys_gen/w11a/nexys4/tb/tbw.dat create mode 100644 rtl/vlib/rlink/ioleds_sp1c.vbom create mode 100644 rtl/vlib/rlink/ioleds_sp1c.vhd create mode 100644 rtl/vlib/xlib/s7_cmt_sfs_gsim.vbom create mode 100644 rtl/vlib/xlib/s7_cmt_sfs_gsim.vhd create mode 100644 rtl/vlib/xlib/s7_cmt_sfs_unisim.vbom create mode 100644 rtl/vlib/xlib/s7_cmt_sfs_unisim.vhd create mode 100644 rtl/w11a/pdp11_bram_memctl.vbom create mode 100644 rtl/w11a/pdp11_bram_memctl.vhd create mode 100644 rtl/w11a/pdp11_dspmux.vbom create mode 100644 rtl/w11a/pdp11_dspmux.vhd create mode 100644 rtl/w11a/pdp11_ledmux.vbom create mode 100644 rtl/w11a/pdp11_ledmux.vhd create mode 100644 rtl/w11a/pdp11_statleds.vbom create mode 100644 rtl/w11a/pdp11_statleds.vhd delete mode 100755 tools/bin/set_ftdi_lat delete mode 100755 tools/bin/xilinx_ghdl_unisim delete mode 100755 tools/bin/xilinx_vhdl_chop rename tools/bin/{xilinx_ghdl_simprim => xise_ghdl_simprim} (53%) create mode 100755 tools/bin/xise_ghdl_unisim rename tools/bin/{isemsg_filter => xise_msg_filter} (88%) create mode 100755 tools/bin/xviv_ghdl_unisim delete mode 100644 tools/fx2/bin/nexys2_jtag_2fifo_as.ihx delete mode 100644 tools/fx2/bin/nexys2_jtag_3fifo_as.ihx delete mode 100644 tools/fx2/bin/nexys3_jtag_2fifo_as.ihx delete mode 100644 tools/fx2/bin/nexys3_jtag_3fifo_as.ihx create mode 100644 tools/oskit/211bsd_rl/.cvsignore create mode 100644 tools/oskit/211bsd_rl/211bsd_rl_boot.scmd create mode 100644 tools/oskit/211bsd_rl/211bsd_rl_boot.tcl create mode 100644 tools/oskit/211bsd_rl/README_211bsd_rlset.txt create mode 100644 tools/oskit/rt11-53_rl/.cvsignore create mode 100644 tools/oskit/rt11-53_rl/README_rt11-53_rlset.txt create mode 100644 tools/oskit/rt11-53_rl/rt11-53_rl_boot.scmd create mode 100644 tools/oskit/rt11-53_rl/rt11-53_rl_boot.tcl create mode 100644 tools/oskit/xxdp_rl/.cvsignore create mode 100644 tools/oskit/xxdp_rl/README_license.txt create mode 100644 tools/oskit/xxdp_rl/README_xxdp_rlset.txt create mode 100644 tools/oskit/xxdp_rl/xxdp22_rl_boot.scmd create mode 100644 tools/oskit/xxdp_rl/xxdp22_rl_boot.tcl create mode 100644 tools/oskit/xxdp_rl/xxdp25_rl_boot.scmd create mode 100644 tools/oskit/xxdp_rl/xxdp25_rl_boot.tcl create mode 100644 tools/src/librw11/Rw11CntlRL11.cpp create mode 100644 tools/src/librw11/Rw11CntlRL11.hpp create mode 100644 tools/src/librw11/Rw11CntlRL11.ipp create mode 100644 tools/src/librw11/Rw11UnitRL11.cpp create mode 100644 tools/src/librw11/Rw11UnitRL11.hpp create mode 100644 tools/src/librw11/Rw11UnitRL11.ipp create mode 100644 tools/src/librwxxtpp/RtclRw11CntlRL11.cpp create mode 100644 tools/src/librwxxtpp/RtclRw11CntlRL11.hpp create mode 100644 tools/src/librwxxtpp/RtclRw11UnitRL11.cpp create mode 100644 tools/src/librwxxtpp/RtclRw11UnitRL11.hpp diff --git a/Makefile b/Makefile index 419a0444..f212c639 100644 --- a/Makefile +++ b/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 623 2014-12-29 19:11:40Z mueller $ +# $Id: Makefile 650 2015-02-22 21:39:47Z mueller $ # # 'Meta Makefile' for whole retro project # allows to make all synthesis targets @@ -6,6 +6,8 @@ # # Revision History: # Date Rev Version Comment +# 2015-02-01 640 1.2 add vivado targets, separate from ise targets +# 2015-01-25 638 1.1 drop as type fx2 targets # 2014-06-14 562 1.0.8 suspend nexys4 syn targets # 2013-09-28 535 1.0.7 add nexys4 port for sys_gen/tst_sram,w11a # 2013-05-01 513 1.0.6 add clean_sim_tmp and clean_syn_tmp targets @@ -16,98 +18,185 @@ # 2011-11-18 426 1.0.1 add tst_serport and tst_snhumanio # 2011-07-09 391 1.0 Initial version # -SYN_all += rtl/sys_gen/tst_fx2loop/nexys2/ic -SYN_all += rtl/sys_gen/tst_fx2loop/nexys2/ic3 -SYN_all += rtl/sys_gen/tst_fx2loop/nexys3/ic -SYN_all += rtl/sys_gen/tst_fx2loop/nexys3/ic3 -SYN_all += rtl/sys_gen/tst_rlink/nexys2 -SYN_all += rtl/sys_gen/tst_rlink/nexys3 -SYN_all += rtl/sys_gen/tst_rlink/s3board -SYN_all += rtl/sys_gen/tst_rlink_cuff/nexys2/ic -SYN_all += rtl/sys_gen/tst_rlink_cuff/nexys2/ic3 -SYN_all += rtl/sys_gen/tst_rlink_cuff/nexys3/ic -SYN_all += rtl/sys_gen/tst_rlink_cuff/atlys/ic -SYN_all += rtl/sys_gen/tst_serloop/nexys2 -SYN_all += rtl/sys_gen/tst_serloop/nexys3 -SYN_all += rtl/sys_gen/tst_serloop/s3board -SYN_all += rtl/sys_gen/tst_snhumanio/atlys -SYN_all += rtl/sys_gen/tst_snhumanio/nexys2 -SYN_all += rtl/sys_gen/tst_snhumanio/nexys3 -SYN_all += rtl/sys_gen/tst_snhumanio/s3board -SYN_all += rtl/sys_gen/w11a/nexys2 -SYN_all += rtl/sys_gen/w11a/nexys3 -SYN_all += rtl/sys_gen/w11a/s3board -SIM_all += rtl/bplib/nxcramlib/tb -SIM_all += rtl/sys_gen/tst_rlink/nexys2/tb -SIM_all += rtl/sys_gen/tst_rlink/nexys3/tb -SIM_all += rtl/sys_gen/tst_rlink/s3board/tb -SIM_all += rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb -SIM_all += rtl/sys_gen/tst_rlink_cuff/nexys3/ic/tb -SIM_all += rtl/sys_gen/tst_serloop/nexys2/tb -SIM_all += rtl/sys_gen/tst_serloop/nexys3/tb -SIM_all += rtl/sys_gen/tst_serloop/s3board/tb -SIM_all += rtl/sys_gen/w11a/nexys2/tb -SIM_all += rtl/sys_gen/w11a/nexys3/tb -SIM_all += rtl/sys_gen/w11a/s3board/tb -SIM_all += rtl/vlib/comlib/tb -SIM_all += rtl/vlib/rlink/tb -SIM_all += rtl/vlib/serport/tb -SIM_all += rtl/w11a/tb +# Synthesis targets -------------------------------------------------- +# ISE based targets, by board type ----------------------- +# S3board ------------------------------------ + +SYN_ise += rtl/sys_gen/tst_rlink/s3board +SYN_ise += rtl/sys_gen/tst_serloop/s3board +SYN_ise += rtl/sys_gen/tst_snhumanio/s3board +SYN_ise += rtl/sys_gen/w11a/s3board + +# Nexys2 ------------------------------------- +SYN_ise += rtl/sys_gen/tst_fx2loop/nexys2/ic +SYN_ise += rtl/sys_gen/tst_fx2loop/nexys2/ic3 +SYN_ise += rtl/sys_gen/tst_rlink/nexys2 +SYN_ise += rtl/sys_gen/tst_rlink_cuff/nexys2/ic +SYN_ise += rtl/sys_gen/tst_rlink_cuff/nexys2/ic3 +SYN_ise += rtl/sys_gen/tst_serloop/nexys2 +SYN_ise += rtl/sys_gen/tst_snhumanio/nexys2 +SYN_ise += rtl/sys_gen/w11a/nexys2 + +# Nexys3 ------------------------------------- +SYN_ise += rtl/sys_gen/tst_fx2loop/nexys3/ic +SYN_ise += rtl/sys_gen/tst_fx2loop/nexys3/ic3 +SYN_ise += rtl/sys_gen/tst_rlink/nexys3 +SYN_ise += rtl/sys_gen/tst_rlink_cuff/nexys3/ic +SYN_ise += rtl/sys_gen/tst_serloop/nexys3 +SYN_ise += rtl/sys_gen/tst_snhumanio/nexys3 +SYN_ise += rtl/sys_gen/w11a/nexys3 + +# xc2 ---------------------------------------- + +# Vivado based targets, by board type -------------------- +# Basys3 ------------------------------------- +SYN_viv += rtl/sys_gen/tst_snhumanio/basys3 +#SYN_viv += rtl/sys_gen/tst_serloop/basys3 +SYN_viv += rtl/sys_gen/tst_rlink/basys3 +SYN_viv += rtl/sys_gen/w11a/basys3 + +# Nexys4 ------------------------------------- +SYN_viv += rtl/sys_gen/tst_rlink/nexys4 +SYN_viv += rtl/sys_gen/tst_serloop/nexys4 +SYN_viv += rtl/sys_gen/tst_snhumanio/nexys4 +SYN_viv += rtl/sys_gen/w11a/nexys4 + +# Simulation targets ------------------------------------------------- +# ISE flow ----------------------------------------------- + +# Component tests ---------------------------- +SIM_ise += rtl/bplib/nxcramlib/tb +SIM_ise += rtl/vlib/comlib/tb +SIM_ise += rtl/vlib/rlink/tb +SIM_ise += rtl/vlib/serport/tb +SIM_ise += rtl/w11a/tb + +# S3board ------------------------------------ +SIM_ise += rtl/sys_gen/tst_rlink/s3board/tb +SIM_ise += rtl/sys_gen/tst_serloop/s3board/tb +SIM_ise += rtl/sys_gen/w11a/s3board/tb + +# Nexys2 ------------------------------------- +SIM_ise += rtl/sys_gen/tst_rlink/nexys2/tb +SIM_ise += rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb +SIM_ise += rtl/sys_gen/tst_serloop/nexys2/tb +SIM_ise += rtl/sys_gen/w11a/nexys2/tb + +# Nexys3 ------------------------------------- +SIM_ise += rtl/sys_gen/tst_rlink/nexys3/tb +SIM_ise += rtl/sys_gen/tst_rlink_cuff/nexys3/ic/tb +SIM_ise += rtl/sys_gen/tst_serloop/nexys3/tb +SIM_ise += rtl/sys_gen/w11a/nexys3/tb + +# xc2 ---------------------------------------- + +# Vivado flow -------------------------------------------- +# Basys3 ------------------------------------- +SIM_viv += rtl/sys_gen/tst_rlink/basys3/tb +#SIM_viv += rtl/sys_gen/tst_serloop/basys3/tb +SIM_viv += rtl/sys_gen/w11a/basys3/tb +# Nexys4 ------------------------------------- +SIM_viv += rtl/sys_gen/tst_rlink/nexys4/tb +SIM_viv += rtl/sys_gen/tst_serloop/nexys4/tb +SIM_viv += rtl/sys_gen/w11a/nexys4/tb # -.PHONY : default all all_sim all_syn -.PHONY : clean clean_sim clean_sim_tmp clean_sym clean_sym_tmp -.PHONY : $(SYN_all) $(SIM_all) +.PHONY : default +.PHONY : all all_ise all_viv +.PHONY : all_sim_ise all_syn_ise all_syn_viv +.PHONY : clean +.PHONY : clean_sim_ise clean_sim_ise_tmp +.PHONY : clean_sym_ise clean_sim_viv clean_sym_ise_tmp clean_sym_viv_tmp +# +# all directories most be declared as phony targets +.PHONY : $(SYN_ise) $(SIM_ise) +.PHONY : $(SYN_viv) $(SIM_viv) # default : @echo "No default action defined:" @echo " for VHDL simulation/synthesis use:" - @echo " make -j `nproc` all_sim" - @echo " make -j `nproc` all_syn" + @echo " make -j `nproc` all" + @echo " make -j `nproc` all_ise" + @echo " make -j `nproc` all_viv" + @echo " make -j `nproc` all_sim_ise" + @echo " make -j `nproc` all_syn_ise" + @echo " make -j `nproc` all_sim_viv" + @echo " make -j `nproc` all_syn_viv" @echo " make clean" - @echo " make clean_sim" - @echo " make clean_syn" - @echo " make clean_sim_tmp" - @echo " make clean_syn_tmp" + @echo " make clean_sim_ise" + @echo " make clean_syn_ise" + @echo " make clean_sim_viv" + @echo " make clean_syn_viv" + @echo " make clean_sim_ise_tmp" + @echo " make clean_syn_ise_tmp" + @echo " make clean_sim_viv_tmp" + @echo " make clean_syn_viv_tmp" @echo " for tool/documentation generation use:" @echo " make -j `nproc` all_lib" @echo " make clean_lib" @echo " make all_tcl" @echo " make all_dox" # -all : - make -j `nproc` all_sim - make -j `nproc` all_syn - make -j `nproc` all_lib +all : all_ise all_viv all_lib +all_ise : all_sim_ise all_syn_ise +all_viv : all_sim_viv all_syn_viv # -clean : clean_sim clean_syn +clean : clean_sim_ise clean_syn_ise clean_sim_viv clean_syn_viv # -clean_sim : - for dir in $(SIM_all); do $(MAKE) -C $$dir clean; done -clean_syn : - for dir in $(SYN_all); do $(MAKE) -C $$dir clean; done +clean_sim_ise : + for dir in $(SIM_ise); do $(MAKE) -C $$dir clean; done +clean_syn_ise : + for dir in $(SYN_ise); do $(MAKE) -C $$dir clean; done # -clean_sim_tmp : - for dir in $(SIM_all); do $(MAKE) -C $$dir ghdl_tmp_clean; done -clean_syn_tmp : - for dir in $(SYN_all); do $(MAKE) -C $$dir ise_tmp_clean; done +clean_sim_viv : + for dir in $(SIM_viv); do $(MAKE) -C $$dir clean; done +clean_syn_viv : + for dir in $(SYN_viv); do $(MAKE) -C $$dir clean; done # -all_sim : $(SIM_all) +clean_sim_ise_tmp : + for dir in $(SIM_ise); do $(MAKE) -C $$dir ghdl_tmp_clean; done +clean_syn_ise_tmp : + for dir in $(SYN_ise); do $(MAKE) -C $$dir ise_tmp_clean; done # -all_syn : $(SYN_all) +clean_sim_viv_tmp : + for dir in $(SIM_viv); do $(MAKE) -C $$dir ghdl_tmp_clean; done +clean_syn_viv_tmp : + for dir in $(SYN_viv); do $(MAKE) -C $$dir viv_tmp_clean; done +# +all_sim_ise : $(SIM_ise) +# +all_syn_ise : $(SYN_ise) @if [ -n "`find -name "*_par.log" | xargs grep -L 'All constraints were met'`" ] ; then \ echo "++++++++++ some designs have no timing closure: ++++++++++"; \ find -name "*_par.log" | xargs grep -L 'All constraints were met'; \ echo "++++++++++ ++++++++++++++++++++++++++++++++++++ ++++++++++"; \ + else \ + echo "++++++++++ all ISE designs have timing closure ++++++++++"; \ fi # -# Neither ghdl nor xst allow multiple parallel compiles in one directory. -# The following ensures that the sub-makes are called with -j 1 and will -# not try to run multiple compiles on one directory. +all_sim_viv : $(SIM_viv) # -$(SIM_all): +all_syn_viv : $(SYN_viv) + @if [ -n "`find -name "*_rou_tim.rpt" | xargs grep -L 'All user specified timing constraints are met'`" ] ; then \ + echo "++++++++++ some designs have no timing closure: ++++++++++"; \ + find -name "*_rou_tim.rpt" | xargs grep -L 'All user specified timing constraints are met'; \ + echo "++++++++++ ++++++++++++++++++++++++++++++++++++ ++++++++++"; \ + else \ + echo "++++++++++ all Vivado designs have timing closure ++++++++++"; \ + fi +# +# Neither ghdl nor Xilinx tools allow multiple parallel compiles in one +# directory. The following ensures that the sub-makes are called with -j 1 +# and will not try to run multiple compiles on one directory. +# +$(SIM_ise): $(MAKE) -j 1 -C $@ -$(SYN_all): +$(SYN_ise): + $(MAKE) -j 1 -C $@ +# +$(SIM_viv): + $(MAKE) -j 1 -C $@ +$(SYN_viv): $(MAKE) -j 1 -C $@ # all_lib : @@ -122,3 +211,4 @@ all_dox : (cd tools/dox; make_doxy) # all_all : all_sim all_syn all_lib all_tcl + diff --git a/doc/.cvsignore b/doc/.cvsignore new file mode 100644 index 00000000..485d9b20 --- /dev/null +++ b/doc/.cvsignore @@ -0,0 +1,2 @@ +*_flow.dot +*_flow.pdf diff --git a/doc/FILES.txt b/doc/FILES.txt index 1f5ebd61..6659dddd 100644 --- a/doc/FILES.txt +++ b/doc/FILES.txt @@ -1,4 +1,4 @@ -$Id: FILES.txt 577 2014-08-03 20:49:42Z mueller $ +$Id: FILES.txt 645 2015-02-13 21:44:03Z mueller $ Short description of the directory layout, what is where ? @@ -7,27 +7,33 @@ Short description of the directory layout, what is where ? rtl VHDL sources rtl/bplib - board and component support libs rtl/bplib/atlys - for Digilent Atlys board + rtl/bplib/basys3 - for Digilent Basys3 board rtl/bplib/fx2lib - for Cypress FX2 USB interface controller rtl/bplib/issi - for ISSI parts rtl/bplib/micron - for Micron parts rtl/bplib/nexys2 - for Digilent Nexsy2 board rtl/bplib/nexys3 - for Digilent Nexsy3 board + rtl/bplib/nexys4 - for Digilent Nexsy4 board rtl/bplib/nxcramlib - for CRAM part used in Nexys2/3 - rtl/bplib/s3board - for Digilent S3BOARD + rtl/bplib/s3board - for Digilent S3board rtl/ibus - ibus devices (UNIBUS peripherals) rtl/sys_gen - top level designs rtl/sys_gen/tst_fx2loop - top level designs for Cypress FX2 tester nexys2,nexys3 - systems for Nexsy2,Nexsy3 rtl/sys_gen/tst_rlink - top level designs for an rlink tester - nexys2,nexys3,s3board - systems for Nexsy2,Nexsy3,S3BOARD + nexys2,nexys3,s3board - systems for Nexsy2,Nexsy3,S3board + basys3,nexys4 - systems for Basys3,Nexys4 rtl/sys_gen/tst_rlink_cuff - top level designs for rlink over FX2 tester nexys2,nexys3,atlys - systems for Atlys,Nexsy2,Nexsy3 rtl/sys_gen/tst_serloop - top level designs for serport loop tester - nexys2,nexys3,s3board - systems for Nexsy2,Nexsy3,S3BOARD + nexys2,nexys3,s3board - systems for Nexsy2,Nexsy3,S3board + nexys4 - systems for Nexys4 rtl/sys_gen/tst_snhumanio - top level designs for human I/O tester - atlys,nexys2,nexys3,s3board - systems for Atlys,Nexsy2,Nexsy3,S3BOARD + atlys,nexys2,nexys3,s3board - systems for Atlys,Nexsy2,Nexsy3,S3board + basys3,nexys4 - systems for Basys3,Nexys4 rtl/sys_gen/w11a - top level designs for w11a SoC - nexys2,nexys3,s3board - w11a systems for Nexsy2,Nexsy3,S3BOARD + nexys2,nexys3,s3board - w11a systems for Nexsy2,Nexsy3,S3board + basys3,nexys4 - systems for Basys3,Nexys4 rtl/vlib - VHDL component libs rtl/vlib/comlib - communication rtl/vlib/genlib - general @@ -44,7 +50,8 @@ Short description of the directory layout, what is where ? tools/asm-11/tests-err - test bench for asm-11 (error check part) tools/bin - scripts and binaries tools/dox - Doxygen documentation configuration - tools/make - make includes + tools/make_ise - make includes for ISE + tools/make_viv - make includes for Vivado tools/fx2 - Firmware for Cypress FX2 USB Interface tools/fx2/bin - pre-build firmware images in .ihx format tools/fx2/src - C and asm sources diff --git a/doc/INSTALL.txt b/doc/INSTALL.txt index 6a38b4e1..01424efc 100644 --- a/doc/INSTALL.txt +++ b/doc/INSTALL.txt @@ -1,4 +1,4 @@ -# $Id: INSTALL.txt 604 2014-11-16 22:33:09Z mueller $ +# $Id: INSTALL.txt 654 2015-03-01 18:45:38Z mueller $ Guide to install and build w11a systems, test benches and support software @@ -6,23 +6,14 @@ Guide to install and build w11a systems, test benches and support software 1. Download 2. System requirements - 3. Setup system environment - a. Setup environment variables - b. Setup USB access + 3. Setup environment variables 4. Compile UNISIM/SIMPRIM libraries for ghdl 5. Compile and install the support software a. Compile sharable libraries b. Setup Tcl packages - c. Rebuild Cypress FX2 firmware 6. The build system - 6 a. Setting up Xilinx environment with xtwi 7. Building test benches - a. General instructions - b. Available test benches 8. Building systems - a. General instructions - b. Configuring FPGAs (via make flow) - c. Configuring FPGAs (directly via config_wrapper) d. Available systems e. Available bitkits with bit and log files 9. Generate Doxygen based source code view @@ -56,7 +47,6 @@ Guide to install and build w11a systems, test benches and support software cd svn co -r http://opencores.org/ocsvn/w11/w11/trunk - 2. System requirements ---------------------------------------------------- This project contains not only VHDL code but also support software. Therefore @@ -64,7 +54,7 @@ Guide to install and build w11a systems, test benches and support software list gives the Ubuntu/Debian package names, but mapping this to other distributions should be straight forward. - - building the bit files for the FPGAs requires a Xilinx WebPACK installation + - building the bit files requires a Xilinx ISE WebPACK installation - building and using the RLink backend software requires: - full C/C++ development chain (gcc,g++,cpp,make) @@ -75,25 +65,16 @@ Guide to install and build w11a systems, test benches and support software - libusb 1.0 (>= 1.0.6) -> package: libusb-1.0-0-dev - Perl (>= 5.10) (usually included in base installations) - - Tcl (>= 8.4), with tclreadline support + - Tcl (>= 8.5), with tclreadline support -> package: tcl tcl-dev tcllib tclreadline - - the download contains pre-build firmware images for the Cypress FX2 - USB Interface. Re-building them requires - - Small Device C Compiler - -> package: sdcc sdcc-ucsim - - - for FX2 firmware download and jtag programming over USB one needs - - fxload - -> package: fxload - - urjtag - -> package: urjtag for Ubuntu 12.04 - -> see INSTALL_urjtag.txt for other distributions !! - - for VHDL simulations one needs - ghdl -> see INSTALL_ghdl.txt for the unfortunately gory details + - additional requirements for using Cypress FX (on Nexys2/3) see + INSTALL_fx2_support.txt + - for doxygen documentation an up-to-date installation of doxygen is required, version 1.8.3.1 or later @@ -101,13 +82,11 @@ Guide to install and build w11a systems, test benches and support software - gtkwave -> package: gtkwave -3. Setup system environment ----------------------------------------------- - -3a. Setup environment variables -------------------------------------- +3. Setup environment variables -------------------------------------------- The make flow for building test benches (ghdl and ISim based) and systems - (Xilinx xst based) as well as the support software (mainly the rlink backend - server) requires + (Xilinx ISE xst based) as well as the support software (mainly the rlink + backend server) requires - the definition of the environment variables: - RETROBASE: must refer to the installation root directory @@ -143,32 +122,7 @@ Guide to install and build w11a systems, test benches and support software After that building functional model based test benches will work. If you want to also build post-xst or post-par test benches read next section. - If the Cypress USB controller available on Digilent Nexys2, Nexys3 and - Atlys boards is used the default USB VID and PID is defined by two - environment variables. For internal lab use one can use - - export RETRO_FX2_VID=16c0 - export RETRO_FX2_PID=03ef - - !! Carefully read the disclaimer about usage of USB VID/PID numbers !! - !! in the file README_USB-VID-PID.txt. You'll be responsible for any !! - !! misuse of the defaults provided with the project sources. !! - !! Usage of this VID/PID in any commercial product is forbidden. !! - -3b. Setup USB access ------------------------------------------------- - - For using the Cypress FX2 USB interface on Digilent Nexys2, Nexys3 and - Atlys boards 'udev' rules must be setup to allow user level access to - these devices. A set of rules is provided under - - $RETROBASE/tools/fx2/sys - - Follow the 'README.txt' file in this directory. - - Notes: - - the provided udev rules use the VID/PID for 'internal lab use' as - described above. If other VID/PID used the file must be modified. - - your user account must be in group 'plugdev' (should be the default). + For Cypress FX2 (on Nexys2/3) related setup see INSTALL_fx2_support.txt 4. Compile UNISIM/SIMPRIM libraries for ghdl ------------------------------ @@ -176,7 +130,7 @@ Guide to install and build w11a systems, test benches and support software the gate level models derived after the xst, map or par step. In this case ghdl has to link against a compiled UNISIM or SIMPRIM library. - To make handling of the parallel installion of several WebPack versions + To make handling of the parallel installion of several ISE WebPack versions easy the compiled libraries are stored in sub-directories under $XILINX: $XILINX/ghdl/unisim @@ -187,8 +141,8 @@ Guide to install and build w11a systems, test benches and support software cd $RETROBASE - xtwi xilinx_ghdl_unisim - xtwi xilinx_ghdl_simprim + xise_ghdl_unisim + xise_ghdl_simprim If you have several WebPack versions installed, repeat for each version. @@ -196,14 +150,20 @@ Guide to install and build w11a systems, test benches and support software 5a. Compile sharable libraries --------------------------------------- + Note: some c++11 features are used in the code + - N2343: decltype (used by boost bind) -> since gcc 4.3 + - N2431: nullptr -> since gcc 4.6 + - N2930: range based for -> since gcc 4.6 + - N1984: auto-types variables -> since gcc 4.4 + Required tools and libraries: - g++ >= 4.3 (decltype support assumed in usage of boost::bind) + g++ >= 4.6 (see c++11 usage above) boost >= 1.35 (boost::thread api changed, new one is used) linusb >= 1.0.5 (timerfd support) Build was tested under: - ubuntu lucid (12.04 LTS): gcc 4.6.3 boost 1.46.1 libusb 1.0.9 - debian squezze (6.0.6): gcc 4.4.5 boost 1.46.1 libusb 1.0.8 + ubuntu precise (14.04 LTS): gcc 4.8.2 boost 1.54 libusb 1.0.17 + debian wheezy (7.0.8): gcc 4.7.2 boost 1.49 libusb 1.0.11 To build all sharable libraries @@ -248,228 +208,60 @@ Guide to install and build w11a systems, test benches and support software ln -s $RETROBASE/tools/tcl/.tclshrc . ln -s $RETROBASE/tools/tcl/.wishrc . -5c. Rebuild Cypress FX2 firmware ------------------------------------- - - The download includes pre-build firmware images for the Cypress FX2 - USB interface used on the Digilent Nexys2, Nexys3 and Atlys Boards. - These firmware images are under - - $RETROBASE/tools/fx2/bin - - To re-build them, e.g. because a different USB VID/PID is to be used - - cd $RETROBASE/tools/fx2/src - make clean - make - make install - - Note: The default build assumes that sdcc with a version 3.x is installed. - In case sdcc 2.x is installed use - make SDCC29=1 - instead. See also tools/fx2/src/README.txt in the - - Please read README_USB_VID-PID.txt carefully to understand the usage - of USB VID and PID. - 6. The build system ------------------------------------------------------- - Simulation and synthesis tools usually need a list of the VHDL source - files, often in proper compilation order (libraries before components). - The different tools have different formats of these 'project files'. - - The build system employed in this project is based on manifest files called - 'vbom' or "VHDL bill of material" files - which list for each vhdl source file the libraries and sources for the - instantiated components, the later via their vbom, and last but not least - the name of the vhdl source file. - All file name are relative to the current directory. A recursive traversal - through all vbom's gives for each vhld module all sources needed to compile - it. The vbomconv script in tools/bin does this, and generates depending on - options - - make dependency files - - ISE xst project files - - ISE ISim project files - - ghdl commands for analysis, inspection and make step - - The master make files contain pattern rules like - %.ngc : %.vbom -- synthesize with xst - % : %.vbom -- build functional model test bench - which encapsulate all the vbomconf magic - - A full w11a is build from about 100 source files, test benches from - even more. Using the vbom's a large number of designs can be easily - maintained. - -6a. Setting up Xilinx environment with xtwi -------------------------- - - The Xilinx ISE setup script redefines PATH and LD_LIBRARY_PATH. The ISE - tools run fine in this environment, but other installed programs on the - system can (and actually do) fail. - - The build system uses a small wrapper script called xtwi to encapsulate - the Xilinx environment. It expects that the environment variable XTWI_PATH - is setup to the install path of the ISE version to be used. Without the - /ISE_DS/ which is added by the ISE installation procedure ! - - Note: don't run the ISE setup scripts ..../settings(32|64).sh in your - working shell. Setup only XTWI_PATH ! + The generation of + - FPGA firmware (e.g. .bit files) + - test benches (e.g. simulator images) + is based on make flows. + + Two design tools are currently supported + - Xilinx Vivado + - Artix-7 based board (Basys3, Nexys4) + - see README_buildsystem_Vivado.txt + - Xilinx ISE + - Spartan-3 and Spartan-6 based boards (S3board, Nexys2, Nexys3) + - see README_buildsystem_ISE.txt 7. Building test benches -------------------------------------------------- -7a. General instructions --------------------------------------------- + General instructions are in + - README_buildsystem_Vivado.txt (for Basys3, Nexys4) + - README_buildsystem_ISE.txt (for S3board, Nexys2, Nexys3) - To compile a test bench named all is needed is + For available test benches see w11a_tb_guide.txt - make +8. Building systems and configuring FPGAs --------------------------------- - The make file will use .vbom, create all make dependency files, - and generate the needed ghdl commands. - - In many cases the test benches can also be compiled against the gate - level models derived after the xst, map or par step. To compile them - - make ghdl_tmp_clean - make _ssim # for post-xst - make _fsim # for post-map - make _tsim # for post-par - - The 'make ghdl_tmp_clean' is needed to flush the ghdl work area from - the compilation remains of earlier functional model compiles. - -7b. Available test benches ------------------------------------------- - - See file w11a_tb_guide.txt - -8. Building systems ------------------------------------------------------- - -8a. General instructions --------------------------------------------- - - First ensure that XTWI_PATH is setup, see section 6a. - - To generate a bit file for a system named all is needed is - - make .bit - - The make file will use .vbom, create all make dependency files, build - the ucf file with cpp, and run the synthesis flow (xst, ngdbuild, par, trce). - The log files will be named - - _xst.log # xst log file - _tra.log # translate (ngdbuild) log file (renamed %.bld) - _map.log # map log file (renamed %_map.mrp) - _par.log # par log file (renamed %.par) - _pad.log # pad file (renamed %_pad.txt) - _twr.log # trce log file (renamed %.twr) - - To load the bitfile with WebPack impact into the target board use - - make .iconfig - - For boards with a Cypress FX2 USB controller load the bitfile directly with - - make .jconfig - - If a svf file is required for configuring the FPGA a svf can be created - from a bit file with - - make .svf - - If only the xst or par output is wanted just use - - make .ngc - make .ncd - - A simple 'message filter' system is also integrated into the make build flow. - For many (though not all) systems a .mfset file has been provided which - defines the xst,par and bitgen messages which are considered ok. To see - only the remaining message extracted from the vaious .log files simply - use the make target - - make .mfsum - - after a re-build. - -8b. Configuring FPGAs (via make flow) -------------------------------- - - The make flow supports also loading the bitstream into FPGAs, either - via Xilinx Impact, or via the Cypress FX2 USB controller is available. - - For Xilinx Impact a Xilinx USB Cable II has to be properly setup, than - simply use - - make .iconfig - - For using the Cypress FX2 USB controller on Digilent Nexys2, Nexys3 and - Atlys boards just connect the USB cable and - - make .jconfig - - This will automatically check and optionaly re-load the FX2 firmware - to a version matching the FPGA design, generate a .svf file from the - .bit file, and configure the FPGA. In case the bit file is out-of-date - the whole design will be re-implemented before. - -8c. Configuring FPGAs (directly via config_wrapper) ------------------ - - The make flow described above uses two scripts - config_wrapper # must be used with xtwi ! - fx2load_wrapper - which can be used directly for loading available bit or svf files into - the FPGA. For detailed documentation see the respective man pages. - - Examples for the supported boards are given in section 8e. + General instructions are in + - README_buildsystem_Vivado.txt (for Basys3, Nexys4) + - README_buildsystem_ISE.txt (for S3board, Nexys2, Nexys3) 8d. Available systems ------------------------------------------------ - Currently ready to build versions exist for - - Digilent S3BOARD (-1000 FPGA version) - - Digilent Nexys2 board (-1200 FPGA version) - - Digilent Nexys3 board + Ready to build designs are organized in the directories + + $RETROBASE/rtl/sys_gen// + + with + w11a w11a system + tst_rlink rlink over serial link tester + tst_rlink_cuff rlink over FX2 interface tester + + and + basys3 b3: Digilent Basys3 board + nexys4 n4: Digilent Nexys4 board (cellular RAM version) + nexys3 n3: Digilent Nexys3 board + nexys2 n2: Digilent Nexys2 board (-1200 FPGA version) + s3board s3: Digilent S3board (-1000 FPGA version) To build the designs locally use - 1. rlink tester - a. for Digilent S3BOARD + cd $RETROBASE/rtl/sys_gen// + make sys__.bit - cd $RETROBASE/rtl/sys_gen/tst_rlink/s3board - make sys_tst_rlink_s3.bit - - b. for Digilent Nexys2 board - - cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys2 - make sys_tst_rlink_n2.bit - - c. for Digilent Nexys3 board - - cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys3 - make sys_tst_rlink_n3.bit - - 2. rlink over USB tester - a. for Digilent Nexys2 board - - cd $RETROBASE/rtl/sys_gen/tst_rlink_cuff/nexys2/ic - make sys_tst_rlink_cuff_ic_n2.bit - - b. for Digilent Nexys3 board - - cd $RETROBASE/rtl/sys_gen/tst_rlink_cuff/nexys3/ic - make sys_tst_rlink_cuff_ic_n3.bit - - 3. w11a systems - a. for Digilent S3BOARD - - cd $RETROBASE/rtl/sys_gen/w11a/s3board - make sys_w11a_s3.bit - - b. for Digilent Nexys2 board - - cd $RETROBASE/rtl/sys_gen/w11a/nexys2 - make sys_w11a_n2.bit - - c. for Digilent Nexys3 board - - cd $RETROBASE/rtl/sys_gen/w11a/nexys3 - make sys_w11a_n3.bit + with in most cases = and = 2 letter abriviation for + the board, e.g. n4 for nexys4. 8e. Available bitkits with bit and log files ------------------------- @@ -480,29 +272,35 @@ Guide to install and build w11a systems, test benches and support software file names contain information about release, Xlinix tool, and design: __.tgz - These designs can be loaded with config_wrapper into the FPGA. The - procedures for the supported boards are given below. + - Vivado based designs: + These designs can be loaded with the Vivado hardware server into the FPGA. - Notes: - 1. XTWI_PATH and RETROBASE environment variables must be defined. - 2. config_wrapper bit2svf is only needed once to create the svf files. - 3. fx2load_wrapper is needed once after each board power on. + - ISE based designs: - a. for Digilent S3BOARD (using ISE Impact) + These designs can be loaded with config_wrapper into the FPGA. The + procedures for the supported boards are given below. - xtwi config_wrapper --board=s3board iconfig .bit + Notes: + 1. XTWI_PATH and RETROBASE environment variables must be defined. + 2. config_wrapper bit2svf is only needed once to create the svf files. + 3. fx2load_wrapper is needed once after each board power on. - b. for Digilent Nexys2 board (using Cypress FX2 USB controller) + a. for Digilent Nexys3 board (using Cypress FX2 USB controller) + + xtwi config_wrapper --board=nexys3 bit2svf .bit + fx2load_wrapper --board=nexys3 + xtwi config_wrapper --board=nexys3 jconfig .svf + + b. for Digilent Nexys2 board (using Cypress FX2 USB controller) xtwi config_wrapper --board=nexys2 bit2svf .bit fx2load_wrapper --board=nexys2 xtwi config_wrapper --board=nexys2 jconfig .svf - c. for Digilent Nexys3 board (using Cypress FX2 USB controller) + c. for Digilent S3board (using ISE Impact) + + xtwi config_wrapper --board=s3board iconfig .bit - xtwi config_wrapper --board=nexys3 bit2svf .bit - fx2load_wrapper --board=nexys3 - xtwi config_wrapper --board=nexys3 jconfig .svf 9. Generate Doxygen based source code view -------------------------------- diff --git a/doc/INSTALL_fx2_support.txt b/doc/INSTALL_fx2_support.txt new file mode 100644 index 00000000..c47dbe82 --- /dev/null +++ b/doc/INSTALL_fx2_support.txt @@ -0,0 +1,79 @@ +# $Id: INSTALL_fx2_support.txt 654 2015-03-01 18:45:38Z mueller $ + +The Nexys2 and Nexys3 board feature a Cypress FX2 USB interface. It allows +to configure the FPGA and to transfer between FPGA and a PC. The retro +project uses a custom firmware in the FX2, this writeup describes the +installation of tools, environment setup and generation of the FX2 firmware. + + Table of content: + + 1. System requirements + 2. Setup environment variables + 3. Setup USB access + 4. Rebuild Cypress FX2 firmware + +1. System requirements ---------------------------------------------------- + + - the download contains pre-build firmware images for the Cypress FX2 + USB Interface. Re-building them requires + - Small Device C Compiler + -> package: sdcc sdcc-ucsim + + - for FX2 firmware download and jtag programming over USB one needs + - fxload + -> package: fxload + - urjtag + -> package: urjtag for Ubuntu 12.04 + -> see INSTALL_urjtag.txt for other distributions !! + +2. Setup environment variables --------------------------------------------- + + The default USB VID and PID is defined by two environment variables. + For internal lab use one can use + + export RETRO_FX2_VID=16c0 + export RETRO_FX2_PID=03ef + + !! Carefully read the disclaimer about usage of USB VID/PID numbers !! + !! in the file README_USB-VID-PID.txt. You'll be responsible for any !! + !! misuse of the defaults provided with the project sources. !! + !! Usage of this VID/PID in any commercial product is forbidden. !! + +3. Setup USB access ------------------------------------------------------- + + For using the Cypress FX2 USB interface on Digilent Nexys2, Nexys3 and + Atlys boards 'udev' rules must be setup to allow user level access to + these devices. A set of rules is provided under + + $RETROBASE/tools/fx2/sys + + Follow the 'README.txt' file in this directory. + + Notes: + - the provided udev rules use the VID/PID for 'internal lab use' as + described above. If other VID/PID used the file must be modified. + - your user account must be in group 'plugdev' (should be the default). + +4. Rebuild Cypress FX2 firmware ------------------------------------------- + + The download includes pre-build firmware images for the Cypress FX2 + USB interface used on the Digilent Nexys2, Nexys3 and Atlys Boards. + These firmware images are under + + $RETROBASE/tools/fx2/bin + + To re-build them, e.g. because a different USB VID/PID is to be used + + cd $RETROBASE/tools/fx2/src + make clean + make + make install + + Note: The default build assumes that sdcc with a version 3.x is installed. + In case sdcc 2.x is installed use + make SDCC29=1 + instead. See also tools/fx2/src/README.txt in the + + Please read README_USB_VID-PID.txt carefully to understand the usage + of USB VID and PID. + diff --git a/doc/INSTALL_ghdl.txt b/doc/INSTALL_ghdl.txt index db618a81..3b01e506 100644 --- a/doc/INSTALL_ghdl.txt +++ b/doc/INSTALL_ghdl.txt @@ -1,4 +1,4 @@ -# $Id: INSTALL_ghdl.txt 537 2013-10-06 09:06:23Z mueller $ +# $Id: INSTALL_ghdl.txt 651 2015-02-26 21:32:15Z mueller $ The w11 project uses the open source VHDL simulator @@ -6,18 +6,18 @@ The w11 project uses the open source VHDL simulator It used to be part of most distributions. Unfortunately the Debian maintainer for ghdl refused at some point to integrate ghdl into Debian Etch. Therefore -ghdl was part of Debian Lenny, and again of Debian Squeeze, and is missing -again in Debian Wheezy (the current 'stable'). +ghdl was part of Debian 5 "Lenny", and again of Debian 6 "Squeeze", and is +missing again in Debian 7 "Wheezy" (the current 'stable'). The glitch at Debian unfortunately lead to the removal of ghdl from Ubuntu, -which is based on Debian. Ubuntu Lucid (10.04) and up to Oneiric (11.10) -included ghdl, the currently maintained versions Precise (12.04 LTS) and -alter don't. +which is based on Debian. Ubuntu 10.04 "Lucid" up to 11.10 "Oneiric" included +ghdl, the currently maintained versions 12.04 LTS "Precise", 14.04 LTS "Trusty" +and 14.10 "Utopic" unfortunately don't. To install ghdl on an up-to-date Debian or Ubuntu systems you have the -following options {as of early October 2013}: +following options {as of early February 2015}: -- Ubuntu Precise, Quantal, and Raring +- Ubuntu Precise and Trusty Thanks to Peter Gavin Ubuntu packages for GHDL are available from his PPA 'Personal Package Archives', see @@ -39,9 +39,9 @@ following options {as of early October 2013}: There are also Ubuntu packages, but Joris focus is clearly on Debian. -Only Debian and Ubuntu are actively used by the w11a developer. The -situation for other linux distributions is therefore just taken from -the respective web sites: +Only Debian and Ubuntu are actively used by the w11a developer. The situation +for other Linux distributions is therefore just taken from the respective web +sites {status October 2013}: - Suse For Suse 12.2 and 12.3 un-official ghdl packages are available, but they diff --git a/doc/README.txt b/doc/README.txt index c0e6f523..bf6b391c 100644 --- a/doc/README.txt +++ b/doc/README.txt @@ -1,4 +1,4 @@ -$Id: README.txt 614 2014-12-20 15:00:45Z mueller $ +$Id: README.txt 655 2015-03-04 20:35:21Z mueller $ Release notes for w11a @@ -21,6 +21,152 @@ Release notes for w11a 2. Change Log ---------------------------------------------------------------- +- trunk (2015-03-01: svn rev 29(oc) 655(wfjm); untagged w11a_V0.64) +++++++++ + + - Preface + - The w11 project started on a Spartan-3 based Digilent S3board, and soon + moved on to a Nexys2 with much better connectivity. Next step was the + Spartan-6 based Nexys3. Now is time to continue with 7-Series FPGAs. + - When Vivado started in 2013 it was immediately clear that the architecture + is far superior to ISE. But tests with the first versions were sobering, + the w11a design either didn't compile at all, or produced faulty synthesis + results. In 2014 Vivado matured, and the current version 2014.4 works + fine with the w11a code base. + - The original Nexys4 board allowed to quickly port Nexys3 version because + both have the same memory chip. The newer Nexys4 DDR will be addressed + later. + - The BRAM capacity of FPGAs increased significantly over time. The low + cost Basys3 board with the second smallest Artix-7 (XC7A35T) has 200 KB + BRAM. That allows to implement a purely BRAM based w11a system with + 176 kB memory. Not enough for 2.11BSD, but for many other less demanding + OS available for a PDP11. + - The Nexyx4 and Basys3 have 16 LEDs. Not quite the 'blinking lights' + console of the classic 11/45 and 11/70, but enough to display the + well known OS typical light patterns the veterans remember so well. + - With a new design tool, a new FPGA generation, two new boards, and a + new interface for the rlink connection that some of the code and tools + base had to be re-organized. + - Last but not least: finally access to a bit bigger disks: RL11 support + - Many changes, some known issues, some rough edges may still lurke around + + - Summary + - added support for Vivado + - added support for Nexys4 and Basys3 boards + - added RL11 disk support + - lots of documentation updated + + - New features + - new directory trees for + - rtl/bplib/basys3 - support for Digilent Basys3 board + - rtl/bplib/nexys4 - support for Digilent Nexys4 board + - rtl/make_viv - make includes for Vivado + - new files + - tools/bin/xviv_ghdl_unisim - ghdl compile Vivado UNISIM & UNIMACRO libs + - new modules + - rtl/ibus/ibdr_rl11 - ibus controller for RL11 + - rtl/vlib/rlink/ioleds_sp1c - io activity leds for rlink+serport_1clk + - rtl/vlib/xlib + - s7_cmt_sfs_gsim - Series-7 CMT: simple vhdl model + - s7_cmt_sfs_unisim - Series-7 CMT: wrapper for UNISIM + - rtl/w11a + - pdp11_bram_memctl - simple BRAM based memctl + - pdp11_dspmux - mux for hio display + - pdp11_ledmux - mux for hio leds + - pdp11_statleds - status led generator + - tools/src/librw11/ + - Rw11*RL11 - classes for RL11 disk handling + - tools/src/librwxxtpp + - RtclRw11*RL11 - tcl iface for RL11 disk handling + - new systems + - rtl/sys_gen/tst_rlink - rlink tester + - basys3/sys_tst_rlink_b3 - for Basys3 + - nexys4/sys_tst_rlink_n4 - for Nexys4 + - rtl/sys_gen/tst_serloop - serport loop tester + - nexys4/sys_tst_serloop_n4 - for Nexys4 + - rtl/sys_gen/tst_snhumanio - human I/O tester + - basys3/sys_tst_snhumanio_b3 - for Basys3 + - nexys4/sys_tst_snhumanio_n4 - for Nexys4 + - rtl/sys_gen/w11a - w11a + - basys3/sys_w11a_b3 - small BRAM only (176 kB memory) + - nexys4/sys_w11a_n4 - with full 4 MB memory using cram + - new oskits + - tools/oskit/211bsd_rl - new oskit for 2.11BSD on RL02 + - tools/oskit/rt11-53_rl - new oskit for RT11 V5.3 on RL02 + - tools/oskit/xxdp_rl - new oskit for XXDP 22 and 25 on RL02 + + - Changes + - renames + - ensure that old ISE and new Vivado co-exists, ensure telling names + - rtl/make -> make_ise + - rtl/bplib/bpgen/sn_4x7segctl -> sn_7segctl + - tools/bin/isemsg_filter -> xise_msg_filter + - tools/bin/xilinx_ghdl_unisim -> xise_ghdl_unisim + - tools/bin/xilinx_ghdl_simprim -> xise_ghdl_simprim + + - retired files + - rtl/bplib/fx2lib + - fx2_2fifoctl_as - obsolete, wasn't actively used since long + - tools/bin + - set_ftdi_lat - obsolete, since kernel 2.6.32 the default is 1 ms + - xilinx_vhdl_chop - obsolete, since ISE 11 sources come chopped + + - functional changes + - $RETROBASE/Makefile - re-structured, many new targets + - rtl/bplib/bpgen + - sn_7segctl - handle also 8 digit displays + - sn_humanio - configurable SWI and DSP width + - sn_humanio_rbus - configurable SWI and DSP width + - rtl/vlib/serport + - serport_1clock - export fractional part of divider + - rtl/ibus + - ibdr_maxisys - add RL11 (ibdr_rl11) + - rtl/sys_gen/w11a/* + - sys_w11a_* - use new led and dsp control modules + - tools/src/librlink + - RlinkConnect - drop LogOpts, indivitual getter/setter + - RlinkPortTerm - support custom baud rates (5M,6M,10M,12M) + - tools/src/librtcltools + - RtclGetList - add '?' (key list) and '*' (kv list) + - RtclSetList - add '?' (key list) + - RlogFile - Open(): now with cout/cerr support + - tools/src/librlinktpp + - RtclRlinkConnect - drop config cmd, use get/set cmd + - RtclRlinkPort - drop config cmd, use get/set cmd + - tools/src/librw11 + - Rw11Rdma - PreExecCB() with nwdone and nwnext + - Rw11UnitDisk - add Nwrd2Nblk() + - tools/src/librwxxtpp + - RtclRw11CntlFactory - add RL11 support + - tools/bin + - xise_ghdl_unisim - handle also UNIMACRO lib + - vbomconv - handle Vivado flows too + + - Bug fixes + - tools/src/librw11 + - Rw11CntlRK11 - revise RdmaPostExecCB() logic + + - Known issues + - V0.64-7: ghdl simulated OS boots via ti_w11 (-n4 ect options) fail due to + a flow control issue (likely since V0.63). + - V0.64-6: IO delays still unconstraint in vivado. All critical IOs use + explicitly IOB flops, thus timing well defined. + - V0.64-5: w11a_tb_guide.txt covers only ISE based tests (see also V0.64-4). + - V0.64-4: No support for the Vivado simulator (xsim) yet. With ghdl only + functional simulations, post synthesis (_ssim) fails to compile. + - V0.64-3: Highest baud rate with basys3 and nexys4 is 10 MBaud. 10 MBaud + is not supported according to FTDI, but works. 12 MBaud in next release. + - V0.64-2: rlink throughput on basys3/nexys4 limited by serial port stack + round trip times. Will be overcome by libusb based custom driver. + - V0.64-1: The large default transfer size for disk accesses leads to bad + throughput in the DL11 emulation for low speed links, like the + 460kBaud the S3board is limited too. Will be overcome by a DL11 + controller with more buffering. + - V0.62-2: rlink v4 error recovery not yet implemented, will crash on error + - V0.62-1: Command lists aren't split to fit in retransmit buffer size + {last two issues not relevant for w11 backend over USB usage because + the backend produces proper command lists and the USB channel is + usually error free} + - trunk (2015-01-04: svn rev 28(oc) 629(wfjm); untagged w11a_V0.63) +++++++++ - Summary @@ -214,5 +360,5 @@ Release notes for w11a - basic set of peripherals: kw11l, dl11, lp11, pc11, rk11/rk05 - just for fun: iist (not fully implemented and tested yet) - two complete system configurations with - - for a Digilent S3BOARD rtl/sys_gen/w11a/s3board/sys_w11a_s3 + - for a Digilent S3board rtl/sys_gen/w11a/s3board/sys_w11a_s3 - for a Digilent Nexys2 rtl/sys_gen/w11a/nexys2/sys_w11a_n2 diff --git a/doc/README_buildsystem_ISE.txt b/doc/README_buildsystem_ISE.txt new file mode 100644 index 00000000..fe728f3f --- /dev/null +++ b/doc/README_buildsystem_ISE.txt @@ -0,0 +1,235 @@ +# $Id: README_buildsystem_ISE.txt 651 2015-02-26 21:32:15Z mueller $ + +Guide to the Build System (Xilinx ISE Version) + + Table of content: + + 1. Concept + 2. Setup system environment + a. Setup environment variables + b. Compile UNISIM/UNIMACRO/SIMPRIM libraries for ghdl + 3. Building test benches + a. With ghdl + b. With ISE ISim + 4. Building systems + 5. Configuring FPGAs (via make flow) + 6. Configuring FPGAs (directly via config_wrapper) + 7. Note on Artix-7 based designs + +1. Concept ---------------------------------------------------------------- + + This projects uses GNU make to + - generate bit files (synthesis with xst and place&route with par) + - generate test benches (with ghdl or Xilinx ISim) + - configure the FPGA (with Xilinx Impact or Linux jtag) + + The Makefile's in general contain only a few definitions, all the make logic + is concentrated in a few master makefiles which are included. + + Simulation and synthesis tools usually need a list of the VHDL source + files, often in proper compilation order (libraries before components). + The different tools have different formats of these 'project files'. + + The build system employed in this project is based on manifest files called + 'vbom' or "VHDL bill of material" files + which list for each vhdl source file the libraries and sources for the + instantiated components, the later via their vbom, and last but not least + the name of the vhdl source file. + All file name are relative to the current directory. A recursive traversal + through all vbom's gives for each vhld module all sources needed to compile + it. The vbomconv script in tools/bin does this, and generates depending on + options + - make dependency files + - ISE xst project files (synthesis) + - ISE ISim project files (simulation) + - ghdl commands for analysis, inspection and make step + + The master make files contain pattern rules like + %.ngc : %.vbom -- synthesize with xst + % : %.vbom -- build functional model test bench + which encapsulate all the vbomconv magic + + A full w11a system is build from about 100 source files, test benches + from even more. Using the vbom's a large number of designs can be easily + maintained. + + For more details on vbomconv consult the man page. + +2. Setup system environment ----------------------------------------------- + +2a. Setup environment variables -------------------------------------- + + The build flows require the environment variables: + + - RETROBASE: must refer to the installation root directory + - XTWI_PATH: install path of the ISE version, without /ISE_DS/ ! + - RETRO_FX2_VID and RETRO_FX2_PID: default USB VID/PID for Cypress FX2 + + For general instructions on environment see INSTALL.txt . + For details on RETRO_FX2_VID and RETRO_FX2_PID see INSTALL_fx2.txt. + + Notes: + - The build system uses a small wrapper script called xtwi to encapsulate + the Xilinx environment. It uses XTWI_PATH to setup the ISE environment on + the fly. For details consult 'man xtwi'. + - don't run the ISE setup scripts ..../settings(32|64).sh in your working + shell. Setup only XTWI_PATH ! + +2b. Compile UNISIM/UNIMACRO/SIMPRIM libraries for ghdl --------------- + + A few entities use UNISIM or UNIMACRO primitives, and models derived after + the par step require also SIMPRIM primitives. In these cases ghdl has to + link against a compiled UNISIM, UNIMACRO or SIMPRIM libraries. + + To make handling of the parallel installation of several ISE versions + easy the compiled libraries are stored in sub-directories under $XILINX: + + $XILINX/ghdl/unisim + $XILINX/ghdl/unimacro + $XILINX/ghdl/simprim + + Two helper scripts will create these libraries: + + cd $RETROBASE + xise_ghdl_unisim # does UNISIM and UNIMACRO + xise_ghdl_simprim # does SIMPRIM + + Run these scripts for each ISE version which is installed. + +3. Building test benches -------------------------------------------------- + + The build flows support two simulators + - ghdl -> open source, with VHPI support, doesn't accept sdf files + - ISE ISim -> limited to 50k lines in WebPack, no VHPI support + +3a. With ghdl -------------------------------------------------------- + + To compile a ghdl based test bench named all is needed is + + make + + The make file will use .vbom, create all make dependency files, + and generate the needed ghdl commands. + + In many cases the test benches can also be compiled against the gate + level models derived after the xst, map or par step. To compile them + + make ghdl_tmp_clean + make _ssim # for post-xst + make _fsim # for post-map + make _tsim # for post-par + + The 'make ghdl_tmp_clean' is needed to flush the ghdl work area from + the compilation remains of earlier functional model compiles. + + Notes: + - the post-xst simulation (_ssim targets) proved to be a valuable tool. + - ghdl fails to read sdf files generated by Xilinx tools, and thus does + not support a post-par simulation with full timing. + - post-par simulations without timing annotation often fail, most likely + due to clocking and delta cycle issues due to inserted clock buffers. + +3b. With ISE ISim ---------------------------------------------------- + + To compile a ISE ISim based test bench named all is needed is + + make _ISim + + The make file will use .vbom, create all make dependency files, + and generate the needed ISE ISim project files and commands. + + In many cases the test benches can also be compiled against the gate + level models derived after the xst, map or par step. To compile them + + make ise_tmp_clean + make _ISim_ssim # for post-xst + make _ISim_fsim # for post-map + make _ISim_tsim # for post-par + + Notes: + - ISim in ISE WebPack is limited to about 50k lines source code. That is + enough for many functional simulations, a w11a system has about 27k lines, + the test bench adds another 3k lines. But the limit gets quickly exceeded + with post-xst and especially post-par models. If the limit is exceeded, the + simulation engine throttles to snails speed. + - ISim does not support VHPI (interfacing of external C routines to VHDL). + Since VHPI is used in the rlink simulation all system test benches with + an rlink interface, thus most, will only run with ghdl and not with ISim. + +4. Building systems ------------------------------------------------------- + + To generate a bit file for a system named all is needed is + + make .bit + + The make file will use .vbom, create all make dependency files, build + the ucf file with cpp, and run the synthesis flow (xst, ngdbuild, par, trce). + The log files will be conveniently renamed + + _xst.log # xst log file + _tra.log # translate (ngdbuild) log file (renamed %.bld) + _map.log # map log file (renamed %_map.mrp) + _par.log # par log file (renamed %.par) + _pad.log # pad file (renamed %_pad.txt) + _twr.log # trce log file (renamed %.twr) + _tsi.log # trce tsi file (renamed %.tsi) + _bgn.log # bitgen log file (renamed %.bgn) + + If only the xst or par output is wanted just use + + make .ngc + make .ncd + + Some tools require a .svf rather than a .bit file. It can be created with + + make .svf + + A simple 'message filter' system is also integrated into the make build flow. + For many (though not all) systems a .mfset file has been provided which + defines the xst,par and bitgen messages which are considered ok. To see + only the remaining message extracted from the various .log files simply + use the make target + + make .mfsum + + after a re-build. + +5. Configuring FPGAs (via make flow) -------------------------------------- + + The make flow supports also loading the bitstream into FPGAs, either + via Xilinx Impact, or via the Cypress FX2 USB controller is available. + + For Xilinx Impact a Xilinx USB Cable II has to be properly setup, than + simply use + + make .iconfig + + For using the Cypress FX2 USB controller on Digilent Nexys2, Nexys3 and + Atlys boards just connect the USB cable and + + make .jconfig + + This will automatically check and optionally re-load the FX2 firmware + to a version matching the FPGA design, generate a .svf file from the + .bit file, and configure the FPGA. In case the bit file is out-of-date + the whole design will be re-implemented before. + +6. Configuring FPGAs (directly via config_wrapper) ------------------------- + + The make flow described above uses two scripts + config_wrapper # must be used with xtwi ! + fx2load_wrapper + which can be used directly for loading available bit or svf files into + the FPGA. For detailed documentation see the respective man pages. + +7. Note on Artix-7 based designs ------------------------------------------ + + The development for Nexys4 started with ISE, but has now fully moved to + Vivado. The make files for the ISE build flows have been kept for comparison + are have the name Makefile.ise. So for some Nexys4 designs and associated + one can still start with a + + make -f Makefile.ise + + an ISE based build. To be used for tool comparisons, the ISE generated bit + files were never tested in an FPGA. diff --git a/doc/README_buildsystem_Vivado.txt b/doc/README_buildsystem_Vivado.txt new file mode 100644 index 00000000..9896e534 --- /dev/null +++ b/doc/README_buildsystem_Vivado.txt @@ -0,0 +1,190 @@ +# $Id: README_buildsystem_Vivado.txt 651 2015-02-26 21:32:15Z mueller $ + +Guide to the Build System (Xilinx Vivado Version) + + Table of content: + + 1. Concept + 2. Setup system environment + a. Setup environment variables + b. Compile UNISIM/UNIMACRO libraries for ghdl + 3. Building test benches + a. With ghdl + 4. Building systems + 5. Configuring FPGAs (via make flow) + 6. Note on ISE + +1. Concept ---------------------------------------------------------------- + + This projects uses GNU make to + - generate bit files (with Vivado synthesis) + - generate test benches (with ghdl or Vivado XSim) + - configure the FPGA (with Vivado hardware server) + + The Makefile's in general contain only a few definitions. By far most of + the build flow logic in Vivado is in tcl scripts, only a thin interface + layer is needed at the make level, which is concentrated in a few master + makefiles which are included. + + Simulation and synthesis tools usually need a list of the VHDL source + files, sometimes in proper compilation order (libraries before components). + The different tools have different formats of these 'project descriptions. + + The build system employed in this project is based on manifest files called + 'vbom' or "VHDL bill of material" files + which list for each vhdl source file the libraries and sources for the + instantiated components, the later via their vbom, and last but not least + the name of the vhdl source file. + All file name are relative to the current directory. A recursive traversal + through all vbom's gives for each vhld module all sources needed to compile + it. The vbomconv script in tools/bin does this, and generates depending on + options + - make dependency files + - Vivado synthesis setup files + - Vivado simulation setup files + - ghdl commands for analysis, inspection and make step + + The master make files contain pattern rules like + %.bit : %.vbom -- create bit file + % : %.vbom -- build functional model test bench + which encapsulate all the vbomconv magic + + A full w11a system is build from about 100 source files, test benches + from even more. Using the vbom's a large number of designs can be easily + maintained. + + For more details on vbomconv consult the man page. + +2. Setup system environment ----------------------------------------------- + +2a. Setup environment variables -------------------------------------- + + The build flows require the environment variables: + + - RETROBASE: must refer to the installation root directory + - XTWV_PATH: install path of the Vivado version + + For general instructions on environment see INSTALL.txt . + + Notes: + - The build system uses a small wrapper script called xtwv to encapsulate + the Xilinx environment. It uses XTWV_PATH to setup the Vivado environment + on the fly. For details consult 'man xtwv'. + - don't run the Vivado setup scripts ..../settings(32|64).sh in your working + shell. Setup only XTWV_PATH ! + +2b. Compile UNISIM/UNIMACRO libraries for ghdl ----------------------- + + A few entities use UNISIM or UNIMACRO primitives, and post synthesis models + require also UNISIM primitives. In these cases ghdl has to link against a + compiled UNISIM or UNIMACRO libraries. + + To make handling of the parallel installation of several Vivado versions + easy the compiled libraries are stored in sub-directories under $XTWV_PATH: + + $XTWV_PATH/ghdl/unisim + $XTWV_PATH/ghdl/unimacro + + A helper scripts will create these libraries: + + cd $RETROBASE + xviv_ghdl_unisim # does UNISIM and UNIMACRO + + Run these scripts for each Vivado version which is installed. + + Notes: + - Vivado supports SIMPRIM libraries only in Verilog form, there is no vhdl + version anymore. + - ghdl can therefore not be used to do timing simulations with Vivado. + However: under ISE SIMPRIM was available in vhdl, but ghdl did never accept + the sdf files, making ghdl timing simulations impossible under ISE too. + +3. Building test benches -------------------------------------------------- + + The build flows currently supports only ghdl. + Support for the Vivado simulator XSim will be added in a future release. + +3a. With ghdl -------------------------------------------------------- + + To compile a ghdl based test bench named all is needed is + + make + + The make file will use .vbom, create all make dependency files, + and generate the needed ghdl commands. + + In some cases the test benches can also be compiled against the gate + level models derived after the synthesis or optimize step. To compile them + + make ghdl_tmp_clean + make _ssim # for post synthesis {see Notes} + make _osim # for post optimize {see Notes} + + The 'make ghdl_tmp_clean' is needed to flush the ghdl work area from + the compilation remains of earlier functional model compiles. + + Notes: + - post synthesis or optimize models currently very often fail to compile + in ghdl due to a bug in the ghdl code generator. + +4. Building systems ------------------------------------------------------- + + To generate a bit file for a system named all is needed is + + make .bit + + The make file will use .vbom, create all make dependency files and + starts Vivado in batch mode with the proper scripts which will handle the + build steps. The log files and reports are conveniently renamed + + _syn.log # synthesis log (from runme.log) + _imp.log # implementation log (from runme.log) + _bit.log # write_bitstream log (from runme.log) + + _syn_util.rpt # (from _utilization_synth.rpt) + _opt_drc.rpt # (from _opt_drc.rpt) + _pla_io.rpt # (from _io_placed.rpt) + _pla_clk.rpt # (from _clock_utilization_placed.rpt) + _pla_util.rpt # (from _utilization_placed.rpt) + _pla_cset.rpt # (from _control_sets_placed.rpt) + _rou_sta.rpt # (from _route_status.rpt) + _rou_drc.rpt # (from _drc_routed.rpt) + _rou_tim.rpt # (from _timing_summary_routed.rpt) + _rou_pwr.rpt # (from _power_routed.rpt) + _rou_util.rpt # (extra report_utilization) + _rou_util_h.rpt # (extra report_utilization -hierarchical) + _ds.rpt # (extra report_datasheet) + + The design check points are also kept + + _syn.dcp # (from .dcp) + _opt.dcp # (from _opt.dcp) + _pla.dcp # (from _placed.dcp) + _rou.dcp # (from _routed.dcp) + + If only the post synthesis, optimize or route design checkpoints are wanted + + make _syn.dcp + make _opt.dcp + make _rou.dcp + +5. Configuring FPGAs ------------------------------------------------------ + + The make flow supports also loading the bitstream into FPGAs via the + Vivado hardware server. Simply use + + make .vconfig + + Note: works with Basys3 and Nexys4, only one board must connected. + +6. Note on ISE ------------------------------------------------------------ + + The development for Nexys4 started with ISE, but has now fully moved to + Vivado. The make files for the ISE build flows have been kept for comparison + are have the name Makefile.ise. So for some Nexys4 designs and associated + one can still start with a + + make -f Makefile.ise + + an ISE based build. To be used for tool comparisons, the ISE generated bit + files were never tested in an FPGA. diff --git a/doc/man/man1/config_wrapper.1 b/doc/man/man1/config_wrapper.1 index e6a8fffb..b1e82f0e 100644 --- a/doc/man/man1/config_wrapper.1 +++ b/doc/man/man1/config_wrapper.1 @@ -1,5 +1,5 @@ .\" -*- nroff -*- -.\" $Id: config_wrapper.1 580 2014-08-10 15:47:10Z mueller $ +.\" $Id: config_wrapper.1 651 2015-02-26 21:32:15Z mueller $ .\" .\" Copyright 2013- by Walter F.J. Mueller .\" @@ -116,6 +116,9 @@ Cypress FX2 USB controller emulating an Altera USB-Blaster cable. Path to current XILINX ISE installation. Required by all sub commands, mainly to locate the \fI.bsdl\fP files which describe the JTAG commands of all devices in the JTAG chain. +.br +Best is to use \fBconfig_wrapper\fP with the \fBxtwi\fP(1) wrapper, this will +automatically define this environment variable. . .\" ------------------------------------------------------------------ .SH EXAMPLES @@ -131,7 +134,8 @@ Configures a Nexys3 board with \fItest.svf\fP using \fBjtag\fP(1). .\" ------------------------------------------------------------------ .SH "SEE ALSO" .BR jtag (1), -.BR fx2load_wrapper (1) +.BR fx2load_wrapper (1), +.BR xtwi (1) .\" ------------------------------------------------------------------ .SH AUTHOR diff --git a/doc/man/man1/set_ftdi_lat.1 b/doc/man/man1/set_ftdi_lat.1 deleted file mode 100644 index 524ce22f..00000000 --- a/doc/man/man1/set_ftdi_lat.1 +++ /dev/null @@ -1,67 +0,0 @@ -.\" -*- nroff -*- -.\" $Id: set_ftdi_lat.1 547 2013-12-29 13:10:07Z mueller $ -.\" -.\" Copyright 2010-2013 by Walter F.J. Mueller -.\" -.\" ------------------------------------------------------------------ -. -.TH SET_FTDI_LAT 1 2013-12-26 "Retro Project" "Retro Project Manual" -.\" ------------------------------------------------------------------ -.SH NAME -set_ftdi_lat \- set latency timer in FTDI USB UART or FIFO -.\" ------------------------------------------------------------------ -.SH SYNOPSIS -. -.SY set_ftdi_lat -.RI [ dev ] -.RI [ time ] -.YS -. -.\" ------------------------------------------------------------------ -.SH DESCRIPTION -\fBNote:\fP command is obsolete when kernel 2.6.32 or newer is used. -See NOTES section. -. -.PP -FTDI USB UART or FIFO adapters of type FT232, FT245, and other similar -models have a latency timer which controls the maximal time between reception -of a byte by the UART or FIFO and the emission of a USB frame. The default -is 16 msec on kernels prior to 2.6.32 and can lead to unsatisfactory -response times. -The -.B set_ftdi_lat -script allows to set this latency timer via a node in the \fI/sys\fP -virtual file system, specifically -.IP "" 4 -.I /sys/bus/usb-serial/devices/ttyUSBn/latency_timer -. -.PP -The first optional argument \fIdev\fP allows to specify the device name -in the form \fIUSBn\fP with the default \fIUSB0\fP. The second optional -argument \fItime\fP allows to specify the new value of the latency timer, -given in msec. Default is 1 msec. -. -.\" ------------------------------------------------------------------ -.SH EXIT STATUS -If device tty\fIdev\fP is not found or the entry in \fI/sys\fP is not -writable an exit status 1 is returned. - -.\" ------------------------------------------------------------------ -.SH EXAMPLES -In general the command is given via \fBsudo\fP(8) like - -.EX - sudo set_ftdi_lat USB0 1 -.EE -.\" ------------------------------------------------------------------ -.SH "SEE ALSO" -.BR sudo (8) -. -.\" ------------------------------------------------------------------ -.SH NOTES -For linux kernel 2.6.32 or newer the default is 1 ms already. On all -up-to-date systems therefore no need to use this command. -. -.\" ------------------------------------------------------------------ -.SH AUTHOR -Walter F.J. Mueller diff --git a/doc/man/man1/ti_rri.1 b/doc/man/man1/ti_rri.1 index d7f9656b..2fd25280 100644 --- a/doc/man/man1/ti_rri.1 +++ b/doc/man/man1/ti_rri.1 @@ -1,11 +1,11 @@ .\" -*- nroff -*- -.\" $Id: ti_rri.1 558 2014-06-01 22:20:51Z mueller $ +.\" $Id: ti_rri.1 653 2015-03-01 12:53:01Z mueller $ .\" -.\" Copyright 2013- by Walter F.J. Mueller +.\" Copyright 2013-2015 by Walter F.J. Mueller .\" .\" ------------------------------------------------------------------ . -.TH TI_RRI 1 2013-05-20 "Retro Project" "Retro Project Manual" +.TH TI_RRI 1 2015-01-28 "Retro Project" "Retro Project Manual" .\" ------------------------------------------------------------------ .SH NAME ti_rri \- \fBRlink\fP Backend Server @@ -103,7 +103,10 @@ serial port baud rate, default is '115k'. Allowed baud rate settings are: 460800, 460k, 500000, 500k, 921600, 921k, 1000000, 1000k, 1M, 1500000, 1500k, 2000000, 2000k, 2M, 2500000, 2500k, -3000000, 3000k, 3M, 4000000, 4000k, 4M +3000000, 3000k, 3M, 4000000, 4000k, 4M, +5000000, 5000k, 5M, 6000000, 6000k, 6M, +1000000, 10000k, 10M, 12000000, 12000k, 12M + .PD .RE .IP \fBopts\fP @@ -197,6 +200,10 @@ with eval. . .\" ------------------------------------------------------------------ .SH EXAMPLES +.IP "\fBti_rri --fifo --run='tbw tb_tst_rlink_n3'" 4 +Starts the \fBghdl\fP(1) test bench 'tb_tst_rlink_n3' located in CWD via +\fBtbw\fP(1). It is assumed that the local \fItbw.dat\fP file configures +fifo communication for the test bench. .\" ------------------------------------------------------------------ .SH "SEE ALSO" diff --git a/doc/man/man1/ti_w11.1 b/doc/man/man1/ti_w11.1 index 588998dc..6e5a2869 100644 --- a/doc/man/man1/ti_w11.1 +++ b/doc/man/man1/ti_w11.1 @@ -1,11 +1,11 @@ .\" -*- nroff -*- -.\" $Id: ti_w11.1 620 2014-12-25 10:48:35Z mueller $ +.\" $Id: ti_w11.1 654 2015-03-01 18:45:38Z mueller $ .\" -.\" Copyright 2013- by Walter F.J. Mueller +.\" Copyright 2013-2015 by Walter F.J. Mueller .\" .\" ------------------------------------------------------------------ . -.TH TI_W11 1 2013-05-20 "Retro Project" "Retro Project Manual" +.TH TI_W11 1 2015-02-22 "Retro Project" "Retro Project Manual" .\" ------------------------------------------------------------------ .SH NAME ti_w11 \- Quick starter for \fBti_rri\fP with \fBw11\fP CPU designs @@ -49,12 +49,18 @@ use /dev/ttyUSB* (* is device number \fIN\fP) .RE . .SS "setup options for ghdl simulation runs" -.IP \fB-s3\fP -start \fItb_w11a_s3\fP simulation (w11a on S3BOARD) -.IP \fB-n2\fP -start \fItb_w11a_n2\fP simulation (w11a on Nexys2 board) +.PD 0 +.IP \fB-b3\fP +start \fItb_w11a_b3\fP simulation (w11a on Basys3 board) +.IP \fB-n4\fP +start \fItb_w11a_n4\fP simulation (w11a on Nexys4 board) .IP \fB-n3\fP start \fItb_w11a_n3\fP simulation (w11a on Nexys3 board) +.IP \fB-n2\fP +start \fItb_w11a_n2\fP simulation (w11a on Nexys2 board) +.IP \fB-s3\fP +start \fItb_w11a_s3\fP simulation (w11a on S3board) +.PD . .SS "common options" .IP \fB-e "\fR=\fIfile"\fR @@ -65,9 +71,18 @@ it is assumed that they are in \fBlda\fP(5) format. .\" ------------------------------------------------------------------ .SH EXAMPLES .IP "\fBti_w11 -u @211bsd_rk_boot.tcl\fR" 4 -Assumes a FPGA board, with a \fBw11\fP CPU design already configured, -is connected via USB. \fBti_rri\fP(1) will be started and the given -boot script executed. +Assumes a FPGA board with a \fBw11\fP CPU design already configured. +Connected via USB, communication via Cypress FX2. +\fBti_rri\fP(1) will be started and the given boot script executed. +Typical way to start Nexys2 and Nexys3 boards. + +.IP "\fBti_w11 -tu2,10M,break,cts @211bsd_rl_boot.tcl\fR" 4 +Assumes a FPGA board with a \fBw11\fP CPU design already configured. +Connected via USB, communication via an USB UART. In this case the +device \fI/dev/ttyUSB2\fP will be used, with \fI10 MBaud\fP, \fIbreak\fP to +trigger auto-bauding, and \fIcts\fP to use hardware handshake. +\fBti_rri\fP(1) will be started and the given boot script executed. +Typical way to start Nexys4 boards. .IP "\fBti_w11 -n3 -e $RETROBASE/tools/asm-11/w11/sys/dl11/simple_out.mac\fR" Will start the \fItb_w11a_n3\fP test bench in \fBghdl\fP(1), on the fly diff --git a/doc/man/man1/vbomconv.1 b/doc/man/man1/vbomconv.1 index 27b7286a..40ec6dee 100644 --- a/doc/man/man1/vbomconv.1 +++ b/doc/man/man1/vbomconv.1 @@ -1,12 +1,12 @@ .\" -*- nroff -*- -.\" $Id: vbomconv.1 558 2014-06-01 22:20:51Z mueller $ +.\" $Id: vbomconv.1 646 2015-02-15 12:04:55Z mueller $ .\" -.\" Copyright 2010-2013 by Walter F.J. Mueller +.\" Copyright 2010-2015 by Walter F.J. Mueller .\" .\" .\" ------------------------------------------------------------------ . -.TH VBOMCONV 1 2013-10-20 "Retro Project" "Retro Project Manual" +.TH VBOMCONV 1 2015-02-15 "Retro Project" "Retro Project Manual" .\" ------------------------------------------------------------------ .SH NAME vbomconv \- generate files and actions from vbom manifest files @@ -18,25 +18,19 @@ vbomconv \- generate files and actions from vbom manifest files . .SY vbomconv .OP \-\-trace -.B \-\-dep_xst -| .B \-\-dep_ghdl +.I vbom +. +.SY vbomconv +.OP \-\-trace +.B \-\-dep_xst | .B \-\-dep_isim .I vbom . .SY vbomconv .OP \-\-trace -.B \-\-xst_prj -| -.B \-\-isim_prj -.I vbom -. -.SY vbomconv -.OP \-\-trace -.B \-\-ghdl_a_cmd -| -.B \-\-ghdl_a +.B \-\-dep_vsyn .I vbom . .SY vbomconv @@ -48,6 +42,15 @@ vbomconv \- generate files and actions from vbom manifest files . .SY vbomconv .OP \-\-trace +.OP \-\-xlpath=\fIpath\fP +.B \-\-ghdl_a_cmd +| +.B \-\-ghdl_a +.I vbom +. +.SY vbomconv +.OP \-\-trace +.OP \-\-xlpath=\fIpath\fP .B \-\-ghdl_m_cmd | .B \-\-ghdl_m @@ -55,18 +58,30 @@ vbomconv \- generate files and actions from vbom manifest files . .SY vbomconv .OP \-\-trace -.BI \-\-xst_export "\fR=\fPpath" -| .BI \-\-ghdl_export "\fR=\fPpath" .I vbom . .SY vbomconv .OP \-\-trace +.B \-\-xst_prj +| +.B \-\-isim_prj +.I vbom +. +.SY vbomconv +.OP \-\-trace +.BI \-\-xst_export "\fR=\fPpath" +| .BI \-\-isim_export "\fR=\fPpath" .I vbom . .SY vbomconv .OP \-\-trace +.B \-\-vsyn_prj +.I vbom +. +.SY vbomconv +.OP \-\-trace .B \-\-get_top .I vbom . @@ -96,17 +111,19 @@ and top level design last. The \fBvbomconv\fP tool does this traversal of \fBvbom\fP files and generates, depending on command line options, the files and/or commands needed to run a synthesis tool or to build a simulation model. -Currently supported is synthesis with ISE \fBxst\fP and simulation with -\fBghdl\fP(1) or ISE \fBISim\fP. +Currently supported is synthesis with Xilinx ISE \fBxst\fP Xilinx Vivado +and simulation with \fBghdl\fP(1) or Xilinx ISE \fBISim\fP. \fBvbomconv\fP therefore currently generates .PD 0 -.IP "\fB- xst\fP" 8 -project files .IP "\fB- ghdl\fP" 8 commands for analysis, inspection and make step +.IP "\fB- xst\fP" 8 +project files .IP "\fB- ISim\fP" 8 project files +.IP "\fB- vsyn\fP" 8 +project setups for Vivado synthesis .IP "\fB- make\fP" 8 dependency files .PD @@ -183,7 +200,8 @@ stem of the \fIvbom\fP file name. . .IP "\fB@lib\fP:\fIname\fP" allows to specify additional system libraries. Currently used to indicate -that the \fIunisim\fP or \fIsimprim\fP libraries are needed by \fBghdl\fP. +that the \fIunisim\fP, \fIunimacro\fP or \fIsimprim\fP libraries are +needed by \fBghdl\fP. . .IP "\fB@ucf_cpp\fP:\fIfile\fP" indicates that a \fIfile\fP.ucf file is to be generated by \fBcpp\fP(1) @@ -213,6 +231,17 @@ of the vbom file traversal and processing, the process of source file ranking to determine the compilation order, and of the final internal file list and property table. . +.\" ---------------------------------------------- +.TP +.BI \-\-xlpath \fR=\fPpath +Defines the location where the \fBghdl\fP compiled Xilinx unisim, unimacro +or simprim libraries are located. This option is mandatory for +\fB\-\-ghdl_a\fP and \fB\-\-ghdl_m\fP commands when the design contains +a \fB@lib\fP directive. +These compiled libs are typically created with the +\fBxise_ghdl_unisim\fP(1) or \fBxise_ghdl_simprim\fP(1) commands. +. +.\" -------------------------------------------------------- .SH ACTIONS .P .\" ---------------------------------------------- @@ -222,16 +251,26 @@ one not requiring a \fIvbom\fP file. . .\" ---------------------------------------------- .TP -.B \-\-dep_xst -.TQ .B \-\-dep_ghdl .TQ +.B \-\-dep_xst +.TQ .B \-\-dep_isim -These three actions write to \fIstdout\fP dependency rules for inclusion in +.TQ +.B \-\-dep_vsyn +These four actions write to \fIstdout\fP dependency rules for inclusion in \fIMakefile\fPs. Together with an appropruate pattern rule they allow to automatitize the dependency handling, see the EXAMPLES section for practical usage. +\fB\-\-dep_ghdl\fP creates the dependencies for \fBghdl\fP +based simulation models and produces the following types of dependencies +.EX + \fI\fP : \fI\fP.dep_ghdl + \fI\fP : \fB*\fP.vhd + \fI\fP.dep_ghdl : \fB*\fP.vbom +.EE + \fB\-\-dep_xst\fP creates the dependencies for \fBxst\fP synthesis make flows and produces the following types of dependencies .EX @@ -258,14 +297,6 @@ for example sed 's/\.o:/\.ucf:/' > $*.dep_ucf_cpp .EE -\fB\-\-dep_ghdl\fP creates the dependencies for \fBghdl\fP -based simulation models and produces the following types of dependencies -.EX - \fI\fP : \fI\fP.dep_ghdl - \fI\fP : \fB*\fP.vhd - \fI\fP.dep_ghdl : \fB*\fP.vbom -.EE - \fB\-\-dep_isim\fP creates the dependencies for ISE \fBISim\fP based simulation models and produces the following types of dependencies .EX @@ -273,26 +304,16 @@ based simulation models and produces the following types of dependencies \fI\fP_ISim : \fB*\fP.vhd \fI\fP.dep_isim : \fB*\fP.vbom .EE -. -.\" ---------------------------------------------- -.TP -.B \-\-xst_prj -.TQ -.B \-\-isim_prj -These two actions write to \fIstdout\fP a project file suitable for ISE -\fBxst\fP or \fBISim\fP, respectively. -The vhdl source files are in proper compilation order. See -the EXAMPLES section for practical usage in a make flow. -. -.\" ---------------------------------------------- -.TP -.B \-\-ghdl_a_cmd -.TQ -.B \-\-ghdl_a -The \fB\-\-ghdl_a_cmd\fP action writes to \fIstdout\fP a list of -\fB"ghdl -a"\fP commands for the \fBghdl\fP analysis step. -The commands are in proper compilation order. The \fB\-\-ghdl_a\fP -action immediately executes these commands via \fBexec\fP(3). + +\fB\-\-dep_vsyn\fP creates the dependencies for Vivado synthesis make flows +and produces the following types of dependencies +.EX + \fI\fP.bit : \fI\fP.dep_vsyn + \fI\fP.bit : \fB*\fP.vhd \fB*\fP.xdc + \fI\fP_syn.dcp : \fB*\fP.vhd \fB*\fP.xdc + \fI\fP_rou.dcp : \fB*\fP.vhd \fB*\fP.xdc + \fI\fP.dep_vsyn : \fB*\fP.vbom +.EE . .\" ---------------------------------------------- .TP @@ -306,6 +327,16 @@ action immediately executes this command via \fBexec\fP(3). . .\" ---------------------------------------------- .TP +.B \-\-ghdl_a_cmd +.TQ +.B \-\-ghdl_a +The \fB\-\-ghdl_a_cmd\fP action writes to \fIstdout\fP a list of +\fB"ghdl -a"\fP commands for the \fBghdl\fP analysis step. +The commands are in proper compilation order. The \fB\-\-ghdl_a\fP +action immediately executes these commands via \fBexec\fP(3). +. +.\" ---------------------------------------------- +.TP .B \-\-ghdl_m_cmd .TQ .B \-\-ghdl_m @@ -317,6 +348,24 @@ The \fB\-\-ghdl_m\fP action immediately executes this command via . .\" ---------------------------------------------- .TP +.B \-\-xst_prj +.TQ +.B \-\-isim_prj +These two actions write to \fIstdout\fP a project file suitable for ISE +\fBxst\fP or \fBISim\fP, respectively. +The vhdl source files are in proper compilation order. See +the EXAMPLES section for practical usage in a make flow. +. +.\" ---------------------------------------------- +.TP +.B \-\-vsym_prj +This action write to \fIstdout\fP a Tcl script suitable as project definition +for Vivado synthesis. This script is source'ed or eval'ed and defines the +source fileset and the constraints fileset. The vhdl source files are in +proper compilation order. +. +.\" ---------------------------------------------- +.TP .BI \-\-xst_export \fR=\fPpath .TQ .BI \-\-ghdl_export \fR=\fPpath @@ -388,7 +437,7 @@ of the GNU \fBmake\fP(1) \fIinclude\fP directive to fully automatize the proper generation of dependencies. Just add to the \fIMakefile\fP a pattern rule to create the dependency rule files from the \fBvbom\fP -files and include them. In case they don't yet exists or are out of date +files and include them. In case they don't yet exist or are out of date \fBmake\fP(1) will (re-)create them and restart. Example for using \fB\-\-dep_xst\fP in a \fIMakefile\fP : .PP @@ -461,8 +510,8 @@ output like in .BR xtwi (1), .BR cpp (1), .br -.BR xilinx_ghdl_simprim (1), -.BR xilinx_ghdl_unisim (1) +.BR xise_ghdl_simprim (1), +.BR xise_ghdl_unisim (1) . .\" ------------------------------------------------------------------ .SH AUTHOR diff --git a/doc/man/man1/xilinx_ghdl_unisim.1 b/doc/man/man1/xilinx_ghdl_unisim.1 deleted file mode 100644 index 8e396c0d..00000000 --- a/doc/man/man1/xilinx_ghdl_unisim.1 +++ /dev/null @@ -1,67 +0,0 @@ -.\" -*- nroff -*- -.\" $Id: xilinx_ghdl_unisim.1 522 2013-05-24 17:50:29Z mueller $ -.\" -.\" Copyright 2010- by Walter F.J. Mueller -.\" -.\" ------------------------------------------------------------------ -. -.TH XILINX_GHDL_UNISIM 1 2010-07-25 "Retro Project" "Retro Project Manual" -.\" ------------------------------------------------------------------ -.SH NAME -xilinx_ghdl_unisim \- compile Xilinx ISE UNISIM libraries for ghdl -.\" ------------------------------------------------------------------ -.SH SYNOPSIS -. -.B xilinx_ghdl_unisim -. -.\" ------------------------------------------------------------------ -.SH DESCRIPTION -\fBxilinx_ghdl_unisim\fP compiles the Xilinx ISE/WebPack UNISIM libraries for -\fBghdl\fP. The object files generated by \fBghdl\fP -are stored in the directory tree of the currently active version of -ISE/WebPack under \fI$XILINX/ghdl/unisim\fP. -This is convenient when several ISE/WebPack versions are installed in -parallel, the \fB$XILINX\fP -environment variable is enough to setup the context for the synthesis -flows as well as for build of \fBghdl\fP models. Just use the -\fBghdl\fP option - -.EX - -P${XILINX}/ghdl/unisim -.EE - -to link to the UNISIM library. - -Up to ISE 10 the VITAL models were all concatinated in one large file -\fIunisim_VITAL.vhd\fP. In this case the \fBxilinx_vhdl_chop\fP -helper script will create individual source files for each model. -For ISE 11 and later the modules are shipped as separate files. - -The XILINX source code has since many releases some buggy statements with -self-referencial initializations. They seem to be tolerated by the commercial -tools but not by \fBghdl\fP. -The \fBxilinx_vhdl_memcolltype_fix\fP -helper script simply removes them, no further problems seen so far. - -.\" ------------------------------------------------------------------ -.SH ENVIRONMENT VARIABLES -.IP \fBXILINX\fP -points to the root of the currently active ISE/WebPack installation. -. -.\" ------------------------------------------------------------------ -.SH FILES -.IP \fI$XILINX/vhdl/src/unisims\fP -The vhdl sources for the UNISIM library are looked for in this directory tree. -.IP \fI$XILINX/ghdl/unisim\fP -The created object files will be written into this directory. The directory -is created if not yet existing. Note that the \fI$XILINX\fP -directory must be writable for the script. -. -.\" ------------------------------------------------------------------ -.SH "SEE ALSO" -.BR ghdl (1), -.BR xilinx_ghdl_simprim (1) -. -.\" ------------------------------------------------------------------ -.SH AUTHOR -Walter F.J. Mueller diff --git a/doc/man/man1/xilinx_ghdl_simprim.1 b/doc/man/man1/xise_ghdl_simprim.1 similarity index 65% rename from doc/man/man1/xilinx_ghdl_simprim.1 rename to doc/man/man1/xise_ghdl_simprim.1 index aecb58cf..2d81e46f 100644 --- a/doc/man/man1/xilinx_ghdl_simprim.1 +++ b/doc/man/man1/xise_ghdl_simprim.1 @@ -1,34 +1,35 @@ .\" -*- nroff -*- -.\" $Id: xilinx_ghdl_simprim.1 522 2013-05-24 17:50:29Z mueller $ +.\" $Id: xise_ghdl_simprim.1 639 2015-01-30 18:12:19Z mueller $ .\" -.\" Copyright 2010- by Walter F.J. Mueller +.\" Copyright 2010-2015 by Walter F.J. Mueller .\" .\" ------------------------------------------------------------------ . -.TH XILINX_GHDL_SIMPRIM 1 2010-07-25 "Retro Project" "Retro Project Manual" +.TH XISE_GHDL_SIMPRIM 1 2015-01-29 "Retro Project" "Retro Project Manual" .\" ------------------------------------------------------------------ .SH NAME -xilinx_ghdl_simprim \- compile Xilinx ISE SIMPRIM libraries for ghdl +xise_ghdl_simprim \- compile Xilinx ISE SIMPRIM libraries for ghdl .\" ------------------------------------------------------------------ .SH SYNOPSIS . -.B xilinx_ghdl_simprim +.B xise_ghdl_simprim . .\" ------------------------------------------------------------------ .SH DESCRIPTION -\fBxilinx_ghdl_simprim\fP compiles the Xilinx ISE/WebPack SIMPRIM libraries +\fBxise_ghdl_simprim\fP compiles the Xilinx ISE/WebPack SIMPRIM libraries for \fBghdl\fP. The object files generated by \fBghdl\fP are stored in the directory tree of the currently active version of ISE/WebPack under \fI$XILINX/ghdl/simprim\fP. -This is convenient when several ISE/WebPack versions are installed in -parallel, the \fB$XILINX\fP -environment variable is enough to setup the context for the synthesis -flows as well as for build of \fBghdl\fP models. Just use the \fBghdl\fP -option + +Since direct calls to ISE tools are in general encapsulated with \fBxtwi\fP(1) +the \fI$XTWI_PATH\fP is used instead of \fI$XILINX\fP. +This allows to use this script and \fBghdl\fP without a \fBxtwi\fP wrapper. + +Just use the \fBghdl\fP option .EX - -P${XILINX}/ghdl/simprim + -P${XWTI_PATH}/ISE_DE/ISE/ghdl/unisim .EE to link to the SIMPRIM library. @@ -39,7 +40,7 @@ In this case the \fBxilinx_vhdl_chop\fP helper script will create individual source files for each model. For ISE 11 and later the modules are shipped as separate files. -The XILINX source code has since many releases some buggy statements with +The Xilinx source code has since many releases some buggy statements with self-referencial initializations. They seem to be tolerated by the commercial tools but not by \fBghdl\fP. The \fBxilinx_vhdl_memcolltype_fix\fP @@ -47,21 +48,21 @@ helper script simply removes them, no further problems seen so far. .\" ------------------------------------------------------------------ .SH ENVIRONMENT VARIABLES -.TP -.B XILINX +.IP \fBXTWI_PATH\fP points to the root of the currently active ISE/WebPack installation. . .\" ------------------------------------------------------------------ .SH FILES -.IP \fI$XILINX/vhdl/src/simprims\fP +.IP \fI$XTWI_PATH/ISE_DS/ISE/vhdl/src/simprims\fP The vhdl sources for the SIMPRIM library are looked for in this directory tree. -.IP \fI$XILINX/ghdl/simprim\fP +.IP \fI$XTWI_PATH/ISE_DS/ISE/ghdl/simprim\fP The created object files will be written into this directory. The directory -is created if not yet existing. Note that the \fI$XILINX\fP +is created if not yet existing. Note that the \fI$XTWI_PATH\fP directory must be writable for the script. . .\" ------------------------------------------------------------------ .SH "SEE ALSO" +.BR xtwi (1), .BR ghdl (1), .BR xilinx_ghdl_unisim (1) . diff --git a/doc/man/man1/xise_ghdl_unisim.1 b/doc/man/man1/xise_ghdl_unisim.1 new file mode 100644 index 00000000..60599628 --- /dev/null +++ b/doc/man/man1/xise_ghdl_unisim.1 @@ -0,0 +1,68 @@ +.\" -*- nroff -*- +.\" $Id: xise_ghdl_unisim.1 642 2015-02-06 18:53:12Z mueller $ +.\" +.\" Copyright 2010-2015 by Walter F.J. Mueller +.\" +.\" ------------------------------------------------------------------ +. +.TH XISE_GHDL_UNISIM 1 2015-02-04 "Retro Project" "Retro Project Manual" +.\" ------------------------------------------------------------------ +.SH NAME +xise_ghdl_unisim \- compile Xilinx ISE UNISIM and UNIMACRO libraries for ghdl +.\" ------------------------------------------------------------------ +.SH SYNOPSIS +. +.B xise_ghdl_unisim +. +.\" ------------------------------------------------------------------ +.SH DESCRIPTION +\fBxise_ghdl_unisim\fP compiles the Xilinx ISE UNISIM and UNIMACRO +libraries for \fBghdl\fP. The object files generated by \fBghdl\fP +are stored in the directory tree of the currently active version of +ISE under \fI$XILINX/ghdl/unisim\fP and \fI$XILINX/ghdl/unimacro\fP. + +Since direct calls to ISE tools are in general encapsulated with \fBxtwi\fP(1) +the \fI$XTWI_PATH\fP is used instead of \fI$XILINX\fP. +This allows to use this script and \fBghdl\fP without a \fBxtwi\fP wrapper. + +Just use the \fBghdl\fP option + +.EX + -P${XWTI_PATH}/ISE_DE/ISE/ghdl/unisim + -P${XWTI_PATH}/ISE_DE/ISE/ghdl/unimacro +.EE + +to link to the UNISIM or UNIMACRO library. + +The Xilinx source code has since many releases some buggy statements with +self-referencial initializations. They seem to be tolerated by the commercial +tools but not by \fBghdl\fP. +The \fBxilinx_vhdl_memcolltype_fix\fP +helper script simply removes them, no further problems seen so far. + +.\" ------------------------------------------------------------------ +.SH ENVIRONMENT VARIABLES +.IP \fBXTWI_PATH\fP +points to the root of the currently active ISE installation. +. +.\" ------------------------------------------------------------------ +.SH FILES +.IP \fI$XTWI_PATH/ISE_DS/ISE/vhdl/src/unisims\fP +The vhdl sources for the Xilinx ISE UNISIM library +.IP \fI$XTWI_PATH/ISE_DS/ISE/vhdl/src/unimacro\fP +The vhdl sources for the Xilinx ISE UNIMACRO library +.IP \fI$XTWI_PATH/ISE_DS/ISE/ghdl\fP +The created object files will be written into this directory. The directory +is created if not yet existing. Note that the \fI$XTWI_PATH\fP +directory must be writable for the script. +. +.\" ------------------------------------------------------------------ +.SH "SEE ALSO" +.BR xtwi (1), +.BR ghdl (1), +.BR xise_ghdl_simprim (1), +.BR xviv_ghdl_unisim (1) +. +.\" ------------------------------------------------------------------ +.SH AUTHOR +Walter F.J. Mueller diff --git a/doc/man/man1/isemsg_filter.1 b/doc/man/man1/xise_msg_filter.1 similarity index 81% rename from doc/man/man1/isemsg_filter.1 rename to doc/man/man1/xise_msg_filter.1 index a174e39e..1c1a8840 100644 --- a/doc/man/man1/isemsg_filter.1 +++ b/doc/man/man1/xise_msg_filter.1 @@ -1,23 +1,23 @@ .\" -*- nroff -*- -.\" $Id: isemsg_filter.1 550 2014-02-03 08:16:57Z mueller $ +.\" $Id: xise_msg_filter.1 640 2015-02-01 09:56:53Z mueller $ .\" -.\" Copyright 2014- by Walter F.J. Mueller +.\" Copyright 2014-2015 by Walter F.J. Mueller .\" .\" ------------------------------------------------------------------ -.TH ISEMSG_FILTER 1 2014-01-02 "Retro Project" "Retro Project Manual" +.TH ISEMSG_FILTER 1 2015-01-30 "Retro Project" "Retro Project Manual" .\" ------------------------------------------------------------------ .SH NAME -isemsg_filter \- message filter for Xilinx ISE tool chain log files +xise_msg_filter \- message filter for Xilinx ISE tool chain log files .\" ------------------------------------------------------------------ .SH SYNOPSIS . -.SY isemsg_filter +.SY xise_msg_filter .OP \-\-pack .I TYPE .I MFSET .I LOGFILE . -.SY isemsg_filter +.SY xise_msg_filter .B \-\-help .YS . @@ -28,12 +28,12 @@ Scans the log file \fILOGFILE\fP generated by Xilinx ISE tool specified by \fITYPE\fP for informational, warning and error messages and compares these messages against a set of message filter rules defined in the \fIMFSET\fP file. -isemsg_filter will print all no-matching messages. +xise_msg_filter will print all no-matching messages. All filter rules which do not match a message are also listed, these messages are considered missing. Matched messages are considered accepted. In normal operation they will not create output. -isemsg_filter is useful for example in \fBmake\fP(1) based flows to +xise_msg_filter is useful for example in \fBmake\fP(1) based flows to create a short summary from the log files. The accepted values for \fITYPE\fP are: @@ -72,7 +72,7 @@ print full help. Simply a list of regular expression patters structured by section headers of the form "[TYPE]". Blank lines and lines starting with '#' will be ignored. -isemsg_filter will extract the patters of the section matching the +xise_msg_filter will extract the patters of the section matching the \fITYPE\fP argument. .SS Example message filter file .EX @@ -91,14 +91,14 @@ can't be opend an exit status 1 is returned. .\" ------------------------------------------------------------------ .SH EXAMPLES -.IP "\fBisemsg_filter xst proj.mfset proj_xst.log\fR" 4 +.IP "\fBxise_msg_filter xst proj.mfset proj_xst.log\fR" 4 Generate a short summary of a ISE xst log file. . .\" ------------------------------------------------------------------ .SH "BUGS" The \fIMFSET\fP file is flat, no structuring possible, e.g. with includes. It be great to have for example default rules for each target device. -Since ISE is 'end-of-life' no further work on isemsg_filter will be done. +Since ISE is 'end-of-life' no further work on xise_msg_filter will be done. . .\" ------------------------------------------------------------------ .SH "SEE ALSO" diff --git a/doc/man/man1/xtwi.1 b/doc/man/man1/xtwi.1 index 3cd8e54c..fd02bd98 100644 --- a/doc/man/man1/xtwi.1 +++ b/doc/man/man1/xtwi.1 @@ -1,5 +1,5 @@ .\" -*- nroff -*- -.\" $Id: xtwi.1 558 2014-06-01 22:20:51Z mueller $ +.\" $Id: xtwi.1 651 2015-02-26 21:32:15Z mueller $ .\" .\" Copyright 2014- by Walter F.J. Mueller .\" @@ -47,6 +47,16 @@ $XTWI_PATH/ISE_DS/settings64.sh ISE setup script located and sourced on 32 or 64 bit systems . .\" ------------------------------------------------------------------ +.SH EXAMPLES +.IP "\fBxtwi netgen -sim -intstyle xflow -ofmt vhdl -w test.ngc" 4 +Starts the ISE netlister and generates a vhdl model from \fItest.ngc\fP. +. +.\" ------------------------------------------------------------------ +.SH "NOTES" +If both ISE and Vivado are used \fBxtwi\fP and \fBxtwv\fP(1) offer a convenient +way to have both tools available in one session without interference. +. +.\" ------------------------------------------------------------------ .SH "SEE ALSO" .BR xtwv (1) . diff --git a/doc/man/man1/xtwv.1 b/doc/man/man1/xtwv.1 index 7d0f2855..008b7f59 100644 --- a/doc/man/man1/xtwv.1 +++ b/doc/man/man1/xtwv.1 @@ -1,5 +1,5 @@ .\" -*- nroff -*- -.\" $Id: xtwv.1 558 2014-06-01 22:20:51Z mueller $ +.\" $Id: xtwv.1 651 2015-02-26 21:32:15Z mueller $ .\" .\" Copyright 2014- by Walter F.J. Mueller .\" @@ -18,7 +18,7 @@ xtwv \- Xilinx Tool Wrapper script for Vivado . .\" ------------------------------------------------------------------ .SH DESCRIPTION -The Xilinx Vivado setup script redefines PATH and potentially LD_LIBRARY_PATH. +The Xilinx Vivado setup script redefines PATH and LD_LIBRARY_PATH. The Vivado tools run fine in this environment, but other installed programs on the system might fail. \fBxtwv\fP helps to keep the Vivado environment separate from the normal working environment. @@ -46,6 +46,19 @@ $XTWV_PATH/settings64.sh Vivado setup script located and sourced on 32 or 64 bit systems . .\" ------------------------------------------------------------------ +.SH EXAMPLES +.IP "\fBxtwv vivado -mode batch -source test.tcl" 4 +Starts vivado in batch mode and executes the script \fItest.tcl\fP. +. +.\" ------------------------------------------------------------------ +.SH "NOTES" +Vivado is a lot less intrusive as ISE, but it's still a good precaution to +wrap calls of Vivado tools with \fBxtwv\fP. +.br +If both Vivado and ISE are used \fBxtwv\fP and \fBxtwi\fP(1) offer a convenient +way to have both tools available in one session without interference. +. +.\" ------------------------------------------------------------------ .SH "SEE ALSO" .BR xtwi (1) . diff --git a/doc/man/man1/xviv_ghdl_unisim.1 b/doc/man/man1/xviv_ghdl_unisim.1 new file mode 100644 index 00000000..766290ea --- /dev/null +++ b/doc/man/man1/xviv_ghdl_unisim.1 @@ -0,0 +1,67 @@ +.\" -*- nroff -*- +.\" $Id: xviv_ghdl_unisim.1 642 2015-02-06 18:53:12Z mueller $ +.\" +.\" Copyright 2015- by Walter F.J. Mueller +.\" +.\" ------------------------------------------------------------------ +. +.TH XVIV_GHDL_UNISIM 1 2015-02-04 "Retro Project" "Retro Project Manual" +.\" ------------------------------------------------------------------ +.SH NAME +xviv_ghdl_unisim \- compile Xilinx Vivado UNISIM and UNIMACRO libraries for ghdl +.\" ------------------------------------------------------------------ +.SH SYNOPSIS +. +.B xviv_ghdl_unisim +. +.\" ------------------------------------------------------------------ +.SH DESCRIPTION +\fBxviv_ghdl_unisim\fP compiles the Xilinx Vivado UNISIM and UNIMACRO +libraries for \fBghdl\fP. The object files generated by \fBghdl\fP +are stored in the directory tree of the currently active version of +Vivado under \fI$XTWV_PATH/ghdl/unisim\fP and \fI$XTWV_PATH/ghdl/unimacro\fP. + +This script build the 'retarget' version of UNISIM, thus most legacy entities +from the ISE UNISIM library are available and will be mapped to the matching +Series-7 entities. + +Just use the \fBghdl\fP option + +.EX + -P${XWTI_PATH}/ghdl/unisim + -P${XWTI_PATH}/ghdl/unimacro +.EE + +to link to the UNISIM or UNIMACRO library. +\fBghdl\fP can be used without a \fBxtwv\fP wrapper. + +The Xilinx source code has since many releases some buggy statements with +self-referencial initializations. They seem to be tolerated by the commercial +tools but not by \fBghdl\fP. +The \fBxilinx_vhdl_memcolltype_fix\fP +helper script simply removes them, no further problems seen so far. + +.\" ------------------------------------------------------------------ +.SH ENVIRONMENT VARIABLES +.IP \fBXTWV_PATH\fP +points to the root of the currently active Vivado installation. +. +.\" ------------------------------------------------------------------ +.SH FILES +.IP \fI$XTWV_PATH/data/vhdl/src/unisims\fP +The vhdl sources for the Xilinx Vivado UNISIM library +.IP \fI$XTWV_PATH/data/vhdl/src/unimacro\fP +The vhdl sources for the Xilinx Vivado UNIMACRO library +.IP \fI$XTWV_PATH/ghdl\fP +The created object files will be written into this directory. The directory +is created if not yet existing. Note that the \fI$XTWV_PATH\fP +directory must be writable for the script. +. +.\" ------------------------------------------------------------------ +.SH "SEE ALSO" +.BR xtwv (1), +.BR ghdl (1) +. +.\" ------------------------------------------------------------------ +.SH AUTHOR +Walter F.J. Mueller diff --git a/doc/man/man5/vbom.5 b/doc/man/man5/vbom.5 index 30515b7a..97442f85 100644 --- a/doc/man/man5/vbom.5 +++ b/doc/man/man5/vbom.5 @@ -1,11 +1,11 @@ .\" -*- nroff -*- -.\" $Id: vbom.5 558 2014-06-01 22:20:51Z mueller $ +.\" $Id: vbom.5 646 2015-02-15 12:04:55Z mueller $ .\" -.\" Copyright 2010-2013 by Walter F.J. Mueller +.\" Copyright 2010-2015 by Walter F.J. Mueller .\" .\" ------------------------------------------------------------------ . -.TH VBOM 2013-10-20 "Retro Project" "Retro Project Manual" +.TH VBOM 2015-02-15 "Retro Project" "Retro Project Manual" .\" ------------------------------------------------------------------ .SH NAME vbom \- vhdl manifest file format - 'vhdl bill of material' @@ -72,14 +72,18 @@ Currently supported \fItag\fP names are .RS .RS 3 .PD 0 -.IP "\fBxst\fP" 6 -included in conjunction with xst synthesis -.IP "\fBghdl\fP" +.IP "\fBghdl\fP" 6 included in conjunction with ghdl simulation -.IP "\fBisim\fP" -included in conjunction with isim simulation -.IP "\fBsim\fP" -included in conjunction with simulation (ghdl or isim) +.IP "\fBxst\fP" 6 +included in conjunction with ISE xst synthesis +.IP "\fBisim\fP" 6 +included in conjunction with ISE ISim simulation +.IP "\fBvsyn\fP" 6 +included in conjunction with Vivado synthesis +.IP "\fBvsim\fP" 6 +included in conjunction with Vivado simulation +.IP "\fBsim\fP" 6 +included in conjunction with simulation (ghdl,isim,vsim) .PD .RE .RE @@ -114,13 +118,17 @@ from the stem of the \fBvbom\fP file name. . .IP "\fB@lib\fP:\fIname\fP" Specifies an additional system library. Allowed values for \fIname\fP are -\fIunisim\fP and \fIsimprim\fP. Currently used to generate the appropriate --L options for \fBghdl\fP commands, e.g. generated by the -\fBvbomconv\fP action \fB\-\-ghdl_m\fP. +\fIunisim\fP, \fIunimacro\fP and \fIsimprim\fP. +Currently used to generate the appropriate -L options for \fBghdl\fP commands, +e.g. generated by the \fBvbomconv\fP action \fB\-\-ghdl_m\fP. . .IP "\fB@ucf_cpp\fP:\fIfile\fP" Specifies that a \fIfile\fP.ucf file is to be generated by \fBcpp\fP(1) from a \fIfile\fP.ucf_cpp source file. This allows to modularize ISE ucf files. +. +.IP "\fB@xdc\fP:\fIfile\fP" +Specifies that \fIfile\fP is a constraint file for Vivado synthesis and should +be included in the constraints fileset. .RE . .\" ------------------------------------------------------------------ diff --git a/doc/w11a_os_guide.txt b/doc/w11a_os_guide.txt index c4ecf0ad..3cee30ef 100644 --- a/doc/w11a_os_guide.txt +++ b/doc/w11a_os_guide.txt @@ -1,4 +1,4 @@ -# $Id: w11a_os_guide.txt 581 2014-08-10 21:48:46Z mueller $ +# $Id: w11a_os_guide.txt 654 2015-03-01 18:45:38Z mueller $ Guide to run operating system images on w11a systems @@ -14,59 +14,74 @@ Guide to run operating system images on w11a systems 1. I/O emulation setup ---------------------------------------------------- - All UNIBUS peripherals which exchange data (currently DL11, LP11, PC11, RK11) - are currently emulated via a backend process. The communication between - FPGA board and backend server can be via + All UNIBUS peripherals which exchange data (currently DL11, LP11, PC11, RK11, + and RL11) are currently emulated via a backend process. The communication + between FPGA board and backend server can be via + - Serial port + - via an integrated USB-UART bridge + - on basys3 and nexys4 with a FT2232HQ, allows up to 12M Baud + - on nexys3 with a FT232R, allows up to 2M Baud + - via RS232 port, as on s3board and nexys2 + - using a serial port (/dev/ttySx) is limited to 115 kBaud on most PCs. + - using a USB-RS232 adapter was tested up to 460k Baud. + - Direct USB connection using a Cypress FX2 USB controller - is supported on the nexys2 and nexys3 FPGA boards - much faster than serial port connections (see below) - also allows to configure the FPGA over the same USB connection - - Serial port - - via direct (/dev/ttySx) or via a USB-RS232 adapter. A direct connection - is limited to 115k Baud on most PCs, while a connection via a USB-RS232 - adapter was tested up to 460k Baud. A USB-RS232 adapter is thus highly - recommended - - via integrated USB-RS232 adapter, like on nexys3 board. This is much - faster, allows bitrates up to 2 M Baud. - - Notes: - A USB-RS232 cable with a FTDI FT232R chip, like the cable offered - by FTDI as US232R-100 works fine. - - A USB-RS232 cable with a Prolific Technology PL2303 chip simply - never gave reliable connections for higher Baud rates. - - The rest assumes that a USB-RS232 cable with FTDI chip is used - - A 460k Baud connection gives in practice a disk throughput of - about 20 kB/s. This allows to test the system but is a bit slow - to real usage. In an OS with good disk caching like 2.11BSD the - impact of such a 'slow disk' is actually smaller than the bare - numbers suggest. - - On older linux kernels (prior 2.6.32) it is essential to set the - latency timer for the FTDI USB-RS232 cable to 1 ms (from the - power up default of 16 ms), e.g. with - sudo $RETROBASE/tools/bin/set_ftdi_lat USB0 1 - For linux kernel 2.6.32 or newer the default is 1 ms already. + Notes: + - A 10M Baud connection, like on a nexys4, gives disk access rates and + throughputs much better than the real hardware of the 70's and is well + suitable for practical usage. + - In an OS with good disk caching like 2.11BSD the impact of disk speed + is actually smaller than the bare numbers suggest. + - A 460k Baud connection gives in practice a disk throughput of ~20 kB/s. + This allows to test the system but is a bit slow for real usage. + - USB-RS232 cables with a FTDI FT232R chip work fine, tests with Prolific + Technology PL2303 based cable never gave reliable connections for higher + Baud rates. + Recommended setup for best performance (boards ordered by vintage): + + Board Channel/Interface nom. speed peak transfer rate + + basys3 USB-UART bridge 10M Baud 910 kB/sec + nexys4 USB-UART bridge 10M Baud 910 kb/sec + nexys3 Cypress FX2 USB USB2.0 speed 30000 kB/sec + nexys2 Cypress FX2 USB USB2.0 speed 30000 kB/sec + s3board RS232+USB-RS232 cable 460k Baud 41 kB/sec + 2. FPGA Board setup ------------------------------------------------------- - - Using Cypress FX2 USB controller for configuration and rlink communication - - for nexys2 - - connect USB cable to mini-USB connector (between RS232 and PS/2 port) - - for nexys3 - - connect USB cable to micro-USB connector labeled 'USB PROG' + Recommended setups - - Using serial port for rlink communication - - for s3board and nexys2 - - connect the USB-RS232 cable to the RS232 port - - for nexys3 - - connect USB cable to the micro-USB connector 'UART' - (next to the 5 buttons) - - connect a JTAG programmer (e.g. Xilinx USB Cable II) to JTAG pins + - Basys3 + - connect USB cable to micro-USB connector labeled 'PROG' + - to configure via vivado hardware server + make .vconfig - - Configure the FPGA - - if Cypress FX2 port is connected load design with + - Nexys4 + - connect USB cable to micro-USB connector labeled 'PROG' + - to configure via vivado hardware server + make .vconfig + + - Nexys3 + - use Cypress FX for configure and and rlink communication + - connect USB cable to micro-USB connector labeled 'USB PROG' + - to configure via FX2 and jtag tool make .jconfig - - otherwise use impact with + + - Nexys2 + - connect USB cable to mini-USB connector (between RS232 and PS/2 port) + - to configure via FX2 and jtag tool + make .jconfig + + - S3board + - connect the USB-RS232 cable to the RS232 port + - connect a JTAG programmer (e.g. Xilinx USB Cable II) to JTAG pins + - to configure via ISE Impact make .iconfig 3. Rlink and Backend Server setup ----------------------------------------- @@ -84,17 +99,55 @@ Guide to run operating system images on w11a systems are in the indicated positions (SWI=...). The concrete boot script name is given in the following sections - [for n2,n3 over fx2:] - SWI = 00000100 - ti_w11 -u @_boot.tcl + - for b3 over serial + SWI = 00000000 00101010 + ti_w11 -tu,10M,break,xon @_boot.tcl - [for s3,n2 over serial:] - SWI = 00000010 - ti_w11 -tu0,460k,break,xon @_boot.tcl - [for n3 over serial:] - SWI = 00000010 - ti_w11 -tu0,2M,break,xon @_boot.tcl + NOTE: the basys3 w11a has only 176 kB memory (all from BRAMS!) + unix-v5 works fine. XXDP, RT11 and RSX-11M should work. + 211bsd will not boot, either most RSX-11M+ systems. + + - for n4 over serial + SWI = 00000000 00101000 + ti_w11 -tu,10M,break,cts @_boot.tcl + + - for n2,n3 over fx2 + SWI = 00101100 + ti_w11 -u @_boot.tcl + + - for s3 serial + SWI = 00101010 + ti_w11 -tu,460k,break,xon @_boot.tcl + Notes: + - on , the serial device number + - check with 'ls /dev/ttyUSB*' to see what is available + - is typically '1' if only a single basys3 or nexys4 is connected + Initially two ttyUSB devices show up, the lower is for FPGA config + and will disappear when Vivado hardware server is used once. The + upper provides the data connection. + - is typically '0' if only a single USB-RS232 cable is connected + + - on LED display + - is controlled by SWI(3) + 0 -> system status + 1 -> DR emulation --> OS specific light patterns + + - on Hex display + - is controlled by SWI(5:4) + - boards with a 4 digit display + 00 -> serial link rate divider + 01 -> PC + 10 -> DISPREG + 11 -> DR emulation + - boards with 8 digit display + - SWI(5) select for DSP(7:4) display + 0 -> serial link rate divider + 1 -> PC + - SWI(4) select for DSP(3:0) display + 0 -> DISPREG + 1 -> DR emulation + 4. simh simulator setup --------------------------------------------------- Sometimes it is good to compare the w11a behaviour with the PDP-11 software @@ -103,7 +156,7 @@ Guide to run operating system images on w11a systems Under $RETROBASE/tools/simh two setup files are provided with configure simh to reflect the w11a setup as close as possible: - setup_w11a_min.scmd - Very close the current w11a state when it runs on an S3BOARD + Very close the current w11a state when it runs on an s3board - processor: 11/70, no FPP, 1 Mbyte - periphery: 2 DL11, LP11, RK11, PC11 - setup_w11a_max.scmd @@ -153,7 +206,8 @@ Guide to run operating system images on w11a systems - unix-v5_rk: Unix V5 System on RK05 - 211bsd_rk: 2.11BSD system on RK05 - + - 211bsd_rl: 2.11BSD system on RL02 + For further details consult the README_set.txt file in the oskit directory. @@ -186,11 +240,13 @@ Guide to run operating system images on w11a systems out the W11A and let the author know whether is works as it should. For convenience the boot scripts are also included ( .tcl ). - Three oskits are currently provided + Several osskits are currently provided - - rsx11m-31_rk: RSX-11M V3.1 on RK05 - - rsx11m-40_rk: RSX-11M V4.0 on RK05 - - rt11-40_rk: RT-11 V4.0 on RK05 + - rsx11m-31_rk: RSX-11M V3.1 on RK05 + - rsx11m-40_rk: RSX-11M V4.0 on RK05 + - rt11-40_rk: RT-11 V4.0 on RK05 + - rt11-53_rl: RT-11 V5.3 on RL02 + - xxdp_rl: XXDP 22 and 25 on RL02 For further details consult the README_set.txt file in the oskit directory. diff --git a/doc/w11a_tb_guide.txt b/doc/w11a_tb_guide.txt index b4a4ede5..421eb541 100644 --- a/doc/w11a_tb_guide.txt +++ b/doc/w11a_tb_guide.txt @@ -1,4 +1,7 @@ -# $Id: w11a_tb_guide.txt 622 2014-12-28 20:45:26Z mueller $ +# $Id: w11a_tb_guide.txt 654 2015-03-01 18:45:38Z mueller $ + +Note: Only ISE based test benches are currently documented ! + The Vivado test environemnt is still in it's infancy ! Guide to running w11a test benches diff --git a/rtl/bplib/basys3/basys3_pclk.xdc b/rtl/bplib/basys3/basys3_pclk.xdc new file mode 100644 index 00000000..5029f0a9 --- /dev/null +++ b/rtl/bplib/basys3/basys3_pclk.xdc @@ -0,0 +1,14 @@ +# -*- tcl -*- +# $Id: basys3_pclk.xdc 639 2015-01-30 18:12:19Z mueller $ +# +# Copyright 2015- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# Primary clocks for Basys3 +# +# Revision History: +# Date Rev Version Comment +# 2015-01-25 637 1.0 Initial version +# + +create_clock -name I_CLK100 -period 10 -waveform {0 5} [get_ports I_CLK100] diff --git a/rtl/bplib/basys3/basys3_pins.xdc b/rtl/bplib/basys3/basys3_pins.xdc new file mode 100644 index 00000000..ac82a8ca --- /dev/null +++ b/rtl/bplib/basys3/basys3_pins.xdc @@ -0,0 +1,111 @@ +# -*- tcl -*- +# $Id: basys3_pins.xdc 640 2015-02-01 09:56:53Z mueller $ +# +# Copyright 2015- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# Pin locks for Basys 3 core functionality +# - USB UART +# - human I/O (switches, buttons, leds, display) +# +# Revision History: +# Date Rev Version Comment +# 2015-01-30 640 1.0 Initial version +# + +# config setup -------------------------------------------------------------- +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] + +# clocks -- in bank 34 ------------------------------------------------------ +set_property PACKAGE_PIN w5 [get_ports {I_CLK100}] +set_property IOSTANDARD LVCMOS33 [get_ports {I_CLK100}] + +# +# USB UART Interface -- in bank 16 ------------------------------------------ +set_property PACKAGE_PIN b18 [get_ports {I_RXD}] +set_property PACKAGE_PIN a18 [get_ports {O_TXD}] + +set_property IOSTANDARD LVCMOS33 [get_ports {I_RXD O_TXD}] +set_property DRIVE 12 [get_ports {O_TXD}] +set_property SLEW SLOW [get_ports {O_TXD}] + +# +# switches -- in bank 14+34 ------------------------------------------------- +set_property PACKAGE_PIN v17 [get_ports {I_SWI[0]}] +set_property PACKAGE_PIN v16 [get_ports {I_SWI[1]}] +set_property PACKAGE_PIN w16 [get_ports {I_SWI[2]}] +set_property PACKAGE_PIN w17 [get_ports {I_SWI[3]}] +set_property PACKAGE_PIN w15 [get_ports {I_SWI[4]}] +set_property PACKAGE_PIN v15 [get_ports {I_SWI[5]}] +set_property PACKAGE_PIN w14 [get_ports {I_SWI[6]}] +set_property PACKAGE_PIN w13 [get_ports {I_SWI[7]}] +set_property PACKAGE_PIN v2 [get_ports {I_SWI[8]}] +set_property PACKAGE_PIN t3 [get_ports {I_SWI[9]}] +set_property PACKAGE_PIN t2 [get_ports {I_SWI[10]}] +set_property PACKAGE_PIN r3 [get_ports {I_SWI[11]}] +set_property PACKAGE_PIN w2 [get_ports {I_SWI[12]}] +set_property PACKAGE_PIN u1 [get_ports {I_SWI[13]}] +set_property PACKAGE_PIN t1 [get_ports {I_SWI[14]}] +set_property PACKAGE_PIN r2 [get_ports {I_SWI[15]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {I_SWI[*]}] + +# +# buttons -- in bank 14 ----------------------------------------------------- +# sequence: clockwise(U-R-D-L) - middle - reset +set_property PACKAGE_PIN t18 [get_ports {I_BTN[0]}] +set_property PACKAGE_PIN t17 [get_ports {I_BTN[1]}] +set_property PACKAGE_PIN u17 [get_ports {I_BTN[2]}] +set_property PACKAGE_PIN w19 [get_ports {I_BTN[3]}] +set_property PACKAGE_PIN u18 [get_ports {I_BTN[4]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {I_BTN[*]}] + +# +# LEDs -- in bank 14+34+35 -------------------------------------------------- +set_property PACKAGE_PIN u16 [get_ports {O_LED[0]}] +set_property PACKAGE_PIN e19 [get_ports {O_LED[1]}] +set_property PACKAGE_PIN u19 [get_ports {O_LED[2]}] +set_property PACKAGE_PIN v19 [get_ports {O_LED[3]}] +set_property PACKAGE_PIN w18 [get_ports {O_LED[4]}] +set_property PACKAGE_PIN u15 [get_ports {O_LED[5]}] +set_property PACKAGE_PIN u14 [get_ports {O_LED[6]}] +set_property PACKAGE_PIN v14 [get_ports {O_LED[7]}] +set_property PACKAGE_PIN v13 [get_ports {O_LED[8]}] +set_property PACKAGE_PIN v3 [get_ports {O_LED[9]}] +set_property PACKAGE_PIN w3 [get_ports {O_LED[10]}] +set_property PACKAGE_PIN u3 [get_ports {O_LED[11]}] +set_property PACKAGE_PIN p3 [get_ports {O_LED[12]}] +set_property PACKAGE_PIN n3 [get_ports {O_LED[13]}] +set_property PACKAGE_PIN p1 [get_ports {O_LED[14]}] +set_property PACKAGE_PIN l1 [get_ports {O_LED[15]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {O_LED[*]}] +set_property DRIVE 12 [get_ports {O_LED[*]}] +set_property SLEW SLOW [get_ports {O_LED[*]}] + +# +# 7 segment display -- in bank 34 ------------------------------------------- +set_property PACKAGE_PIN u2 [get_ports {O_ANO_N[0]}] +set_property PACKAGE_PIN u4 [get_ports {O_ANO_N[1]}] +set_property PACKAGE_PIN v4 [get_ports {O_ANO_N[2]}] +set_property PACKAGE_PIN w4 [get_ports {O_ANO_N[3]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {O_ANO_N[*]}] +set_property DRIVE 12 [get_ports {O_ANO_N[*]}] +set_property SLEW SLOW [get_ports {O_ANO_N[*]}] +# +set_property PACKAGE_PIN w7 [get_ports {O_SEG_N[0]}] +set_property PACKAGE_PIN w6 [get_ports {O_SEG_N[1]}] +set_property PACKAGE_PIN u8 [get_ports {O_SEG_N[2]}] +set_property PACKAGE_PIN v8 [get_ports {O_SEG_N[3]}] +set_property PACKAGE_PIN u5 [get_ports {O_SEG_N[4]}] +set_property PACKAGE_PIN v5 [get_ports {O_SEG_N[5]}] +set_property PACKAGE_PIN u7 [get_ports {O_SEG_N[6]}] +set_property PACKAGE_PIN v7 [get_ports {O_SEG_N[7]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {O_SEG_N[*]}] +set_property DRIVE 12 [get_ports {O_SEG_N[*]}] +set_property SLEW SLOW [get_ports {O_SEG_N[*]}] + diff --git a/rtl/bplib/basys3/basys3_setup.tcl b/rtl/bplib/basys3/basys3_setup.tcl new file mode 100644 index 00000000..3cf4128b --- /dev/null +++ b/rtl/bplib/basys3/basys3_setup.tcl @@ -0,0 +1,4 @@ +# $ Id: $ +# +set rvtb_part "xc7a35tcpg236-1" +set rvtb_board "basys3" diff --git a/rtl/bplib/basys3/basys3lib.vhd b/rtl/bplib/basys3/basys3lib.vhd new file mode 100644 index 00000000..e2bb6a2d --- /dev/null +++ b/rtl/bplib/basys3/basys3lib.vhd @@ -0,0 +1,46 @@ +-- $Id: basys3lib.vhd 635 2015-01-16 17:37:08Z mueller $ +-- +-- Copyright 2015- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: basys3ib +-- Description: Basys 3 components +-- +-- Dependencies: - +-- Tool versions: xst 14.7; viv 2014.4; ghdl 0.31 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2015-01-15 634 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package basys3lib is + +component basys3_aif is -- BASYS 3, abstract iface, base + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv16; -- b3 switches + I_BTN : in slv5; -- b3 buttons + O_LED : out slv16; -- b3 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8 -- 7 segment disp: segments (act.low) + ); +end component; + +end package basys3lib; diff --git a/rtl/bplib/basys3/tb/tb_basys3.vbom b/rtl/bplib/basys3/tb/tb_basys3.vbom new file mode 100644 index 00000000..0081d950 --- /dev/null +++ b/rtl/bplib/basys3/tb/tb_basys3.vbom @@ -0,0 +1,25 @@ +# Not meant for direct top level usage. Used with +# tb_basys3_(....)[_ssim].vbom and config +# lines to generate the different cases. +# +# libs +../../../vlib/slvtypes.vhd +../../../vlib/rlink/rlinklib.vbom +../../../vlib/rlink/tb/rlinktblib.vhd +../../../vlib/serport/serportlib.vbom +../../../vlib/xlib/xlib.vhd +../basys3lib.vhd +../../../vlib/simlib/simlib.vhd +../../../vlib/simlib/simbus.vhd +${sys_conf := sys_conf_sim.vhd} +# components +../../../vlib/simlib/simclk.vbom +../../../vlib/simlib/simclkcnt.vbom +../../../vlib/rlink/tb/tbcore_rlink.vbom +../../../vlib/xlib/s7_cmt_sfs_gsim.vbom +tb_basys3_core.vbom +../../../vlib/serport/serport_uart_rxtx.vbom +${basys3_aif := basys3_dummy.vbom} +# design +tb_basys3.vhd +@top:tb_basys3 diff --git a/rtl/bplib/basys3/tb/tb_basys3.vhd b/rtl/bplib/basys3/tb/tb_basys3.vhd new file mode 100644 index 00000000..e49f6148 --- /dev/null +++ b/rtl/bplib/basys3/tb/tb_basys3.vhd @@ -0,0 +1,175 @@ +-- $Id: tb_basys3.vhd 648 2015-02-20 20:16:21Z mueller $ +-- +-- Copyright 2015- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_basys3 - sim +-- Description: Test bench for basys3 (base) +-- +-- Dependencies: simlib/simclk +-- simlib/simclkcnt +-- rlink/tb/tbcore_rlink +-- xlib/s7_cmt_sfs +-- tb_basys3_core +-- serport/serport_uart_rxtx +-- basys3_aif [UUT] +-- +-- To test: generic, any basys3_aif target +-- +-- Target Devices: generic +-- Tool versions: viv 2014.4; ghdl 0.31 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2015-02-18 648 1.0 Initial version (derived from tb_nexys4) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.rlinklib.all; +use work.rlinktblib.all; +use work.serportlib.all; +use work.xlib.all; +use work.basys3lib.all; +use work.simlib.all; +use work.simbus.all; +use work.sys_conf.all; + +entity tb_basys3 is +end tb_basys3; + +architecture sim of tb_basys3 is + + signal CLKOSC : slbit := '0'; -- board clock (100 Mhz) + signal CLKCOM : slbit := '0'; -- communication clock + + signal CLK_STOP : slbit := '0'; + signal CLKCOM_CYCLE : integer := 0; + + signal RESET : slbit := '0'; + signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !! + signal RXDATA : slv8 := (others=>'0'); + signal RXVAL : slbit := '0'; + signal RXERR : slbit := '0'; + signal RXACT : slbit := '0'; + signal TXDATA : slv8 := (others=>'0'); + signal TXENA : slbit := '0'; + signal TXBUSY : slbit := '0'; + + signal I_RXD : slbit := '1'; + signal O_TXD : slbit := '1'; + signal I_SWI : slv16 := (others=>'0'); + signal I_BTN : slv5 := (others=>'0'); + signal O_LED : slv16 := (others=>'0'); + signal O_ANO_N : slv4 := (others=>'0'); + signal O_SEG_N : slv8 := (others=>'0'); + + constant clock_period : time := 10 ns; + constant clock_offset : time := 200 ns; + +begin + + CLKGEN : simclk + generic map ( + PERIOD => clock_period, + OFFSET => clock_offset) + port map ( + CLK => CLKOSC, + CLK_STOP => CLK_STOP + ); + + CLKGEN_COM : s7_cmt_sfs + generic map ( + VCO_DIVIDE => sys_conf_clkser_vcodivide, + VCO_MULTIPLY => sys_conf_clkser_vcomultiply, + OUT_DIVIDE => sys_conf_clkser_outdivide, + CLKIN_PERIOD => 10.0, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clksys_gentype) + port map ( + CLKIN => CLKOSC, + CLKFX => CLKCOM, + LOCKED => open + ); + + CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE); + + TBCORE : tbcore_rlink + port map ( + CLK => CLKCOM, + CLK_STOP => CLK_STOP, + RX_DATA => TXDATA, + RX_VAL => TXENA, + RX_HOLD => TXBUSY, + TX_DATA => RXDATA, + TX_ENA => RXVAL + ); + + N4CORE : entity work.tb_basys3_core + port map ( + I_SWI => I_SWI, + I_BTN => I_BTN + ); + + UUT : basys3_aif + port map ( + I_CLK100 => CLKOSC, + I_RXD => I_RXD, + O_TXD => O_TXD, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + UART : serport_uart_rxtx + generic map ( + CDWIDTH => CLKDIV'length) + port map ( + CLK => CLKCOM, + RESET => RESET, + CLKDIV => CLKDIV, + RXSD => O_TXD, + RXDATA => RXDATA, + RXVAL => RXVAL, + RXERR => RXERR, + RXACT => RXACT, + TXSD => I_RXD, + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY + ); + + proc_moni: process + variable oline : line; + begin + + loop + wait until rising_edge(CLKCOM); + + if RXERR = '1' then + writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1"); + writeline(output, oline); + end if; + + end loop; + + end process proc_moni; + +end sim; diff --git a/rtl/bplib/basys3/tb/tb_basys3_core.vbom b/rtl/bplib/basys3/tb/tb_basys3_core.vbom new file mode 100644 index 00000000..a84f8ad3 --- /dev/null +++ b/rtl/bplib/basys3/tb/tb_basys3_core.vbom @@ -0,0 +1,9 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/serport/serportlib.vbom +../../../vlib/simlib/simbus.vhd +# components +../../../vlib/serport/serport_uart_rx.vbom +../../../vlib/serport/serport_uart_tx.vbom +# design +tb_basys3_core.vhd diff --git a/rtl/bplib/basys3/tb/tb_basys3_core.vhd b/rtl/bplib/basys3/tb/tb_basys3_core.vhd new file mode 100644 index 00000000..c0400fdd --- /dev/null +++ b/rtl/bplib/basys3/tb/tb_basys3_core.vhd @@ -0,0 +1,71 @@ +-- $Id: tb_basys3_core.vhd 648 2015-02-20 20:16:21Z mueller $ +-- +-- Copyright 2015- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_basys3_core - sim +-- Description: Test bench for basys3 - core device handling +-- +-- Dependencies: - +-- +-- To test: generic, any basys3 target +-- +-- Target Devices: generic +-- Tool versions: viv 2014.4; ghdl 0.31 +-- Revision History: +-- Date Rev Version Comment +-- 2015-02-18 648 1.0 Initial version (derived from tb_nexys4_core) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.serportlib.all; +use work.simbus.all; + +entity tb_basys3_core is + port ( + I_SWI : out slv16; -- b3 switches + I_BTN : out slv5 -- b3 buttons + ); +end tb_basys3_core; + +architecture sim of tb_basys3_core is + + signal R_SWI : slv16 := (others=>'0'); + signal R_BTN : slv5 := (others=>'0'); + + constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8)); + constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8)); + +begin + + proc_simbus: process (SB_VAL) + begin + if SB_VAL'event and to_x01(SB_VAL)='1' then + if SB_ADDR = sbaddr_swi then + R_SWI <= to_x01(SB_DATA(R_SWI'range)); + end if; + if SB_ADDR = sbaddr_btn then + R_BTN <= to_x01(SB_DATA(R_BTN'range)); + end if; + end if; + end process proc_simbus; + + I_SWI <= R_SWI; + I_BTN <= R_BTN; + +end sim; diff --git a/rtl/bplib/bpgen/Makefile b/rtl/bplib/bpgen/Makefile index b56e89d5..68c92e49 100644 --- a/rtl/bplib/bpgen/Makefile +++ b/rtl/bplib/bpgen/Makefile @@ -1,7 +1,8 @@ -# $Id: Makefile 575 2014-07-27 20:55:41Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment +# 2015-01-24 637 1.1.2 use nexys3 as default XTW_BOARD # 2014-07-27 545 1.1.1 make reference board configurable via XTW_BOARD # 2011-08-13 405 1.1 use includes from rtl/make # 2007-12-09 100 1.0.1 drop ISE_p definition @@ -11,9 +12,9 @@ VBOM_all = $(wildcard *.vbom) NGC_all = $(VBOM_all:.vbom=.ngc) # ifndef XTW_BOARD - XTW_BOARD=s3board + XTW_BOARD=nexys3 endif -include $(RETROBASE)/rtl/make/xflow_default_$(XTW_BOARD).mk +include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # .PHONY : all clean # @@ -23,7 +24,7 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/bplib/bpgen/bp_rs232_2l4l_iob.vhd b/rtl/bplib/bpgen/bp_rs232_2l4l_iob.vhd index 93670ecb..d0c9549a 100644 --- a/rtl/bplib/bpgen/bp_rs232_2l4l_iob.vhd +++ b/rtl/bplib/bpgen/bp_rs232_2l4l_iob.vhd @@ -1,4 +1,4 @@ --- $Id: bp_rs232_2l4l_iob.vhd 534 2013-09-22 21:37:24Z mueller $ +-- $Id: bp_rs232_2l4l_iob.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2010-2011 by Walter F.J. Mueller -- @@ -21,7 +21,7 @@ -- Test bench: - -- -- Target Devices: generic --- Tool versions: xst 12.1; ghdl 0.26-0.29 +-- Tool versions: xst 12.1-14,7; ghdl 0.26-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/bplib/bpgen/bp_rs232_2line_iob.vhd b/rtl/bplib/bpgen/bp_rs232_2line_iob.vhd index e50ce691..8fe1f512 100644 --- a/rtl/bplib/bpgen/bp_rs232_2line_iob.vhd +++ b/rtl/bplib/bpgen/bp_rs232_2line_iob.vhd @@ -1,4 +1,4 @@ --- $Id: bp_rs232_2line_iob.vhd 426 2011-11-18 18:14:08Z mueller $ +-- $Id: bp_rs232_2line_iob.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2010-2011 by Walter F.J. Mueller -- @@ -21,7 +21,7 @@ -- Test bench: - -- -- Target Devices: generic --- Tool versions: xst 11.4, 12.1; ghdl 0.26-0.29 +-- Tool versions: xst 11.4-14.7; viv 2014.4; ghdl 0.26-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/bplib/bpgen/bp_rs232_4line_iob.vhd b/rtl/bplib/bpgen/bp_rs232_4line_iob.vhd index 9570c0fe..c771f503 100644 --- a/rtl/bplib/bpgen/bp_rs232_4line_iob.vhd +++ b/rtl/bplib/bpgen/bp_rs232_4line_iob.vhd @@ -1,4 +1,4 @@ --- $Id: bp_rs232_4line_iob.vhd 426 2011-11-18 18:14:08Z mueller $ +-- $Id: bp_rs232_4line_iob.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2010-2011 by Walter F.J. Mueller -- @@ -21,7 +21,7 @@ -- Test bench: - -- -- Target Devices: generic --- Tool versions: xst 11.4, 12.1; ghdl 0.26-0.29 +-- Tool versions: ise 11.4-14.7; viv 2014.4; ghdl 0.26-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/bplib/bpgen/bp_swibtnled.vhd b/rtl/bplib/bpgen/bp_swibtnled.vhd index b5d6e3d8..33971cd8 100644 --- a/rtl/bplib/bpgen/bp_swibtnled.vhd +++ b/rtl/bplib/bpgen/bp_swibtnled.vhd @@ -1,4 +1,4 @@ --- $Id: bp_swibtnled.vhd 410 2011-09-18 11:23:09Z mueller $ +-- $Id: bp_swibtnled.vhd 637 2015-01-25 18:36:40Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -22,7 +22,7 @@ -- Test bench: - -- -- Target Devices: generic --- Tool versions: xst 11.4, 12.1; ghdl 0.26-0.29 +-- Tool versions: ise 11.4-14.7; viv 2014.4; ghdl 0.26-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/bplib/bpgen/bpgenlib.vhd b/rtl/bplib/bpgen/bpgenlib.vhd index 2af8130f..3e60bec6 100644 --- a/rtl/bplib/bpgen/bpgenlib.vhd +++ b/rtl/bplib/bpgen/bpgenlib.vhd @@ -1,6 +1,6 @@ --- $Id: bpgenlib.vhd 534 2013-09-22 21:37:24Z mueller $ +-- $Id: bpgenlib.vhd 637 2015-01-25 18:36:40Z mueller $ -- --- Copyright 2011-2013 by Walter F.J. Mueller +-- Copyright 2011-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,9 +16,10 @@ -- Description: Generic Board/Part components -- -- Dependencies: - --- Tool versions: 12.1, 13.3; ghdl 0.26-0.29 +-- Tool versions: ise 12.1-14.7; viv 2014.4; ghdl 0.26-0.31 -- Revision History: -- Date Rev Version Comment +-- 2015-01-24 637 1.1.2 add generics to sn_humanio and sn_7segctl -- 2013-09-21 534 1.1.1 add bp_rs232_4l4l_iob -- 2013-01-26 476 1.1 moved rbus depended components to bpgenrbuslib -- 2013-01-06 472 1.0.7 add sn_humanio_demu_rbus @@ -124,36 +125,40 @@ component bp_swibtnled is -- generic SWI, BTN and LED handling ); end component; -component sn_4x7segctl is -- Quad 7 segment display controller +component sn_7segctl is -- 7 segment display controller generic ( + DCWIDTH : positive := 2; -- digit counter width (2 or 3) CDWIDTH : positive := 6); -- clk divider width (must be >= 5) port ( CLK : in slbit; -- clock - DIN : in slv16; -- data - DP : in slv4; -- decimal points - ANO_N : out slv4; -- anodes (act.low) - SEG_N : out slv8 -- segements (act.low) + DIN : in slv(4*(2**DCWIDTH)-1 downto 0); -- data 16 or 32 + DP : in slv((2**DCWIDTH)-1 downto 0); -- decimal points 4 or 8 + ANO_N : out slv((2**DCWIDTH)-1 downto 0); -- anodes (act.low) 4 or 8 + SEG_N : out slv8 -- segements (act.low) ); end component; component sn_humanio is -- human i/o handling: swi,btn,led,dsp generic ( + SWIDTH : positive := 8; -- SWI port width BWIDTH : positive := 4; -- BTN port width + LWIDTH : positive := 8; -- LED port width + DCWIDTH : positive := 2; -- digit counter width (2 or 3) DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN port ( CLK : in slbit; -- clock RESET : in slbit := '0'; -- reset CE_MSEC : in slbit; -- 1 ms clock enable - SWI : out slv8; -- switch settings, debounced + SWI : out slv(SWIDTH-1 downto 0); -- switch settings, debounced BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced - LED : in slv8; -- led data - DSP_DAT : in slv16; -- display data - DSP_DP : in slv4; -- display decimal points - I_SWI : in slv8; -- pad-i: switches + LED : in slv(LWIDTH-1 downto 0); -- led data + DSP_DAT : in slv(4*(2**DCWIDTH)-1 downto 0); -- display data + DSP_DP : in slv((2**DCWIDTH)-1 downto 0); -- display decimal points + I_SWI : in slv(SWIDTH-1 downto 0); -- pad-i: switches I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons - O_LED : out slv8; -- pad-o: leds - O_ANO_N : out slv4; -- pad-o: 7 seg disp: anodes (act.low) - O_SEG_N : out slv8 -- pad-o: 7 seg disp: segments (act.low) + O_LED : out slv(LWIDTH-1 downto 0); -- pad-o: leds + O_ANO_N : out slv((2**DCWIDTH)-1 downto 0); -- pad-o: disp: anodes (act.low) + O_SEG_N : out slv8 -- pad-o: disp: segments (act.low) ); end component; diff --git a/rtl/bplib/bpgen/bpgenrbuslib.vhd b/rtl/bplib/bpgen/bpgenrbuslib.vhd index 8c0edfd3..e73e2b9d 100644 --- a/rtl/bplib/bpgen/bpgenrbuslib.vhd +++ b/rtl/bplib/bpgen/bpgenrbuslib.vhd @@ -1,6 +1,6 @@ --- $Id: bpgenrbuslib.vhd 583 2014-08-16 07:40:12Z mueller $ +-- $Id: bpgenrbuslib.vhd 637 2015-01-25 18:36:40Z mueller $ -- --- Copyright 2013-2014 by Walter F.J. Mueller +-- Copyright 2013-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,9 +16,10 @@ -- Description: Generic Board/Part components using rbus -- -- Dependencies: - --- Tool versions: 12.1-14.7; ghdl 0.26-0.31 +-- Tool versions: ise 12.1-14.7; viv 2014.4; ghdl 0.26-0.31 -- Revision History: -- Date Rev Version Comment +-- 2015-01-25 637 1.2 add generics to sn_humanio_rbus -- 2014-08-15 583 1.1 rb_mreq addr now 16 bit -- 2013-01-26 476 1.0 Initial version (extracted from bpgenlib) ------------------------------------------------------------------------------ @@ -38,7 +39,7 @@ component bp_swibtnled_rbus is -- swi,btn,led handling /w rbus icept BWIDTH : positive := 4; -- BTN port width LWIDTH : positive := 4; -- LED port width DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN - RB_ADDR : slv16 := slv(to_unsigned(2#0000000010000000#,16))); + RB_ADDR : slv16 := slv(to_unsigned(16#fef0#,16))); port ( CLK : in slbit; -- clock RESET : in slbit := '0'; -- reset @@ -56,32 +57,35 @@ end component; component sn_humanio_rbus is -- human i/o handling /w rbus intercept generic ( + SWIDTH : positive := 8; -- SWI port width BWIDTH : positive := 4; -- BTN port width + LWIDTH : positive := 8; -- LED port width + DCWIDTH : positive := 2; -- digit counter width (2 or 3) DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN - RB_ADDR : slv16 := slv(to_unsigned(2#0000000010000000#,16))); + RB_ADDR : slv16 := slv(to_unsigned(16#fef0#,16))); port ( CLK : in slbit; -- clock RESET : in slbit := '0'; -- reset CE_MSEC : in slbit; -- 1 ms clock enable RB_MREQ : in rb_mreq_type; -- rbus: request RB_SRES : out rb_sres_type; -- rbus: response - SWI : out slv8; -- switch settings, debounced + SWI : out slv(SWIDTH-1 downto 0); -- switch settings, debounced BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced - LED : in slv8; -- led data - DSP_DAT : in slv16; -- display data - DSP_DP : in slv4; -- display decimal points - I_SWI : in slv8; -- pad-i: switches + LED : in slv(LWIDTH-1 downto 0); -- led data + DSP_DAT : in slv(4*(2**DCWIDTH)-1 downto 0); -- display data + DSP_DP : in slv((2**DCWIDTH)-1 downto 0); -- display decimal points + I_SWI : in slv(SWIDTH-1 downto 0); -- pad-i: switches I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons - O_LED : out slv8; -- pad-o: leds - O_ANO_N : out slv4; -- pad-o: 7 seg disp: anodes (act.low) - O_SEG_N : out slv8 -- pad-o: 7 seg disp: segments (act.low) + O_LED : out slv(LWIDTH-1 downto 0); -- pad-o: leds + O_ANO_N : out slv((2**DCWIDTH)-1 downto 0); -- pad-o: disp: anodes (act.low) + O_SEG_N : out slv8 -- pad-o: disp: segments (act.low) ); end component; component sn_humanio_demu_rbus is -- human i/o swi,btn,led only /w rbus generic ( DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN - RB_ADDR : slv16 := slv(to_unsigned(2#0000000010000000#,16))); + RB_ADDR : slv16 := slv(to_unsigned(16#fef0#,16))); port ( CLK : in slbit; -- clock RESET : in slbit := '0'; -- reset diff --git a/rtl/bplib/bpgen/sn_4x7segctl.vbom b/rtl/bplib/bpgen/sn_7segctl.vbom similarity index 75% rename from rtl/bplib/bpgen/sn_4x7segctl.vbom rename to rtl/bplib/bpgen/sn_7segctl.vbom index af92f9dc..b7985ceb 100644 --- a/rtl/bplib/bpgen/sn_4x7segctl.vbom +++ b/rtl/bplib/bpgen/sn_7segctl.vbom @@ -2,4 +2,4 @@ ../../vlib/slvtypes.vhd # components # design -sn_4x7segctl.vhd +sn_7segctl.vhd diff --git a/rtl/bplib/bpgen/sn_4x7segctl.vhd b/rtl/bplib/bpgen/sn_7segctl.vhd similarity index 64% rename from rtl/bplib/bpgen/sn_4x7segctl.vhd rename to rtl/bplib/bpgen/sn_7segctl.vhd index 9acdd23d..71698900 100644 --- a/rtl/bplib/bpgen/sn_4x7segctl.vhd +++ b/rtl/bplib/bpgen/sn_7segctl.vhd @@ -1,6 +1,6 @@ --- $Id: sn_4x7segctl.vhd 410 2011-09-18 11:23:09Z mueller $ +-- $Id: sn_7segctl.vhd 637 2015-01-25 18:36:40Z mueller $ -- --- Copyright 2007-2011 by Walter F.J. Mueller +-- Copyright 2007-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -12,15 +12,24 @@ -- for complete details. -- ------------------------------------------------------------------------------ --- Module Name: sn_4x7segctl - syn --- Description: Quad 7 segment display controller (for s3board and nexys2/3) +-- Module Name: sn_7segctl - syn +-- Description: 7 segment display controller (for s3board,nexys,basys) -- -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2015-01-24 637 14.7 131013 xc6slx16-2 9 27 0 16 s 3.1 ns DC=3 +-- 2015-01-24 637 14.7 131013 xc6slx16-2 8 19 0 9 s 3.1 ns DC=2 +-- 2015-01-24 410 14.7 131013 xc6slx16-2 8 19 0 8 s 3.1 ns + -- Revision History: -- Date Rev Version Comment +-- 2015-01-24 637 1.3 renamed from sn_4x7segctl; add DCWIDTH, +-- allow 4(DC=2) or 8(DC=3) digit display -- 2011-09-17 410 1.2.1 now numeric_std clean -- 2011-07-30 400 1.2 digit dark in last quarter (not 16 clocks) -- 2011-07-08 390 1.1.2 renamed from s3_dispdrv @@ -37,28 +46,28 @@ use ieee.numeric_std.all; use work.slvtypes.all; -entity sn_4x7segctl is -- Quad 7 segment display controller +entity sn_7segctl is -- 7 segment display controller generic ( + DCWIDTH : positive := 2; -- digit counter width (2 or 3) CDWIDTH : positive := 6); -- clk divider width (must be >= 5) port ( CLK : in slbit; -- clock - DIN : in slv16; -- data - DP : in slv4; -- decimal points - ANO_N : out slv4; -- anodes (act.low) - SEG_N : out slv8 -- segements (act.low) + DIN : in slv(4*(2**DCWIDTH)-1 downto 0); -- data 16 or 32 + DP : in slv((2**DCWIDTH)-1 downto 0); -- decimal points 4 or 8 + ANO_N : out slv((2**DCWIDTH)-1 downto 0); -- anodes (act.low) 4 or 8 + SEG_N : out slv8 -- segements (act.low) ); -end sn_4x7segctl; - -architecture syn of sn_4x7segctl is +end sn_7segctl; +architecture syn of sn_7segctl is type regs_type is record cdiv : slv(CDWIDTH-1 downto 0); -- clock divider counter - dcnt : slv2; -- digit counter + dcnt : slv(DCWIDTH-1 downto 0); -- digit counter end record regs_type; constant regs_init : regs_type := ( - slv(to_unsigned(0,CDWIDTH)), - (others=>'0') + slv(to_unsigned(0,CDWIDTH)), -- cdiv + slv(to_unsigned(0,DCWIDTH)) -- dcnt ); type hex2segtbl_type is array (0 to 15) of slv7; @@ -84,9 +93,15 @@ architecture syn of sn_4x7segctl is signal R_REGS : regs_type := regs_init; -- state registers signal N_REGS : regs_type := regs_init; -- next value state regs + signal CHEX : slv4 := (others=>'0'); -- current hex number + signal CDP : slbit := '0'; -- current decimal point begin + assert DCWIDTH=2 or DCWIDTH=3 + report "assert(DCWIDTH=2 or DCWIDTH=3): unsupported DCWIDTH" + severity FAILURE; + assert CDWIDTH >= 5 report "assert(CDWIDTH >= 5): CDWIDTH too small" severity FAILURE; @@ -101,14 +116,12 @@ begin end process proc_regs; - proc_next: process (R_REGS, DIN, DP) + proc_next: process (R_REGS, CHEX, CDP) variable r : regs_type := regs_init; variable n : regs_type := regs_init; - variable cano : slv4 := "0000"; - variable chex : slv4 := "0000"; - variable cdp : slbit := '0'; - + variable cano : slv((2**DCWIDTH)-1 downto 0) := (others=>'0'); + begin r := R_REGS; @@ -119,17 +132,6 @@ begin n.dcnt := slv(unsigned(r.dcnt) + 1); end if; - chex := "0000"; - cdp := '0'; - - case r.dcnt is - when "00" => chex := DIN( 3 downto 0); cdp := DP(0); - when "01" => chex := DIN( 7 downto 4); cdp := DP(1); - when "10" => chex := DIN(11 downto 8); cdp := DP(2); - when "11" => chex := DIN(15 downto 12); cdp := DP(3); - when others => chex := "----"; cdp := '-'; - end case; - -- the logic below ensures that the anode PNP driver transistor is switched -- off in the last quarter of the digit cycle.This prevents 'cross talk' -- between digits due to transistor turn off delays. @@ -141,7 +143,7 @@ begin -- larger 160 ns and below 320 ns. -- As consquence CDWIDTH should be at least 6 for 50 MHz and 7 for 100 MHz. - cano := "1111"; + cano := (others=>'1'); if r.cdiv(CDWIDTH-1 downto CDWIDTH-2) /= "00" then cano(to_integer(unsigned(r.dcnt))) := '0'; end if; @@ -149,8 +151,17 @@ begin N_REGS <= n; ANO_N <= cano; - SEG_N <= not (cdp & hex2segtbl(to_integer(unsigned(chex)))); + SEG_N <= not (CDP & hex2segtbl(to_integer(unsigned(CHEX)))); end process proc_next; + + proc_mux: process (R_REGS, DIN, DP) + begin + CDP <= DP(to_integer(unsigned(R_REGS.dcnt))); + CHEX(0) <= DIN(0+4*to_integer(unsigned(R_REGS.dcnt))); + CHEX(1) <= DIN(1+4*to_integer(unsigned(R_REGS.dcnt))); + CHEX(2) <= DIN(2+4*to_integer(unsigned(R_REGS.dcnt))); + CHEX(3) <= DIN(3+4*to_integer(unsigned(R_REGS.dcnt))); + end process proc_mux; end syn; diff --git a/rtl/bplib/bpgen/sn_humanio.vbom b/rtl/bplib/bpgen/sn_humanio.vbom index 56f4fda6..0f2815a8 100644 --- a/rtl/bplib/bpgen/sn_humanio.vbom +++ b/rtl/bplib/bpgen/sn_humanio.vbom @@ -5,6 +5,6 @@ bpgenlib.vbom # components ../../vlib/xlib/iob_reg_o_gen.vbom bp_swibtnled.vbom -sn_4x7segctl.vbom +sn_7segctl.vbom # design sn_humanio.vhd diff --git a/rtl/bplib/bpgen/sn_humanio.vhd b/rtl/bplib/bpgen/sn_humanio.vhd index b67651e6..4228dbd0 100644 --- a/rtl/bplib/bpgen/sn_humanio.vhd +++ b/rtl/bplib/bpgen/sn_humanio.vhd @@ -1,6 +1,6 @@ --- $Id: sn_humanio.vhd 410 2011-09-18 11:23:09Z mueller $ +-- $Id: sn_humanio.vhd 637 2015-01-25 18:36:40Z mueller $ -- --- Copyright 2010-2011 by Walter F.J. Mueller +-- Copyright 2010-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -13,25 +13,29 @@ -- ------------------------------------------------------------------------------ -- Module Name: sn_humanio - syn --- Description: All BTN, SWI, LED and DSP handling for s3board, nexys2/3 +-- Description: BTN,SWI,LED and DSP handling for s3board, nexys, basys -- -- Dependencies: xlib/iob_reg_o_gen -- bpgen/bp_swibtnled --- bpgen/sn_4x7segctl +-- bpgen/sn_7segctl -- -- Test bench: - -- -- Target Devices: generic --- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26 +-- Tool versions: ise 11.4-14.7; viv 2014.4; ghdl 0.26-0.31 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri +-- 2015-01-24 637 14.7 131013 xc6slx16-2 77 79 0 28 s 3.5 ns (n4) +-- 2015-01-24 637 14.7 131013 xc6slx16-2 47 52 0 18 s 3.4 ns (n2) +-- 2015-01-24 410 14.7 131013 xc6slx16-2 47 52 0 18 s 3.4 ns -- 2011-09-17 409 13.1 O40d xc3s1000-4 49 86 0 53 s 5.3 ns -- 2011-07-02 387 12.1 M53d xc3s1000-4 48 87 0 53 s 5.1 ns -- 2010-04-10 275 11.4 L68 xc3s1000-4 48 87 0 53 s 5.2 ns -- -- Revision History: -- Date Rev Version Comment +-- 2015-01-24 637 1.3 add SWIDTH,LWIDTH,DCWIDTH (for nexys4,basys3) -- 2011-07-30 400 1.2.1 use CDWIDTH=7 for sn_4x7segctl (for 100 MHz) -- 2011-07-08 390 1.2 renamed from s3_humanio, add BWIDTH generic -- 2011-07-02 387 1.1.2 use bp_swibtnled @@ -52,34 +56,37 @@ use work.bpgenlib.all; entity sn_humanio is -- human i/o handling: swi,btn,led,dsp generic ( + SWIDTH : positive := 8; -- SWI port width BWIDTH : positive := 4; -- BTN port width + LWIDTH : positive := 8; -- LED port width + DCWIDTH : positive := 2; -- digit counter width (2 or 3) DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN port ( CLK : in slbit; -- clock RESET : in slbit := '0'; -- reset CE_MSEC : in slbit; -- 1 ms clock enable - SWI : out slv8; -- switch settings, debounced + SWI : out slv(SWIDTH-1 downto 0); -- switch settings, debounced BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced - LED : in slv8; -- led data - DSP_DAT : in slv16; -- display data - DSP_DP : in slv4; -- display decimal points - I_SWI : in slv8; -- pad-i: switches + LED : in slv(LWIDTH-1 downto 0); -- led data + DSP_DAT : in slv(4*(2**DCWIDTH)-1 downto 0); -- display data + DSP_DP : in slv((2**DCWIDTH)-1 downto 0); -- display decimal points + I_SWI : in slv(SWIDTH-1 downto 0); -- pad-i: switches I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons - O_LED : out slv8; -- pad-o: leds - O_ANO_N : out slv4; -- pad-o: 7 seg disp: anodes (act.low) - O_SEG_N : out slv8 -- pad-o: 7 seg disp: segments (act.low) + O_LED : out slv(LWIDTH-1 downto 0); -- pad-o: leds + O_ANO_N : out slv((2**DCWIDTH)-1 downto 0); -- pad-o: disp: anodes (act.low) + O_SEG_N : out slv8 -- pad-o: disp: segments (act.low) ); end sn_humanio; architecture syn of sn_humanio is - signal N_ANO_N : slv4 := (others=>'0'); + signal N_ANO_N : slv((2**DCWIDTH)-1 downto 0) := (others=>'0'); signal N_SEG_N : slv8 := (others=>'0'); begin IOB_ANO_N : iob_reg_o_gen - generic map (DWIDTH => 4) + generic map (DWIDTH => 2**DCWIDTH) port map (CLK => CLK, CE => '1', DO => N_ANO_N, PAD => O_ANO_N); IOB_SEG_N : iob_reg_o_gen @@ -88,9 +95,9 @@ begin HIO : bp_swibtnled generic map ( - SWIDTH => 8, + SWIDTH => SWIDTH, BWIDTH => BWIDTH, - LWIDTH => 8, + LWIDTH => LWIDTH, DEBOUNCE => DEBOUNCE) port map ( CLK => CLK, @@ -104,8 +111,9 @@ begin O_LED => O_LED ); - DRV : sn_4x7segctl + DRV : sn_7segctl generic map ( + DCWIDTH => DCWIDTH, CDWIDTH => 7) -- 7 good for 100 MHz on nexys2 port map ( CLK => CLK, diff --git a/rtl/bplib/bpgen/sn_humanio_demu.vhd b/rtl/bplib/bpgen/sn_humanio_demu.vhd index 0efe8a4b..a28ef717 100644 --- a/rtl/bplib/bpgen/sn_humanio_demu.vhd +++ b/rtl/bplib/bpgen/sn_humanio_demu.vhd @@ -1,4 +1,4 @@ --- $Id: sn_humanio_demu.vhd 414 2011-10-11 19:38:12Z mueller $ +-- $Id: sn_humanio_demu.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -20,7 +20,7 @@ -- Test bench: - -- -- Target Devices: generic --- Tool versions: xst 13.1; ghdl 0.29 +-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri diff --git a/rtl/bplib/bpgen/sn_humanio_demu_rbus.vhd b/rtl/bplib/bpgen/sn_humanio_demu_rbus.vhd index d6c64df0..011cbea1 100644 --- a/rtl/bplib/bpgen/sn_humanio_demu_rbus.vhd +++ b/rtl/bplib/bpgen/sn_humanio_demu_rbus.vhd @@ -1,4 +1,4 @@ --- $Id: sn_humanio_demu_rbus.vhd 583 2014-08-16 07:40:12Z mueller $ +-- $Id: sn_humanio_demu_rbus.vhd 637 2015-01-25 18:36:40Z mueller $ -- -- Copyright 2013-2014 by Walter F.J. Mueller -- @@ -69,7 +69,7 @@ use work.bpgenlib.all; entity sn_humanio_demu_rbus is -- human i/o swi,btn,led only /w rbus generic ( DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN - RB_ADDR : slv16 := slv(to_unsigned(2#0000000010000000#,16))); + RB_ADDR : slv16 := slv(to_unsigned(16#fef0#,16))); port ( CLK : in slbit; -- clock RESET : in slbit := '0'; -- reset diff --git a/rtl/bplib/bpgen/sn_humanio_rbus.vhd b/rtl/bplib/bpgen/sn_humanio_rbus.vhd index f9076e1f..f92a31a0 100644 --- a/rtl/bplib/bpgen/sn_humanio_rbus.vhd +++ b/rtl/bplib/bpgen/sn_humanio_rbus.vhd @@ -1,6 +1,6 @@ --- $Id: sn_humanio_rbus.vhd 583 2014-08-16 07:40:12Z mueller $ +-- $Id: sn_humanio_rbus.vhd 640 2015-02-01 09:56:53Z mueller $ -- --- Copyright 2010-2014 by Walter F.J. Mueller +-- Copyright 2010-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -20,10 +20,13 @@ -- Test bench: - -- -- Target Devices: generic --- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31 +-- Tool versions: ise 11.4-14.7; viv 2014.4; ghdl 0.26-0.31 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri +-- 2015-01-28 639 14.7 131013 xc6slx16-2 253 223 0 97 s 3.6 ns (n4) +-- 2015-01-28 639 14.7 131013 xc6slx16-2 141 120 0 42 s 3.5 ns (n2) +-- 2015-01-25 583 14.7 131013 xc6slx16-2 140 120 0 46 s 3.5 ns -- 2011-08-14 406 12.1 M53d xc3s1000-4 142 156 0 123 s 5.1 ns -- 2011-08-07 404 12.1 M53d xc3s1000-4 142 157 0 124 s 5.1 ns -- 2010-12-29 351 12.1 M53d xc3s1000-4 93 138 0 111 s 6.8 ns @@ -31,6 +34,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2015-01-31 640 2.0 add SWIDTH,LWIDTH,DCWIDTH, change register layout -- 2014-08-15 583 1.3 rb_mreq addr now 16 bit -- 2011-11-19 427 1.2.1 now numeric_std clean -- 2011-08-14 406 1.2 common register layout with bp_swibtnled_rbus @@ -43,26 +47,36 @@ -- -- rbus registers: -- --- Address Bits Name r/w/f Function --- bbbbbb00 cntl r/w/- Control register and BTN access --- x:08 btn r/w/- r: return hio BTN status --- w: ored with hio BTN to drive BTN --- 3 dsp_en r/w/- if 1 display data will be driven by rbus --- 2 dp_en r/w/- if 1 display dp's will be driven by rbus --- 1 led_en r/w/- if 1 LED will be driven by rri --- 0 swi_en r/w/- if 1 SWI will be driven by rri --- --- bbbbbb01 7:00 swi r/w/- r: return hio SWI status --- w: will drive SWI when swi_en=1 --- --- bbbbbb10 led r/w/- Interface to LED and DSP_DP --- 15:12 dp r/w/- r: returns DSP_DP status --- w: will drive display dp's when dp_en=1 --- 7:00 led r/w/- r: returns LED status --- w: will drive led's when led_en=1 --- --- bbbbbb11 15:00 dsp r/w/- r: return hio DSP_DAT status --- w: will drive DSP_DAT when dsp_en=1 +-- Addr Bits Name r/w/f Function +-- 000 stat r/-/- Status register +-- 14:12 hdig r/-/- display size as (2**DCWIDTH)-1 +-- 11:08 hled r/-/- led size as LWIDTH-1 +-- 7:04 hbtn r/-/- button size as BWIDTH-1 +-- 3:00 hswi r/-/- switch size as SWIDTH-1 +-- +-- 001 cntl r/w/- Control register +-- 4 dsp1_en r/w/- if 1 display msb will be driven by rbus +-- 3 dsp0_en r/w/- if 1 display lsb will be driven by rbus +-- 2 dp_en r/w/- if 1 display dp's will be driven by rbus +-- 1 led_en r/w/- if 1 LED will be driven by rbus +-- 0 swi_en r/w/- if 1 SWI will be driven by rbus +-- +-- 010 x:00 btn r/-/f r: return hio BTN status +-- w: will pulse BTN +-- +-- 011 x:00 swi r/w/- r: return hio SWI status +-- w: will drive SWI when swi_en=1 +-- +-- 100 x:00 led r/w/- r: return hio LED status +-- w: will drive LED when led_en=1 +-- +-- 101 x:00 dp r/w/- r: return hio DSP_DP status +-- w: will drive dp's when dp_en=1 +-- +-- 110 15:00 dsp0 r/w/- r: return hio DSP_DAT lsb status +-- w: will drive DSP_DAT lsb when dsp_en=1 +-- 111 15:00 dsp1 r/w/- r: return hio DSP_DAT msb status +-- w: will drive DSP_DAT msb when dsp_en=1 -- library ieee; @@ -77,25 +91,28 @@ use work.bpgenlib.all; entity sn_humanio_rbus is -- human i/o handling /w rbus intercept generic ( + SWIDTH : positive := 8; -- SWI port width BWIDTH : positive := 4; -- BTN port width + LWIDTH : positive := 8; -- LED port width + DCWIDTH : positive := 2; -- digit counter width (2 or 3) DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN - RB_ADDR : slv16 := slv(to_unsigned(2#0000000010000000#,16))); + RB_ADDR : slv16 := slv(to_unsigned(16#fef0#,16))); port ( CLK : in slbit; -- clock RESET : in slbit := '0'; -- reset CE_MSEC : in slbit; -- 1 ms clock enable RB_MREQ : in rb_mreq_type; -- rbus: request RB_SRES : out rb_sres_type; -- rbus: response - SWI : out slv8; -- switch settings, debounced + SWI : out slv(SWIDTH-1 downto 0); -- switch settings, debounced BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced - LED : in slv8; -- led data - DSP_DAT : in slv16; -- display data - DSP_DP : in slv4; -- display decimal points - I_SWI : in slv8; -- pad-i: switches + LED : in slv(LWIDTH-1 downto 0); -- led data + DSP_DAT : in slv(4*(2**DCWIDTH)-1 downto 0); -- display data + DSP_DP : in slv((2**DCWIDTH)-1 downto 0); -- display decimal points + I_SWI : in slv(SWIDTH-1 downto 0); -- pad-i: switches I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons - O_LED : out slv8; -- pad-o: leds - O_ANO_N : out slv4; -- pad-o: 7 seg disp: anodes (act.low) - O_SEG_N : out slv8 -- pad-o: 7 seg disp: segments (act.low) + O_LED : out slv(LWIDTH-1 downto 0); -- pad-o: leds + O_ANO_N : out slv((2**DCWIDTH)-1 downto 0); -- pad-o: disp: anodes (act.low) + O_SEG_N : out slv8 -- pad-o: disp: segments (act.low) ); end sn_humanio_rbus; @@ -103,68 +120,100 @@ architecture syn of sn_humanio_rbus is type regs_type is record rbsel : slbit; -- rbus select - swi : slv8; -- rbus swi + swi : slv(SWIDTH-1 downto 0); -- rbus swi btn : slv(BWIDTH-1 downto 0); -- rbus btn - led : slv8; -- rbus led - dsp_dat : slv16; -- rbus dsp_dat - dsp_dp : slv4; -- rbus dsp_dp - ledin : slv8; -- led from design - swieff : slv8; -- effective swi + led : slv(LWIDTH-1 downto 0); -- rbus led + dsp_dat : slv(4*(2**DCWIDTH)-1 downto 0); -- rbus dsp_dat + dsp_dp : slv((2**DCWIDTH)-1 downto 0); -- rbus dsp_dp + ledin : slv(LWIDTH-1 downto 0); -- led from design + swieff : slv(SWIDTH-1 downto 0); -- effective swi btneff : slv(BWIDTH-1 downto 0); -- effective btn - ledeff : slv8; -- effective led - dpeff : slv4; -- effective dsp_dp - dateff : slv16; -- effective dsp_dat + ledeff : slv(LWIDTH-1 downto 0); -- effective led + dateff : slv(4*(2**DCWIDTH)-1 downto 0); -- effective dsp_dat + dpeff : slv((2**DCWIDTH)-1 downto 0); -- effective dsp_dp swi_en : slbit; -- enable: swi from rbus led_en : slbit; -- enable: led from rbus - dsp_en : slbit; -- enable: dsp_dat from rbus + dsp0_en : slbit; -- enable: dsp_dat lsb from rbus + dsp1_en : slbit; -- enable: dsp_dat msb from rbus dp_en : slbit; -- enable: dsp_dp from rbus end record regs_type; + constant swizero : slv(SWIDTH-1 downto 0) := (others=>'0'); constant btnzero : slv(BWIDTH-1 downto 0) := (others=>'0'); - + constant ledzero : slv(LWIDTH-1 downto 0) := (others=>'0'); + constant dpzero : slv((2**DCWIDTH)-1 downto 0) := (others=>'0'); + constant datzero : slv(4*(2**DCWIDTH)-1 downto 0) := (others=>'0'); + constant regs_init : regs_type := ( '0', -- rbsel - (others=>'0'), -- swi + swizero, -- swi btnzero, -- btn - (others=>'0'), -- led - (others=>'0'), -- dsp_dat - (others=>'0'), -- dsp_dp - (others=>'0'), -- ledin - (others=>'0'), -- swieff + ledzero, -- led + datzero, -- dsp_dat + dpzero, -- dsp_dp + ledzero, -- ledin + swizero, -- swieff btnzero, -- btneff - (others=>'0'), -- ledeff - (others=>'0'), -- dpeff - (others=>'0'), -- dateff - '0','0','0','0' -- (swi|led|dsp|dp)_en + ledzero, -- ledeff + datzero, -- dateff + dpzero, -- dpeff + '0','0','0','0','0' -- (swi|led|dsp0|dsp1|dp)_en ); signal R_REGS : regs_type := regs_init; -- state registers signal N_REGS : regs_type := regs_init; -- next value state regs - subtype cntl_rbf_btn is integer range BWIDTH+8-1 downto 8; - constant cntl_rbf_dsp_en: integer := 3; + subtype stat_rbf_hdig is integer range 14 downto 12; + subtype stat_rbf_hled is integer range 11 downto 8; + subtype stat_rbf_hbtn is integer range 7 downto 4; + subtype stat_rbf_hswi is integer range 3 downto 0; + + constant cntl_rbf_dsp1_en: integer := 4; + constant cntl_rbf_dsp0_en: integer := 3; constant cntl_rbf_dp_en: integer := 2; constant cntl_rbf_led_en: integer := 1; constant cntl_rbf_swi_en: integer := 0; - subtype led_rbf_dp is integer range 15 downto 12; - subtype led_rbf_led is integer range 7 downto 0; - constant rbaddr_cntl: slv2 := "00"; -- 0 r/w/- - constant rbaddr_swi: slv2 := "01"; -- 1 r/w/- - constant rbaddr_led: slv2 := "10"; -- 2 r/w/- - constant rbaddr_dsp: slv2 := "11"; -- 3 r/w/- + constant rbaddr_stat: slv3 := "000"; -- 0 r/-/- + constant rbaddr_cntl: slv3 := "001"; -- 0 r/w/- + constant rbaddr_btn: slv3 := "010"; -- 1 r/-/f + constant rbaddr_swi: slv3 := "011"; -- 1 r/w/- + constant rbaddr_led: slv3 := "100"; -- 2 r/w/- + constant rbaddr_dp: slv3 := "101"; -- 3 r/w/- + constant rbaddr_dsp0: slv3 := "110"; -- 4 r/w/- + constant rbaddr_dsp1: slv3 := "111"; -- 5 r/w/- - signal HIO_SWI : slv8 := (others=>'0'); + subtype dspdat_msb is integer range 4*(2**DCWIDTH)-1 downto 4*(2**DCWIDTH)-16; + subtype dspdat_lsb is integer range 15 downto 0; + + signal HIO_SWI : slv(SWIDTH-1 downto 0) := (others=>'0'); signal HIO_BTN : slv(BWIDTH-1 downto 0) := (others=>'0'); - signal HIO_LED : slv8 := (others=>'0'); - signal HIO_DSP_DAT : slv16 := (others=>'0'); - signal HIO_DSP_DP : slv4 := (others=>'0'); + signal HIO_LED : slv(LWIDTH-1 downto 0) := (others=>'0'); + signal HIO_DSP_DAT : slv(4*(2**DCWIDTH)-1 downto 0) := (others=>'0'); + signal HIO_DSP_DP : slv((2**DCWIDTH)-1 downto 0) := (others=>'0'); begin + assert SWIDTH<=16 + report "assert (SWIDTH<=16)" + severity failure; + assert BWIDTH<=8 + report "assert (BWIDTH<=8)" + severity failure; + assert LWIDTH<=16 + report "assert (LWIDTH<=16)" + severity failure; + + assert DCWIDTH=2 or DCWIDTH=3 + report "assert(DCWIDTH=2 or DCWIDTH=3): unsupported DCWIDTH" + severity FAILURE; + HIO : sn_humanio generic map ( + SWIDTH => SWIDTH, BWIDTH => BWIDTH, + LWIDTH => LWIDTH, + DCWIDTH => DCWIDTH, DEBOUNCE => DEBOUNCE) port map ( CLK => CLK, @@ -224,7 +273,7 @@ begin -- rbus address decoder n.rbsel := '0'; - if RB_MREQ.aval='1' and RB_MREQ.addr(15 downto 2)=RB_ADDR(15 downto 2) then + if RB_MREQ.aval='1' and RB_MREQ.addr(15 downto 3)=RB_ADDR(15 downto 3) then n.rbsel := '1'; end if; @@ -232,20 +281,35 @@ begin if r.rbsel = '1' then irb_ack := irbena; -- ack all accesses - case RB_MREQ.addr(1 downto 0) is - - when rbaddr_cntl => - irb_dout(cntl_rbf_btn) := HIO_BTN; - irb_dout(cntl_rbf_dsp_en) := r.dsp_en; - irb_dout(cntl_rbf_dp_en) := r.dp_en; - irb_dout(cntl_rbf_led_en) := r.led_en; - irb_dout(cntl_rbf_swi_en) := r.swi_en; + case RB_MREQ.addr(2 downto 0) is + + when rbaddr_stat => + irb_dout(stat_rbf_hdig) := slv(to_unsigned((2**DCWIDTH)-1,3)); + irb_dout(stat_rbf_hled) := slv(to_unsigned(LWIDTH-1,4)); + irb_dout(stat_rbf_hbtn) := slv(to_unsigned(BWIDTH-1,4)); + irb_dout(stat_rbf_hswi) := slv(to_unsigned(SWIDTH-1,4)); if RB_MREQ.we = '1' then - n.btn := RB_MREQ.din(cntl_rbf_btn); - n.dsp_en := RB_MREQ.din(cntl_rbf_dsp_en); - n.dp_en := RB_MREQ.din(cntl_rbf_dp_en); - n.led_en := RB_MREQ.din(cntl_rbf_led_en); - n.swi_en := RB_MREQ.din(cntl_rbf_swi_en); + irb_ack := '0'; + end if; + + when rbaddr_cntl => + irb_dout(cntl_rbf_dsp1_en) := r.dsp1_en; + irb_dout(cntl_rbf_dsp0_en) := r.dsp0_en; + irb_dout(cntl_rbf_dp_en) := r.dp_en; + irb_dout(cntl_rbf_led_en) := r.led_en; + irb_dout(cntl_rbf_swi_en) := r.swi_en; + if RB_MREQ.we = '1' then + n.dsp1_en := RB_MREQ.din(cntl_rbf_dsp1_en); + n.dsp0_en := RB_MREQ.din(cntl_rbf_dsp0_en); + n.dp_en := RB_MREQ.din(cntl_rbf_dp_en); + n.led_en := RB_MREQ.din(cntl_rbf_led_en); + n.swi_en := RB_MREQ.din(cntl_rbf_swi_en); + end if; + + when rbaddr_btn => + irb_dout(HIO_BTN'range) := HIO_BTN; + if RB_MREQ.we = '1' then + n.btn := RB_MREQ.din(n.btn'range); end if; when rbaddr_swi => @@ -255,20 +319,30 @@ begin end if; when rbaddr_led => - irb_dout(led_rbf_dp) := HIO_DSP_DP; - irb_dout(led_rbf_led) := r.ledin; + irb_dout(r.ledin'range) := r.ledin; if RB_MREQ.we = '1' then - n.dsp_dp := RB_MREQ.din(led_rbf_dp); - n.led := RB_MREQ.din(led_rbf_led); + n.led := RB_MREQ.din(n.led'range); end if; - when rbaddr_dsp => - irb_dout := HIO_DSP_DAT; + when rbaddr_dp => + irb_dout(HIO_DSP_DP'range) := HIO_DSP_DP; if RB_MREQ.we = '1' then - n.dsp_dat := RB_MREQ.din; + n.dsp_dp := RB_MREQ.din(n.dsp_dp'range); + end if; + + when rbaddr_dsp0 => + irb_dout := HIO_DSP_DAT(dspdat_lsb); + if RB_MREQ.we = '1' then + n.dsp_dat(dspdat_lsb) := RB_MREQ.din; end if; - when others => null; + when rbaddr_dsp1 => + irb_dout := HIO_DSP_DAT(dspdat_msb); + if RB_MREQ.we = '1' then + n.dsp_dat(dspdat_msb) := RB_MREQ.din; + end if; + + when others => null; end case; end if; @@ -293,10 +367,18 @@ begin n.dpeff := r.dsp_dp; end if; - if r.dsp_en = '0' then - n.dateff := DSP_DAT; + if r.dsp0_en = '0' then + n.dateff(dspdat_lsb) := DSP_DAT(dspdat_lsb); else - n.dateff := r.dsp_dat; + n.dateff(dspdat_lsb) := r.dsp_dat(dspdat_lsb); + end if; + + if DCWIDTH=3 then + if r.dsp1_en = '0' then + n.dateff(dspdat_msb) := DSP_DAT(dspdat_msb); + else + n.dateff(dspdat_msb) := r.dsp_dat(dspdat_msb); + end if; end if; N_REGS <= n; diff --git a/rtl/bplib/fx2lib/Makefile b/rtl/bplib/fx2lib/Makefile index d62b2a43..174b8dac 100644 --- a/rtl/bplib/fx2lib/Makefile +++ b/rtl/bplib/fx2lib/Makefile @@ -1,7 +1,8 @@ -# $Id: Makefile 575 2014-07-27 20:55:41Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment +# 2015-01-24 637 1.1.2 use nexys3 as default XTW_BOARD # 2014-07-27 545 1.1.1 make reference board configurable via XTW_BOARD # 2011-08-13 405 1.1 use includes from rtl/make # 2010-05-23 293 1.0 Initial version (cloned..) @@ -10,9 +11,9 @@ VBOM_all = $(wildcard *.vbom) NGC_all = $(VBOM_all:.vbom=.ngc) # ifndef XTW_BOARD - XTW_BOARD=nexys2 + XTW_BOARD=nexys3 endif -include $(RETROBASE)/rtl/make/xflow_default_$(XTW_BOARD).mk +include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # .PHONY : all clean # @@ -22,7 +23,7 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/bplib/fx2lib/fx2_2fifoctl_as.vbom b/rtl/bplib/fx2lib/fx2_2fifoctl_as.vbom deleted file mode 100644 index 0f7602b5..00000000 --- a/rtl/bplib/fx2lib/fx2_2fifoctl_as.vbom +++ /dev/null @@ -1,13 +0,0 @@ -# libs -../../vlib/slvtypes.vhd -../../vlib/xlib/xlib.vhd -../../vlib/memlib/memlib.vhd -fx2lib.vhd -# components -../../vlib/xlib/iob_reg_o.vbom -../../vlib/xlib/iob_reg_i_gen.vbom -../../vlib/xlib/iob_reg_o_gen.vbom -../../vlib/xlib/iob_reg_io_gen.vbom -../../vlib/memlib/fifo_1c_dram.vbom -# design -fx2_2fifoctl_as.vhd diff --git a/rtl/bplib/fx2lib/fx2_2fifoctl_as.vhd b/rtl/bplib/fx2lib/fx2_2fifoctl_as.vhd deleted file mode 100644 index 8422d3fb..00000000 --- a/rtl/bplib/fx2lib/fx2_2fifoctl_as.vhd +++ /dev/null @@ -1,647 +0,0 @@ --- $Id: fx2_2fifoctl_as.vhd 453 2012-01-15 17:51:18Z mueller $ --- --- Copyright 2011-2012 by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Module Name: fx2_2fifoctl_as - syn --- Description: Cypress EZ-USB FX2 driver (2 fifo; async) --- --- Dependencies: vlib/xlib/iob_reg_o --- vlib/xlib/iob_reg_i_gen --- vlib/xlib/iob_reg_o_gen --- vlib/xlib/iob_reg_io_gen --- memlib/fifo_1c_dram --- --- Test bench: - --- Target Devices: generic --- Tool versions: xst 12.1, 13.1, 13.3; ghdl 0.26-0.29 --- --- Synthesized (xst): --- Date Rev ise Target flop lutl lutm slic t peri --- 2012-01-14 453 13.3 O76x xc3s1200e-4 65 153 64 133 s 7.2 --- 2012-01-03 449 13.3 O76x xc3s1200e-4 67 149 64 133 s 7.2 --- 2011-12-25 445 13.3 O76x xc3s1200e-4 61 147 64 127 s 7.2 --- 2011-12-25 444 13.3 O76x xc3s1200e-4 54 140 64 123 s 7.2 --- 2011-07-07 389 12.1 M53d xc3s1200e-4 45 132 64 109 s 7.9 --- --- Revision History: --- Date Rev Version Comment --- 2012-01-14 453 1.3 common DELAY for PE and WR; use aempty/afull logic --- 2012-01-04 450 1.2.2 use new FLAG layout (EF,FF now fixed) --- 2012-01-03 449 1.2.1 use new fx2ctl_moni layout; hardcode ep's --- 2011-12-25 445 1.2 change pktend handling, now timer based --- 2011-11-25 433 1.1.1 now numeric_std clean --- 2011-07-30 400 1.1 capture rx data in 2nd last s_rdpwh cycle --- 2011-07-24 389 1.0.2 use FX2_FLAG_N to signal that flags are act.low --- 2011-07-17 394 1.0.1 (RX|TX)FIFOEP now generics; add MONI port --- 2011-07-08 390 1.0 Initial version --- ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -use work.slvtypes.all; -use work.xlib.all; -use work.memlib.all; -use work.fx2lib.all; - -entity fx2_2fifoctl_as is -- EZ-USB FX2 driver (2 fifo; async) - generic ( - RXFAWIDTH : positive := 5; -- receive fifo address width - TXFAWIDTH : positive := 5; -- transmit fifo address width - PETOWIDTH : positive := 7; -- packet end time-out counter width - CCWIDTH : positive := 5; -- chunk counter width - RXAEMPTY_THRES : natural := 1; -- threshold for rx aempty flag - TXAFULL_THRES : natural := 1; -- threshold for tx afull flag - RDPWLDELAY : positive := 5; -- slrd low delay in clock cycles - RDPWHDELAY : positive := 5; -- slrd high delay in clock cycles - WRPWLDELAY : positive := 5; -- slwr low delay in clock cycles - WRPWHDELAY : positive := 7; -- slwr high delay in clock cycles - FLAGDELAY : positive := 2); -- flag delay in clock cycles - port ( - CLK : in slbit; -- clock - CE_USEC : in slbit; -- 1 usec clock enable - RESET : in slbit := '0'; -- reset - RXDATA : out slv8; -- receive data out - RXVAL : out slbit; -- receive data valid - RXHOLD : in slbit; -- receive data hold - RXAEMPTY : out slbit; -- receive almost empty flag - TXDATA : in slv8; -- transmit data in - TXENA : in slbit; -- transmit data enable - TXBUSY : out slbit; -- transmit data busy - TXAFULL : out slbit; -- transmit almost full flag - MONI : out fx2ctl_moni_type; -- monitor port data - I_FX2_IFCLK : in slbit; -- fx2: interface clock - O_FX2_FIFO : out slv2; -- fx2: fifo address - I_FX2_FLAG : in slv4; -- fx2: fifo flags - O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low) - O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low) - O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low) - O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low) - IO_FX2_DATA : inout slv8 -- fx2: data lines - ); -end fx2_2fifoctl_as; - - -architecture syn of fx2_2fifoctl_as is - - constant c_rxfifo : slv2 := c_fifo_ep4; - constant c_txfifo : slv2 := c_fifo_ep6; - - constant c_flag_prog : integer := 0; - constant c_flag_tx_ff : integer := 1; - constant c_flag_rx_ef : integer := 2; - constant c_flag_tx2_ff : integer := 3; - - type state_type is ( - s_init, -- s_init: init state - s_rdprep, -- s_rdprep: prepare read - s_rdwait, -- s_rdwait: wait for data - s_rdpwl, -- s_rdpwl: read, strobe low - s_rdpwh, -- s_rdpwh: read, strobe high - s_wrprep, -- s_wrprep: prepare write - s_wrpwl, -- s_wrpwl: write, strobe low - s_wrpwh, -- s_wrpwh: write, strobe high - s_peprep, -- s_peprep: prepare pktend - s_pepwl, -- s_pepwl: pktend, strobe low - s_pepwh -- s_pepwh: pktend, strobe high - ); - - type regs_type is record - state : state_type; -- state - petocnt : slv(PETOWIDTH-1 downto 0); -- pktend time out counter - pepend : slbit; -- pktend pending - dlycnt : slv4; -- wait delay counter - moni_ep4_sel : slbit; -- ep4 (rx) select - moni_ep6_sel : slbit; -- ep6 (tx) select - moni_ep4_pf : slbit; -- ep4 (rx) prog flag - moni_ep6_pf : slbit; -- ep6 (rx) prog flag - end record regs_type; - - constant petocnt_init : slv(PETOWIDTH-1 downto 0) := (others=>'0'); - - constant regs_init : regs_type := ( - s_init, -- state - petocnt_init, -- petocnt - '0', -- pepend - (others=>'0'), -- cntdly - '0','0', -- moni_ep(4|6)_sel - '0','0' -- moni_ep(4|6)_pf - ); - - signal R_REGS : regs_type := regs_init; -- state registers - signal N_REGS : regs_type := regs_init; -- next value state regs - - signal FX2_FIFO : slv2 := (others=>'0'); - signal FX2_FIFO_CE : slbit := '0'; - signal FX2_FLAG_N : slv4 := (others=>'0'); - signal FX2_SLRD_N : slbit := '1'; - signal FX2_SLWR_N : slbit := '1'; - signal FX2_SLOE_N : slbit := '1'; - signal FX2_PKTEND_N : slbit := '1'; - signal FX2_DATA_CEI : slbit := '0'; - signal FX2_DATA_CEO : slbit := '0'; - signal FX2_DATA_OE : slbit := '0'; - - signal RXFIFO_DI : slv8 := (others=>'0'); - signal RXFIFO_ENA : slbit := '0'; - signal RXFIFO_BUSY : slbit := '0'; - signal RXSIZE : slv(RXFAWIDTH downto 0) := (others=>'0'); - signal TXFIFO_DO : slv8 := (others=>'0'); - signal TXFIFO_VAL : slbit := '0'; - signal TXFIFO_HOLD : slbit := '0'; - signal TXSIZE : slv(TXFAWIDTH downto 0) := (others=>'0'); - - signal TXBUSY_L : slbit := '0'; - -begin - - assert RDPWLDELAY<=2**R_REGS.dlycnt'length and - RDPWHDELAY<=2**R_REGS.dlycnt'length and RDPWHDELAY>=2 and - WRPWLDELAY<=2**R_REGS.dlycnt'length and - WRPWHDELAY<=2**R_REGS.dlycnt'length and - FLAGDELAY<=2**R_REGS.dlycnt'length - report "assert(*DELAY <= 2**dlycnt'length and RDPWHDELAY >=2)" - severity failure; - - assert RXAEMPTY_THRES<=2**RXFAWIDTH and - TXAFULL_THRES<=2**TXFAWIDTH - report "assert((RXAEMPTY|TXAFULL)_THRES <= 2**(RX|TX)FAWIDTH)" - severity failure; - - IOB_FX2_FIFO : iob_reg_o_gen - generic map ( - DWIDTH => 2, - INIT => '0') - port map ( - CLK => CLK, - CE => FX2_FIFO_CE, - DO => FX2_FIFO, - PAD => O_FX2_FIFO - ); - - IOB_FX2_FLAG : iob_reg_i_gen - generic map ( - DWIDTH => 4, - INIT => '0') - port map ( - CLK => CLK, - CE => '1', - DI => FX2_FLAG_N, - PAD => I_FX2_FLAG - ); - - IOB_FX2_SLRD : iob_reg_o - generic map ( - INIT => '1') - port map ( - CLK => CLK, - CE => '1', - DO => FX2_SLRD_N, - PAD => O_FX2_SLRD_N - ); - - IOB_FX2_SLWR : iob_reg_o - generic map ( - INIT => '1') - port map ( - CLK => CLK, - CE => '1', - DO => FX2_SLWR_N, - PAD => O_FX2_SLWR_N - ); - - IOB_FX2_SLOE : iob_reg_o - generic map ( - INIT => '1') - port map ( - CLK => CLK, - CE => '1', - DO => FX2_SLOE_N, - PAD => O_FX2_SLOE_N - ); - - IOB_FX2_PKTEND : iob_reg_o - generic map ( - INIT => '1') - port map ( - CLK => CLK, - CE => '1', - DO => FX2_PKTEND_N, - PAD => O_FX2_PKTEND_N - ); - - IOB_FX2_DATA : iob_reg_io_gen - generic map ( - DWIDTH => 8, - PULL => "KEEP") - port map ( - CLK => CLK, - CEI => FX2_DATA_CEI, - CEO => FX2_DATA_CEO, - OE => FX2_DATA_OE, - DI => RXFIFO_DI, -- input data (read from pad) - DO => TXFIFO_DO, -- output data (write to pad) - PAD => IO_FX2_DATA - ); - - RXFIFO : fifo_1c_dram -- input fifo, 1 clock, dram based - generic map ( - AWIDTH => RXFAWIDTH, - DWIDTH => 8) - port map ( - CLK => CLK, - RESET => RESET, - DI => RXFIFO_DI, - ENA => RXFIFO_ENA, - BUSY => RXFIFO_BUSY, - DO => RXDATA, - VAL => RXVAL, - HOLD => RXHOLD, - SIZE => RXSIZE - ); - - TXFIFO : fifo_1c_dram -- output fifo, 1 clock, dram based - generic map ( - AWIDTH => TXFAWIDTH, - DWIDTH => 8) - port map ( - CLK => CLK, - RESET => RESET, - DI => TXDATA, - ENA => TXENA, - BUSY => TXBUSY_L, - DO => TXFIFO_DO, - VAL => TXFIFO_VAL, - HOLD => TXFIFO_HOLD, - SIZE => TXSIZE - ); - - proc_regs: process (CLK) - begin - - if rising_edge(CLK) then - if RESET = '1' then - R_REGS <= regs_init; - else - R_REGS <= N_REGS; - end if; - end if; - - end process proc_regs; - - proc_next: process (R_REGS, CE_USEC, - FX2_FLAG_N, TXFIFO_VAL, RXFIFO_BUSY, TXBUSY_L) - - variable r : regs_type := regs_init; - variable n : regs_type := regs_init; - - variable idly_ld : slbit := '0'; - variable idly_val : slv(r.dlycnt'range) := (others=>'0'); - variable idly_end : slbit := '0'; - variable idly_end1 : slbit := '0'; - - variable iflag_rdok : slbit := '0'; - variable iflag_wrok : slbit := '0'; - - variable ififo_ce : slbit := '0'; - variable ififo : slv2 := "00"; - - variable irxfifo_ena : slbit := '0'; - variable itxfifo_hold : slbit := '0'; - - variable islrd : slbit := '0'; - variable islwr : slbit := '0'; - variable isloe : slbit := '0'; - variable ipktend : slbit := '0'; - - variable idata_cei : slbit := '0'; - variable idata_ceo : slbit := '0'; - variable idata_oe : slbit := '0'; - - variable imoni : fx2ctl_moni_type := fx2ctl_moni_init; - - procedure go_rdprep(nstate : out state_type; - idly_ld : out slbit; - idly_val : out slv4; - ififo_ce : out slbit; - ififo : out slv2) is - begin - idly_ld := '1'; - idly_val := slv(to_unsigned(FLAGDELAY-1, idly_val'length)); - ififo_ce := '1'; - ififo := c_rxfifo; - nstate := s_rdprep; - end procedure go_rdprep; - - procedure go_wrprep(nstate : out state_type; - idly_ld : out slbit; - idly_val : out slv4; - ififo_ce : out slbit; - ififo : out slv2) is - begin - idly_ld := '1'; - idly_val := slv(to_unsigned(FLAGDELAY-1, idly_val'length)); - ififo_ce := '1'; - ififo := c_txfifo; - nstate := s_wrprep; - end procedure go_wrprep; - - procedure go_peprep(nstate : out state_type; - idly_ld : out slbit; - idly_val : out slv4; - ififo_ce : out slbit; - ififo : out slv2) is - begin - idly_ld := '1'; - idly_val := slv(to_unsigned(FLAGDELAY-1, idly_val'length)); - ififo_ce := '1'; - ififo := c_txfifo; - nstate := s_peprep; - end procedure go_peprep; - - procedure go_rdpwl(nstate : out state_type; - idly_ld : out slbit; - idly_val : out slv4; - islrd : out slbit) is - begin - idly_ld := '1'; - idly_val := slv(to_unsigned(RDPWLDELAY-1, n.dlycnt'length)); - islrd := '1'; - nstate := s_rdpwl; - end procedure go_rdpwl; - - procedure go_wrpwl(nstate : out state_type; - idly_ld : out slbit; - idly_val : out slv4; - islwr : out slbit) is - begin - idly_ld := '1'; - idly_val := slv(to_unsigned(WRPWLDELAY-1, n.dlycnt'length)); - islwr := '1'; - nstate := s_wrpwl; - end procedure go_wrpwl; - - procedure go_pepwl(nstate : out state_type; - idly_ld : out slbit; - idly_val : out slv4; - ipktend : out slbit) is - begin - idly_ld := '1'; - idly_val := slv(to_unsigned(WRPWLDELAY-1, n.dlycnt'length)); - ipktend := '1'; - nstate := s_pepwl; - end procedure go_pepwl; - - begin - - r := R_REGS; - n := R_REGS; - - ififo_ce := '0'; - ififo := "00"; - - irxfifo_ena := '0'; - itxfifo_hold := '1'; - - islrd := '0'; - islwr := '0'; - isloe := '0'; - ipktend := '0'; - - idata_cei := '0'; - idata_ceo := '0'; - idata_oe := '0'; - - imoni := fx2ctl_moni_init; - - iflag_rdok := FX2_FLAG_N(c_flag_rx_ef); -- empty flag is act.low! - iflag_wrok := FX2_FLAG_N(c_flag_tx_ff); -- full flag is act.low! - - idly_ld := '0'; - idly_val := (others=>'0'); - idly_end := '1'; - idly_end1 := '0'; - if unsigned(r.dlycnt) /= 0 then - idly_end := '0'; - end if; - if unsigned(r.dlycnt) = 1 then - idly_end1 := '1'; - end if; - - case r.state is - when s_init => -- s_init: - go_rdprep(n.state, idly_ld, idly_val, ififo_ce, ififo); - - when s_rdprep => -- s_rdprep: prepare read - if idly_end = '1' then - n.state := s_rdwait; - end if; - - when s_rdwait => -- s_rdwait: wait for data - if r.pepend='1' and TXFIFO_VAL='0' then - go_peprep(n.state, idly_ld, idly_val, ififo_ce, ififo); - - elsif iflag_rdok='1' and - (RXFIFO_BUSY='0' and TXBUSY_L='0') then - go_rdpwl(n.state, idly_ld, idly_val, islrd); - - elsif TXFIFO_VAL = '1' then - go_wrprep(n.state, idly_ld, idly_val, ififo_ce, ififo); - end if; - - when s_rdpwl => -- s_rdpwl: read, strobe low - idata_cei := '1'; - isloe := '1'; - if idly_end = '1' then - idly_ld := '1'; - idly_val := slv(to_unsigned(RDPWHDELAY-1, n.dlycnt'length)); - n.state := s_rdpwh; - else - islrd := '1'; - n.state := s_rdpwl; - end if; - - -- Note: data is sampled and written into rxfifo in 2nd last cycle in the - -- last cycle the rxfifo busy reflects therefore last written byte - -- and safely indicates whether another byte will fit. - when s_rdpwh => -- s_rdpwh: read, strobe high - idata_cei := '1'; - isloe := '1'; - if idly_end1 = '1' then -- 2nd last cycle - irxfifo_ena := '1'; -- capture rxdata - end if; - if idly_end = '1' then -- last cycle - if iflag_rdok='1' and - (RXFIFO_BUSY='0' and TXBUSY_L='0') then - go_rdpwl(n.state, idly_ld, idly_val, islrd); - - elsif TXFIFO_VAL = '1' then - go_wrprep(n.state, idly_ld, idly_val, ififo_ce, ififo); - - else - n.state := s_rdwait; - end if; - end if; - - when s_wrprep => -- s_wrprep: prepare write - if idly_end = '1' then - if iflag_wrok = '1' then - go_wrpwl(n.state, idly_ld, idly_val, islwr); - else - go_rdprep(n.state, idly_ld, idly_val, ififo_ce, ififo); - end if; - end if; - - when s_wrpwl => -- s_wrpwl: write, strobe low - idata_ceo := '1'; - idata_oe := '1'; - if idly_end = '1' then - idata_ceo := '0'; - itxfifo_hold := '0'; - idly_ld := '1'; - idly_val := slv(to_unsigned(WRPWHDELAY-1, n.dlycnt'length)); - n.state := s_wrpwh; - else - islwr := '1'; - n.state := s_wrpwl; - end if; - - when s_wrpwh => -- s_wrpwh: write, strobe high - idata_oe := '1'; - if idly_end = '1' then - if iflag_wrok='1' and TXFIFO_VAL='1' then - go_wrpwl(n.state, idly_ld, idly_val, islwr); - elsif iflag_wrok='1' and r.pepend='1' and TXFIFO_VAL='0' then - go_pepwl(n.state, idly_ld, idly_val, ipktend); - else - go_rdprep(n.state, idly_ld, idly_val, ififo_ce, ififo); - end if; - end if; - - when s_peprep => -- s_peprep: prepare pktend - if idly_end = '1' then - if iflag_wrok = '1' then - go_pepwl(n.state, idly_ld, idly_val, ipktend); - else - go_rdprep(n.state, idly_ld, idly_val, ififo_ce, ififo); - end if; - end if; - - when s_pepwl => -- s_pepwl: pktend, strobe low - if idly_end = '1' then - idly_ld := '1'; - idly_val := slv(to_unsigned(WRPWHDELAY-1, n.dlycnt'length)); - n.state := s_pepwh; - else - ipktend := '1'; - n.state := s_pepwl; - end if; - - when s_pepwh => -- s_pepwh: pktend, strobe high - if idly_end = '1' then - n.pepend := '0'; - go_rdprep(n.state, idly_ld, idly_val, ififo_ce, ififo); - end if; - - when others => null; - end case; - - if idly_ld = '1' then - n.dlycnt := idly_val; - elsif idly_end = '0' then - n.dlycnt := slv(unsigned(r.dlycnt) - 1); - end if; - - -- pktend time-out handling: - -- if tx fifo is non-empty, set counter to max - -- if tx fifo is empty, count down every usec - -- on 1->0 transition queue pktend request - if TXFIFO_VAL = '1' then - n.petocnt := (others=>'1'); - else - if CE_USEC = '1' and unsigned(r.petocnt) /= 0 then - n.petocnt := slv(unsigned(r.petocnt) - 1); - if unsigned(r.petocnt) = 1 then - n.pepend := '1'; - end if; - end if; - end if; - - n.moni_ep4_sel := '0'; - n.moni_ep6_sel := '0'; - if r.state = s_wrprep or r.state = s_wrpwl or r.state = s_wrpwh or - r.state = s_peprep or r.state = s_pepwl or r.state = s_pepwh then - n.moni_ep6_sel := '1'; - n.moni_ep6_pf := not FX2_FLAG_N(c_flag_prog); - else - n.moni_ep4_sel := '1'; - n.moni_ep4_pf := not FX2_FLAG_N(c_flag_prog); - end if; - - imoni.fifo_ep4 := r.moni_ep4_sel; - imoni.fifo_ep6 := r.moni_ep6_sel; - imoni.flag_ep4_empty := not FX2_FLAG_N(c_flag_rx_ef); - imoni.flag_ep4_almost := r.moni_ep4_pf; - imoni.flag_ep6_full := not FX2_FLAG_N(c_flag_tx_ff); - imoni.flag_ep6_almost := r.moni_ep6_pf; - imoni.slrd := islrd; - imoni.slwr := islwr; - imoni.pktend := ipktend; - - N_REGS <= n; - - FX2_FIFO_CE <= ififo_ce; - FX2_FIFO <= ififo; - - FX2_SLRD_N <= not islrd; - FX2_SLWR_N <= not islwr; - FX2_SLOE_N <= not isloe; - FX2_PKTEND_N <= not ipktend; - - FX2_DATA_CEI <= idata_cei; - FX2_DATA_CEO <= idata_ceo; - FX2_DATA_OE <= idata_oe; - - RXFIFO_ENA <= irxfifo_ena; - TXFIFO_HOLD <= itxfifo_hold; - - MONI <= imoni; - - end process proc_next; - - proc_almost: process (RXSIZE, TXSIZE) - begin - - -- (rx|tx)size is the number of bytes in fifo - -- --> rxsize is number of bytes which can be read - -- --> 2**txfawidth-txsize is is number of bytes which can be written - - if unsigned(RXSIZE) <= RXAEMPTY_THRES then - RXAEMPTY <= '1'; - else - RXAEMPTY <= '0'; - end if; - - if unsigned(TXSIZE) >= 2**TXFAWIDTH-TXAFULL_THRES then - TXAFULL <= '1'; - else - TXAFULL <= '0'; - end if; - - end process proc_almost; - - TXBUSY <= TXBUSY_L; - -end syn; diff --git a/rtl/bplib/fx2lib/fx2_2fifoctl_ic.vhd b/rtl/bplib/fx2lib/fx2_2fifoctl_ic.vhd index ffef3c02..b53bc383 100644 --- a/rtl/bplib/fx2lib/fx2_2fifoctl_ic.vhd +++ b/rtl/bplib/fx2lib/fx2_2fifoctl_ic.vhd @@ -1,4 +1,4 @@ --- $Id: fx2_2fifoctl_ic.vhd 472 2013-01-06 14:39:10Z mueller $ +-- $Id: fx2_2fifoctl_ic.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2012-2013 by Walter F.J. Mueller -- @@ -23,7 +23,7 @@ -- -- Test bench: - -- Target Devices: generic --- Tool versions: xst 13.3; ghdl 0.29 +-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri diff --git a/rtl/bplib/fx2lib/fx2_3fifoctl_ic.vhd b/rtl/bplib/fx2lib/fx2_3fifoctl_ic.vhd index b7540957..cc1b2bdf 100644 --- a/rtl/bplib/fx2lib/fx2_3fifoctl_ic.vhd +++ b/rtl/bplib/fx2lib/fx2_3fifoctl_ic.vhd @@ -1,4 +1,4 @@ --- $Id: fx2_3fifoctl_ic.vhd 472 2013-01-06 14:39:10Z mueller $ +-- $Id: fx2_3fifoctl_ic.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2012-2013 by Walter F.J. Mueller -- @@ -23,7 +23,7 @@ -- -- Test bench: - -- Target Devices: generic --- Tool versions: xst 13.3; ghdl 0.29 +-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri diff --git a/rtl/bplib/fx2lib/fx2lib.vhd b/rtl/bplib/fx2lib/fx2lib.vhd index 1c4deb6b..9a346925 100644 --- a/rtl/bplib/fx2lib/fx2lib.vhd +++ b/rtl/bplib/fx2lib/fx2lib.vhd @@ -1,6 +1,6 @@ --- $Id: fx2lib.vhd 453 2012-01-15 17:51:18Z mueller $ +-- $Id: fx2lib.vhd 638 2015-01-25 22:01:38Z mueller $ -- --- Copyright 2011-2012 by Walter F.J. Mueller +-- Copyright 2011-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,10 +16,11 @@ -- Description: Cypress ez-usb fx2 support -- -- Dependencies: - --- Tool versions: xst 12.1, 13.1, 13.3; ghdl 0.26-0.29 +-- Tool versions: xst 12.1-14.7; ghdl 0.26-0.31 -- -- Revision History: -- Date Rev Version Comment +-- 2015-01-25 638 1.4 retire fx2_2fifoctl_as -- 2012-01-14 453 1.3 use afull/aempty logic instead of exporting size -- 2012-01-03 449 1.2.1 reorganize fx2ctl_moni; hardcode ep's -- 2012-01-01 448 1.2 add fx2_2fifoctl_ic @@ -65,43 +66,6 @@ package fx2lib is -- ------------------------------------- -component fx2_2fifoctl_as is -- EZ-USB FX2 driver (2 fifo; async) - generic ( - RXFAWIDTH : positive := 5; -- receive fifo address width - TXFAWIDTH : positive := 5; -- transmit fifo address width - PETOWIDTH : positive := 7; -- packet end time-out counter width - CCWIDTH : positive := 5; -- chunk counter width - RXAEMPTY_THRES : natural := 1; -- threshold for rx aempty flag - TXAFULL_THRES : natural := 1; -- threshold for tx afull flag - RDPWLDELAY : positive := 5; -- slrd low delay in clock cycles - RDPWHDELAY : positive := 5; -- slrd high delay in clock cycles - WRPWLDELAY : positive := 5; -- slwr low delay in clock cycles - WRPWHDELAY : positive := 7; -- slwr high delay in clock cycles - FLAGDELAY : positive := 2); -- flag delay in clock cycles - port ( - CLK : in slbit; -- clock - CE_USEC : in slbit; -- 1 usec clock enable - RESET : in slbit := '0'; -- reset - RXDATA : out slv8; -- receive data out - RXVAL : out slbit; -- receive data valid - RXHOLD : in slbit; -- receive data hold - RXAEMPTY : out slbit; -- receive almost empty flag - TXDATA : in slv8; -- transmit data in - TXENA : in slbit; -- transmit data enable - TXBUSY : out slbit; -- transmit data busy - TXAFULL : out slbit; -- transmit almost full flag - MONI : out fx2ctl_moni_type; -- monitor port data - I_FX2_IFCLK : in slbit; -- fx2: interface clock - O_FX2_FIFO : out slv2; -- fx2: fifo address - I_FX2_FLAG : in slv4; -- fx2: fifo flags - O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low) - O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low) - O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low) - O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low) - IO_FX2_DATA : inout slv8 -- fx2: data lines - ); -end component; - component fx2_2fifoctl_ic is -- EZ-USB FX2 driver (2 fifo; int clk) generic ( RXFAWIDTH : positive := 5; -- receive fifo address width diff --git a/rtl/bplib/fx2lib/tb/fx2_2fifo_core.vhd b/rtl/bplib/fx2lib/tb/fx2_2fifo_core.vhd index cb28ed49..1022ddea 100644 --- a/rtl/bplib/fx2lib/tb/fx2_2fifo_core.vhd +++ b/rtl/bplib/fx2lib/tb/fx2_2fifo_core.vhd @@ -1,4 +1,4 @@ --- $Id: fx2_2fifo_core.vhd 469 2013-01-05 12:29:44Z mueller $ +-- $Id: fx2_2fifo_core.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2013- by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: memlib/fifo_2c_dram -- Test bench: - -- Target Devices: generic --- Tool versions: xst 13.3; ghdl 0.29 +-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31 -- Revision History: -- Date Rev Version Comment -- 2013-01-04 469 1.0 Initial version diff --git a/rtl/bplib/fx2rlink/Makefile b/rtl/bplib/fx2rlink/Makefile index 5d5e1ceb..214305b8 100644 --- a/rtl/bplib/fx2rlink/Makefile +++ b/rtl/bplib/fx2rlink/Makefile @@ -1,7 +1,8 @@ -# $Id: Makefile 575 2014-07-27 20:55:41Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment +# 2015-01-24 637 1.0.2 use nexys3 as default XTW_BOARD # 2014-07-27 545 1.0.1 make reference board configurable via XTW_BOARD # 2013-04-20 509 1.0 Initial version (cloned..) # @@ -9,9 +10,9 @@ VBOM_all = $(wildcard *.vbom) NGC_all = $(VBOM_all:.vbom=.ngc) # ifndef XTW_BOARD - XTW_BOARD=nexys2 + XTW_BOARD=nexys3 endif -include $(RETROBASE)/rtl/make/xflow_default_$(XTW_BOARD).mk +include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # .PHONY : all clean # @@ -21,7 +22,7 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/bplib/fx2rlink/ioleds_sp1c_fx2.vhd b/rtl/bplib/fx2rlink/ioleds_sp1c_fx2.vhd index baae6371..a1a0c079 100644 --- a/rtl/bplib/fx2rlink/ioleds_sp1c_fx2.vhd +++ b/rtl/bplib/fx2rlink/ioleds_sp1c_fx2.vhd @@ -1,4 +1,4 @@ --- $Id: ioleds_sp1c_fx2.vhd 509 2013-04-21 20:46:20Z mueller $ +-- $Id: ioleds_sp1c_fx2.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2013- by Walter F.J. Mueller -- @@ -15,12 +15,12 @@ -- Module Name: ioleds_sp1c_fx2 - syn -- Description: io activity leds for rlink+serport_1clk+fx2_ic combo -- --- Dependencies: +-- Dependencies: genlib/led_pulse_stretch -- -- Test bench: - -- -- Target Devices: generic --- Tool versions: xst 13.1; ghdl 0.29 +-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/bplib/issi/Makefile b/rtl/bplib/issi/Makefile index d10a02db..58da1088 100644 --- a/rtl/bplib/issi/Makefile +++ b/rtl/bplib/issi/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -12,7 +12,7 @@ clean : ghdl_clean # #----- # -include $(RETROBASE)/rtl/make/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/bplib/issi/is61lv25616al.vhd b/rtl/bplib/issi/is61lv25616al.vhd index c56f4778..f463799d 100644 --- a/rtl/bplib/issi/is61lv25616al.vhd +++ b/rtl/bplib/issi/is61lv25616al.vhd @@ -1,4 +1,4 @@ --- $Id: is61lv25616al.vhd 427 2011-11-19 21:04:11Z mueller $ +-- $Id: is61lv25616al.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2007-2011 by Walter F.J. Mueller -- @@ -21,7 +21,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-11-19 427 1.0.2 now numeric_std clean diff --git a/rtl/bplib/micron/mt45w8mw16b.vhd b/rtl/bplib/micron/mt45w8mw16b.vhd index 1b1467e8..bb2b2283 100644 --- a/rtl/bplib/micron/mt45w8mw16b.vhd +++ b/rtl/bplib/micron/mt45w8mw16b.vhd @@ -1,4 +1,4 @@ --- $Id: mt45w8mw16b.vhd 427 2011-11-19 21:04:11Z mueller $ +-- $Id: mt45w8mw16b.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2010-2011 by Walter F.J. Mueller -- @@ -23,7 +23,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29 +-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-11-19 427 1.3.2 now numeric_std clean diff --git a/rtl/bplib/nexys2/Makefile b/rtl/bplib/nexys2/Makefile index d62b2a43..4df28ce4 100644 --- a/rtl/bplib/nexys2/Makefile +++ b/rtl/bplib/nexys2/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 575 2014-07-27 20:55:41Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -12,7 +12,7 @@ NGC_all = $(VBOM_all:.vbom=.ngc) ifndef XTW_BOARD XTW_BOARD=nexys2 endif -include $(RETROBASE)/rtl/make/xflow_default_$(XTW_BOARD).mk +include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # .PHONY : all clean # @@ -22,7 +22,7 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/bplib/nexys2/nexys2lib.vhd b/rtl/bplib/nexys2/nexys2lib.vhd index 5a046c4c..5fbdce55 100644 --- a/rtl/bplib/nexys2/nexys2lib.vhd +++ b/rtl/bplib/nexys2/nexys2lib.vhd @@ -1,4 +1,4 @@ --- $Id: nexys2lib.vhd 509 2013-04-21 20:46:20Z mueller $ +-- $Id: nexys2lib.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2010-2013 by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Nexys 2 components -- -- Dependencies: - --- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26-0.29 +-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/bplib/nexys2/tb/Makefile b/rtl/bplib/nexys2/tb/Makefile index c53bc6b5..91976da8 100644 --- a/rtl/bplib/nexys2/tb/Makefile +++ b/rtl/bplib/nexys2/tb/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 575 2014-07-27 20:55:41Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -17,7 +17,7 @@ EXE_all += tb_nexys2_fusp_cuff_dummy ifndef XTW_BOARD XTW_BOARD=nexys2 endif -include $(RETROBASE)/rtl/make/xflow_default_$(XTW_BOARD).mk +include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # .PHONY : all all_ssim all_tsim clean # @@ -29,9 +29,9 @@ clean : ise_clean ghdl_clean isim_clean # #----- # -include $(RETROBASE)/rtl/make/generic_ghdl.mk -include $(RETROBASE)/rtl/make/generic_isim.mk -include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_isim.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/bplib/nexys2/tb/tb_nexys2_core.vhd b/rtl/bplib/nexys2/tb/tb_nexys2_core.vhd index 8c6b8a2b..57fc897a 100644 --- a/rtl/bplib/nexys2/tb/tb_nexys2_core.vhd +++ b/rtl/bplib/nexys2/tb/tb_nexys2_core.vhd @@ -1,4 +1,4 @@ --- $Id: tb_nexys2_core.vhd 476 2013-01-26 22:23:53Z mueller $ +-- $Id: tb_nexys2_core.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2010-2011 by Walter F.J. Mueller -- @@ -20,7 +20,7 @@ -- To test: generic, any nexys2 target -- -- Target Devices: generic --- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29 +-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-11-26 433 1.1.1 remove O_FLA_CE_N from tb_nexys2_core diff --git a/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vhd b/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vhd index a74b6578..3b587107 100644 --- a/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vhd +++ b/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vhd @@ -1,4 +1,4 @@ --- $Id: tb_nexys2_fusp.vhd 476 2013-01-26 22:23:53Z mueller $ +-- $Id: tb_nexys2_fusp.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2010-2011 by Walter F.J. Mueller -- @@ -26,7 +26,7 @@ -- To test: generic, any nexys2_fusp_aif target -- -- Target Devices: generic --- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26-0.29 +-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vhd b/rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vhd index 350b039b..246f06cf 100644 --- a/rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vhd +++ b/rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vhd @@ -1,4 +1,4 @@ --- $Id: tb_nexys2_fusp_cuff.vhd 509 2013-04-21 20:46:20Z mueller $ +-- $Id: tb_nexys2_fusp_cuff.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2013- by Walter F.J. Mueller -- @@ -27,7 +27,7 @@ -- To test: generic, any nexys2_fusp_cuff_aif target -- -- Target Devices: generic --- Tool versions: xst 13.3; ghdl 0.29 +-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/bplib/nexys3/nexys3lib.vhd b/rtl/bplib/nexys3/nexys3lib.vhd index fb74fb8c..1c51b5d8 100644 --- a/rtl/bplib/nexys3/nexys3lib.vhd +++ b/rtl/bplib/nexys3/nexys3lib.vhd @@ -1,4 +1,4 @@ --- $Id: nexys3lib.vhd 509 2013-04-21 20:46:20Z mueller $ +-- $Id: nexys3lib.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2011-2013 by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Nexys 3 components -- -- Dependencies: - --- Tool versions: xst 13.1; ghdl 0.29 +-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/bplib/nexys3/tb/Makefile b/rtl/bplib/nexys3/tb/Makefile index 7f7a46e7..7d334b44 100644 --- a/rtl/bplib/nexys3/tb/Makefile +++ b/rtl/bplib/nexys3/tb/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 575 2014-07-27 20:55:41Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -11,7 +11,7 @@ EXE_all += tb_nexys3_fusp_cuff_dummy ifndef XTW_BOARD XTW_BOARD=nexys3 endif -include $(RETROBASE)/rtl/make/xflow_default_$(XTW_BOARD).mk +include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # .PHONY : all all_ssim all_tsim clean # @@ -23,9 +23,9 @@ clean : ise_clean ghdl_clean isim_clean # #----- # -include $(RETROBASE)/rtl/make/generic_ghdl.mk -include $(RETROBASE)/rtl/make/generic_isim.mk -include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_isim.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/bplib/nexys3/tb/tb_nexys3_core.vhd b/rtl/bplib/nexys3/tb/tb_nexys3_core.vhd index cc790c05..b8ee4f43 100644 --- a/rtl/bplib/nexys3/tb/tb_nexys3_core.vhd +++ b/rtl/bplib/nexys3/tb/tb_nexys3_core.vhd @@ -1,4 +1,4 @@ --- $Id: tb_nexys3_core.vhd 476 2013-01-26 22:23:53Z mueller $ +-- $Id: tb_nexys3_core.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -20,7 +20,7 @@ -- To test: generic, any nexys3 target -- -- Target Devices: generic --- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29 +-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-11-25 432 1.0 Initial version (derived from tb_nexys2_core) diff --git a/rtl/bplib/nexys3/tb/tb_nexys3_fusp.vhd b/rtl/bplib/nexys3/tb/tb_nexys3_fusp.vhd index 9ddd79ea..8b37b4e5 100644 --- a/rtl/bplib/nexys3/tb/tb_nexys3_fusp.vhd +++ b/rtl/bplib/nexys3/tb/tb_nexys3_fusp.vhd @@ -1,4 +1,4 @@ --- $Id: tb_nexys3_fusp.vhd 538 2013-10-06 17:21:25Z mueller $ +-- $Id: tb_nexys3_fusp.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2011-2013 by Walter F.J. Mueller -- @@ -26,7 +26,7 @@ -- To test: generic, any nexys3_fusp_aif target -- -- Target Devices: generic --- Tool versions: xst 13.1, 14.6; ghdl 0.29 +-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vhd b/rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vhd index 35db5b1a..ed54c4ca 100644 --- a/rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vhd +++ b/rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vhd @@ -1,4 +1,4 @@ --- $Id: tb_nexys3_fusp_cuff.vhd 538 2013-10-06 17:21:25Z mueller $ +-- $Id: tb_nexys3_fusp_cuff.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2013- by Walter F.J. Mueller -- @@ -27,7 +27,7 @@ -- To test: generic, any nexys3_fusp_cuff_aif target -- -- Target Devices: generic --- Tool versions: xst 13.1, 14.6; ghdl 0.29 +-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/bplib/nexys4/nexys4_pclk.xdc b/rtl/bplib/nexys4/nexys4_pclk.xdc new file mode 100644 index 00000000..c63e1cdf --- /dev/null +++ b/rtl/bplib/nexys4/nexys4_pclk.xdc @@ -0,0 +1,13 @@ +# $Id: nexys4_pclk.xdc 640 2015-02-01 09:56:53Z mueller $ +# +# Copyright 2015- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# Primary clocks for Nexys4 +# +# Revision History: +# Date Rev Version Comment +# 2015-01-25 639 1.0 Initial version +# + +create_clock -name I_CLK100 -period 10 -waveform {0 5} [get_ports I_CLK100] diff --git a/rtl/bplib/nexys4/nexys4_pins.xdc b/rtl/bplib/nexys4/nexys4_pins.xdc new file mode 100644 index 00000000..7f426076 --- /dev/null +++ b/rtl/bplib/nexys4/nexys4_pins.xdc @@ -0,0 +1,132 @@ +# -*- tcl -*- +# $Id: nexys4_pins.xdc 643 2015-02-07 17:41:53Z mueller $ +# +# Pin locks for Nexys 4 core functionality +# - USB UART +# - human I/O (switches, buttons, leds, display) +# +# Revision History: +# Date Rev Version Comment +# 2015-02-06 643 1.3 factor out cram +# 2015-02-01 641 1.2 separate I_BTNRST_N +# 2015-01-31 640 1.1 fix RTS/CTS +# 2013-10-12 539 1.0 Initial version (converted from ucf) +# + +# config setup -------------------------------------------------------------- +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] + +# clocks -- in bank 35 ------------------------------------------------------ +set_property PACKAGE_PIN e3 [get_ports {I_CLK100}] +set_property IOSTANDARD LVCMOS33 [get_ports {I_CLK100}] + +# +# USB UART Interface -- in bank 35 ------------------------------------------ +set_property PACKAGE_PIN c4 [get_ports {I_RXD}] +set_property PACKAGE_PIN d4 [get_ports {O_TXD}] +set_property PACKAGE_PIN d3 [get_ports {O_RTS_N}] +set_property PACKAGE_PIN e5 [get_ports {I_CTS_N}] + +set_property IOSTANDARD LVCMOS33 [get_ports {I_RXD O_TXD O_RTS_N I_CTS_N}] +set_property DRIVE 12 [get_ports {O_TXD O_RTS_N}] +set_property SLEW SLOW [get_ports {O_TXD O_RTS_N}] + +# +# switches -- in bank 34 ---------------------------------------------------- +set_property PACKAGE_PIN u9 [get_ports {I_SWI[0]}] +set_property PACKAGE_PIN u8 [get_ports {I_SWI[1]}] +set_property PACKAGE_PIN r7 [get_ports {I_SWI[2]}] +set_property PACKAGE_PIN r6 [get_ports {I_SWI[3]}] +set_property PACKAGE_PIN r5 [get_ports {I_SWI[4]}] +set_property PACKAGE_PIN v7 [get_ports {I_SWI[5]}] +set_property PACKAGE_PIN v6 [get_ports {I_SWI[6]}] +set_property PACKAGE_PIN v5 [get_ports {I_SWI[7]}] +set_property PACKAGE_PIN u4 [get_ports {I_SWI[8]}] +set_property PACKAGE_PIN v2 [get_ports {I_SWI[9]}] +set_property PACKAGE_PIN u2 [get_ports {I_SWI[10]}] +set_property PACKAGE_PIN t3 [get_ports {I_SWI[11]}] +set_property PACKAGE_PIN t1 [get_ports {I_SWI[12]}] +set_property PACKAGE_PIN r3 [get_ports {I_SWI[13]}] +set_property PACKAGE_PIN p3 [get_ports {I_SWI[14]}] +set_property PACKAGE_PIN p4 [get_ports {I_SWI[15]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {I_SWI[*]}] + +# +# buttons -- in bank 15+14 -------------------------------------------------- +# sequence: clockwise(U-R-D-L) - middle - reset +set_property PACKAGE_PIN f15 [get_ports {I_BTN[0]}] +set_property PACKAGE_PIN r10 [get_ports {I_BTN[1]}] +set_property PACKAGE_PIN v10 [get_ports {I_BTN[2]}] +set_property PACKAGE_PIN t16 [get_ports {I_BTN[3]}] +set_property PACKAGE_PIN e16 [get_ports {I_BTN[4]}] +set_property PACKAGE_PIN c12 [get_ports {I_BTNRST_N}] + +set_property IOSTANDARD LVCMOS33 [get_ports {I_BTN[*]}] +set_property IOSTANDARD LVCMOS33 [get_ports {I_BTNRST_N}] + +# +# LEDs -- in bank 34 -------------------------------------------------------- +set_property PACKAGE_PIN t8 [get_ports {O_LED[0]}] +set_property PACKAGE_PIN v9 [get_ports {O_LED[1]}] +set_property PACKAGE_PIN r8 [get_ports {O_LED[2]}] +set_property PACKAGE_PIN t6 [get_ports {O_LED[3]}] +set_property PACKAGE_PIN t5 [get_ports {O_LED[4]}] +set_property PACKAGE_PIN t4 [get_ports {O_LED[5]}] +set_property PACKAGE_PIN u7 [get_ports {O_LED[6]}] +set_property PACKAGE_PIN u6 [get_ports {O_LED[7]}] +set_property PACKAGE_PIN v4 [get_ports {O_LED[8]}] +set_property PACKAGE_PIN u3 [get_ports {O_LED[9]}] +set_property PACKAGE_PIN v1 [get_ports {O_LED[10]}] +set_property PACKAGE_PIN r1 [get_ports {O_LED[11]}] +set_property PACKAGE_PIN p5 [get_ports {O_LED[12]}] +set_property PACKAGE_PIN u1 [get_ports {O_LED[13]}] +set_property PACKAGE_PIN r2 [get_ports {O_LED[14]}] +set_property PACKAGE_PIN p2 [get_ports {O_LED[15]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {O_LED[*]}] +set_property DRIVE 12 [get_ports {O_LED[*]}] +set_property SLEW SLOW [get_ports {O_LED[*]}] + +# +# RGB-LEDs -- in bank 15+34+35 ---------------------------------------------- +set_property PACKAGE_PIN k5 [get_ports {O_RGBLED0[0]}] +set_property PACKAGE_PIN f13 [get_ports {O_RGBLED0[1]}] +set_property PACKAGE_PIN f6 [get_ports {O_RGBLED0[2]}] +set_property PACKAGE_PIN k6 [get_ports {O_RGBLED1[0]}] +set_property PACKAGE_PIN h6 [get_ports {O_RGBLED1[1]}] +set_property PACKAGE_PIN l16 [get_ports {O_RGBLED1[2]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {O_RGBLED0[*] O_RGBLED1[*]}] +set_property DRIVE 12 [get_ports {O_RGBLED0[*] O_RGBLED1[*]}] +set_property SLEW SLOW [get_ports {O_RGBLED0[*] O_RGBLED1[*]}] + +# +# 7 segment display -- in bank 34 ------------------------------------------- +set_property PACKAGE_PIN n6 [get_ports {O_ANO_N[0]}] +set_property PACKAGE_PIN m6 [get_ports {O_ANO_N[1]}] +set_property PACKAGE_PIN m3 [get_ports {O_ANO_N[2]}] +set_property PACKAGE_PIN n5 [get_ports {O_ANO_N[3]}] +set_property PACKAGE_PIN n2 [get_ports {O_ANO_N[4]}] +set_property PACKAGE_PIN n4 [get_ports {O_ANO_N[5]}] +set_property PACKAGE_PIN l1 [get_ports {O_ANO_N[6]}] +set_property PACKAGE_PIN m1 [get_ports {O_ANO_N[7]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {O_ANO_N[*]}] +set_property DRIVE 12 [get_ports {O_ANO_N[*]}] +set_property SLEW SLOW [get_ports {O_ANO_N[*]}] +# +set_property PACKAGE_PIN l3 [get_ports {O_SEG_N[0]}] +set_property PACKAGE_PIN n1 [get_ports {O_SEG_N[1]}] +set_property PACKAGE_PIN l5 [get_ports {O_SEG_N[2]}] +set_property PACKAGE_PIN l4 [get_ports {O_SEG_N[3]}] +set_property PACKAGE_PIN k3 [get_ports {O_SEG_N[4]}] +set_property PACKAGE_PIN m2 [get_ports {O_SEG_N[5]}] +set_property PACKAGE_PIN l6 [get_ports {O_SEG_N[6]}] +set_property PACKAGE_PIN m4 [get_ports {O_SEG_N[7]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {O_SEG_N[*]}] +set_property DRIVE 12 [get_ports {O_SEG_N[*]}] +set_property SLEW SLOW [get_ports {O_SEG_N[*]}] +# diff --git a/rtl/bplib/nexys4/nexys4_pins_cram.xdc b/rtl/bplib/nexys4/nexys4_pins_cram.xdc new file mode 100644 index 00000000..fc6984f2 --- /dev/null +++ b/rtl/bplib/nexys4/nexys4_pins_cram.xdc @@ -0,0 +1,90 @@ +# -*- tcl -*- +# $Id: nexys4_pins_cram.xdc 643 2015-02-07 17:41:53Z mueller $ +# +# Pin locks for Nexys 4 cram +# +# Revision History: +# Date Rev Version Comment +# 2015-02-06 643 1.0 Initial version (derived from nexys4_pins.xdc) +# + +# CRAM -- in bank 14+15 ----------------------------------------------------- +set_property PACKAGE_PIN l18 [get_ports {O_MEM_CE_N}] +set_property PACKAGE_PIN r11 [get_ports {O_MEM_WE_N}] +set_property PACKAGE_PIN h14 [get_ports {O_MEM_OE_N}] + +set_property IOSTANDARD LVCMOS33 [get_ports {O_MEM_CE_N O_MEM_WE_N O_MEM_OE_N}] +set_property DRIVE 12 [get_ports {O_MEM_CE_N O_MEM_WE_N O_MEM_OE_N}] +set_property SLEW FAST [get_ports {O_MEM_CE_N O_MEM_WE_N O_MEM_OE_N}] +# +set_property PACKAGE_PIN j15 [get_ports {O_MEM_BE_N[0]}] +set_property PACKAGE_PIN j13 [get_ports {O_MEM_BE_N[1]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {O_MEM_BE_N[*]}] +set_property DRIVE 12 [get_ports {O_MEM_BE_N[*]}] +set_property SLEW FAST [get_ports {O_MEM_BE_N[*]}] +# +set_property PACKAGE_PIN t13 [get_ports {O_MEM_ADV_N}] +set_property PACKAGE_PIN t15 [get_ports {O_MEM_CLK}] +set_property PACKAGE_PIN j14 [get_ports {O_MEM_CRE}] + +set_property IOSTANDARD LVCMOS33 [get_ports {O_MEM_ADV_N O_MEM_CLK O_MEM_CRE}] +set_property DRIVE 12 [get_ports {O_MEM_ADV_N O_MEM_CLK O_MEM_CRE}] +set_property SLEW FAST [get_ports {O_MEM_ADV_N O_MEM_CLK O_MEM_CRE}] + +# +set_property PACKAGE_PIN t14 [get_ports {I_MEM_WAIT}] +set_property IOSTANDARD LVCMOS33 [get_ports {I_MEM_WAIT}] + +# +set_property PACKAGE_PIN j18 [get_ports {O_MEM_ADDR[0]}] +set_property PACKAGE_PIN h17 [get_ports {O_MEM_ADDR[1]}] +set_property PACKAGE_PIN h15 [get_ports {O_MEM_ADDR[2]}] +set_property PACKAGE_PIN j17 [get_ports {O_MEM_ADDR[3]}] +set_property PACKAGE_PIN h16 [get_ports {O_MEM_ADDR[4]}] +set_property PACKAGE_PIN k15 [get_ports {O_MEM_ADDR[5]}] +set_property PACKAGE_PIN k13 [get_ports {O_MEM_ADDR[6]}] +set_property PACKAGE_PIN n15 [get_ports {O_MEM_ADDR[7]}] +set_property PACKAGE_PIN v16 [get_ports {O_MEM_ADDR[8]}] +set_property PACKAGE_PIN u14 [get_ports {O_MEM_ADDR[9]}] +set_property PACKAGE_PIN v14 [get_ports {O_MEM_ADDR[10]}] +set_property PACKAGE_PIN v12 [get_ports {O_MEM_ADDR[11]}] +set_property PACKAGE_PIN p14 [get_ports {O_MEM_ADDR[12]}] +set_property PACKAGE_PIN u16 [get_ports {O_MEM_ADDR[13]}] +set_property PACKAGE_PIN r15 [get_ports {O_MEM_ADDR[14]}] +set_property PACKAGE_PIN n14 [get_ports {O_MEM_ADDR[15]}] +set_property PACKAGE_PIN n16 [get_ports {O_MEM_ADDR[16]}] +set_property PACKAGE_PIN m13 [get_ports {O_MEM_ADDR[17]}] +set_property PACKAGE_PIN v17 [get_ports {O_MEM_ADDR[18]}] +set_property PACKAGE_PIN u17 [get_ports {O_MEM_ADDR[19]}] +set_property PACKAGE_PIN t10 [get_ports {O_MEM_ADDR[20]}] +set_property PACKAGE_PIN m16 [get_ports {O_MEM_ADDR[21]}] +set_property PACKAGE_PIN u13 [get_ports {O_MEM_ADDR[22]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {O_MEM_ADDR[*]}] +set_property DRIVE 8 [get_ports {O_MEM_ADDR[*]}] +set_property SLEW FAST [get_ports {O_MEM_ADDR[*]}] + +# +set_property PACKAGE_PIN r12 [get_ports {IO_MEM_DATA[0]}] +set_property PACKAGE_PIN t11 [get_ports {IO_MEM_DATA[1]}] +set_property PACKAGE_PIN u12 [get_ports {IO_MEM_DATA[2]}] +set_property PACKAGE_PIN r13 [get_ports {IO_MEM_DATA[3]}] +set_property PACKAGE_PIN u18 [get_ports {IO_MEM_DATA[4]}] +set_property PACKAGE_PIN r17 [get_ports {IO_MEM_DATA[5]}] +set_property PACKAGE_PIN t18 [get_ports {IO_MEM_DATA[6]}] +set_property PACKAGE_PIN r18 [get_ports {IO_MEM_DATA[7]}] +set_property PACKAGE_PIN f18 [get_ports {IO_MEM_DATA[8]}] +set_property PACKAGE_PIN g18 [get_ports {IO_MEM_DATA[9]}] +set_property PACKAGE_PIN g17 [get_ports {IO_MEM_DATA[10]}] +set_property PACKAGE_PIN m18 [get_ports {IO_MEM_DATA[11]}] +set_property PACKAGE_PIN m17 [get_ports {IO_MEM_DATA[12]}] +set_property PACKAGE_PIN p18 [get_ports {IO_MEM_DATA[13]}] +set_property PACKAGE_PIN n17 [get_ports {IO_MEM_DATA[14]}] +set_property PACKAGE_PIN p17 [get_ports {IO_MEM_DATA[15]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {IO_MEM_DATA[*]}] +set_property DRIVE 8 [get_ports {IO_MEM_DATA[*]}] +set_property SLEW SLOW [get_ports {IO_MEM_DATA[*]}] +set_property KEEPER true [get_ports {IO_MEM_DATA[*]}] +# diff --git a/rtl/bplib/nexys4/nexys4_setup.tcl b/rtl/bplib/nexys4/nexys4_setup.tcl new file mode 100644 index 00000000..2e76a06b --- /dev/null +++ b/rtl/bplib/nexys4/nexys4_setup.tcl @@ -0,0 +1,4 @@ +# $ Id: $ +# +set rvtb_part "xc7a100tcsg324-1" +set rvtb_board "nexys4" diff --git a/rtl/bplib/nexys4/nexys4lib.vhd b/rtl/bplib/nexys4/nexys4lib.vhd new file mode 100644 index 00000000..cb7f2c3c --- /dev/null +++ b/rtl/bplib/nexys4/nexys4lib.vhd @@ -0,0 +1,81 @@ +-- $Id: nexys4lib.vhd 643 2015-02-07 17:41:53Z mueller $ +-- +-- Copyright 2013-2015 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: nexys4lib +-- Description: Nexys 4 components +-- +-- Dependencies: - +-- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2015-02-06 643 1.2 factor out memory, add nexys4_cram_aif +-- 2015-02-01 641 1.1 drop nexys4_fusp_aif; separate I_BTNRST_N +-- 2013-09-21 534 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package nexys4lib is + +component nexys4_aif is -- NEXYS 4, abstract iface, base + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + O_RTS_N : out slbit; -- rx rts (board view; act.low) + I_CTS_N : in slbit; -- tx cts (board view; act.low) + I_SWI : in slv16; -- n4 switches + I_BTN : in slv5; -- n4 buttons + I_BTNRST_N : in slbit; -- n4 reset button + O_LED : out slv16; -- n4 leds + O_RGBLED0 : out slv3; -- n4 rgb-led 0 + O_RGBLED1 : out slv3; -- n4 rgb-led 1 + O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8 -- 7 segment disp: segments (act.low) + ); +end component; + +component nexys4_cram_aif is -- NEXYS 4, abstract iface, base+cram + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + O_RTS_N : out slbit; -- rx rts (board view; act.low) + I_CTS_N : in slbit; -- tx cts (board view; act.low) + I_SWI : in slv16; -- n4 switches + I_BTN : in slv5; -- n4 buttons + I_BTNRST_N : in slbit; -- n4 reset button + O_LED : out slv16; -- n4 leds + O_RGBLED0 : out slv3; -- n4 rgb-led 0 + O_RGBLED1 : out slv3; -- n4 rgb-led 1 + O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16 -- cram: data lines + ); +end component; + +end package nexys4lib; diff --git a/rtl/bplib/nexys4/tb/.cvsignore b/rtl/bplib/nexys4/tb/.cvsignore new file mode 100644 index 00000000..b4a99093 --- /dev/null +++ b/rtl/bplib/nexys4/tb/.cvsignore @@ -0,0 +1,5 @@ +tb_nexys4_dummy +tb_nexys4_cram_dummy +nexys4_dummy.ucf +nexys4_cram_dummy.ucf +*.dep_ucf_cpp diff --git a/rtl/bplib/nexys4/tb/Makefile.ise b/rtl/bplib/nexys4/tb/Makefile.ise new file mode 100644 index 00000000..6b0cd113 --- /dev/null +++ b/rtl/bplib/nexys4/tb/Makefile.ise @@ -0,0 +1,39 @@ +# $Id: Makefile.ise 648 2015-02-20 20:16:21Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2015-02-06 643 1.2 add nexys4_cram_aif +# 2015-02-01 641 1.1 drop nexys4_fusp_aif +# 2014-07-27 545 1.0.1 make reference board configurable via XTW_BOARD +# 2013-09-21 534 1.0 Initial version +# +EXE_all = tb_nexys4_dummy tb_nexys4_cram_dummy +# +ifndef XTW_BOARD + XTW_BOARD=nexys4 +endif +include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk +# +.PHONY : all all_ssim all_tsim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_tsim : $(EXE_all:=_tsim) +# +clean : ise_clean ghdl_clean isim_clean +# +#----- +# +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_isim.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(VBOM_all:.vbom=.dep_isim) +include $(wildcard *.o.dep_ghdl) +endif +# diff --git a/rtl/bplib/nexys4/tb/tb_nexys4.vbom b/rtl/bplib/nexys4/tb/tb_nexys4.vbom new file mode 100644 index 00000000..9cc7aa9c --- /dev/null +++ b/rtl/bplib/nexys4/tb/tb_nexys4.vbom @@ -0,0 +1,25 @@ +# Not meant for direct top level usage. Used with +# tb_nexys4_(....)[_ssim].vbom and config +# lines to generate the different cases. +# +# libs +../../../vlib/slvtypes.vhd +../../../vlib/rlink/rlinklib.vbom +../../../vlib/rlink/tb/rlinktblib.vhd +../../../vlib/serport/serportlib.vbom +../../../vlib/xlib/xlib.vhd +../nexys4lib.vhd +../../../vlib/simlib/simlib.vhd +../../../vlib/simlib/simbus.vhd +${sys_conf := sys_conf_sim.vhd} +# components +../../../vlib/simlib/simclk.vbom +../../../vlib/simlib/simclkcnt.vbom +../../../vlib/rlink/tb/tbcore_rlink.vbom +../../../vlib/xlib/s7_cmt_sfs_gsim.vbom +tb_nexys4_core.vbom +../../../vlib/serport/serport_uart_rxtx.vbom +${nexys4_aif := nexys4_dummy.vbom} +# design +tb_nexys4.vhd +@top:tb_nexys4 diff --git a/rtl/bplib/nexys4/tb/tb_nexys4.vhd b/rtl/bplib/nexys4/tb/tb_nexys4.vhd new file mode 100644 index 00000000..943ae2c9 --- /dev/null +++ b/rtl/bplib/nexys4/tb/tb_nexys4.vhd @@ -0,0 +1,189 @@ +-- $Id: tb_nexys4.vhd 643 2015-02-07 17:41:53Z mueller $ +-- +-- Copyright 2013-2015 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_nexys4 - sim +-- Description: Test bench for nexys4 (base) +-- +-- Dependencies: simlib/simclk +-- simlib/simclkcnt +-- rlink/tb/tbcore_rlink +-- xlib/s7_cmt_sfs +-- tb_nexys4_core +-- serport/serport_uart_rxtx +-- nexys4_aif [UUT] +-- +-- To test: generic, any nexys4_aif target +-- +-- Target Devices: generic +-- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2015-02-06 643 1.2 factor out memory +-- 2015-02-01 641 1.1 separate I_BTNRST_N +-- 2013-09-28 535 1.0.1 use proper clock manager +-- 2013-09-21 534 1.0 Initial version (derived from tb_nexys3) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.rlinklib.all; +use work.rlinktblib.all; +use work.serportlib.all; +use work.xlib.all; +use work.nexys4lib.all; +use work.simlib.all; +use work.simbus.all; +use work.sys_conf.all; + +entity tb_nexys4 is +end tb_nexys4; + +architecture sim of tb_nexys4 is + + signal CLKOSC : slbit := '0'; -- board clock (100 Mhz) + signal CLKCOM : slbit := '0'; -- communication clock + + signal CLK_STOP : slbit := '0'; + signal CLKCOM_CYCLE : integer := 0; + + signal RESET : slbit := '0'; + signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !! + signal RXDATA : slv8 := (others=>'0'); + signal RXVAL : slbit := '0'; + signal RXERR : slbit := '0'; + signal RXACT : slbit := '0'; + signal TXDATA : slv8 := (others=>'0'); + signal TXENA : slbit := '0'; + signal TXBUSY : slbit := '0'; + + signal I_RXD : slbit := '1'; + signal O_TXD : slbit := '1'; + signal O_RTS_N : slbit := '0'; + signal I_CTS_N : slbit := '0'; + signal I_SWI : slv16 := (others=>'0'); + signal I_BTN : slv5 := (others=>'0'); + signal I_BTNRST_N : slbit := '1'; + signal O_LED : slv16 := (others=>'0'); + signal O_RGBLED0 : slv3 := (others=>'0'); + signal O_RGBLED1 : slv3 := (others=>'0'); + signal O_ANO_N : slv8 := (others=>'0'); + signal O_SEG_N : slv8 := (others=>'0'); + + constant clock_period : time := 10 ns; + constant clock_offset : time := 200 ns; + +begin + + CLKGEN : simclk + generic map ( + PERIOD => clock_period, + OFFSET => clock_offset) + port map ( + CLK => CLKOSC, + CLK_STOP => CLK_STOP + ); + + CLKGEN_COM : s7_cmt_sfs + generic map ( + VCO_DIVIDE => sys_conf_clkser_vcodivide, + VCO_MULTIPLY => sys_conf_clkser_vcomultiply, + OUT_DIVIDE => sys_conf_clkser_outdivide, + CLKIN_PERIOD => 10.0, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clksys_gentype) + port map ( + CLKIN => CLKOSC, + CLKFX => CLKCOM, + LOCKED => open + ); + + CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE); + + TBCORE : tbcore_rlink + port map ( + CLK => CLKCOM, + CLK_STOP => CLK_STOP, + RX_DATA => TXDATA, + RX_VAL => TXENA, + RX_HOLD => TXBUSY, + TX_DATA => RXDATA, + TX_ENA => RXVAL + ); + + N4CORE : entity work.tb_nexys4_core + port map ( + I_SWI => I_SWI, + I_BTN => I_BTN, + I_BTNRST_N => I_BTNRST_N + ); + + UUT : nexys4_aif + port map ( + I_CLK100 => CLKOSC, + I_RXD => I_RXD, + O_TXD => O_TXD, + O_RTS_N => O_RTS_N, + I_CTS_N => I_CTS_N, + I_SWI => I_SWI, + I_BTN => I_BTN, + I_BTNRST_N => I_BTNRST_N, + O_LED => O_LED, + O_RGBLED0 => O_RGBLED0, + O_RGBLED1 => O_RGBLED1, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + UART : serport_uart_rxtx + generic map ( + CDWIDTH => CLKDIV'length) + port map ( + CLK => CLKCOM, + RESET => RESET, + CLKDIV => CLKDIV, + RXSD => O_TXD, + RXDATA => RXDATA, + RXVAL => RXVAL, + RXERR => RXERR, + RXACT => RXACT, + TXSD => I_RXD, + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY + ); + + proc_moni: process + variable oline : line; + begin + + loop + wait until rising_edge(CLKCOM); + + if RXERR = '1' then + writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1"); + writeline(output, oline); + end if; + + end loop; + + end process proc_moni; + +end sim; diff --git a/rtl/bplib/nexys4/tb/tb_nexys4_core.vbom b/rtl/bplib/nexys4/tb/tb_nexys4_core.vbom new file mode 100644 index 00000000..1c980cc1 --- /dev/null +++ b/rtl/bplib/nexys4/tb/tb_nexys4_core.vbom @@ -0,0 +1,9 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/serport/serportlib.vbom +../../../vlib/simlib/simbus.vhd +# components +../../../vlib/serport/serport_uart_rx.vbom +../../../vlib/serport/serport_uart_tx.vbom +# design +tb_nexys4_core.vhd diff --git a/rtl/bplib/nexys4/tb/tb_nexys4_core.vhd b/rtl/bplib/nexys4/tb/tb_nexys4_core.vhd new file mode 100644 index 00000000..592275d0 --- /dev/null +++ b/rtl/bplib/nexys4/tb/tb_nexys4_core.vhd @@ -0,0 +1,77 @@ +-- $Id: tb_nexys4_core.vhd 643 2015-02-07 17:41:53Z mueller $ +-- +-- Copyright 2013-2015 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_nexys4_core - sim +-- Description: Test bench for nexys4 - core device handling +-- +-- Dependencies: - +-- +-- To test: generic, any nexys4 target +-- +-- Target Devices: generic +-- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31 +-- Revision History: +-- Date Rev Version Comment +-- 2015-02-06 643 1.2 factor out memory +-- 2015-02-01 641 1.1 separate I_BTNRST_N +-- 2013-09-21 534 1.0 Initial version (derived from tb_nexys3_core) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.serportlib.all; +use work.simbus.all; + +entity tb_nexys4_core is + port ( + I_SWI : out slv16; -- n4 switches + I_BTN : out slv5; -- n4 buttons + I_BTNRST_N : out slbit -- n4 reset button + ); +end tb_nexys4_core; + +architecture sim of tb_nexys4_core is + + signal R_SWI : slv16 := (others=>'0'); + signal R_BTN : slv5 := (others=>'0'); + signal R_BTNRST : slbit := '0'; + + constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8)); + constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8)); + +begin + + proc_simbus: process (SB_VAL) + begin + if SB_VAL'event and to_x01(SB_VAL)='1' then + if SB_ADDR = sbaddr_swi then + R_SWI <= to_x01(SB_DATA(R_SWI'range)); + end if; + if SB_ADDR = sbaddr_btn then + R_BTN <= to_x01(SB_DATA(R_BTN'range)); + R_BTNRST <= to_x01(SB_DATA(5)); + end if; + end if; + end process proc_simbus; + + I_SWI <= R_SWI; + I_BTN <= R_BTN; + I_BTNRST_N <= not R_BTNRST; + +end sim; diff --git a/rtl/bplib/nexys4/tb/tb_nexys4_cram.vbom b/rtl/bplib/nexys4/tb/tb_nexys4_cram.vbom new file mode 100644 index 00000000..82437874 --- /dev/null +++ b/rtl/bplib/nexys4/tb/tb_nexys4_cram.vbom @@ -0,0 +1,26 @@ +# Not meant for direct top level usage. Used with +# tb_nexys4_(....)[_ssim].vbom and config +# lines to generate the different cases. +# +# libs +../../../vlib/slvtypes.vhd +../../../vlib/rlink/rlinklib.vbom +../../../vlib/rlink/tb/rlinktblib.vhd +../../../vlib/serport/serportlib.vbom +../../../vlib/xlib/xlib.vhd +../nexys4lib.vhd +../../../vlib/simlib/simlib.vhd +../../../vlib/simlib/simbus.vhd +${sys_conf := sys_conf_sim.vhd} +# components +../../../vlib/simlib/simclk.vbom +../../../vlib/simlib/simclkcnt.vbom +../../../vlib/rlink/tb/tbcore_rlink.vbom +../../../vlib/xlib/s7_cmt_sfs_gsim.vbom +tb_nexys4_core.vbom +../../micron/mt45w8mw16b.vbom +../../../vlib/serport/serport_uart_rxtx.vbom +${nexys4_cram_aif := nexys4_cram_dummy.vbom} +# design +tb_nexys4_cram.vhd +@top:tb_nexys4_cram diff --git a/rtl/bplib/nexys4/tb/tb_nexys4_cram.vhd b/rtl/bplib/nexys4/tb/tb_nexys4_cram.vhd new file mode 100644 index 00000000..303b53db --- /dev/null +++ b/rtl/bplib/nexys4/tb/tb_nexys4_cram.vhd @@ -0,0 +1,224 @@ +-- $Id: tb_nexys4_cram.vhd 643 2015-02-07 17:41:53Z mueller $ +-- +-- Copyright 2013-2015 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_nexys4_cram - sim +-- Description: Test bench for nexys4 (base+cram) +-- +-- Dependencies: simlib/simclk +-- simlib/simclkcnt +-- rlink/tb/tbcore_rlink +-- xlib/s7_cmt_sfs +-- tb_nexys4_core +-- serport/serport_uart_rxtx +-- nexys4_cram_aif [UUT] +-- vlib/parts/micron/mt45w8mw16b +-- +-- To test: generic, any nexys4_cram_aif target +-- +-- Target Devices: generic +-- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2015-02-01 641 1.1 separate I_BTNRST_N +-- 2013-09-28 535 1.0.1 use proper clock manager +-- 2013-09-21 534 1.0 Initial version (derived from tb_nexys3) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.rlinklib.all; +use work.rlinktblib.all; +use work.serportlib.all; +use work.xlib.all; +use work.nexys4lib.all; +use work.simlib.all; +use work.simbus.all; +use work.sys_conf.all; + +entity tb_nexys4_cram is +end tb_nexys4_cram; + +architecture sim of tb_nexys4_cram is + + signal CLKOSC : slbit := '0'; -- board clock (100 Mhz) + signal CLKCOM : slbit := '0'; -- communication clock + + signal CLK_STOP : slbit := '0'; + signal CLKCOM_CYCLE : integer := 0; + + signal RESET : slbit := '0'; + signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !! + signal RXDATA : slv8 := (others=>'0'); + signal RXVAL : slbit := '0'; + signal RXERR : slbit := '0'; + signal RXACT : slbit := '0'; + signal TXDATA : slv8 := (others=>'0'); + signal TXENA : slbit := '0'; + signal TXBUSY : slbit := '0'; + + signal I_RXD : slbit := '1'; + signal O_TXD : slbit := '1'; + signal O_RTS_N : slbit := '0'; + signal I_CTS_N : slbit := '0'; + signal I_SWI : slv16 := (others=>'0'); + signal I_BTN : slv5 := (others=>'0'); + signal I_BTNRST_N : slbit := '1'; + signal O_LED : slv16 := (others=>'0'); + signal O_RGBLED0 : slv3 := (others=>'0'); + signal O_RGBLED1 : slv3 := (others=>'0'); + signal O_ANO_N : slv8 := (others=>'0'); + signal O_SEG_N : slv8 := (others=>'0'); + signal O_MEM_CE_N : slbit := '1'; + signal O_MEM_BE_N : slv2 := (others=>'1'); + signal O_MEM_WE_N : slbit := '1'; + signal O_MEM_OE_N : slbit := '1'; + signal O_MEM_ADV_N : slbit := '1'; + signal O_MEM_CLK : slbit := '0'; + signal O_MEM_CRE : slbit := '0'; + signal I_MEM_WAIT : slbit := '0'; + signal O_MEM_ADDR : slv23 := (others=>'Z'); + signal IO_MEM_DATA : slv16 := (others=>'0'); + + constant clock_period : time := 10 ns; + constant clock_offset : time := 200 ns; + +begin + + CLKGEN : simclk + generic map ( + PERIOD => clock_period, + OFFSET => clock_offset) + port map ( + CLK => CLKOSC, + CLK_STOP => CLK_STOP + ); + + CLKGEN_COM : s7_cmt_sfs + generic map ( + VCO_DIVIDE => sys_conf_clkser_vcodivide, + VCO_MULTIPLY => sys_conf_clkser_vcomultiply, + OUT_DIVIDE => sys_conf_clkser_outdivide, + CLKIN_PERIOD => 10.0, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clksys_gentype) + port map ( + CLKIN => CLKOSC, + CLKFX => CLKCOM, + LOCKED => open + ); + + CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE); + + TBCORE : tbcore_rlink + port map ( + CLK => CLKCOM, + CLK_STOP => CLK_STOP, + RX_DATA => TXDATA, + RX_VAL => TXENA, + RX_HOLD => TXBUSY, + TX_DATA => RXDATA, + TX_ENA => RXVAL + ); + + N4CORE : entity work.tb_nexys4_core + port map ( + I_SWI => I_SWI, + I_BTN => I_BTN, + I_BTNRST_N => I_BTNRST_N + ); + + UUT : nexys4_cram_aif + port map ( + I_CLK100 => CLKOSC, + I_RXD => I_RXD, + O_TXD => O_TXD, + O_RTS_N => O_RTS_N, + I_CTS_N => I_CTS_N, + I_SWI => I_SWI, + I_BTN => I_BTN, + I_BTNRST_N => I_BTNRST_N, + O_LED => O_LED, + O_RGBLED0 => O_RGBLED0, + O_RGBLED1 => O_RGBLED1, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N, + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + MEM : entity work.mt45w8mw16b + port map ( + CLK => O_MEM_CLK, + CE_N => O_MEM_CE_N, + OE_N => O_MEM_OE_N, + WE_N => O_MEM_WE_N, + UB_N => O_MEM_BE_N(1), + LB_N => O_MEM_BE_N(0), + ADV_N => O_MEM_ADV_N, + CRE => O_MEM_CRE, + MWAIT => I_MEM_WAIT, + ADDR => O_MEM_ADDR, + DATA => IO_MEM_DATA + ); + + UART : serport_uart_rxtx + generic map ( + CDWIDTH => CLKDIV'length) + port map ( + CLK => CLKCOM, + RESET => RESET, + CLKDIV => CLKDIV, + RXSD => O_TXD, + RXDATA => RXDATA, + RXVAL => RXVAL, + RXERR => RXERR, + RXACT => RXACT, + TXSD => I_RXD, + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY + ); + + proc_moni: process + variable oline : line; + begin + + loop + wait until rising_edge(CLKCOM); + + if RXERR = '1' then + writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1"); + writeline(output, oline); + end if; + + end loop; + + end process proc_moni; + +end sim; diff --git a/rtl/bplib/nxcramlib/Makefile b/rtl/bplib/nxcramlib/Makefile index e62e9773..cc4063d0 100644 --- a/rtl/bplib/nxcramlib/Makefile +++ b/rtl/bplib/nxcramlib/Makefile @@ -1,7 +1,8 @@ -# $Id: Makefile 575 2014-07-27 20:55:41Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment +# 2015-01-24 637 1.0.2 use nexys3 as default XTW_BOARD # 2014-07-27 545 1.0.1 make reference board configurable via XTW_BOARD # 2011-11-26 433 1.0 Initial version (cloned..) # @@ -9,9 +10,9 @@ VBOM_all = $(wildcard *.vbom) NGC_all = $(VBOM_all:.vbom=.ngc) # ifndef XTW_BOARD - XTW_BOARD=nexys2 + XTW_BOARD=nexys3 endif -include $(RETROBASE)/rtl/make/xflow_default_$(XTW_BOARD).mk +include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # .PHONY : all clean # @@ -21,7 +22,7 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/bplib/nxcramlib/nx_cram_dummy.vhd b/rtl/bplib/nxcramlib/nx_cram_dummy.vhd index aba7958d..1f88df2b 100644 --- a/rtl/bplib/nxcramlib/nx_cram_dummy.vhd +++ b/rtl/bplib/nxcramlib/nx_cram_dummy.vhd @@ -1,4 +1,4 @@ --- $Id: nx_cram_dummy.vhd 433 2011-11-27 22:04:39Z mueller $ +-- $Id: nx_cram_dummy.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2010-2011 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29 +-- Tool versions: ise 11.4-14.7; viv 2014.4; ghdl 0.26-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-11-26 433 1.2 renamed from n2_cram_dummy diff --git a/rtl/bplib/nxcramlib/nx_cram_memctl_as.vhd b/rtl/bplib/nxcramlib/nx_cram_memctl_as.vhd index 48496cda..7957ede2 100644 --- a/rtl/bplib/nxcramlib/nx_cram_memctl_as.vhd +++ b/rtl/bplib/nxcramlib/nx_cram_memctl_as.vhd @@ -1,4 +1,4 @@ --- $Id: nx_cram_memctl_as.vhd 563 2014-06-22 15:49:09Z mueller $ +-- $Id: nx_cram_memctl_as.vhd 644 2015-02-08 22:56:54Z mueller $ -- -- Copyright 2010-2011 by Walter F.J. Mueller -- @@ -21,7 +21,7 @@ -- Test bench: tb/tb_nx_cram_memctl_as -- sys_gen/tst_sram/nexys2/tb/tb_tst_sram_n2 -- Target Devices: generic --- Tool versions: xst 11.4, 13.1; ghdl 0.26 +-- Tool versions: ise 11.4-14.7; viv 2014.4; ghdl 0.26-0.31 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri @@ -182,7 +182,7 @@ architecture syn of nx_cram_memctl_as is end record regs_type; constant regs_init : regs_type := ( - s_idle, -- + s_idle, -- state '0', -- ackr '0', -- addr0 "00", -- be2nd diff --git a/rtl/bplib/nxcramlib/nxcramlib.vhd b/rtl/bplib/nxcramlib/nxcramlib.vhd index 6abd4b9f..1e03a5a1 100644 --- a/rtl/bplib/nxcramlib/nxcramlib.vhd +++ b/rtl/bplib/nxcramlib/nxcramlib.vhd @@ -1,4 +1,4 @@ --- $Id: nxcramlib.vhd 433 2011-11-27 22:04:39Z mueller $ +-- $Id: nxcramlib.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Nexys 2/3 CRAM drivers -- -- Dependencies: - --- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26-0.29 +-- Tool versions: ise 11.4-14.7; viv 2014.4; ghdl 0.26-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/bplib/nxcramlib/tb/Makefile b/rtl/bplib/nxcramlib/tb/Makefile index d25390da..9930caf8 100644 --- a/rtl/bplib/nxcramlib/tb/Makefile +++ b/rtl/bplib/nxcramlib/tb/Makefile @@ -1,16 +1,17 @@ -# $Id: Makefile 575 2014-07-27 20:55:41Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment +# 2015-01-24 637 1.0.2 use nexys3 as default XTW_BOARD # 2014-07-27 545 1.0.1 make reference board configurable via XTW_BOARD # 2011-11-26 433 1.0 Initial version (cloned) # EXE_all = tb_nx_cram_memctl_as # ifndef XTW_BOARD - XTW_BOARD=nexys2 + XTW_BOARD=nexys3 endif -include $(RETROBASE)/rtl/make/xflow_default_$(XTW_BOARD).mk +include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # .PHONY : all all_ssim all_tsim clean # @@ -22,9 +23,9 @@ clean : ise_clean ghdl_clean isim_clean # #----- # -include $(RETROBASE)/rtl/make/generic_ghdl.mk -include $(RETROBASE)/rtl/make/generic_isim.mk -include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_isim.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl.vhd b/rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl.vhd index 08110592..b9637d7f 100644 --- a/rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl.vhd +++ b/rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl.vhd @@ -1,4 +1,4 @@ --- $Id: tb_nx_cram_memctl.vhd 444 2011-12-25 10:04:58Z mueller $ +-- $Id: tb_nx_cram_memctl.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2010-2011 by Walter F.J. Mueller -- @@ -23,7 +23,7 @@ -- To test: nx_cram_memctl_as (via tbd_nx_cram_memctl_as) -- -- Target Devices: generic --- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29 +-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-12-23 444 1.4 use new simclk/simclkcnt diff --git a/rtl/bplib/nxcramlib/tb/tbd_nx_cram_memctl_as.vhd b/rtl/bplib/nxcramlib/tb/tbd_nx_cram_memctl_as.vhd index b76a3ad2..37a70435 100644 --- a/rtl/bplib/nxcramlib/tb/tbd_nx_cram_memctl_as.vhd +++ b/rtl/bplib/nxcramlib/tb/tbd_nx_cram_memctl_as.vhd @@ -1,4 +1,4 @@ --- $Id: tbd_nx_cram_memctl_as.vhd 433 2011-11-27 22:04:39Z mueller $ +-- $Id: tbd_nx_cram_memctl_as.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2010-2011 by Walter F.J. Mueller -- @@ -27,7 +27,7 @@ -- 2010-06-03 299 11.4 L68 xc3s1200e-4 91 122 0 107 t 11.4 -- 2010-05-30 297 11.4 L68 xc3s1200e-4 91 99 0 95 t 13.1 -- --- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29 +-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-11-26 433 1.2 renamed from tbd_n2_cram_memctl_as diff --git a/rtl/bplib/s3board/Makefile b/rtl/bplib/s3board/Makefile index b56e89d5..7864f63d 100644 --- a/rtl/bplib/s3board/Makefile +++ b/rtl/bplib/s3board/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 575 2014-07-27 20:55:41Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -13,7 +13,7 @@ NGC_all = $(VBOM_all:.vbom=.ngc) ifndef XTW_BOARD XTW_BOARD=s3board endif -include $(RETROBASE)/rtl/make/xflow_default_$(XTW_BOARD).mk +include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # .PHONY : all clean # @@ -23,7 +23,7 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/bplib/s3board/s3_sram_dummy.vhd b/rtl/bplib/s3board/s3_sram_dummy.vhd index 0323d887..57f920b0 100644 --- a/rtl/bplib/s3board/s3_sram_dummy.vhd +++ b/rtl/bplib/s3board/s3_sram_dummy.vhd @@ -1,4 +1,4 @@ --- $Id: s3_sram_dummy.vhd 426 2011-11-18 18:14:08Z mueller $ +-- $Id: s3_sram_dummy.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2007-2010 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26 +-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2010-04-17 278 1.0.2 renamed from sram_dummy diff --git a/rtl/bplib/s3board/s3_sram_memctl.vhd b/rtl/bplib/s3board/s3_sram_memctl.vhd index f7d60ce2..b72242c8 100644 --- a/rtl/bplib/s3board/s3_sram_memctl.vhd +++ b/rtl/bplib/s3board/s3_sram_memctl.vhd @@ -1,4 +1,4 @@ --- $Id: s3_sram_memctl.vhd 427 2011-11-19 21:04:11Z mueller $ +-- $Id: s3_sram_memctl.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2007-2011 by Walter F.J. Mueller -- @@ -21,7 +21,7 @@ -- Test bench: tb/tb_s3_sram_memctl -- fw_gen/tst_sram/s3board/tb/tb_tst_sram_s3 -- Target Devices: generic --- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri @@ -124,7 +124,7 @@ architecture syn of s3_sram_memctl is end record regs_type; constant regs_init : regs_type := ( - s_idle, + s_idle, -- state '0' -- ackr ); diff --git a/rtl/bplib/s3board/s3boardlib.vhd b/rtl/bplib/s3board/s3boardlib.vhd index b92dbe39..01feec62 100644 --- a/rtl/bplib/s3board/s3boardlib.vhd +++ b/rtl/bplib/s3board/s3boardlib.vhd @@ -1,4 +1,4 @@ --- $Id: s3boardlib.vhd 426 2011-11-18 18:14:08Z mueller $ +-- $Id: s3boardlib.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2007-2011 by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: S3BOARD components -- -- Dependencies: - --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-07-09 391 1.3.5 move s3_rs232_iob_int_ext to bpgenlib diff --git a/rtl/bplib/s3board/tb/Makefile b/rtl/bplib/s3board/tb/Makefile index fc98f7d5..fd086f48 100644 --- a/rtl/bplib/s3board/tb/Makefile +++ b/rtl/bplib/s3board/tb/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 575 2014-07-27 20:55:41Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -17,7 +17,7 @@ EXE_all += tb_s3_sram_memctl ifndef XTW_BOARD XTW_BOARD=s3board endif -include $(RETROBASE)/rtl/make/xflow_default_$(XTW_BOARD).mk +include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # .PHONY : all all_ssim all_tsim clean # @@ -29,9 +29,9 @@ clean : ise_clean ghdl_clean isim_clean # #----- # -include $(RETROBASE)/rtl/make/generic_ghdl.mk -include $(RETROBASE)/rtl/make/generic_isim.mk -include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_isim.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/bplib/s3board/tb/s3board_fusp_dummy.vhd b/rtl/bplib/s3board/tb/s3board_fusp_dummy.vhd index cfcd538a..afbcd4cb 100644 --- a/rtl/bplib/s3board/tb/s3board_fusp_dummy.vhd +++ b/rtl/bplib/s3board/tb/s3board_fusp_dummy.vhd @@ -1,4 +1,4 @@ --- $Id: s3board_fusp_dummy.vhd 336 2010-11-06 18:28:27Z mueller $ +-- $Id: s3board_fusp_dummy.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2010- by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- To test: tb_s3board_fusp -- Target Devices: generic --- Tool versions: xst 11.4; ghdl 0.26 +-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31 -- Revision History: -- Date Rev Version Comment -- 2010-11-06 336 1.0.3 rename input pin CLK -> I_CLK50 diff --git a/rtl/bplib/s3board/tb/tb_s3_sram_memctl.vhd b/rtl/bplib/s3board/tb/tb_s3_sram_memctl.vhd index c924f3e1..066c0e10 100644 --- a/rtl/bplib/s3board/tb/tb_s3_sram_memctl.vhd +++ b/rtl/bplib/s3board/tb/tb_s3_sram_memctl.vhd @@ -1,4 +1,4 @@ --- $Id: tb_s3_sram_memctl.vhd 444 2011-12-25 10:04:58Z mueller $ +-- $Id: tb_s3_sram_memctl.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2007-2011 by Walter F.J. Mueller -- @@ -28,7 +28,7 @@ -- 2007-12-16 101 - 0.26 - - c:ok -- -- Target Devices: generic --- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-12-23 444 1.1 use new simclk/simclkcnt diff --git a/rtl/bplib/s3board/tb/tb_s3board_core.vhd b/rtl/bplib/s3board/tb/tb_s3board_core.vhd index 21390749..dc46872d 100644 --- a/rtl/bplib/s3board/tb/tb_s3board_core.vhd +++ b/rtl/bplib/s3board/tb/tb_s3board_core.vhd @@ -1,4 +1,4 @@ --- $Id: tb_s3board_core.vhd 476 2013-01-26 22:23:53Z mueller $ +-- $Id: tb_s3board_core.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2010-2011 by Walter F.J. Mueller -- @@ -20,7 +20,7 @@ -- To test: generic, any s3board target -- -- Target Devices: generic --- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29 +-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-11-19 427 1.0.2 now numeric_std clean diff --git a/rtl/bplib/s3board/tb/tb_s3board_fusp.vhd b/rtl/bplib/s3board/tb/tb_s3board_fusp.vhd index 6b26933b..a0975a81 100644 --- a/rtl/bplib/s3board/tb/tb_s3board_fusp.vhd +++ b/rtl/bplib/s3board/tb/tb_s3board_fusp.vhd @@ -1,4 +1,4 @@ --- $Id: tb_s3board_fusp.vhd 476 2013-01-26 22:23:53Z mueller $ +-- $Id: tb_s3board_fusp.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2010-2011 by Walter F.J. Mueller -- @@ -25,7 +25,7 @@ -- To test: generic, any s3board_fusp_aif target -- -- Target Devices: generic --- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-12-23 444 3.1 new system clock scheme, new tbcore_rlink iface diff --git a/rtl/ibus/Makefile b/rtl/ibus/Makefile index 8c2e943d..21f8a321 100644 --- a/rtl/ibus/Makefile +++ b/rtl/ibus/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 575 2014-07-27 20:55:41Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -13,7 +13,7 @@ NGC_all = $(VBOM_all:.vbom=.ngc) ifndef XTW_BOARD XTW_BOARD=nexys3 endif -include $(RETROBASE)/rtl/make/xflow_default_$(XTW_BOARD).mk +include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # .PHONY : all clean # @@ -23,7 +23,7 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/ibus/ib_intmap.vhd b/rtl/ibus/ib_intmap.vhd index b9d0c16e..2cce71ff 100644 --- a/rtl/ibus/ib_intmap.vhd +++ b/rtl/ibus/ib_intmap.vhd @@ -1,4 +1,4 @@ --- $Id: ib_intmap.vhd 427 2011-11-19 21:04:11Z mueller $ +-- $Id: ib_intmap.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2006-2011 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-11-18 427 1.2.2 now numeric_std clean diff --git a/rtl/ibus/ib_sel.vhd b/rtl/ibus/ib_sel.vhd index a5baabff..2f2af4c8 100644 --- a/rtl/ibus/ib_sel.vhd +++ b/rtl/ibus/ib_sel.vhd @@ -1,4 +1,4 @@ --- $Id: ib_sel.vhd 427 2011-11-19 21:04:11Z mueller $ +-- $Id: ib_sel.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2010- by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: xst 12.1; ghdl 0.29 +-- Tool versions: ise 12.1-14.7; viv 2014.4; ghdl 0.29-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/ibus/ib_sres_or_2.vbom b/rtl/ibus/ib_sres_or_2.vbom index f88609b1..2e6dc876 100644 --- a/rtl/ibus/ib_sres_or_2.vbom +++ b/rtl/ibus/ib_sres_or_2.vbom @@ -2,6 +2,6 @@ ../vlib/slvtypes.vhd iblib.vhd # components -[ghdl,isim]ib_sres_or_mon.vbom +[sim]ib_sres_or_mon.vbom # design ib_sres_or_2.vhd diff --git a/rtl/ibus/ib_sres_or_2.vhd b/rtl/ibus/ib_sres_or_2.vhd index 612dcebc..0e65c497 100644 --- a/rtl/ibus/ib_sres_or_2.vhd +++ b/rtl/ibus/ib_sres_or_2.vhd @@ -1,4 +1,4 @@ --- $Id: ib_sres_or_2.vhd 335 2010-10-24 22:24:23Z mueller $ +-- $Id: ib_sres_or_2.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2007-2010 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29 +-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/ibus/ib_sres_or_3.vbom b/rtl/ibus/ib_sres_or_3.vbom index 322b9442..115a5060 100644 --- a/rtl/ibus/ib_sres_or_3.vbom +++ b/rtl/ibus/ib_sres_or_3.vbom @@ -2,6 +2,6 @@ ../vlib/slvtypes.vhd iblib.vhd # components -[ghdl,isim]ib_sres_or_mon.vbom +[sim]ib_sres_or_mon.vbom # design ib_sres_or_3.vhd diff --git a/rtl/ibus/ib_sres_or_3.vhd b/rtl/ibus/ib_sres_or_3.vhd index 7c35d96b..e88763bb 100644 --- a/rtl/ibus/ib_sres_or_3.vhd +++ b/rtl/ibus/ib_sres_or_3.vhd @@ -1,4 +1,4 @@ --- $Id: ib_sres_or_3.vhd 335 2010-10-24 22:24:23Z mueller $ +-- $Id: ib_sres_or_3.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2007-2010 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29 +-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/ibus/ib_sres_or_4.vbom b/rtl/ibus/ib_sres_or_4.vbom index 42235093..318b1f9c 100644 --- a/rtl/ibus/ib_sres_or_4.vbom +++ b/rtl/ibus/ib_sres_or_4.vbom @@ -2,6 +2,6 @@ ../vlib/slvtypes.vhd iblib.vhd # components -[ghdl,isim]ib_sres_or_mon.vbom +[sim]ib_sres_or_mon.vbom # design ib_sres_or_4.vhd diff --git a/rtl/ibus/ib_sres_or_4.vhd b/rtl/ibus/ib_sres_or_4.vhd index a8a17211..2ce913af 100644 --- a/rtl/ibus/ib_sres_or_4.vhd +++ b/rtl/ibus/ib_sres_or_4.vhd @@ -1,4 +1,4 @@ --- $Id: ib_sres_or_4.vhd 335 2010-10-24 22:24:23Z mueller $ +-- $Id: ib_sres_or_4.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2007-2010 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29 +-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/ibus/ib_sres_or_mon.vhd b/rtl/ibus/ib_sres_or_mon.vhd index 7cc88170..aed995a1 100644 --- a/rtl/ibus/ib_sres_or_mon.vhd +++ b/rtl/ibus/ib_sres_or_mon.vhd @@ -1,4 +1,4 @@ --- $Id: ib_sres_or_mon.vhd 336 2010-11-06 18:28:27Z mueller $ +-- $Id: ib_sres_or_mon.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2010- by Walter F.J. Mueller -- @@ -17,7 +17,7 @@ -- -- Dependencies: - -- Test bench: - --- Tool versions: ghdl 0.29 +-- Tool versions: ghdl 0.29-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/ibus/ibd_iist.vhd b/rtl/ibus/ibd_iist.vhd index 4c8ff781..751ac9d1 100644 --- a/rtl/ibus/ibd_iist.vhd +++ b/rtl/ibus/ibd_iist.vhd @@ -1,4 +1,4 @@ --- $Id: ibd_iist.vhd 427 2011-11-19 21:04:11Z mueller $ +-- $Id: ibd_iist.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2009-2011 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri diff --git a/rtl/ibus/ibd_kw11l.vhd b/rtl/ibus/ibd_kw11l.vhd index e663752f..f75dc14b 100644 --- a/rtl/ibus/ibd_kw11l.vhd +++ b/rtl/ibus/ibd_kw11l.vhd @@ -1,4 +1,4 @@ --- $Id: ibd_kw11l.vhd 427 2011-11-19 21:04:11Z mueller $ +-- $Id: ibd_kw11l.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2008-2011 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 12.1, 13.1; ghdl 0.18-0.29 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri diff --git a/rtl/ibus/ibdlib.vhd b/rtl/ibus/ibdlib.vhd index 00f37275..f318cf9e 100644 --- a/rtl/ibus/ibdlib.vhd +++ b/rtl/ibus/ibdlib.vhd @@ -1,4 +1,4 @@ --- $Id: ibdlib.vhd 561 2014-06-09 17:22:50Z mueller $ +-- $Id: ibdlib.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2008-2014 by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Definitions for ibus devices -- -- Dependencies: - --- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2014-06-08 561 1.2 fix rl11 declaration diff --git a/rtl/ibus/ibdr_dl11.vhd b/rtl/ibus/ibdr_dl11.vhd index 040f6c03..5ad8cfd1 100644 --- a/rtl/ibus/ibdr_dl11.vhd +++ b/rtl/ibus/ibdr_dl11.vhd @@ -1,4 +1,4 @@ --- $Id: ibdr_dl11.vhd 569 2014-07-13 14:36:32Z mueller $ +-- $Id: ibdr_dl11.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2008-2011 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 12.1, 13.1; ghdl 0.18-0.29 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri diff --git a/rtl/ibus/ibdr_lp11.vhd b/rtl/ibus/ibdr_lp11.vhd index 73874dfe..5b569423 100644 --- a/rtl/ibus/ibdr_lp11.vhd +++ b/rtl/ibus/ibdr_lp11.vhd @@ -1,4 +1,4 @@ --- $Id: ibdr_lp11.vhd 515 2013-05-04 17:28:59Z mueller $ +-- $Id: ibdr_lp11.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2009-2013 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 12.1, 13.3; ghdl 0.18-0.29 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri diff --git a/rtl/ibus/ibdr_maxisys.vbom b/rtl/ibus/ibdr_maxisys.vbom index b2577468..0214cd32 100644 --- a/rtl/ibus/ibdr_maxisys.vbom +++ b/rtl/ibus/ibdr_maxisys.vbom @@ -5,7 +5,7 @@ ibdlib.vhd # components ibd_iist.vbom ibd_kw11l.vbom -## ibdr_rl11.vbom +ibdr_rl11.vbom ibdr_rk11.vbom ibdr_dl11.vbom ibdr_pc11.vbom diff --git a/rtl/ibus/ibdr_maxisys.vhd b/rtl/ibus/ibdr_maxisys.vhd index 717f4797..605c57ac 100644 --- a/rtl/ibus/ibdr_maxisys.vhd +++ b/rtl/ibus/ibdr_maxisys.vhd @@ -1,6 +1,6 @@ --- $Id: ibdr_maxisys.vhd 565 2014-06-28 12:54:08Z mueller $ +-- $Id: ibdr_maxisys.vhd 641 2015-02-01 22:12:15Z mueller $ -- --- Copyright 2009-2014 by Walter F.J. Mueller +-- Copyright 2009-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -28,24 +28,25 @@ -- ib_intmap -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri --- 2014-06-08 561 14.7 131013 xc6slx16-2 380 748 18 266 s 7.1 +RL11 +-- 2015-01-04 630 14.7 131013 xc6slx16-2 388 761 20 265 s 8.0 +RL11 -- 2014-06-08 560 14.7 131013 xc6slx16-2 311 615 8 216 s 7.1 -- 2010-10-17 333 12.1 M53d xc3s1000-4 312 1058 16 617 s 10.3 -- 2010-10-17 314 12.1 M53d xc3s1000-4 300 1094 16 626 s 10.4 -- -- Revision History: -- Date Rev Version Comment +-- 2015-01-04 630 1.2.1 RL11 back in -- 2014-06-27 565 1.2.1 temporarily hide RL11 -- 2014-06-08 561 1.2 add rl11 -- 2011-11-18 427 1.1.2 now numeric_std clean --- 2010-10-23 335 1.1.1 rename RRI_LAM->RB_LAM; +-- 2010-10-23 335 1.1.1 rename RRI_LAM->RB_LAM -- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ -- 2009-07-12 233 1.0.4 reorder ports; add RESET, CE_USEC to _dl11 --- 2009-06-20 227 1.0.3 rename generate labels. +-- 2009-06-20 227 1.0.3 rename generate labels -- 2009-06-07 224 1.0.2 add iist_mreq and iist_sres interfaces -- 2009-06-01 221 1.0.1 add CE_USEC; add RESET to kw11l; add _pc11, _iist -- 2009-05-24 219 1.0 Initial version @@ -237,20 +238,20 @@ begin EI_ACK => EI_ACK_KW11L ); --- RL11: if true generate --- begin --- I0 : ibdr_rl11 --- port map ( --- CLK => CLK, --- CE_MSEC => CE_MSEC, --- BRESET => BRESET, --- RB_LAM => RB_LAM_RL11, --- IB_MREQ => IB_MREQ, --- IB_SRES => IB_SRES_RL11, --- EI_REQ => EI_REQ_RL11, --- EI_ACK => EI_ACK_RL11 --- ); --- end generate RL11; + RL11: if true generate + begin + I0 : ibdr_rl11 + port map ( + CLK => CLK, + CE_MSEC => CE_MSEC, + BRESET => BRESET, + RB_LAM => RB_LAM_RL11, + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_RL11, + EI_REQ => EI_REQ_RL11, + EI_ACK => EI_ACK_RL11 + ); + end generate RL11; RK11: if true generate begin diff --git a/rtl/ibus/ibdr_minisys.vhd b/rtl/ibus/ibdr_minisys.vhd index 1c8a2570..7248c503 100644 --- a/rtl/ibus/ibdr_minisys.vhd +++ b/rtl/ibus/ibdr_minisys.vhd @@ -1,4 +1,4 @@ --- $Id: ibdr_minisys.vhd 427 2011-11-19 21:04:11Z mueller $ +-- $Id: ibdr_minisys.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2008-2011 by Walter F.J. Mueller -- @@ -23,7 +23,7 @@ -- ib_intmap -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri diff --git a/rtl/ibus/ibdr_pc11.vhd b/rtl/ibus/ibdr_pc11.vhd index 3beec1b0..57b0172d 100644 --- a/rtl/ibus/ibdr_pc11.vhd +++ b/rtl/ibus/ibdr_pc11.vhd @@ -1,4 +1,4 @@ --- $Id: ibdr_pc11.vhd 515 2013-05-04 17:28:59Z mueller $ +-- $Id: ibdr_pc11.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2009-2013 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: xxdp: zpcae0 -- Target Devices: generic --- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.3; ghdl 0.18-0.29 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri diff --git a/rtl/ibus/ibdr_rk11.vbom b/rtl/ibus/ibdr_rk11.vbom index b40fe6bf..aff5865c 100644 --- a/rtl/ibus/ibdr_rk11.vbom +++ b/rtl/ibus/ibdr_rk11.vbom @@ -3,7 +3,7 @@ ../vlib/memlib/memlib.vhd iblib.vhd # components -[ghdl,isim]../vlib/memlib/ram_1swar_gen.vbom -[xst]../vlib/memlib/ram_1swar_gen_unisim.vbom +[sim]../vlib/memlib/ram_1swar_gen.vbom +[xst,vsyn]../vlib/memlib/ram_1swar_gen_unisim.vbom # design ibdr_rk11.vhd diff --git a/rtl/ibus/ibdr_rk11.vhd b/rtl/ibus/ibdr_rk11.vhd index ed22b359..7e9f9cf7 100644 --- a/rtl/ibus/ibdr_rk11.vhd +++ b/rtl/ibus/ibdr_rk11.vhd @@ -1,4 +1,4 @@ --- $Id: ibdr_rk11.vhd 561 2014-06-09 17:22:50Z mueller $ +-- $Id: ibdr_rk11.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2008-2011 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: ram_1swar_gen -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri diff --git a/rtl/ibus/ibdr_rl11.vbom b/rtl/ibus/ibdr_rl11.vbom new file mode 100644 index 00000000..98bb21fc --- /dev/null +++ b/rtl/ibus/ibdr_rl11.vbom @@ -0,0 +1,9 @@ +# libs +../vlib/slvtypes.vhd +../vlib/memlib/memlib.vhd +iblib.vhd +# components +[sim]../vlib/memlib/ram_1swar_gen.vbom +[xst,vsyn]../vlib/memlib/ram_1swar_gen_unisim.vbom +# design +ibdr_rl11.vhd diff --git a/rtl/ibus/ibdr_rl11.vhd b/rtl/ibus/ibdr_rl11.vhd new file mode 100644 index 00000000..6036379f --- /dev/null +++ b/rtl/ibus/ibdr_rl11.vhd @@ -0,0 +1,660 @@ +-- $Id: ibdr_rl11.vhd 655 2015-03-04 20:35:21Z mueller $ +-- +-- Copyright 2014-2015 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: ibdr_rl11 - syn +-- Description: ibus dev(rem): RL11 +-- +-- Dependencies: ram_1swar_gen +-- Test bench: - +-- Target Devices: generic +-- Tool versions: ise 14.7; viv 2014.4; ghdl 0.31 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2015-02-28 653 14.7 131013 xc6slx16-2 80 197 12 80 s 7.9 +-- 2014-06-15 562 14.7 131013 xc6slx16-2 81 199 13 78 s 8.0 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2015-03-04 655 1.0.1 seek: ignore da(6:5), don't check for 0 anymore +-- 2015-02-28 653 1.0 Initial verison +-- 2014-06-09 561 0.1 First draft +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.memlib.all; +use work.iblib.all; + +-- ---------------------------------------------------------------------------- +entity ibdr_rl11 is -- ibus dev(rem): RL11 + -- fixed address: 174400 + port ( + CLK : in slbit; -- clock + CE_MSEC : in slbit; -- msec pulse + BRESET : in slbit; -- ibus reset + RB_LAM : out slbit; -- remote attention + IB_MREQ : in ib_mreq_type; -- ibus request + IB_SRES : out ib_sres_type; -- ibus response + EI_REQ : out slbit; -- interrupt request + EI_ACK : in slbit -- interrupt acknowledge + ); +end ibdr_rl11; + +architecture syn of ibdr_rl11 is + + constant ibaddr_rl11 : slv16 := slv(to_unsigned(8#174400#,16)); + + constant ibaddr_rlcs : slv2 := "00"; -- rlcs address offset + constant ibaddr_rlba : slv2 := "01"; -- rlba address offset + constant ibaddr_rlda : slv2 := "10"; -- rlda address offset + constant ibaddr_rlmp : slv2 := "11"; -- rlmp address offset + + -- usage of 16x16 memory bank + -- 0 0000 unused (but mirrors rlcs) + -- 1 0001 rlba + -- 2 0010 unused (but mirrors rlda) + -- 3 0011 rlmp (1st value) + -- 4 0100 rlmp (3rd value after gs; the crc) + -- 5 0101 unused + -- 6 0110 unused + -- 7 0111 unused (target for bad mprem states) + -- 11: 8 10-- sta(ds) (drive status) + -- 15:12 11-- pos(ds) (drive disk address) + constant imem_cs : slv4 := "0000"; -- unused + constant imem_ba : slv4 := "0001"; + constant imem_da : slv4 := "0010"; -- unused + constant imem_mp : slv4 := "0011"; + constant imem_crc : slv4 := "0100"; + constant imem_bad : slv4 := "0111"; -- target for bad mprem states + constant imem_sta : slv4 := "1000"; + constant imem_pos : slv4 := "1100"; + + subtype imf_typ is integer range 3 downto 2; + subtype imf_ds is integer range 1 downto 0; + + constant rlcs_ibf_err : integer := 15; + constant rlcs_ibf_de : integer := 14; + subtype rlcs_ibf_e is integer range 13 downto 10; + subtype rlcs_ibf_ds is integer range 9 downto 8; + constant rlcs_ibf_crdy : integer := 7; + constant rlcs_ibf_ie : integer := 6; + subtype rlcs_ibf_bae is integer range 5 downto 4; + subtype rlcs_ibf_func is integer range 3 downto 1; + constant rlcs_ibf_drdy : integer := 0; + + constant func_noop : slv3 := "000"; -- func: noop + constant func_wchk : slv3 := "001"; -- func: write check + constant func_gs : slv3 := "010"; -- func: get status + constant func_seek : slv3 := "011"; -- func: seek + constant func_rhdr : slv3 := "100"; -- func: read header + constant func_write : slv3 := "101"; -- func: write data + constant func_read : slv3 := "110"; -- func: read data + constant func_rnhc : slv3 := "111"; -- func: read data without header check + + constant e_ok : slv4 := "0000"; -- e code: ok + constant e_incomp : slv4 := "0001"; -- e code: operation incomplete + + -- defs for rem access of rlcs; func codes + constant rfunc_wcs : slv3 := "001"; -- rem func: write cs (err,de,e,drdy) + constant rfunc_wmp : slv3 := "010"; -- rem func: write mprem or mploc + + -- rlcs usage or rem func=wmp + subtype rlcs_ibf_mprem is integer range 15 downto 11; + subtype rlcs_ibf_mploc is integer range 10 downto 8; + constant rlcs_ibf_ena_mprem : integer := 5; + constant rlcs_ibf_ena_mploc : integer := 4; + + subtype rlda_ibf_seek_df is integer range 15 downto 7; + constant rlda_ibf_seek_hs : integer := 4; + constant rlda_ibf_seek_dir : integer := 2; + constant rlda_msk_seek : slv16 := "0000000000001011"; + constant rlda_val_seek : slv16 := "0000000000000001"; + + constant rlda_ibf_gs_rst : integer := 3; + constant rlda_msk_gs : slv16 := "0000000011110111"; + constant rlda_val_gs : slv16 := "0000000000000011"; + + constant sta_ibf_wde : integer := 15; -- Write data error - always 0 + constant sta_ibf_che : integer := 14; -- Current head error - always 0 + constant sta_ibf_wl : integer := 13; -- Write lock - used + constant sta_ibf_sto : integer := 12; -- Seek time out - used + constant sta_ibf_spe : integer := 11; -- Spin error - used + constant sta_ibf_wge : integer := 10; -- Write gate error - used + constant sta_ibf_vce : integer := 9; -- Volume check - used + constant sta_ibf_dse : integer := 8; -- Drive select error - used + constant sta_ibf_dt : integer := 7; -- Drive type - used + constant sta_ibf_hs : integer := 6; -- Head select - used + constant sta_ibf_co : integer := 5; -- Cover open - used + constant sta_ibf_ho : integer := 4; -- Heads out - used + constant sta_ibf_bh : integer := 3; -- Brush home - always 1 + subtype sta_ibf_st is integer range 2 downto 0; -- Drive state + + constant st_load : slv3 := "000"; -- st: Load(ing) cartidge - used + constant st_spin : slv3 := "001"; -- st: Spin(ing) up - !unused! + constant st_brush : slv3 := "010"; -- st: Brush(ing) cycle - !unused! + constant st_hload : slv3 := "011"; -- st: Load(ing) heads - !unused! + constant st_seek : slv3 := "100"; -- st: Seek(ing) - may be used + constant st_lock : slv3 := "101"; -- st: Lock(ed) on - used + constant st_unl : slv3 := "110"; -- st: Unload(ing) heads - !unused! + constant st_down : slv3 := "111"; -- st: Spin(ing) down - !unused! + -- only two mayor drive states are used + -- on: st=lock; ho=1; co=0; ( file connected in backend) + -- off: st=load; ho=0; co=1; (no file connected in backend) + + subtype pos_ibf_ca is integer range 15 downto 7; + constant pos_ibf_hs : integer := 6; + subtype pos_ibf_sa is integer range 5 downto 0; + + constant mploc_mp : slv3 := "000"; -- return imem(mp) + constant mploc_sta : slv3 := "001"; -- return sta(ds) + constant mploc_pos : slv3 := "010"; -- return pos(ds) + constant mploc_zero : slv3 := "011"; -- return 0 + constant mploc_crc : slv3 := "100"; -- return imem(crc) + + constant mprem_f_map : integer := 4; -- mprem map enable + subtype mprem_f_addr is integer range 3 downto 0; + constant mprem_f_seq : integer := 3; -- mprem seq enable + subtype mprem_f_state is integer range 2 downto 0; + constant mprem_mapseq : slv2 := "11"; -- enable map + seq + constant mprem_s_mp : slv3 := "000"; -- access imem(mp) + constant mprem_s_sta : slv3 := "001"; -- access sta(ds) + constant mprem_s_pos : slv3 := "010"; -- access pos(ds) + constant mprem_init : slv5 := "10000"; -- enable map,fix, show mp + + constant ca_max_rl01 : slv9 := "011111111"; -- max cylinder for RL01 (255) + constant ca_max_rl02 : slv9 := "111111111"; -- max cylinder for RL02 (511) + + type state_type is ( + s_idle, -- idle: handle ibus + s_csread, -- csread: handle cs read + s_gs_rpos, -- gs_rpos: read pos(ds) + s_gs_sta, -- gs_sta: handle status + s_seek_rsta, -- seek_rsta: read sta(ds) + s_seek_rpos, -- seek_rpos: read pos(ds) + s_seek_clip, -- seek_clip: clip new ca + s_seek_wpos, -- seek_wpos: write pos(ds) + s_init -- init: handle init + ); + + type regs_type is record -- state registers + ibsel : slbit; -- ibus select + state : state_type; -- state + iaddr : slv4; -- init addr counter + cserr : slbit; -- rlcs: composite error + csde : slbit; -- rlcs: drive error + cse : slv4; -- rlcs: error + csds : slv2; -- rlcs: drive select + cscrdy : slbit; -- rlcs: controller ready + csie : slbit; -- rlcs: interrupt enable + csbae : slv2; -- rlcs: bus address extenstion + csfunc : slv3; -- rlcs: function code + csdrdy : slbit; -- rlcs: drive ready + da : slv16; -- rlda shadow reg + gshs : slbit; -- gs: pos(ds)(hs) (head select) + seekdt : slbit; -- seek: drive type: 0=RL01, 1=RL02 + seekcan: slv10; -- seek: cylinder address, new + seekcac: slv9; -- seek: cylinder address, clipped + ireq : slbit; -- interrupt request flag + mploc : slv3; -- mp loc state + mprem : slv5; -- mp rem state + crdone : slbit; -- control reset done since last fdone + end record regs_type; + + constant regs_init : regs_type := ( + '0', -- ibsel + s_init, -- state + imem_ba, -- iaddr + '0','0', -- cserr,csde + (others=>'0'), -- cse + (others=>'0'), -- csds + '1','0', -- cscrdy, csie + (others=>'0'), -- csbae + (others=>'0'), -- csfunc + '0', -- csdrdy + (others=>'0'), -- da + '0', -- gshs + '0', -- seekdt + (others=>'0'), -- seekcan + (others=>'0'), -- seekcac + '0', -- ireq + mploc_mp, -- mploc + mprem_init, -- mprem + '1' -- crdone + ); + + signal R_REGS : regs_type := regs_init; + signal N_REGS : regs_type := regs_init; + + signal MEM_1_WE : slbit := '0'; + signal MEM_0_WE : slbit := '0'; + signal MEM_ADDR : slv4 := (others=>'0'); + signal MEM_DIN : slv16 := (others=>'0'); + signal MEM_DOUT : slv16 := (others=>'0'); + +begin + + MEM_1 : ram_1swar_gen + generic map ( + AWIDTH => 4, + DWIDTH => 8) + port map ( + CLK => CLK, + WE => MEM_1_WE, + ADDR => MEM_ADDR, + DI => MEM_DIN(ibf_byte1), + DO => MEM_DOUT(ibf_byte1)); + + MEM_0 : ram_1swar_gen + generic map ( + AWIDTH => 4, + DWIDTH => 8) + port map ( + CLK => CLK, + WE => MEM_0_WE, + ADDR => MEM_ADDR, + DI => MEM_DIN(ibf_byte0), + DO => MEM_DOUT(ibf_byte0)); + + proc_regs: process (CLK) + begin + if rising_edge(CLK) then + if BRESET='1' then + R_REGS <= regs_init; + else + R_REGS <= N_REGS; + end if; + end if; + end process proc_regs; + + proc_next : process (R_REGS, CE_MSEC, IB_MREQ, MEM_DOUT, EI_ACK) + variable r : regs_type := regs_init; + variable n : regs_type := regs_init; + variable ibhold : slbit := '0'; + variable idout : slv16 := (others=>'0'); + variable ibrem : slbit := '0'; + variable ibreq : slbit := '0'; + variable ibrd : slbit := '0'; + variable ibw0 : slbit := '0'; + variable ibw1 : slbit := '0'; + variable ibwrem : slbit := '0'; + variable ilam : slbit := '0'; + variable iei_req : slbit := '0'; + + variable imem_we0 : slbit := '0'; + variable imem_we1 : slbit := '0'; + variable imem_addr : slv4 := (others=>'0'); + variable imem_din : slv16 := (others=>'0'); + begin + + r := R_REGS; + n := R_REGS; + + ibhold := '0'; + idout := (others=>'0'); + ibrem := IB_MREQ.racc; + ibreq := IB_MREQ.re or IB_MREQ.we; + ibrd := IB_MREQ.re; + ibw0 := IB_MREQ.we and IB_MREQ.be0; + ibw1 := IB_MREQ.we and IB_MREQ.be1; + ibwrem := IB_MREQ.we and ibrem; + ilam := '0'; + iei_req := '0'; + + imem_we0 := '0'; + imem_we1 := '0'; + imem_addr := "00" & IB_MREQ.addr(2 downto 1); + imem_din := IB_MREQ.din; + + -- ibus address decoder + n.ibsel := '0'; + if IB_MREQ.aval = '1' and + IB_MREQ.addr(12 downto 3)=ibaddr_rl11(12 downto 3) then + n.ibsel := '1'; + end if; + + -- internal state machine + case r.state is + when s_idle => -- idle: handle ibus ----------------- + + if r.ibsel='1' then -- selected + idout := MEM_DOUT; + imem_we0 := ibw0; + imem_we1 := ibw1; + + case IB_MREQ.addr(2 downto 1) is + + when ibaddr_rlcs => -- RLCS - control register ------- + imem_we0 := '0'; -- MEM not used for rlcs + imem_we1 := '0'; + imem_addr := imem_sta(imf_typ) & r.csds; -- get sta(ds) + + -- determine DRDY + n.csdrdy := '1'; + if MEM_DOUT(sta_ibf_st) /= st_lock or -- drive not on and locked + MEM_DOUT(sta_ibf_vce) = '1' then -- or volume check + -- ??? also CRDY=0 here ??? + n.csdrdy := '0'; + end if; + + -- determine DE and ERR + n.cserr := '0'; + if MEM_DOUT(sta_ibf_st) = st_load or -- drive off + MEM_DOUT(sta_ibf_vce) = '1' then -- or volume check + n.csde := '1'; + n.cserr := '1'; + end if; + if r.csde = '1' or r.cse /= e_ok then + n.cserr := '1'; + end if; + + if ibrd = '1' then -- cs read + ibhold := '1'; + n.state := s_csread; + + elsif IB_MREQ.we = '1' then -- cs write + + if ibrem = '0' then -- loc write access + + if IB_MREQ.be1 = '1' then + if r.cscrdy = '1' then -- freeze csds when busy + n.csds := IB_MREQ.din(rlcs_ibf_ds); + end if; + end if; + + if IB_MREQ.be0 = '1' then + n.csie := IB_MREQ.din(rlcs_ibf_ie); + n.csbae := IB_MREQ.din(rlcs_ibf_bae); + + if r.cscrdy = '1' then -- controller ready + + n.csfunc := IB_MREQ.din(rlcs_ibf_func); -- latch func + if IB_MREQ.din(rlcs_ibf_crdy) = '1' then -- no crdy clr + if IB_MREQ.din(rlcs_ibf_ie) = '1' and r.csie = '0' then + n.ireq := '1'; + end if; + else -- crdy clr --> handle func + + n.cserr := '0'; -- clear errors + n.csde := '0'; + n.cse := "0000"; + + case IB_MREQ.din(rlcs_ibf_func) is + when func_noop => -- noop ------- + n.ireq := r.csie; -- interrupt + + when func_gs => -- get status - + if (r.da and rlda_msk_gs) /= rlda_val_gs then + n.cserr := '1'; + n.cse := e_incomp; + n.ireq := IB_MREQ.din(rlcs_ibf_ie); + else + ibhold := '1'; + n.state := s_gs_rpos; + end if; + + when func_seek => -- seek ------- + if (r.da and rlda_msk_seek) /= rlda_val_seek then + n.cserr := '1'; + n.cse := e_incomp; + n.ireq := IB_MREQ.din(rlcs_ibf_ie); + else + ibhold := '1'; + n.state := s_seek_rsta; + end if; + + when others => -- all other funcs + n.cscrdy := '0'; -- signal cntl busy + ilam := '1'; -- issue lam + end case; + + end if; -- else IB_MREQ.din(rlcs_ibf_crdy) = '1' + end if; -- r.cscrdy = '1' + end if; -- IB_MREQ.be0 = '1' + + else -- rem write access + case IB_MREQ.din(rlcs_ibf_func) is + + when rfunc_wcs => + n.csde := IB_MREQ.din(rlcs_ibf_de); + n.cse := IB_MREQ.din(rlcs_ibf_e); + n.cscrdy := IB_MREQ.din(rlcs_ibf_crdy); + n.csbae := IB_MREQ.din(rlcs_ibf_bae); + if r.cscrdy = '0' and IB_MREQ.din(rlcs_ibf_crdy) = '1' then + n.ireq := r.csie; + end if; + + when rfunc_wmp => + if IB_MREQ.din(rlcs_ibf_ena_mprem) = '1' then + n.mprem := IB_MREQ.din(rlcs_ibf_mprem); + end if; + if IB_MREQ.din(rlcs_ibf_ena_mploc) = '1' then + n.mploc := IB_MREQ.din(rlcs_ibf_mploc); + end if; + + when others => null; + end case; + + end if; + end if; + + when ibaddr_rlba => -- RLBA - bus address register --- + imem_din(0) := '0'; -- lsb forced 0 + null; + + when ibaddr_rlda => -- RLDA - disk address register -- + if ibw1 = '1' then + n.da(15 downto 8) := IB_MREQ.din(15 downto 8); + end if; + if ibw0 = '1' then + n.da( 7 downto 0) := IB_MREQ.din( 7 downto 0); + end if; + + when ibaddr_rlmp => -- RLMP - multipurpose register -- + + if ibrem = '0' then -- loc access + if ibrd = '1' then -- loc mp read + case r.mploc is + when mploc_mp => -- return imem(mp) + null; + when mploc_sta => -- return sta(ds) + imem_addr := imem_sta(imf_typ) & r.csds; + when mploc_pos => -- return pos(ds) + imem_addr := imem_pos(imf_typ) & r.csds; + n.mploc := mploc_zero; + when mploc_zero => -- return 0 + idout := (others => '0'); + n.mploc := mploc_crc; + when mploc_crc => -- return imem(crc) + imem_addr := imem_crc; + when others => null; + end case; + elsif IB_MREQ.we = '1' then -- loc mp write + n.mploc := mploc_mp; -- use main mp reg in future + end if; + + else -- rem access + if r.mprem(mprem_f_map) = '0' then -- map off - fixed addr + imem_addr := r.mprem(mprem_f_addr); + else -- sequence + case r.mprem(mprem_f_state) is + when mprem_s_mp => -- mp {used as wc} + imem_addr := imem_mp; + if r.mprem(mprem_f_seq) = '1' then -- ??? check re&we !!! + n.mprem := mprem_mapseq & mprem_s_sta; + end if; + when mprem_s_sta => -- sta(ds) + imem_addr := imem_sta(imf_typ) & r.csds; + if r.mprem(mprem_f_seq) = '1' then -- ??? check re&we !!! + n.mprem := mprem_mapseq & mprem_s_pos; + end if; + when mprem_s_pos => -- pos(ds) + imem_addr := imem_pos(imf_typ) & r.csds; + when others => -- bad state + imem_addr := imem_bad; + + end case; + end if; + end if; + + when others => null; + + end case; + + end if; + + when s_csread => -- csread: handle cs read ----------- + idout(rlcs_ibf_err) := r.cserr; + idout(rlcs_ibf_de) := r.csde; + idout(rlcs_ibf_e) := r.cse; + idout(rlcs_ibf_ds) := r.csds; + idout(rlcs_ibf_crdy) := r.cscrdy; + idout(rlcs_ibf_ie) := r.csie; + idout(rlcs_ibf_bae) := r.csbae; + idout(rlcs_ibf_func) := r.csfunc; + idout(rlcs_ibf_drdy) := r.csdrdy; + n.state := s_idle; + + when s_gs_rpos => -- gs_rpos: read pos(ds) ----------- + imem_addr := imem_pos(imf_typ) & r.csds; -- get pos(ds) + n.gshs := MEM_DOUT(pos_ibf_hs); -- get hs bit + ibhold := r.ibsel; + n.state := s_gs_sta; + + when s_gs_sta => -- gs_sta: handle status ----------- + imem_addr := imem_sta(imf_typ) & r.csds; -- get sta(ds) + imem_we0 := '1'; -- always update + imem_we1 := '1'; + imem_din := MEM_DOUT; + imem_din(sta_ibf_hs) := r.gshs; + if r.da(rlda_ibf_gs_rst) = '1' then -- if RST set + imem_din(sta_ibf_wde) := '0'; -- clear error bits + imem_din(sta_ibf_che) := '0'; + imem_din(sta_ibf_sto) := '0'; + imem_din(sta_ibf_spe) := '0'; + imem_din(sta_ibf_wge) := '0'; + imem_din(sta_ibf_vce) := '0'; + imem_din(sta_ibf_dse) := '0'; + end if; + n.mploc := mploc_sta; -- use sta(ds) as mp + n.ireq := r.csie; -- interrupt + n.state := s_idle; + + when s_seek_rsta => -- seek_rsta: read sta(ds) ----------- + imem_addr := imem_sta(imf_typ) & r.csds; -- get sta(ds) + n.seekdt := MEM_DOUT(sta_ibf_dt); + imem_din := MEM_DOUT; + if MEM_DOUT(sta_ibf_st) /= st_lock then -- drive off + imem_we0 := '1'; -- update sta + imem_we1 := '1'; + imem_din(sta_ibf_sto) := '1'; -- set STO (seek time out) + n.cse := e_incomp; + n.ireq := r.csie; -- interrupt + n.state := s_idle; + else -- drive on + ibhold := r.ibsel; + n.state := s_seek_rpos; + end if; + + when s_seek_rpos => -- seek_rpos: read pos(ds) ----------- + imem_addr := imem_pos(imf_typ) & r.csds; -- get pos(ds) + if r.da(rlda_ibf_seek_dir) = '1' then + n.seekcan := slv(unsigned('0' & MEM_DOUT(pos_ibf_ca)) + + unsigned('0' & r.da(rlda_ibf_seek_df)) ); + else + n.seekcan := slv(unsigned('0' & MEM_DOUT(pos_ibf_ca)) - + unsigned('0' & r.da(rlda_ibf_seek_df)) ); + end if; + ibhold := r.ibsel; + n.state := s_seek_clip; + + when s_seek_clip => -- seek_clip: clip new ca ------------ + n.seekcac := r.seekcan(8 downto 0); + -- new ca overflowed ? for RL02 (9) and for RL01 (9:8) must be "00" + if r.seekcan(9) = '1' or + (r.seekdt = '0' and r.seekcan(8) = '1') then + if r.da(rlda_ibf_seek_dir) = '1' then -- outward seek + if r.seekdt = '1' then -- is RL02 + n.seekcac := ca_max_rl02; -- clip to RL02 max ca + else -- is RL01 + n.seekcac := ca_max_rl01; -- clip to RL01 max ca + end if; + else -- inward seek + n.seekcac := "000000000"; -- clip to 0 + end if; + end if; + ibhold := r.ibsel; + n.state := s_seek_wpos; + + when s_seek_wpos => -- seek_wpos: write pos(ds) ---------- + imem_addr := imem_pos(imf_typ) & r.csds; -- get pos(ds) + imem_we0 := '1'; + imem_we1 := '1'; + imem_din := MEM_DOUT; + imem_din(pos_ibf_ca) := r.seekcac; + imem_din(pos_ibf_hs) := r.da(rlda_ibf_seek_hs); + n.ireq := r.csie; -- interrupt + n.state := s_idle; + + when s_init => -- init: handle init ----------------- + ibhold := r.ibsel; -- hold ibus when controller busy + imem_addr := r.iaddr; + imem_din := (others=>'0'); + imem_we0 := '1'; + imem_we1 := '1'; + if r.iaddr(imf_typ) = imem_sta(imf_typ) then -- if sta(x) + imem_din := MEM_DOUT; -- keep state + imem_din(sta_ibf_wde) := '0'; -- and clear err + imem_din(sta_ibf_che) := '0'; + imem_din(sta_ibf_sto) := '0'; + imem_din(sta_ibf_spe) := '0'; + imem_din(sta_ibf_wge) := '0'; + imem_din(sta_ibf_vce) := '0'; + imem_din(sta_ibf_dse) := '0'; + end if; + n.iaddr := slv(unsigned(r.iaddr) + 1); + if unsigned(r.iaddr) = unsigned(imem_sta)+3 then -- stop after sta(3) + n.state := s_idle; + end if; + + when others => null; + end case; + + iei_req := r.ireq; -- ??? simplify, use r.ireq directly + + if EI_ACK = '1' or r.csie = '0' then -- interrupt executed or ie disabled + n.ireq := '0'; -- cancel request + end if; + + N_REGS <= n; + + MEM_0_WE <= imem_we0; + MEM_1_WE <= imem_we1; + MEM_ADDR <= imem_addr; + MEM_DIN <= imem_din; + + IB_SRES.dout <= idout; + IB_SRES.ack <= r.ibsel and ibreq; + IB_SRES.busy <= ibhold and ibreq; + + RB_LAM <= ilam; + EI_REQ <= iei_req; + + end process proc_next; + + +end syn; diff --git a/rtl/ibus/ibdr_sdreg.vhd b/rtl/ibus/ibdr_sdreg.vhd index f4b1c677..3f9d0f7b 100644 --- a/rtl/ibus/ibdr_sdreg.vhd +++ b/rtl/ibus/ibdr_sdreg.vhd @@ -1,4 +1,4 @@ --- $Id: ibdr_sdreg.vhd 427 2011-11-19 21:04:11Z mueller $ +-- $Id: ibdr_sdreg.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2007-2011 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 12.1, 13.1; ghdl 0.18-0.29 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri diff --git a/rtl/ibus/iblib.vhd b/rtl/ibus/iblib.vhd index 0176c9c4..2f17e61c 100644 --- a/rtl/ibus/iblib.vhd +++ b/rtl/ibus/iblib.vhd @@ -1,4 +1,4 @@ --- $Id: iblib.vhd 427 2011-11-19 21:04:11Z mueller $ +-- $Id: iblib.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2008-2010 by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Definitions for ibus interface and bus entities -- -- Dependencies: - --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29 +-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2010-10-23 335 2.0.1 add ib_sel; add ib_sres_or_mon diff --git a/rtl/make/dontincdep.mk b/rtl/make_ise/dontincdep.mk similarity index 72% rename from rtl/make/dontincdep.mk rename to rtl/make_ise/dontincdep.mk index fd65fcac..491ee4d2 100644 --- a/rtl/make/dontincdep.mk +++ b/rtl/make_ise/dontincdep.mk @@ -1,4 +1,7 @@ -# $Id: dontincdep.mk 477 2013-01-27 14:07:10Z mueller $ +# $Id: dontincdep.mk 642 2015-02-06 18:53:12Z mueller $ +# +# Copyright 2013- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory # # Revision History: # Date Rev Version Comment diff --git a/rtl/make/generic_ghdl.mk b/rtl/make_ise/generic_ghdl.mk similarity index 66% rename from rtl/make/generic_ghdl.mk rename to rtl/make_ise/generic_ghdl.mk index 0f972401..10cbf692 100644 --- a/rtl/make/generic_ghdl.mk +++ b/rtl/make_ise/generic_ghdl.mk @@ -1,7 +1,11 @@ -# $Id: generic_ghdl.mk 575 2014-07-27 20:55:41Z mueller $ +# $Id: generic_ghdl.mk 646 2015-02-15 12:04:55Z mueller $ +# +# Copyright 2007-2015 by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory # # Revision History: # Date Rev Version Comment +# 2015-02-14 646 1.4 use --xlpath for vbomconv; drop cygwin support; # 2014-07-26 575 1.3.2 use XTWI_PATH now (ise/vivado switch done later) # 2013-01-27 477 1.3.1 use dontincdep.mk to suppress .dep include on clean # 2011-08-13 405 1.3 renamed, moved to rtl/make; @@ -11,39 +15,33 @@ # 2007-06-16 57 1.1 cleanup ghdl_clean handling # 2007-06-10 52 1.0 Initial version # -GHDLIEEE = --ieee=synopsys -GHDLUNISIM = -P$(XTWI_PATH)/ISE_DS/ISE/ghdl/unisim -GHDLSIMPRIM = -P$(XTWI_PATH)/ISE_DS/ISE/ghdl/simprim -GHDL = ghdl -COMPILE.vhd = $(GHDL) -a $(GHDLIEEE) -LINK.vhd = $(GHDL) -e $(GHDLIEEE) +GHDLIEEE = --ieee=synopsys +GHDLXLPATH = $(XTWI_PATH)/ISE_DS/ISE/ghdl # % : %.vbom vbomconv --ghdl_i $< - vbomconv --ghdl_m $< + vbomconv --ghdl_m --xlpath=$(GHDLXLPATH) $< # # rules for _[ft]sim to use 'virtual' [ft]sim vbom's (derived from _ssim) # %_fsim : %_ssim.vbom vbomconv --ghdl_i $*_fsim.vbom - vbomconv --ghdl_m $*_fsim.vbom + vbomconv --ghdl_m --xlpath=$(GHDLXLPATH) $*_fsim.vbom # %_tsim : %_ssim.vbom vbomconv --ghdl_i $*_tsim.vbom - vbomconv --ghdl_m $*_tsim.vbom + vbomconv --ghdl_m --xlpath=$(GHDLXLPATH) $*_tsim.vbom # %.dep_ghdl: %.vbom vbomconv --dep_ghdl $< > $@ # -include $(RETROBASE)/rtl/make/dontincdep.mk +include $(RETROBASE)/rtl/make_ise/dontincdep.mk # .PHONY: ghdl_clean ghdl_tmp_clean # ghdl_clean: ghdl_tmp_clean rm -f $(EXE_all) rm -f $(EXE_all:%=%_[sft]sim) - rm -f $(EXE_all:%=%.exe) - rm -f $(EXE_all:%=%_[sft]sim.exe) rm -f cext_*.o # ghdl_tmp_clean: diff --git a/rtl/make/generic_isim.mk b/rtl/make_ise/generic_isim.mk similarity index 85% rename from rtl/make/generic_isim.mk rename to rtl/make_ise/generic_isim.mk index 43ccecda..6c7a0738 100644 --- a/rtl/make/generic_isim.mk +++ b/rtl/make_ise/generic_isim.mk @@ -1,4 +1,7 @@ -# $Id: generic_isim.mk 539 2013-10-13 17:06:35Z mueller $ +# $Id: generic_isim.mk 642 2015-02-06 18:53:12Z mueller $ +# +# Copyright 2009-2013 by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory # # Revision History: # Date Rev Version Comment @@ -37,7 +40,7 @@ FUSE = fuse %.dep_isim: %.vbom vbomconv --dep_isim $< > $@ # -include $(RETROBASE)/rtl/make/dontincdep.mk +include $(RETROBASE)/rtl/make_ise/dontincdep.mk # .PHONY: isim_clean isim_tmp_clean # diff --git a/rtl/make/generic_xflow.mk b/rtl/make_ise/generic_xflow.mk similarity index 89% rename from rtl/make/generic_xflow.mk rename to rtl/make_ise/generic_xflow.mk index 980df4a4..62fd0094 100644 --- a/rtl/make/generic_xflow.mk +++ b/rtl/make_ise/generic_xflow.mk @@ -1,7 +1,12 @@ -# $Id: generic_xflow.mk 539 2013-10-13 17:06:35Z mueller $ +# $Id: generic_xflow.mk 646 2015-02-15 12:04:55Z mueller $ +# +# Copyright 2007-2015 by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory # # Revision History: # Date Rev Version Comment +# 2015-02-06 643 1.10 use make_ise; rename xise_msg_filter <- isemsg_filter +# drop --ise_path from vbomconv; # 2013-10-12 539 1.9 use xtwi; support trce tsi file; use -C for cpp # 2013-01-27 477 1.8 remove defaults for ISE_(BOARD|PATH) and XFLOWOPT_* # use dontincdep.mk to suppress .dep include on clean @@ -80,11 +85,11 @@ XFLOW = xflow -p ${ISE_PATH} # %.ngc: %.vbom if [ ! -d ./ise ]; then mkdir ./ise; fi - (cd ./ise; vbomconv --ise_path=${ISE_PATH} --xst_prj ../$< > $*.prj) + (cd ./ise; vbomconv --xst_prj ../$< > $*.prj) (cd ./ise; touch $*.xcf) if [ -r $*.xcf ]; then cp $*.xcf ./ise; fi - if [ -r ${RETROBASE}/rtl/make/${XFLOWOPT_SYN} ]; then \ - cp ${RETROBASE}/rtl/make/${XFLOWOPT_SYN} ./ise; fi + if [ -r ${RETROBASE}/rtl/make_ise/${XFLOWOPT_SYN} ]; then \ + cp ${RETROBASE}/rtl/make_ise/${XFLOWOPT_SYN} ./ise; fi if [ -r ${XFLOWOPT_SYN} ]; then cp ${XFLOWOPT_SYN} ./ise; fi xtwi ${XFLOW} -wd ise -synth ${XFLOWOPT_SYN} \ -g top_entity:`vbomconv --get_top $<` $*.prj @@ -94,7 +99,7 @@ XFLOW = xflow -p ${ISE_PATH} @ echo "===============================================================" @ echo "* XST Diagnostic Summary *" @ echo "===============================================================" - @ if [ -r $*.mfset ]; then isemsg_filter xst $*.mfset $*_xst.log; fi + @ if [ -r $*.mfset ]; then xise_msg_filter xst $*.mfset $*_xst.log; fi @ if [ ! -r $*.mfset ]; then grep -i -A 1 ":.*:" $*_xst.log || true; fi @ echo "===============================================================" # @@ -105,8 +110,8 @@ XFLOW = xflow -p ${ISE_PATH} (cd ./ise; vbomconv --xst_prj ../$< > $*.prj) (cd ./ise; touch $*.xcf) if [ -r $*.xcf ]; then cp $*.xcf ./ise; fi - if [ -r ${RETROBASE}/rtl/make/${XFLOWOPT_SYN} ]; then \ - cp ${RETROBASE}/rtl/make/${XFLOWOPT_SYN} ./ise; fi + if [ -r ${RETROBASE}/rtl/make_ise/${XFLOWOPT_SYN} ]; then \ + cp ${RETROBASE}/rtl/make_ise/${XFLOWOPT_SYN} ./ise; fi if [ -r ${XFLOWOPT_SYN} ]; then cp ${XFLOWOPT_SYN} ./ise; fi xtwi ${XFLOW} -wd ise -synth ${XFLOWOPT_SYN} \ -g top_entity:`vbomconv --get_top $<` $*.prj @@ -116,7 +121,7 @@ XFLOW = xflow -p ${ISE_PATH} @ echo "===============================================================" @ echo "* XST Diagnostic Summary *" @ echo "===============================================================" - @ if [ -r $*.mfset ]; then isemsg_filter xst $*.mfset $*_xst.log; fi + @ if [ -r $*.mfset ]; then xise_msg_filter xst $*.mfset $*_xst.log; fi @ if [ ! -r $*.mfset ]; then grep -i -A 1 ":.*:" $*_xst.log || true; fi @ echo "===============================================================" # @@ -136,8 +141,8 @@ XFLOW = xflow -p ${ISE_PATH} if [ ! -d ./ise ]; then mkdir ./ise; fi if [ -r $*.ngc ]; then cp -p $*.ngc ./ise; fi if [ -r $*.ucf ]; then cp -p $*.ucf ./ise; fi - if [ -r ${RETROBASE}/rtl/make/${XFLOWOPT_IMP} ]; then \ - cp ${RETROBASE}/rtl/make/${XFLOWOPT_IMP} ./ise; fi + if [ -r ${RETROBASE}/rtl/make_ise/${XFLOWOPT_IMP} ]; then \ + cp ${RETROBASE}/rtl/make_ise/${XFLOWOPT_IMP} ./ise; fi if [ -r ${XFLOWOPT_IMP} ]; then cp -p ${XFLOWOPT_IMP} ./ise; fi xtwi ${XFLOW} -wd ise -implement ${XFLOWOPT_IMP} $< (cd ./ise; chmod -x *.* ) @@ -153,15 +158,15 @@ XFLOW = xflow -p ${ISE_PATH} echo "=============================================================";\ echo "* Translate Diagnostic Summary *";\ echo "=============================================================";\ - isemsg_filter tra $*.mfset $*_tra.log;\ + xise_msg_filter tra $*.mfset $*_tra.log;\ echo "=============================================================";\ echo "* MAP Diagnostic Summary *";\ echo "=============================================================";\ - isemsg_filter map $*.mfset $*_map.log;\ + xise_msg_filter map $*.mfset $*_map.log;\ echo "=============================================================";\ echo "* PAR Diagnostic Summary *";\ echo "=============================================================";\ - isemsg_filter par $*.mfset $*_par.log;\ + xise_msg_filter par $*.mfset $*_par.log;\ echo "=============================================================";\ fi # @@ -183,7 +188,7 @@ XFLOW = xflow -p ${ISE_PATH} echo "=============================================================";\ echo "* Bitgen Diagnostic Summary *";\ echo "=============================================================";\ - isemsg_filter bgn $*.mfset $*_bgn.log;\ + xise_msg_filter bgn $*.mfset $*_bgn.log;\ echo "=============================================================";\ fi # @@ -221,15 +226,15 @@ endif # output: .PHONY %.mfsum: %.mfset @ echo "=== XST summary =============================================" - @ if [ -r $*_xst.log ]; then isemsg_filter xst $*.mfset $*_xst.log; fi + @ if [ -r $*_xst.log ]; then xise_msg_filter xst $*.mfset $*_xst.log; fi @ echo "=== Translate summary =======================================" - @ if [ -r $*_tra.log ]; then isemsg_filter tra $*.mfset $*_tra.log; fi + @ if [ -r $*_tra.log ]; then xise_msg_filter tra $*.mfset $*_tra.log; fi @ echo "=== MAP summary =============================================" - @ if [ -r $*_map.log ]; then isemsg_filter map $*.mfset $*_map.log; fi + @ if [ -r $*_map.log ]; then xise_msg_filter map $*.mfset $*_map.log; fi @ echo "=== PAR summary =============================================" - @ if [ -r $*_par.log ]; then isemsg_filter par $*.mfset $*_par.log; fi + @ if [ -r $*_par.log ]; then xise_msg_filter par $*.mfset $*_par.log; fi @ echo "=== Bitgen summary ==========================================" - @ if [ -r $*_bgn.log ]; then isemsg_filter bgn $*.mfset $*_bgn.log; fi + @ if [ -r $*_bgn.log ]; then xise_msg_filter bgn $*.mfset $*_bgn.log; fi # # @@ -303,7 +308,9 @@ endif cpp -C -I${RETROBASE}/rtl -MM $*.ucf_cpp |\ sed 's/\.o:/\.ucf:/' > $*.dep_ucf_cpp # -include $(RETROBASE)/rtl/make/dontincdep.mk +# Cleanup +# +include $(RETROBASE)/rtl/make_ise/dontincdep.mk # .PHONY : ise_clean ise_tmp_clean # diff --git a/rtl/make/generic_xflow_cpld.mk b/rtl/make_ise/generic_xflow_cpld.mk similarity index 95% rename from rtl/make/generic_xflow_cpld.mk rename to rtl/make_ise/generic_xflow_cpld.mk index 1fd1e116..39f9e016 100644 --- a/rtl/make/generic_xflow_cpld.mk +++ b/rtl/make_ise/generic_xflow_cpld.mk @@ -1,4 +1,7 @@ -# $Id: generic_xflow_cpld.mk 539 2013-10-13 17:06:35Z mueller $ +# $Id: generic_xflow_cpld.mk 642 2015-02-06 18:53:12Z mueller $ +# +# Copyright 2010-2013 by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory # # Revision History: # Date Rev Version Comment diff --git a/rtl/make/imp_7a_speed.opt b/rtl/make_ise/imp_7a_speed.opt similarity index 100% rename from rtl/make/imp_7a_speed.opt rename to rtl/make_ise/imp_7a_speed.opt diff --git a/rtl/make/imp_s3_speed.opt b/rtl/make_ise/imp_s3_speed.opt similarity index 100% rename from rtl/make/imp_s3_speed.opt rename to rtl/make_ise/imp_s3_speed.opt diff --git a/rtl/make/imp_s3_speed_maptd.opt b/rtl/make_ise/imp_s3_speed_maptd.opt similarity index 100% rename from rtl/make/imp_s3_speed_maptd.opt rename to rtl/make_ise/imp_s3_speed_maptd.opt diff --git a/rtl/make/imp_s6_speed.opt b/rtl/make_ise/imp_s6_speed.opt similarity index 100% rename from rtl/make/imp_s6_speed.opt rename to rtl/make_ise/imp_s6_speed.opt diff --git a/rtl/make/imp_s6_speed_ise133.opt b/rtl/make_ise/imp_s6_speed_ise133.opt similarity index 100% rename from rtl/make/imp_s6_speed_ise133.opt rename to rtl/make_ise/imp_s6_speed_ise133.opt diff --git a/rtl/make/syn_7a_speed.opt b/rtl/make_ise/syn_7a_speed.opt similarity index 100% rename from rtl/make/syn_7a_speed.opt rename to rtl/make_ise/syn_7a_speed.opt diff --git a/rtl/make/syn_s3_speed.opt b/rtl/make_ise/syn_s3_speed.opt similarity index 100% rename from rtl/make/syn_s3_speed.opt rename to rtl/make_ise/syn_s3_speed.opt diff --git a/rtl/make/syn_s6_speed.opt b/rtl/make_ise/syn_s6_speed.opt similarity index 100% rename from rtl/make/syn_s6_speed.opt rename to rtl/make_ise/syn_s6_speed.opt diff --git a/rtl/make/syn_s6_speed_ise133.opt b/rtl/make_ise/syn_s6_speed_ise133.opt similarity index 100% rename from rtl/make/syn_s6_speed_ise133.opt rename to rtl/make_ise/syn_s6_speed_ise133.opt diff --git a/rtl/make/xflow_default_atlys.mk b/rtl/make_ise/xflow_default_atlys.mk similarity index 100% rename from rtl/make/xflow_default_atlys.mk rename to rtl/make_ise/xflow_default_atlys.mk diff --git a/rtl/make/xflow_default_nexys2.mk b/rtl/make_ise/xflow_default_nexys2.mk similarity index 100% rename from rtl/make/xflow_default_nexys2.mk rename to rtl/make_ise/xflow_default_nexys2.mk diff --git a/rtl/make/xflow_default_nexys3.mk b/rtl/make_ise/xflow_default_nexys3.mk similarity index 100% rename from rtl/make/xflow_default_nexys3.mk rename to rtl/make_ise/xflow_default_nexys3.mk diff --git a/rtl/make/xflow_default_nexys4.mk b/rtl/make_ise/xflow_default_nexys4.mk similarity index 100% rename from rtl/make/xflow_default_nexys4.mk rename to rtl/make_ise/xflow_default_nexys4.mk diff --git a/rtl/make/xflow_default_s3board.mk b/rtl/make_ise/xflow_default_s3board.mk similarity index 100% rename from rtl/make/xflow_default_s3board.mk rename to rtl/make_ise/xflow_default_s3board.mk diff --git a/rtl/make/xflow_default_s3board_200.mk b/rtl/make_ise/xflow_default_s3board_200.mk similarity index 100% rename from rtl/make/xflow_default_s3board_200.mk rename to rtl/make_ise/xflow_default_s3board_200.mk diff --git a/rtl/make_viv/dontincdep.mk b/rtl/make_viv/dontincdep.mk new file mode 100644 index 00000000..57783fbf --- /dev/null +++ b/rtl/make_viv/dontincdep.mk @@ -0,0 +1,24 @@ +# $Id: dontincdep.mk 646 2015-02-15 12:04:55Z mueller $ +# +# Copyright 2013- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# Revision History: +# Date Rev Version Comment +# 2013-01-27 477 1.0 Initial version +# +# DONTINCDEP controls whether dependency files are included. Set it if +# any of the 'clean' type targets is involved +# +ifneq ($(findstring clean, $(MAKECMDGOALS)),) +DONTINCDEP = 1 +endif +ifneq ($(findstring realclean, $(MAKECMDGOALS)),) +DONTINCDEP = 1 +endif +ifneq ($(findstring distclean, $(MAKECMDGOALS)),) +DONTINCDEP = 1 +endif +ifdef DONTINCDEP +$(info DONTINCDEP set, *.dep files not included) +endif diff --git a/rtl/make_viv/generic_ghdl.mk b/rtl/make_viv/generic_ghdl.mk new file mode 100644 index 00000000..602f3cee --- /dev/null +++ b/rtl/make_viv/generic_ghdl.mk @@ -0,0 +1,38 @@ +# $Id: generic_ghdl.mk 646 2015-02-15 12:04:55Z mueller $ +# +# Copyright 2015- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# Revision History: +# Date Rev Version Comment +# 2015-02-14 646 1.0 Initial version (cloned from make_ise) +# +GHDLIEEE = --ieee=synopsys +GHDLXLPATH = $(XTWV_PATH)/ghdl +# +% : %.vbom + vbomconv --ghdl_i $< + vbomconv --ghdl_m --xlpath=$(GHDLXLPATH) $< +# +# rules for _[o]sim to use 'virtual' [o]sim vbom's (derived from _ssim) +# +%_osim : %_ssim.vbom + vbomconv --ghdl_i $*_osim.vbom + vbomconv --ghdl_m --xlpath=$(GHDLXLPATH) $*_osim.vbom +# +%.dep_ghdl: %.vbom + vbomconv --dep_ghdl $< > $@ +# +include $(RETROBASE)/rtl/make_ise/dontincdep.mk +# +.PHONY: ghdl_clean ghdl_tmp_clean +# +ghdl_clean: ghdl_tmp_clean + rm -f $(EXE_all) + rm -f $(EXE_all:%=%_[so]sim) + rm -f cext_*.o +# +ghdl_tmp_clean: + find -maxdepth 1 -name "*.o" | grep -v "^\./cext_" | xargs rm -f + rm -f work-obj93.cf +# diff --git a/rtl/make_viv/generic_vivado.mk b/rtl/make_viv/generic_vivado.mk new file mode 100644 index 00000000..2dc81deb --- /dev/null +++ b/rtl/make_viv/generic_vivado.mk @@ -0,0 +1,142 @@ +# $Id: generic_vivado.mk 646 2015-02-15 12:04:55Z mueller $ +# +# Copyright 2015- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# Revision History: +# Date Rev Version Comment +# 2015-02-15 646 1.0 Initial version +# 2015-01-25 637 0.1 First draft +#--- +# +# check that part is defined +# +ifndef VIV_BOARD_SETUP +$(error VIV_BOARD_SETUP is not defined) +endif +# +# ensure that default tools and flows are defined +# +ifndef VIV_INIT +VIV_INIT = $(RETROBASE)/rtl/make_viv/viv_init.tcl +endif +ifndef VIV_BUILD_FLOW +VIV_BUILD_FLOW = $(RETROBASE)/rtl/make_viv/viv_default_build.tcl +endif +ifndef VIV_CONFIG_FLOW +VIV_CONFIG_FLOW = $(RETROBASE)/rtl/make_viv/viv_default_config.tcl +endif +ifndef VIV_MODEL_FLOW +VIV_MODEL_FLOW = $(RETROBASE)/rtl/make_viv/viv_default_model.tcl +endif +# +# $@ first target +# $< first dependency +# $* stem in rule match +# +# when chaining, don't delete 'expensive' intermediate files: +.SECONDARY : +# +# Synthesize + Implement -> generate bit file +# input: %.vbom vbom project description +# output: %.bit +# +%.bit : %.vbom + rm -rf project_mflow + xtwv vivado -mode batch \ + -source ${VIV_INIT} \ + -source ${VIV_BOARD_SETUP} \ + -source ${VIV_BUILD_FLOW} \ + -tclargs $* bit +# +# Configure FPGA with vivado hardware server +# input: %.bit +# output: .PHONY +# +%.vconfig : %.bit + xtwv vivado -mode batch \ + -source ${VIV_INIT} \ + -source ${VIV_BOARD_SETUP} \ + -source ${VIV_CONFIG_FLOW} \ + -tclargs $* +# +# Partial Synthesize + Implement -> generate dcp for model generation +# +%_syn.dcp : %.vbom + rm -rf project_mflow + xtwv vivado -mode batch \ + -source ${VIV_INIT} \ + -source ${VIV_BOARD_SETUP} \ + -source ${VIV_BUILD_FLOW} \ + -tclargs $* syn +%_opt.dcp %_rou.dcp : %.vbom + rm -rf project_mflow + xtwv vivado -mode batch \ + -source ${VIV_INIT} \ + -source ${VIV_BOARD_SETUP} \ + -source ${VIV_BUILD_FLOW} \ + -tclargs $* imp +# +# Post-synthesis functional simulation model (Vhdl/Unisim) +# input: %_syn.dcp +# output: %_ssim.vhd +# +%_ssim.vhd : %_syn.dcp + xtwv vivado -mode batch \ + -source ${VIV_INIT} \ + -source ${VIV_MODEL_FLOW} \ + -tclargs $* ssim +# +# Post-optimization functional simulation model (Vhdl/Unisim) +# input: %_opt.dcp +# output: %_osim.vhd +# +%_osim.vhd : %_opt.dcp + xtwv vivado -mode batch \ + -source ${VIV_INIT} \ + -source ${VIV_MODEL_FLOW} \ + -tclargs $* osim +# +# Post-routing timing simulation model (Verilog/Simprim) +# input: %_rou.dcp +# output: %_tsim.v +# %_tsim.sdf +# +%_tsim.v %_tsim.sdf : %_rou.dcp + xtwv vivado -mode batch \ + -source ${VIV_INIT} \ + -source ${VIV_MODEL_FLOW} \ + -tclargs $* tsim +# +# vivado project quick starter +# +.PHONY : vivado +vivado : + xtwv vivado -mode gui project_mflow/project_mflow.xpr + +# +# generate dep_vsyn files from vbom +# +%.dep_vsyn: %.vbom + vbomconv --dep_vsyn $< > $@ + +# +# Cleanup +# +include $(RETROBASE)/rtl/make_viv/dontincdep.mk +# +.PHONY : viv_clean viv_tmp_clean +# +viv_clean: viv_tmp_clean + rm -f *.bit + rm -f *.dcp + rm -f *.jou + rm -f *.log + rm -f *.rpt + rm -f *_[so]sim.vhd + rm -f *_tsim.v + rm -f *_tsim.sdf +# +viv_tmp_clean: + rm -rf ./project_mflow +# diff --git a/rtl/make_viv/viv_default_basys3.mk b/rtl/make_viv/viv_default_basys3.mk new file mode 100644 index 00000000..729305fb --- /dev/null +++ b/rtl/make_viv/viv_default_basys3.mk @@ -0,0 +1,16 @@ +# $Id: viv_default_basys3.mk 637 2015-01-25 18:36:40Z mueller $ +# +# Copyright 2015- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# Revision History: +# Date Rev Version Comment +# 2015-01-25 637 1.0 Initial version +#--- +# +# Setup for Digilent Basys3 +# +# setup default board and part +# +VIV_BOARD_SETUP = $(RETROBASE)/rtl/bplib/basys3/basys3_setup.tcl +# diff --git a/rtl/make_viv/viv_default_build.tcl b/rtl/make_viv/viv_default_build.tcl new file mode 100644 index 00000000..b559ee9e --- /dev/null +++ b/rtl/make_viv/viv_default_build.tcl @@ -0,0 +1,12 @@ +# $Id: viv_default_build.tcl 646 2015-02-15 12:04:55Z mueller $ +# +# Copyright 2015- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# Revision History: +# Date Rev Version Comment +# 2015-02-14 646 1.0 Initial version +# 2015-01-25 637 0.1 First draft +# + +rvtb_default_build [lindex $::argv 0] [lindex $::argv 1] diff --git a/rtl/make_viv/viv_default_config.tcl b/rtl/make_viv/viv_default_config.tcl new file mode 100644 index 00000000..eb6705d8 --- /dev/null +++ b/rtl/make_viv/viv_default_config.tcl @@ -0,0 +1,12 @@ +# $Id: viv_default_config.tcl 646 2015-02-15 12:04:55Z mueller $ +# +# Copyright 2015- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# Revision History: +# Date Rev Version Comment +# 2015-02-14 646 1.0 Initial version +# 2015-01-25 637 0.1 First draft +# + +rvtb_default_config [lindex $::argv 0] diff --git a/rtl/make_viv/viv_default_model.tcl b/rtl/make_viv/viv_default_model.tcl new file mode 100644 index 00000000..00d1f7fa --- /dev/null +++ b/rtl/make_viv/viv_default_model.tcl @@ -0,0 +1,11 @@ +# $Id: viv_default_model.tcl 646 2015-02-15 12:04:55Z mueller $ +# +# Copyright 2015- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# Revision History: +# Date Rev Version Comment +# 2015-02-14 646 1.0 Initial version +# + +rvtb_default_model [lindex $::argv 0] [lindex $::argv 1] diff --git a/rtl/make_viv/viv_default_nexys4.mk b/rtl/make_viv/viv_default_nexys4.mk new file mode 100644 index 00000000..4c0637f8 --- /dev/null +++ b/rtl/make_viv/viv_default_nexys4.mk @@ -0,0 +1,16 @@ +# $Id: viv_default_nexys4.mk 640 2015-02-01 09:56:53Z mueller $ +# +# Copyright 2015- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# Revision History: +# Date Rev Version Comment +# 2015-01-25 639 1.0 Initial version +#--- +# +# Setup for Digilent Nexys4 +# +# setup default board and part +# +VIV_BOARD_SETUP = $(RETROBASE)/rtl/bplib/nexys4/nexys4_setup.tcl +# diff --git a/rtl/make_viv/viv_init.tcl b/rtl/make_viv/viv_init.tcl new file mode 100644 index 00000000..f5533f31 --- /dev/null +++ b/rtl/make_viv/viv_init.tcl @@ -0,0 +1,13 @@ +# $Id: viv_init.tcl 646 2015-02-15 12:04:55Z mueller $ +# +# Copyright 2015- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# Revision History: +# Date Rev Version Comment +# 2015-02-14 646 1.0 Initial version +# 2015-01-25 637 0.1 First draft +# +source -notrace "$::env(RETROBASE)/rtl/make_viv/viv_tools_build.tcl" +source -notrace "$::env(RETROBASE)/rtl/make_viv/viv_tools_config.tcl" +source -notrace "$::env(RETROBASE)/rtl/make_viv/viv_tools_model.tcl" diff --git a/rtl/make_viv/viv_tools_build.tcl b/rtl/make_viv/viv_tools_build.tcl new file mode 100644 index 00000000..20552bea --- /dev/null +++ b/rtl/make_viv/viv_tools_build.tcl @@ -0,0 +1,163 @@ +# $Id: viv_tools_build.tcl 649 2015-02-21 21:10:16Z mueller $ +# +# Copyright 2015- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# Revision History: +# Date Rev Version Comment +# 2015-02-21 649 1.1 add 2014.4 specific setups +# 2015-02-14 646 1.0 Initial version +# + +# +# -------------------------------------------------------------------- +# +proc rvtb_trace_cmd {cmd} { + puts "# $cmd" + eval $cmd + return "" +} + +# +# -------------------------------------------------------------------- +# +proc rvtb_locate_setup_file {stem} { + set name "${stem}_setup.tcl" + if {[file readable $name]} {return $name} + set name "$../{stem}_setup.tcl" + if {[file readable $name]} {return $name} + return "" +} + +# +# -------------------------------------------------------------------- +# +proc rvtb_mv_file {src dst} { + if {[file readable $src]} { + exec mv $src $dst + } else { + puts "rvtb_mv_file-W: file '$src' not existing" + } + return "" +} + +# +# -------------------------------------------------------------------- +# +proc rvtb_cp_file {src dst} { + if {[file readable $src]} { + exec cp -p $src $dst + } else { + puts "rvtb_cp_file-W: file '$src' not existing" + } + return "" +} + +# +# -------------------------------------------------------------------- +# +proc rvtb_build_check {step} { + get_msg_config -rules + return "" +} + +# +# -------------------------------------------------------------------- +# +proc rvtb_default_build {stem step} { + + # general setups + switch [version -short] { + "2014.4" { + # suppress nonsense "cannot add Board Part xilinx.com:kc705..." messages + # set here to avoid messages during create_project + set_msg_config -suppress -id {Board 49-26} + } + } + + # read setup + set setup_file [rvtb_locate_setup_file $stem] + if {$setup_file ne ""} {source -notrace $setup_file} + + # Create project + rvtb_trace_cmd "create_project project_mflow ./project_mflow" + + # Setup project properties + set obj [get_projects project_mflow] + set_property "default_lib" "xil_defaultlib" $obj + set_property "part" $::rvtb_part $obj + set_property "simulator_language" "Mixed" $obj + set_property "target_language" "VHDL" $obj + + # version dependent setups + switch [version -short] { + "2014.4" { + # suppress nonsense "cannot add Board Part xilinx.com:kc705..." messages + # repeated here because create_project apparently clears msg_config + set_msg_config -suppress -id {Board 49-26} + } + } + + # Setup filesets + set vbom_prj [exec vbomconv -vsyn_prj "${stem}.vbom"] + eval $vbom_prj + update_compile_order -fileset sources_1 + + # some handy variables + set path_runs "project_mflow/project_mflow.runs" + set path_syn1 "${path_runs}/synth_1" + set path_imp1 "${path_runs}/impl_1" + + # build: synthesize + rvtb_trace_cmd "launch_runs synth_1" + rvtb_trace_cmd "wait_on_run synth_1" + + rvtb_mv_file "$path_syn1/runme.log" "${stem}_syn.log" + + rvtb_cp_file "$path_syn1/${stem}_utilization_synth.rpt" "${stem}_syn_util.rpt" + rvtb_cp_file "$path_syn1/${stem}.dcp" "${stem}_syn.dcp" + + if {$step eq "syn"} {return [rvtb_build_check $step]} + + # build: implement + rvtb_trace_cmd "launch_runs impl_1" + rvtb_trace_cmd "wait_on_run impl_1" + + rvtb_cp_file "$path_imp1/runme.log" "${stem}_imp.log" + + rvtb_cp_file "$path_imp1/${stem}_route_status.rpt" "${stem}_rou_sta.rpt" + rvtb_cp_file "$path_imp1/${stem}_drc_routed.rpt" "${stem}_rou_drc.rpt" + rvtb_cp_file "$path_imp1/${stem}_io_placed.rpt" "${stem}_pla_io.rpt" + rvtb_cp_file "$path_imp1/${stem}_clock_utilization_placed.rpt" \ + "${stem}_pla_clk.rpt" + rvtb_cp_file "$path_imp1/${stem}_timing_summary_routed.rpt" \ + "${stem}_rou_tim.rpt" + rvtb_cp_file "$path_imp1/${stem}_utilization_placed.rpt" \ + "${stem}_pla_util.rpt" + rvtb_cp_file "$path_imp1/${stem}_drc_opted.rpt" "${stem}_opt_drc.rpt" + rvtb_cp_file "$path_imp1/${stem}_control_sets_placed.rpt" \ + "${stem}_pla_cset.rpt" + rvtb_cp_file "$path_imp1/${stem}_power_routed.rpt" "${stem}_rou_pwr.rpt" + + rvtb_cp_file "$path_imp1/${stem}_opt.dcp" "${stem}_opt.dcp" + rvtb_cp_file "$path_imp1/${stem}_placed.dcp" "${stem}_pla.dcp" + rvtb_cp_file "$path_imp1/${stem}_routed.dcp" "${stem}_rou.dcp" + + # additional reports + rvtb_trace_cmd "open_run impl_1" + report_utilization -file "${stem}_rou_util.rpt" + report_utilization -hierarchical -file "${stem}_rou_util_h.rpt" + report_datasheet -file "${stem}_rou_ds.rpt" + + if {$step eq "imp"} {return [rvtb_build_check $step]} + + # build: bitstream + rvtb_trace_cmd "launch_runs impl_1 -to_step write_bitstream" + rvtb_trace_cmd "wait_on_run impl_1" + + rvtb_mv_file "$path_imp1/${stem}.bit" "." + rvtb_mv_file "$path_imp1/runme.log" "${stem}_bit.log" + + return [rvtb_build_check $step] +} + diff --git a/rtl/make_viv/viv_tools_config.tcl b/rtl/make_viv/viv_tools_config.tcl new file mode 100644 index 00000000..22a36a6a --- /dev/null +++ b/rtl/make_viv/viv_tools_config.tcl @@ -0,0 +1,29 @@ +# $Id: viv_tools_config.tcl 646 2015-02-15 12:04:55Z mueller $ +# +# Copyright 2015- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# Revision History: +# Date Rev Version Comment +# 2015-02-14 646 1.0 Initial version +# + +# +# -------------------------------------------------------------------- +# +proc rvtb_default_config {stem} { + # open and connect to hardware server + open_hw + connect_hw_server + + # connect to target + open_hw_target [lindex [get_hw_targets -of_objects [get_hw_servers localhost]] 0] + + # setup bitfile + set_property PROGRAM.FILE "${stem}.bit" [lindex [get_hw_devices] 0] + + # and configure FPGA + program_hw_devices [lindex [get_hw_devices] 0] + + return ""; +} diff --git a/rtl/make_viv/viv_tools_model.tcl b/rtl/make_viv/viv_tools_model.tcl new file mode 100644 index 00000000..9d284428 --- /dev/null +++ b/rtl/make_viv/viv_tools_model.tcl @@ -0,0 +1,38 @@ +# $Id: viv_tools_model.tcl 646 2015-02-15 12:04:55Z mueller $ +# +# Copyright 2015- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# Revision History: +# Date Rev Version Comment +# 2015-02-14 646 1.0 Initial version +# + +# +# -------------------------------------------------------------------- +# +proc rvtb_default_model {stem mode} { + + switch $mode { + ssim { + open_checkpoint "${stem}_syn.dcp" + write_vhdl -mode funcsim -force "${stem}_ssim.vhd" + } + + osim { + open_checkpoint "${stem}_opt.dcp" + write_vhdl -mode funcsim -force "${stem}_osim.vhd" + } + + tsim { + open_checkpoint "${stem}_rou.dcp" + write_verilog -mode timesim -force -sdf_anno true "${stem}_tsim.v" + write_sdf -mode timesim -force "${stem}_tsim.sdf" + } + + default { + error "-E: bad mode: $mode"; + } + } + return ""; +} diff --git a/rtl/sys_gen/tst_fx2loop/Makefile b/rtl/sys_gen/tst_fx2loop/Makefile index 819e4334..4f42ea3d 100644 --- a/rtl/sys_gen/tst_fx2loop/Makefile +++ b/rtl/sys_gen/tst_fx2loop/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 602 2014-11-08 21:42:47Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -10,7 +10,7 @@ VBOM_all = $(wildcard *.vbom) NGC_all = $(VBOM_all:.vbom=.ngc) # -include $(RETROBASE)/rtl/make/xflow_default_nexys2.mk +include $(RETROBASE)/rtl/make_ise/xflow_default_nexys2.mk # .PHONY : all clean distclean # @@ -33,8 +33,7 @@ tst_fx2loop_si : tst_fx2loop_si.c # #---- # -include $(RETROBASE)/tools/make/dontincdep.mk -include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_fx2loop/nexys2/ic/Makefile b/rtl/sys_gen/tst_fx2loop/nexys2/ic/Makefile index 9c7758d9..301b7416 100644 --- a/rtl/sys_gen/tst_fx2loop/nexys2/ic/Makefile +++ b/rtl/sys_gen/tst_fx2loop/nexys2/ic/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -8,7 +8,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make/xflow_default_nexys2.mk +include $(RETROBASE)/rtl/make_ise/xflow_default_nexys2.mk FX2_FILE = nexys2_jtag_2fifo_ic.ihx # .PHONY : all clean @@ -20,8 +20,8 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make/generic_xflow.mk -include $(RETROBASE)/rtl/make/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_fx2loop/nexys2/ic/sys_conf.vhd b/rtl/sys_gen/tst_fx2loop/nexys2/ic/sys_conf.vhd index 6be921fe..fe7e16a9 100644 --- a/rtl/sys_gen/tst_fx2loop/nexys2/ic/sys_conf.vhd +++ b/rtl/sys_gen/tst_fx2loop/nexys2/ic/sys_conf.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf.vhd 453 2012-01-15 17:51:18Z mueller $ +-- $Id: sys_conf.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2012- by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Definitions for sys_tst_fx2loop_ic_n2 (for synthesis) -- -- Dependencies: - --- Tool versions: xst 13.3; ghdl 0.29 +-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31 -- Revision History: -- Date Rev Version Comment -- 2012-01-15 453 1.0 Initial version diff --git a/rtl/sys_gen/tst_fx2loop/nexys2/ic3/Makefile b/rtl/sys_gen/tst_fx2loop/nexys2/ic3/Makefile index 49ddfc32..5f150990 100644 --- a/rtl/sys_gen/tst_fx2loop/nexys2/ic3/Makefile +++ b/rtl/sys_gen/tst_fx2loop/nexys2/ic3/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -8,7 +8,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make/xflow_default_nexys2.mk +include $(RETROBASE)/rtl/make_ise/xflow_default_nexys2.mk FX2_FILE = nexys2_jtag_3fifo_ic.ihx # .PHONY : all clean @@ -20,8 +20,8 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make/generic_xflow.mk -include $(RETROBASE)/rtl/make/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_conf.vhd b/rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_conf.vhd index dc22a104..0df1ffe9 100644 --- a/rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_conf.vhd +++ b/rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_conf.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf.vhd 453 2012-01-15 17:51:18Z mueller $ +-- $Id: sys_conf.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2012- by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Definitions for sys_tst_fx2loop_ic3_n2 (for synthesis) -- -- Dependencies: - --- Tool versions: xst 13.3; ghdl 0.29 +-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31 -- Revision History: -- Date Rev Version Comment -- 2012-01-15 453 1.0 Initial version diff --git a/rtl/sys_gen/tst_fx2loop/nexys2/sys_tst_fx2loop_n2.vbom b/rtl/sys_gen/tst_fx2loop/nexys2/sys_tst_fx2loop_n2.vbom index 2812af04..d2ca6442 100644 --- a/rtl/sys_gen/tst_fx2loop/nexys2/sys_tst_fx2loop_n2.vbom +++ b/rtl/sys_gen/tst_fx2loop/nexys2/sys_tst_fx2loop_n2.vbom @@ -1,6 +1,5 @@ # this is the vbom for the 'generic' top level entity # to be referenced in the vbom's of the specific systems -# ./as/sys_tst_fx2loop_as_n2 # ./ic/sys_tst_fx2loop_ic_n2 # ./ic3/sys_tst_fx2loop_ic3_n2 # @@ -14,13 +13,12 @@ ../../../bplib/nxcramlib/nxcramlib.vhd ${sys_conf} # components -[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom +[xst,vsyn,isim,vsim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom [ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom ../../../vlib/genlib/clkdivce.vbom ../../../bplib/bpgen/sn_humanio.vbom ../tst_fx2loop_hiomap.vbom ../tst_fx2loop.vbom -../../../bplib/fx2lib/fx2_2fifoctl_as.vbom ../../../bplib/fx2lib/fx2_2fifoctl_ic.vbom ../../../bplib/fx2lib/fx2_3fifoctl_ic.vbom ../../../bplib/nxcramlib/nx_cram_dummy.vbom diff --git a/rtl/sys_gen/tst_fx2loop/nexys2/sys_tst_fx2loop_n2.vhd b/rtl/sys_gen/tst_fx2loop/nexys2/sys_tst_fx2loop_n2.vhd index e1c808f6..b07af9db 100644 --- a/rtl/sys_gen/tst_fx2loop/nexys2/sys_tst_fx2loop_n2.vhd +++ b/rtl/sys_gen/tst_fx2loop/nexys2/sys_tst_fx2loop_n2.vhd @@ -1,6 +1,6 @@ --- $Id: sys_tst_fx2loop_n2.vhd 461 2012-04-09 21:17:54Z mueller $ +-- $Id: sys_tst_fx2loop_n2.vhd 649 2015-02-21 21:10:16Z mueller $ -- --- Copyright 2011-2012 by Walter F.J. Mueller +-- Copyright 2011-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -20,7 +20,6 @@ -- bpgen/sn_humanio -- tst_fx2loop_hiomap -- tst_fx2loop --- bplib/fx2lib/fx2_2fifoctl_as [sys_conf_fx2_type="as2"] -- bplib/fx2lib/fx2_2fifoctl_ic [sys_conf_fx2_type="ic2"] -- bplib/fx2lib/fx2_3fifoctl_ic [sys_conf_fx2_type="ic3"] -- bplib/nxcramlib/nx_cram_dummy @@ -28,7 +27,7 @@ -- Test bench: - -- -- Target Devices: generic --- Tool versions: xst 13.3; ghdl 0.29 +-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri ctl/MHz @@ -38,6 +37,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2015-01-25 638 1.1.1 retire fx2_2fifoctl_as -- 2012-01-15 453 1.1 now generic for as,ic,ic3 controllers -- 2011-12-26 445 1.0 Initial version ------------------------------------------------------------------------------ @@ -225,44 +225,6 @@ begin TX2BUSY => FX2_TX2BUSY ); - FX2_CNTL_AS : if sys_conf_fx2_type = "as2" generate - CNTL : fx2_2fifoctl_as - generic map ( - RXFAWIDTH => 5, - TXFAWIDTH => 5, - CCWIDTH => sys_conf_fx2_ccwidth, - RXAEMPTY_THRES => 1, - TXAFULL_THRES => 1, - PETOWIDTH => sys_conf_fx2_petowidth, - RDPWLDELAY => sys_conf_fx2_rdpwldelay, - RDPWHDELAY => sys_conf_fx2_rdpwhdelay, - WRPWLDELAY => sys_conf_fx2_wrpwldelay, - WRPWHDELAY => sys_conf_fx2_wrpwhdelay, - FLAGDELAY => sys_conf_fx2_flagdelay) - port map ( - CLK => CLK, - CE_USEC => CE_USEC, - RESET => RESET, - RXDATA => FX2_RXDATA, - RXVAL => FX2_RXVAL, - RXHOLD => FX2_RXHOLD, - RXAEMPTY => FX2_RXAEMPTY, - TXDATA => FX2_TXDATA, - TXENA => FX2_TXENA, - TXBUSY => FX2_TXBUSY, - TXAFULL => FX2_TXAFULL, - MONI => FX2_MONI, - I_FX2_IFCLK => I_FX2_IFCLK, - O_FX2_FIFO => O_FX2_FIFO, - I_FX2_FLAG => I_FX2_FLAG, - O_FX2_SLRD_N => O_FX2_SLRD_N, - O_FX2_SLWR_N => O_FX2_SLWR_N, - O_FX2_SLOE_N => O_FX2_SLOE_N, - O_FX2_PKTEND_N => O_FX2_PKTEND_N, - IO_FX2_DATA => IO_FX2_DATA - ); - end generate FX2_CNTL_AS; - FX2_CNTL_IC : if sys_conf_fx2_type = "ic2" generate CNTL : fx2_2fifoctl_ic generic map ( diff --git a/rtl/sys_gen/tst_fx2loop/nexys3/ic/Makefile b/rtl/sys_gen/tst_fx2loop/nexys3/ic/Makefile index 907e385f..65917696 100644 --- a/rtl/sys_gen/tst_fx2loop/nexys3/ic/Makefile +++ b/rtl/sys_gen/tst_fx2loop/nexys3/ic/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -8,7 +8,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make/xflow_default_nexys3.mk +include $(RETROBASE)/rtl/make_ise/xflow_default_nexys3.mk FX2_FILE = nexys3_jtag_2fifo_ic.ihx # .PHONY : all clean @@ -20,8 +20,8 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make/generic_xflow.mk -include $(RETROBASE)/rtl/make/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_fx2loop/nexys3/ic/sys_conf.vhd b/rtl/sys_gen/tst_fx2loop/nexys3/ic/sys_conf.vhd index e7150fbc..1ea1f4d4 100644 --- a/rtl/sys_gen/tst_fx2loop/nexys3/ic/sys_conf.vhd +++ b/rtl/sys_gen/tst_fx2loop/nexys3/ic/sys_conf.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf.vhd 538 2013-10-06 17:21:25Z mueller $ +-- $Id: sys_conf.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2012-2013 by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Definitions for sys_tst_fx2loop_ic_n3 (for synthesis) -- -- Dependencies: - --- Tool versions: xst 13.3, 14.5, 14.6; ghdl 0.29 +-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31 -- Revision History: -- Date Rev Version Comment -- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect diff --git a/rtl/sys_gen/tst_fx2loop/nexys3/ic3/Makefile b/rtl/sys_gen/tst_fx2loop/nexys3/ic3/Makefile index f463486f..f0b179e8 100644 --- a/rtl/sys_gen/tst_fx2loop/nexys3/ic3/Makefile +++ b/rtl/sys_gen/tst_fx2loop/nexys3/ic3/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -8,7 +8,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make/xflow_default_nexys3.mk +include $(RETROBASE)/rtl/make_ise/xflow_default_nexys3.mk FX2_FILE = nexys3_jtag_3fifo_ic.ihx # .PHONY : all clean @@ -20,8 +20,8 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make/generic_xflow.mk -include $(RETROBASE)/rtl/make/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_fx2loop/nexys3/ic3/sys_conf.vhd b/rtl/sys_gen/tst_fx2loop/nexys3/ic3/sys_conf.vhd index 191e88c1..56de9076 100644 --- a/rtl/sys_gen/tst_fx2loop/nexys3/ic3/sys_conf.vhd +++ b/rtl/sys_gen/tst_fx2loop/nexys3/ic3/sys_conf.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf.vhd 538 2013-10-06 17:21:25Z mueller $ +-- $Id: sys_conf.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2012-2013 by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Definitions for sys_tst_fx2loop_ic3_n3 (for synthesis) -- -- Dependencies: - --- Tool versions: xst 13.3, 14.5, 14.6; ghdl 0.29 +-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31 -- Revision History: -- Date Rev Version Comment -- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect diff --git a/rtl/sys_gen/tst_fx2loop/nexys3/sys_tst_fx2loop_n3.vbom b/rtl/sys_gen/tst_fx2loop/nexys3/sys_tst_fx2loop_n3.vbom index 2b22f0a4..e6b7207c 100644 --- a/rtl/sys_gen/tst_fx2loop/nexys3/sys_tst_fx2loop_n3.vbom +++ b/rtl/sys_gen/tst_fx2loop/nexys3/sys_tst_fx2loop_n3.vbom @@ -1,6 +1,5 @@ # this is the vbom for the 'generic' top level entity # to be referenced in the vbom's of the specific systems -# ./as/sys_tst_fx2loop_as_n3 # ./ic/sys_tst_fx2loop_ic_n3 # ./ic3/sys_tst_fx2loop_ic3_n3 # @@ -14,13 +13,12 @@ ../../../bplib/nxcramlib/nxcramlib.vhd ${sys_conf} # components -[xst,isim]../../../vlib/xlib/s6_cmt_sfs_unisim.vbom +[xst,vsyn,isim,vsim]../../../vlib/xlib/s6_cmt_sfs_unisim.vbom [ghdl]../../../vlib/xlib/s6_cmt_sfs_gsim.vbom ../../../vlib/genlib/clkdivce.vbom ../../../bplib/bpgen/sn_humanio.vbom ../tst_fx2loop_hiomap.vbom ../tst_fx2loop.vbom -../../../bplib/fx2lib/fx2_2fifoctl_as.vbom ../../../bplib/fx2lib/fx2_2fifoctl_ic.vbom ../../../bplib/fx2lib/fx2_3fifoctl_ic.vbom ../../../bplib/nxcramlib/nx_cram_dummy.vbom diff --git a/rtl/sys_gen/tst_fx2loop/nexys3/sys_tst_fx2loop_n3.vhd b/rtl/sys_gen/tst_fx2loop/nexys3/sys_tst_fx2loop_n3.vhd index 44fad53a..f26e6006 100644 --- a/rtl/sys_gen/tst_fx2loop/nexys3/sys_tst_fx2loop_n3.vhd +++ b/rtl/sys_gen/tst_fx2loop/nexys3/sys_tst_fx2loop_n3.vhd @@ -1,6 +1,6 @@ --- $Id: sys_tst_fx2loop_n3.vhd 538 2013-10-06 17:21:25Z mueller $ +-- $Id: sys_tst_fx2loop_n3.vhd 638 2015-01-25 22:01:38Z mueller $ -- --- Copyright 2012-2013 by Walter F.J. Mueller +-- Copyright 2012-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -20,7 +20,6 @@ -- bpgen/sn_humanio -- tst_fx2loop_hiomap -- tst_fx2loop --- bplib/fx2lib/fx2_2fifoctl_as [sys_conf_fx2_type="as2"] -- bplib/fx2lib/fx2_2fifoctl_ic [sys_conf_fx2_type="ic2"] -- bplib/fx2lib/fx2_3fifoctl_ic [sys_conf_fx2_type="ic3"] -- bplib/nxcramlib/nx_cram_dummy @@ -28,7 +27,7 @@ -- Test bench: - -- -- Target Devices: generic --- Tool versions: xst 13.3, 14.5, 14.6; ghdl 0.29 +-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri ctl/MHz @@ -239,44 +238,6 @@ begin TX2BUSY => FX2_TX2BUSY ); - FX2_CNTL_AS : if sys_conf_fx2_type = "as2" generate - CNTL : fx2_2fifoctl_as - generic map ( - RXFAWIDTH => 5, - TXFAWIDTH => 5, - CCWIDTH => sys_conf_fx2_ccwidth, - RXAEMPTY_THRES => 1, - TXAFULL_THRES => 1, - PETOWIDTH => sys_conf_fx2_petowidth, - RDPWLDELAY => sys_conf_fx2_rdpwldelay, - RDPWHDELAY => sys_conf_fx2_rdpwhdelay, - WRPWLDELAY => sys_conf_fx2_wrpwldelay, - WRPWHDELAY => sys_conf_fx2_wrpwhdelay, - FLAGDELAY => sys_conf_fx2_flagdelay) - port map ( - CLK => CLK, - CE_USEC => CE_USEC, - RESET => RESET, - RXDATA => FX2_RXDATA, - RXVAL => FX2_RXVAL, - RXHOLD => FX2_RXHOLD, - RXAEMPTY => FX2_RXAEMPTY, - TXDATA => FX2_TXDATA, - TXENA => FX2_TXENA, - TXBUSY => FX2_TXBUSY, - TXAFULL => FX2_TXAFULL, - MONI => FX2_MONI, - I_FX2_IFCLK => I_FX2_IFCLK, - O_FX2_FIFO => O_FX2_FIFO, - I_FX2_FLAG => I_FX2_FLAG, - O_FX2_SLRD_N => O_FX2_SLRD_N, - O_FX2_SLWR_N => O_FX2_SLWR_N, - O_FX2_SLOE_N => O_FX2_SLOE_N, - O_FX2_PKTEND_N => O_FX2_PKTEND_N, - IO_FX2_DATA => IO_FX2_DATA - ); - end generate FX2_CNTL_AS; - FX2_CNTL_IC : if sys_conf_fx2_type = "ic2" generate CNTL : fx2_2fifoctl_ic generic map ( diff --git a/rtl/sys_gen/tst_fx2loop/tst_fx2loop.vhd b/rtl/sys_gen/tst_fx2loop/tst_fx2loop.vhd index 8099f7c4..e6aaaba6 100644 --- a/rtl/sys_gen/tst_fx2loop/tst_fx2loop.vhd +++ b/rtl/sys_gen/tst_fx2loop/tst_fx2loop.vhd @@ -1,4 +1,4 @@ --- $Id: tst_fx2loop.vhd 510 2013-04-26 16:14:57Z mueller $ +-- $Id: tst_fx2loop.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2011-2013 by Walter F.J. Mueller -- @@ -20,7 +20,7 @@ -- Test bench: - -- -- Target Devices: generic --- Tool versions: xst 13.3; ghdl 0.29 +-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/sys_gen/tst_fx2loop/tst_fx2loop_hiomap.vhd b/rtl/sys_gen/tst_fx2loop/tst_fx2loop_hiomap.vhd index 3fb6bd42..a8f496db 100644 --- a/rtl/sys_gen/tst_fx2loop/tst_fx2loop_hiomap.vhd +++ b/rtl/sys_gen/tst_fx2loop/tst_fx2loop_hiomap.vhd @@ -1,4 +1,4 @@ --- $Id: tst_fx2loop_hiomap.vhd 453 2012-01-15 17:51:18Z mueller $ +-- $Id: tst_fx2loop_hiomap.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2011-2012 by Walter F.J. Mueller -- @@ -19,7 +19,7 @@ -- Test bench: - -- -- Target Devices: generic --- Tool versions: xst 13.3; ghdl 0.29 +-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/sys_gen/tst_fx2loop/tst_fx2looplib.vhd b/rtl/sys_gen/tst_fx2loop/tst_fx2looplib.vhd index 79ce28f3..5dd81142 100644 --- a/rtl/sys_gen/tst_fx2loop/tst_fx2looplib.vhd +++ b/rtl/sys_gen/tst_fx2loop/tst_fx2looplib.vhd @@ -1,4 +1,4 @@ --- $Id: tst_fx2looplib.vhd 453 2012-01-15 17:51:18Z mueller $ +-- $Id: tst_fx2looplib.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2011-2012 by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Definitions for tst_fx2loop records and helpers -- -- Dependencies: - --- Tool versions: xst 13.3; ghdl 0.29 +-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31 -- Revision History: -- Date Rev Version Comment -- 2012-01-15 453 1.1 drop pecnt, add rxhold,(tx|tx2)busy in hio_stat diff --git a/rtl/sys_gen/tst_rlink/Makefile b/rtl/sys_gen/tst_rlink/Makefile index 61576879..b8493396 100644 --- a/rtl/sys_gen/tst_rlink/Makefile +++ b/rtl/sys_gen/tst_rlink/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 602 2014-11-08 21:42:47Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -7,7 +7,7 @@ VBOM_all = $(wildcard *.vbom) NGC_all = $(VBOM_all:.vbom=.ngc) # -include $(RETROBASE)/rtl/make/xflow_default_s3board.mk +include $(RETROBASE)/rtl/make_ise/xflow_default_s3board.mk # .PHONY : all clean # @@ -18,8 +18,7 @@ clean : ise_clean # #---- # -include $(RETROBASE)/tools/make/dontincdep.mk -include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_rlink/basys3/.cvsignore b/rtl/sys_gen/tst_rlink/basys3/.cvsignore new file mode 100644 index 00000000..bcfb2aa7 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/basys3/.cvsignore @@ -0,0 +1,7 @@ +.Xil +project_mflow +*.jou +*.log +*.rpt +*.dcp +*.dep_* diff --git a/rtl/sys_gen/tst_rlink/basys3/Makefile b/rtl/sys_gen/tst_rlink/basys3/Makefile new file mode 100644 index 00000000..0262221e --- /dev/null +++ b/rtl/sys_gen/tst_rlink/basys3/Makefile @@ -0,0 +1,25 @@ +# $Id: Makefile 646 2015-02-15 12:04:55Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2015-01-25 637 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +include $(RETROBASE)/rtl/make_viv/viv_default_basys3.mk +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : viv_clean +# +#---- +# +include $(RETROBASE)/rtl/make_viv/generic_vivado.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +endif +# diff --git a/rtl/sys_gen/tst_rlink/basys3/sys_conf.vhd b/rtl/sys_gen/tst_rlink/basys3/sys_conf.vhd new file mode 100644 index 00000000..16043b76 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/basys3/sys_conf.vhd @@ -0,0 +1,52 @@ +-- $Id: sys_conf.vhd 636 2015-01-16 22:22:25Z mueller $ +-- +-- Copyright 2015- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_rlink_b3 (for synthesis) +-- +-- Dependencies: - +-- Tool versions: viv 2014.4; ghdl 0.31 +-- Revision History: +-- Date Rev Version Comment +-- 2015-01-16 636 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 1; -- dcm 100 MHz + constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz + constant sys_conf_clksys_gentype : string := "DCM"; + + constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud + + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + + -- derived constants + + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_ser2rri_cdinit : integer := + (sys_conf_clksys/sys_conf_ser2rri_defbaud)-1; + +end package sys_conf; + diff --git a/rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vbom b/rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vbom new file mode 100644 index 00000000..d7129b07 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vbom @@ -0,0 +1,23 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/xlib/xlib.vhd +../../../vlib/genlib/genlib.vhd +../../../vlib/serport/serportlib.vbom +../../../vlib/rbus/rblib.vhd +../../../vlib/rlink/rlinklib.vbom +../../../bplib/bpgen/bpgenlib.vbom +../../../bplib/bpgen/bpgenrbuslib.vbom +${sys_conf := sys_conf.vhd} +# components +[xst,vsyn,isim,vsim]../../../vlib/xlib/s6_cmt_sfs_unisim.vbom +[ghdl]../../../vlib/xlib/s6_cmt_sfs_gsim.vbom +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/bp_rs232_2line_iob.vbom +../../../bplib/bpgen/sn_humanio_rbus.vbom +../../../vlib/rlink/rlink_sp1c.vbom +../rbd_tst_rlink.vbom +../../../vlib/rbus/rb_sres_or_2.vbom +# design +sys_tst_rlink_b3.vhd +@xdc:../../../bplib/basys3/basys3_pclk.xdc +@xdc:../../../bplib/basys3/basys3_pins.xdc diff --git a/rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vhd b/rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vhd new file mode 100644 index 00000000..a93762eb --- /dev/null +++ b/rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vhd @@ -0,0 +1,252 @@ +-- $Id: sys_tst_rlink_b3.vhd 640 2015-02-01 09:56:53Z mueller $ +-- +-- Copyright 2015- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_tst_rlink_b3 - syn +-- Description: rlink tester design for basys3 +-- +-- Dependencies: vlib/xlib/s6_cmt_sfs +-- vlib/genlib/clkdivce +-- bplib/bpgen/bp_rs232_2line_iob +-- bplib/bpgen/sn_humanio_rbus +-- vlib/rlink/rlink_sp1c +-- rbd_tst_rlink +-- vlib/rbus/rb_sres_or_2 +-- +-- Test bench: tb/tb_tst_rlink_b3 +-- +-- Target Devices: generic +-- Tool versions: viv 2014.4; ghdl 0.31 +-- +-- Synthesized (xst): +-- Date Rev viv Target flop lutl lutm bram slic +-- 2015-01-30 636 2014.4 xc7a35t-1 946 1319 64 4.5 476 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2015-01-16 636 1.0 Initial version (derived from sys_tst_rlink_n3) +------------------------------------------------------------------------------ +-- Usage of Basys 3 Switches, Buttons, LEDs: +-- +-- SWI(7:2): no function (only connected to sn_humanio_rbus) +-- SWI(1): 1 enable XON +-- SWI(0): -unused- +-- +-- LED(7): SER_MONI.abact +-- LED(6:2): no function (only connected to sn_humanio_rbus) +-- LED(0): timer 0 busy +-- LED(1): timer 1 busy +-- +-- DSP: SER_MONI.clkdiv (from auto bauder) +-- DP(3): not SER_MONI.txok (shows tx back preasure) +-- DP(2): SER_MONI.txact (shows tx activity) +-- DP(1): not SER_MONI.rxok (shows rx back preasure) +-- DP(0): SER_MONI.rxact (shows rx activity) +-- + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.genlib.all; +use work.serportlib.all; +use work.rblib.all; +use work.rlinklib.all; +use work.bpgenlib.all; +use work.bpgenrbuslib.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_tst_rlink_b3 is -- top level + -- implements basys3_aif + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv16; -- b3 switches + I_BTN : in slv5; -- b3 buttons + O_LED : out slv16; -- b3 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8 -- 7 segment disp: segments (act.low) + ); +end sys_tst_rlink_b3; + +architecture syn of sys_tst_rlink_b3 is + + signal CLK : slbit := '0'; + + signal RXD : slbit := '1'; + signal TXD : slbit := '0'; + signal RTS_N : slbit := '0'; + signal CTS_N : slbit := '0'; + + signal SWI : slv16 := (others=>'0'); + signal BTN : slv5 := (others=>'0'); + signal LED : slv16 := (others=>'0'); + signal DSP_DAT : slv16 := (others=>'0'); + signal DSP_DP : slv4 := (others=>'0'); + + signal RESET : slbit := '0'; + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal RB_MREQ : rb_mreq_type := rb_mreq_init; + signal RB_SRES : rb_sres_type := rb_sres_init; + signal RB_SRES_HIO : rb_sres_type := rb_sres_init; + signal RB_SRES_TST : rb_sres_type := rb_sres_init; + + signal RB_LAM : slv16 := (others=>'0'); + signal RB_STAT : slv4 := (others=>'0'); + + signal SER_MONI : serport_moni_type := serport_moni_init; + signal STAT : slv8 := (others=>'0'); + + constant rbaddr_hio : slv16 := x"fef0"; -- fef0/4: 1111 1110 1111 00xx + +begin + + assert (sys_conf_clksys mod 1000000) = 0 + report "assert sys_conf_clksys on MHz grid" + severity failure; + + RESET <= '0'; -- so far not used + + GEN_CLKSYS : s6_cmt_sfs + generic map ( + VCO_DIVIDE => sys_conf_clksys_vcodivide, + VCO_MULTIPLY => sys_conf_clksys_vcomultiply, + OUT_DIVIDE => sys_conf_clksys_outdivide, + CLKIN_PERIOD => 10.0, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clksys_gentype) + port map ( + CLKIN => I_CLK100, + CLKFX => CLK, + LOCKED => open + ); + + CLKDIV : clkdivce + generic map ( + CDUWIDTH => 7, + USECDIV => sys_conf_clksys_mhz, + MSECDIV => 1000) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC + ); + + IOB_RS232 : bp_rs232_2line_iob + port map ( + CLK => CLK, + RXD => RXD, + TXD => TXD, + I_RXD => I_RXD, + O_TXD => O_TXD + ); + + HIO : sn_humanio_rbus + generic map ( + SWIDTH => 16, + BWIDTH => 5, + LWIDTH => 16, + DEBOUNCE => sys_conf_hio_debounce, + RB_ADDR => rbaddr_hio) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_HIO, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + RLINK : rlink_sp1c + generic map ( + BTOWIDTH => 6, + RTAWIDTH => 12, + SYSID => (others=>'0'), + IFAWIDTH => 5, + OFAWIDTH => 5, + ENAPIN_RLMON => sbcntl_sbf_rlmon, + ENAPIN_RBMON => sbcntl_sbf_rbmon, + CDWIDTH => 15, + CDINIT => sys_conf_ser2rri_cdinit) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + CE_INT => CE_MSEC, + RESET => RESET, + ENAXON => SWI(1), + ENAESC => SWI(1), + RXSD => RXD, + TXSD => TXD, + CTS_N => '0', + RTS_N => open, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT, + RL_MONI => open, + SER_MONI => SER_MONI + ); + + RBDTST : entity work.rbd_tst_rlink + port map ( + CLK => CLK, + RESET => RESET, + CE_USEC => CE_USEC, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_TST, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT, + RB_SRES_TOP => RB_SRES, + RXSD => RXD, + RXACT => SER_MONI.rxact, + STAT => STAT + ); + + RB_SRES_OR1 : rb_sres_or_2 + port map ( + RB_SRES_1 => RB_SRES_HIO, + RB_SRES_2 => RB_SRES_TST, + RB_SRES_OR => RB_SRES + ); + + DSP_DAT <= SER_MONI.abclkdiv; + + DSP_DP(3) <= not SER_MONI.txok; + DSP_DP(2) <= SER_MONI.txact; + DSP_DP(1) <= not SER_MONI.rxok; + DSP_DP(0) <= SER_MONI.rxact; + + LED(15 downto 8) <= SWI(15 downto 8); + LED(7) <= SER_MONI.abact; + LED(6 downto 2) <= (others=>'0'); + LED(1) <= STAT(1); + LED(0) <= STAT(0); + +end syn; diff --git a/rtl/sys_gen/tst_rlink/basys3/tb/.cvsignore b/rtl/sys_gen/tst_rlink/basys3/tb/.cvsignore new file mode 100644 index 00000000..68d85658 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/basys3/tb/.cvsignore @@ -0,0 +1,6 @@ +tb_tst_rlink_b3 +tb_tst_rlink_b3_[so]sim +rlink_cext_fifo_rx +rlink_cext_fifo_tx +rlink_cext_conf +*.dep_* diff --git a/rtl/sys_gen/tst_rlink/basys3/tb/Makefile b/rtl/sys_gen/tst_rlink/basys3/tb/Makefile new file mode 100644 index 00000000..ab01f372 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/basys3/tb/Makefile @@ -0,0 +1,30 @@ +# $Id: Makefile 648 2015-02-20 20:16:21Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2015-02-18 648 1.0 Initial version +# +EXE_all = tb_tst_rlink_b3 +# +include $(RETROBASE)/rtl/make_viv/viv_default_basys3.mk +# +.PHONY : all all_ssim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +# +clean : viv_clean ghdl_clean +# +#----- +# +include $(RETROBASE)/rtl/make_viv/generic_vivado.mk +include $(RETROBASE)/rtl/make_viv/generic_ghdl.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(wildcard *.o.dep_ghdl) +endif +# diff --git a/rtl/sys_gen/tst_rlink/basys3/tb/sys_conf_sim.vhd b/rtl/sys_gen/tst_rlink/basys3/tb/sys_conf_sim.vhd new file mode 100644 index 00000000..92362dc6 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/basys3/tb/sys_conf_sim.vhd @@ -0,0 +1,58 @@ +-- $Id: sys_conf_sim.vhd 648 2015-02-20 20:16:21Z mueller $ +-- +-- Copyright 2015- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_rlink_b3 (for simulation) +-- +-- Dependencies: - +-- Tool versions: viv 2014.4; ghdl 0.31 +-- Revision History: +-- Date Rev Version Comment +-- 2015-02-18 648 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 1; -- vco --- MHz + constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + -- single clock design, clkser = clksys + constant sys_conf_clkser_vcodivide : positive := sys_conf_clksys_vcodivide; + constant sys_conf_clkser_vcomultiply : positive := sys_conf_clksys_vcomultiply; + constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide; + constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype; + + constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim + + constant sys_conf_hio_debounce : boolean := false; -- no debouncers + + -- derived constants + + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_clkser : integer := + ((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) / + sys_conf_clkser_outdivide; + constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000; + +end package sys_conf; diff --git a/rtl/sys_gen/tst_rlink/basys3/tb/tb_tst_rlink_b3.vbom b/rtl/sys_gen/tst_rlink/basys3/tb/tb_tst_rlink_b3.vbom new file mode 100644 index 00000000..bbd4a8c4 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/basys3/tb/tb_tst_rlink_b3.vbom @@ -0,0 +1,7 @@ +# configure tb_basys3 with sys_tst_rlink_b3 target; +# use vhdl configure file (tb_tst_rlink_b3.vhd) to allow +# that all configurations will co-exist in work library +${basys3_aif := ../sys_tst_rlink_b3.vbom} +sys_conf = sys_conf_sim.vhd +../../../../bplib/basys3/tb/tb_basys3.vbom +tb_tst_rlink_b3.vhd diff --git a/rtl/sys_gen/tst_rlink/basys3/tb/tb_tst_rlink_b3.vhd b/rtl/sys_gen/tst_rlink/basys3/tb/tb_tst_rlink_b3.vhd new file mode 100644 index 00000000..c9975fa5 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/basys3/tb/tb_tst_rlink_b3.vhd @@ -0,0 +1,35 @@ +-- $Id: tb_tst_rlink_b3.vhd 648 2015-02-20 20:16:21Z mueller $ +-- +-- Copyright 2015- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_tst_rlink_b3 +-- Description: Configuration for tb_tst_rlink_b3 for tb_basys3 +-- +-- Dependencies: sys_tst_rlink_b3 +-- +-- To test: sys_tst_rlink_b3 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2015-02-18 648 1.0 Initial version +------------------------------------------------------------------------------ + +configuration tb_tst_rlink_b3 of tb_basys3 is + + for sim + for all : basys3_aif + use entity work.sys_tst_rlink_b3; + end for; + end for; + +end tb_tst_rlink_b3; diff --git a/rtl/sys_gen/tst_rlink/basys3/tb/tb_tst_rlink_b3_ssim.vbom b/rtl/sys_gen/tst_rlink/basys3/tb/tb_tst_rlink_b3_ssim.vbom new file mode 100644 index 00000000..ba602221 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/basys3/tb/tb_tst_rlink_b3_ssim.vbom @@ -0,0 +1,6 @@ +# configure for _*sim case +# Note: this tb uses sys_tst_rlink_b3.vbom in local directory +# (not in .. as usual) to allow a tb specific configure !!! +basys3_aif = sys_tst_rlink_b3_ssim.vhd +tb_tst_rlink_b3.vbom +@top:tb_tst_rlink_b3 diff --git a/rtl/sys_gen/tst_rlink/basys3/tb/tbw.dat b/rtl/sys_gen/tst_rlink/basys3/tb/tbw.dat new file mode 100644 index 00000000..bb2e936b --- /dev/null +++ b/rtl/sys_gen/tst_rlink/basys3/tb/tbw.dat @@ -0,0 +1,6 @@ +# $Id: tbw.dat 648 2015-02-20 20:16:21Z mueller $ +# +[tb_tst_rlink_b3] +rlink_cext_fifo_rx = +rlink_cext_fifo_tx = +rlink_cext_conf = diff --git a/rtl/sys_gen/tst_rlink/nexys2/Makefile b/rtl/sys_gen/tst_rlink/nexys2/Makefile index f220dbd7..94ca8134 100644 --- a/rtl/sys_gen/tst_rlink/nexys2/Makefile +++ b/rtl/sys_gen/tst_rlink/nexys2/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -8,7 +8,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make/xflow_default_nexys2.mk +include $(RETROBASE)/rtl/make_ise/xflow_default_nexys2.mk # .PHONY : all clean # @@ -19,8 +19,8 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make/generic_xflow.mk -include $(RETROBASE)/rtl/make/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_rlink/nexys2/sys_conf.vhd b/rtl/sys_gen/tst_rlink/nexys2/sys_conf.vhd index 1cf8cbcd..398190dd 100644 --- a/rtl/sys_gen/tst_rlink/nexys2/sys_conf.vhd +++ b/rtl/sys_gen/tst_rlink/nexys2/sys_conf.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf.vhd 351 2010-12-30 21:50:54Z mueller $ +-- $Id: sys_conf.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2010- by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Definitions for sys_tst_rlink_n2 (for synthesis) -- -- Dependencies: - --- Tool versions: xst 12.1; ghdl 0.29 +-- Tool versions: xst 12.1-14.7; ghdl 0.29-0.31 -- Revision History: -- Date Rev Version Comment -- 2010-12-29 351 1.0 Initial version diff --git a/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vbom b/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vbom index baa4cca0..7c7f7502 100644 --- a/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vbom +++ b/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vbom @@ -10,7 +10,7 @@ ../../../bplib/nxcramlib/nxcramlib.vhd ${sys_conf := sys_conf.vhd} # components -[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom +[xst,vsyn,isim,vsim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom [ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom ../../../vlib/genlib/clkdivce.vbom ../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom diff --git a/rtl/sys_gen/tst_rlink/nexys2/tb/Makefile b/rtl/sys_gen/tst_rlink/nexys2/tb/Makefile index 7d03fc43..ea4f8ba3 100644 --- a/rtl/sys_gen/tst_rlink/nexys2/tb/Makefile +++ b/rtl/sys_gen/tst_rlink/nexys2/tb/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -7,7 +7,7 @@ # EXE_all = tb_tst_rlink_n2 # -include $(RETROBASE)/rtl/make/xflow_default_nexys2.mk +include $(RETROBASE)/rtl/make_ise/xflow_default_nexys2.mk # .PHONY : all all_ssim all_tsim clean # @@ -20,8 +20,8 @@ clean : ise_clean ghdl_clean # #----- # -include $(RETROBASE)/rtl/make/generic_ghdl.mk -include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/sys_gen/tst_rlink/nexys2/tb/sys_conf_sim.vhd b/rtl/sys_gen/tst_rlink/nexys2/tb/sys_conf_sim.vhd index d14eb965..ea7a4d67 100644 --- a/rtl/sys_gen/tst_rlink/nexys2/tb/sys_conf_sim.vhd +++ b/rtl/sys_gen/tst_rlink/nexys2/tb/sys_conf_sim.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf_sim.vhd 351 2010-12-30 21:50:54Z mueller $ +-- $Id: sys_conf_sim.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2010- by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Definitions for sys_tst_rlink_n2 (for simulation) -- -- Dependencies: - --- Tool versions: xst 12.1; ghdl 0.29 +-- Tool versions: xst 12.1-14.7; ghdl 0.29-0.31 -- Revision History: -- Date Rev Version Comment -- 2010-12-29 351 1.0 Initial version diff --git a/rtl/sys_gen/tst_rlink/nexys3/Makefile b/rtl/sys_gen/tst_rlink/nexys3/Makefile index 6e4efee7..dc768ad8 100644 --- a/rtl/sys_gen/tst_rlink/nexys3/Makefile +++ b/rtl/sys_gen/tst_rlink/nexys3/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -7,7 +7,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make/xflow_default_nexys3.mk +include $(RETROBASE)/rtl/make_ise/xflow_default_nexys3.mk # .PHONY : all clean # @@ -18,8 +18,8 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make/generic_xflow.mk -include $(RETROBASE)/rtl/make/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_rlink/nexys3/sys_conf.vhd b/rtl/sys_gen/tst_rlink/nexys3/sys_conf.vhd index dd475caa..909fae62 100644 --- a/rtl/sys_gen/tst_rlink/nexys3/sys_conf.vhd +++ b/rtl/sys_gen/tst_rlink/nexys3/sys_conf.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf.vhd 538 2013-10-06 17:21:25Z mueller $ +-- $Id: sys_conf.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2011-2013 by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Definitions for sys_tst_rlink_n3 (for synthesis) -- -- Dependencies: - --- Tool versions: xst 13.1, 14.6; ghdl 0.29 +-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 -- Revision History: -- Date Rev Version Comment -- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect diff --git a/rtl/sys_gen/tst_rlink/nexys3/sys_tst_rlink_n3.vbom b/rtl/sys_gen/tst_rlink/nexys3/sys_tst_rlink_n3.vbom index eee2936c..06674d1d 100644 --- a/rtl/sys_gen/tst_rlink/nexys3/sys_tst_rlink_n3.vbom +++ b/rtl/sys_gen/tst_rlink/nexys3/sys_tst_rlink_n3.vbom @@ -10,7 +10,7 @@ ../../../bplib/nxcramlib/nxcramlib.vhd ${sys_conf := sys_conf.vhd} # components -[xst,isim]../../../vlib/xlib/s6_cmt_sfs_unisim.vbom +[xst,vsyn,isim,vsim]../../../vlib/xlib/s6_cmt_sfs_unisim.vbom [ghdl]../../../vlib/xlib/s6_cmt_sfs_gsim.vbom ../../../vlib/genlib/clkdivce.vbom ../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom diff --git a/rtl/sys_gen/tst_rlink/nexys3/tb/Makefile b/rtl/sys_gen/tst_rlink/nexys3/tb/Makefile index c562ec3d..2ac11ecc 100644 --- a/rtl/sys_gen/tst_rlink/nexys3/tb/Makefile +++ b/rtl/sys_gen/tst_rlink/nexys3/tb/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -6,7 +6,7 @@ # EXE_all = tb_tst_rlink_n3 # -include $(RETROBASE)/rtl/make/xflow_default_nexys3.mk +include $(RETROBASE)/rtl/make_ise/xflow_default_nexys3.mk # .PHONY : all all_ssim all_tsim clean # @@ -19,8 +19,8 @@ clean : ise_clean ghdl_clean # #----- # -include $(RETROBASE)/rtl/make/generic_ghdl.mk -include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/sys_gen/tst_rlink/nexys3/tb/sys_conf_sim.vhd b/rtl/sys_gen/tst_rlink/nexys3/tb/sys_conf_sim.vhd index 426d43ff..7fc35a1b 100644 --- a/rtl/sys_gen/tst_rlink/nexys3/tb/sys_conf_sim.vhd +++ b/rtl/sys_gen/tst_rlink/nexys3/tb/sys_conf_sim.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf_sim.vhd 538 2013-10-06 17:21:25Z mueller $ +-- $Id: sys_conf_sim.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2011-2013 by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Definitions for sys_tst_rlink_n3 (for simulation) -- -- Dependencies: - --- Tool versions: xst 13.1, 14.6; ghdl 0.29 +-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 -- Revision History: -- Date Rev Version Comment -- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect diff --git a/rtl/sys_gen/tst_rlink/nexys4/.cvsignore b/rtl/sys_gen/tst_rlink/nexys4/.cvsignore new file mode 100644 index 00000000..9a32754a --- /dev/null +++ b/rtl/sys_gen/tst_rlink/nexys4/.cvsignore @@ -0,0 +1,11 @@ +_impactbatch.log +sys_tst_rlink_n4.ucf +*.dep_ucf_cpp +*.svf +.Xil +project_mflow +*.jou +*.log +*.rpt +*.dcp +*.dep_* diff --git a/rtl/sys_gen/tst_rlink/nexys4/Makefile b/rtl/sys_gen/tst_rlink/nexys4/Makefile new file mode 100644 index 00000000..c2b6b663 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/nexys4/Makefile @@ -0,0 +1,26 @@ +# $Id: Makefile 646 2015-02-15 12:04:55Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2015-01-25 639 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +include $(RETROBASE)/rtl/make_viv/viv_default_nexys4.mk +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : viv_clean +# +#---- +# +include $(RETROBASE)/rtl/make_viv/generic_vivado.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +##include $(VBOM_all:.vbom=.dep_ghdl) +endif +# diff --git a/rtl/sys_gen/tst_rlink/nexys4/Makefile.ise b/rtl/sys_gen/tst_rlink/nexys4/Makefile.ise new file mode 100644 index 00000000..5d849476 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/nexys4/Makefile.ise @@ -0,0 +1,29 @@ +# -*- makefile-gmake -*- +# $Id: Makefile.ise 646 2015-02-15 12:04:55Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2013-09-28 535 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +include $(RETROBASE)/rtl/make_ise/xflow_default_nexys4.mk +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : ise_clean + rm -f $(VBOM_all:.vbom=.ucf) +# +#---- +# +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +endif +# diff --git a/rtl/sys_gen/tst_rlink/nexys4/sys_conf.vhd b/rtl/sys_gen/tst_rlink/nexys4/sys_conf.vhd new file mode 100644 index 00000000..16bd9fbb --- /dev/null +++ b/rtl/sys_gen/tst_rlink/nexys4/sys_conf.vhd @@ -0,0 +1,62 @@ +-- $Id: sys_conf.vhd 640 2015-02-01 09:56:53Z mueller $ +-- +-- Copyright 2013- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_rlink_n4 (for synthesis) +-- +-- Dependencies: - +-- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31 +-- Revision History: +-- Date Rev Version Comment +-- 2013-09-28 535 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 12; -- vco 1200 MHz + constant sys_conf_clksys_outdivide : positive := 10; -- sys 120 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + -- single clock design, clkser = clksys + constant sys_conf_clkser_vcodivide : positive := sys_conf_clksys_vcodivide; + constant sys_conf_clkser_vcomultiply : positive := sys_conf_clksys_vcomultiply; + constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide; + constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype; + + constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud + + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + + -- derived constants + + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_clkser : integer := + ((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) / + sys_conf_clkser_outdivide; + constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000; + + constant sys_conf_ser2rri_cdinit : integer := + (sys_conf_clksys/sys_conf_ser2rri_defbaud)-1; + +end package sys_conf; + diff --git a/rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.ucf_cpp b/rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.ucf_cpp new file mode 100644 index 00000000..81b597f3 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.ucf_cpp @@ -0,0 +1,17 @@ +## $Id: sys_tst_rlink_n4.ucf_cpp 640 2015-02-01 09:56:53Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2015-01-25 639 1.1 drop fusp iface +## 2013-09-28 535 1.0 Initial version +## + +NET "I_CLK100" TNM_NET = "I_CLK100"; +TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %; +OFFSET = IN 10 ns BEFORE "I_CLK100"; +OFFSET = OUT 20 ns AFTER "I_CLK100"; + +## std board +## +#include "bplib/nexys4/nexys4_pins.ucf" +## diff --git a/rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vbom b/rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vbom new file mode 100644 index 00000000..26773c66 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vbom @@ -0,0 +1,24 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/xlib/xlib.vhd +../../../vlib/genlib/genlib.vhd +../../../vlib/serport/serportlib.vbom +../../../vlib/rbus/rblib.vhd +../../../vlib/rlink/rlinklib.vbom +../../../bplib/bpgen/bpgenlib.vbom +../../../bplib/bpgen/bpgenrbuslib.vbom +${sys_conf := sys_conf.vhd} +# components +[xst,vsyn,isim,vsim]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom +[ghdl]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/bp_rs232_4line_iob.vbom +../../../bplib/bpgen/sn_humanio_rbus.vbom +../../../vlib/rlink/rlink_sp1c.vbom +../rbd_tst_rlink.vbom +../../../vlib/rbus/rb_sres_or_2.vbom +# design +sys_tst_rlink_n4.vhd +@ucf_cpp: sys_tst_rlink_n4.ucf +@xdc:../../../bplib/nexys4/nexys4_pclk.xdc +@xdc:../../../bplib/nexys4/nexys4_pins.xdc diff --git a/rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vhd b/rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vhd new file mode 100644 index 00000000..99ed746e --- /dev/null +++ b/rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vhd @@ -0,0 +1,276 @@ +-- $Id: sys_tst_rlink_n4.vhd 643 2015-02-07 17:41:53Z mueller $ +-- +-- Copyright 2013-2015 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_tst_rlink_n4 - syn +-- Description: rlink tester design for nexys4 +-- +-- Dependencies: vlib/xlib/s7_cmt_sfs +-- vlib/genlib/clkdivce +-- bplib/bpgen/bp_rs232_4line_iob +-- bplib/bpgen/sn_humanio_rbus +-- vlib/rlink/rlink_sp1c +-- rbd_tst_rlink +-- vlib/rbus/rb_sres_or_2 +-- +-- Test bench: tb/tb_tst_rlink_n4 +-- +-- Target Devices: generic +-- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31 +-- +-- Synthesized: +-- Date Rev viv Target flop lutl lutm bram slic +-- 2015-01-31 640 2014.4 xc7a100t-1 990 1360 64 0 495 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2015-02-06 643 1.4 factor out memory +-- 2015-02-01 641 1.3.1 separate I_BTNRST_N; autobaud on msb of display +-- 2015-01-31 640 1.3 drop fusp iface; use new sn_hio +-- 2014-11-09 603 1.2 use new rlink v4 iface and 4 bit STAT +-- 2014-08-15 583 1.1 rb_mreq addr now 16 bit +-- 2013-09-28 535 1.0 Initial version (derived from sys_tst_rlink_n3) +------------------------------------------------------------------------------ +-- Usage of Nexys 4 Switches, Buttons, LEDs: +-- +-- SWI(7:2): no function (only connected to sn_humanio_rbus) +-- SWI(1): 1 enable XON +-- SWI(0): -unused- +-- +-- LED(7): SER_MONI.abact +-- LED(6:2): no function (only connected to sn_humanio_rbus) +-- LED(0): timer 0 busy +-- LED(1): timer 1 busy +-- +-- DSP: SER_MONI.clkdiv (from auto bauder) +-- DP(3): not SER_MONI.txok (shows tx back preasure) +-- DP(2): SER_MONI.txact (shows tx activity) +-- DP(1): not SER_MONI.rxok (shows rx back preasure) +-- DP(0): SER_MONI.rxact (shows rx activity) +-- + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.genlib.all; +use work.serportlib.all; +use work.rblib.all; +use work.rlinklib.all; +use work.bpgenlib.all; +use work.bpgenrbuslib.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_tst_rlink_n4 is -- top level + -- implements nexys4_aif + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + O_RTS_N : out slbit; -- rx rts (board view; act.low) + I_CTS_N : in slbit; -- tx cts (board view; act.low) + I_SWI : in slv16; -- n4 switches + I_BTN : in slv5; -- n4 buttons + I_BTNRST_N : in slbit; -- n4 reset button + O_LED : out slv16; -- n4 leds + O_RGBLED0 : out slv3; -- n4 rgb-led 0 + O_RGBLED1 : out slv3; -- n4 rgb-led 1 + O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8 -- 7 segment disp: segments (act.low) + ); +end sys_tst_rlink_n4; + +architecture syn of sys_tst_rlink_n4 is + + signal CLK : slbit := '0'; + + signal RXD : slbit := '1'; + signal TXD : slbit := '0'; + signal RTS_N : slbit := '0'; + signal CTS_N : slbit := '0'; + + signal SWI : slv16 := (others=>'0'); + signal BTN : slv5 := (others=>'0'); + signal LED : slv16 := (others=>'0'); + signal DSP_DAT : slv32 := (others=>'0'); + signal DSP_DP : slv8 := (others=>'0'); + + signal RESET : slbit := '0'; + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal RB_MREQ : rb_mreq_type := rb_mreq_init; + signal RB_SRES : rb_sres_type := rb_sres_init; + signal RB_SRES_HIO : rb_sres_type := rb_sres_init; + signal RB_SRES_TST : rb_sres_type := rb_sres_init; + + signal RB_LAM : slv16 := (others=>'0'); + signal RB_STAT : slv4 := (others=>'0'); + + signal SER_MONI : serport_moni_type := serport_moni_init; + signal STAT : slv8 := (others=>'0'); + + constant rbaddr_hio : slv16 := x"fef0"; -- fef0/4: 1111 1110 1111 0xxx + +begin + + assert (sys_conf_clksys mod 1000000) = 0 + report "assert sys_conf_clksys on MHz grid" + severity failure; + + RESET <= '0'; -- so far not used + + GEN_CLKSYS : s7_cmt_sfs + generic map ( + VCO_DIVIDE => sys_conf_clksys_vcodivide, + VCO_MULTIPLY => sys_conf_clksys_vcomultiply, + OUT_DIVIDE => sys_conf_clksys_outdivide, + CLKIN_PERIOD => 10.0, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clksys_gentype) + port map ( + CLKIN => I_CLK100, + CLKFX => CLK, + LOCKED => open + ); + + CLKDIV : clkdivce + generic map ( + CDUWIDTH => 8, -- good up to 254 MHz + USECDIV => sys_conf_clksys_mhz, + MSECDIV => 1000) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC + ); + + IOB_RS232 : bp_rs232_4line_iob + port map ( + CLK => CLK, + RXD => RXD, + TXD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + I_RXD => I_RXD, + O_TXD => O_TXD, + I_CTS_N => I_CTS_N, + O_RTS_N => O_RTS_N + ); + + HIO : sn_humanio_rbus + generic map ( + SWIDTH => 16, + BWIDTH => 5, + LWIDTH => 16, + DCWIDTH => 3, + DEBOUNCE => sys_conf_hio_debounce, + RB_ADDR => rbaddr_hio) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_HIO, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + RLINK : rlink_sp1c + generic map ( + BTOWIDTH => 6, + RTAWIDTH => 12, + SYSID => (others=>'0'), + IFAWIDTH => 5, + OFAWIDTH => 5, + ENAPIN_RLMON => sbcntl_sbf_rlmon, + ENAPIN_RBMON => sbcntl_sbf_rbmon, + CDWIDTH => 15, + CDINIT => sys_conf_ser2rri_cdinit) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + CE_INT => CE_MSEC, + RESET => RESET, + ENAXON => SWI(1), + ENAESC => SWI(1), + RXSD => RXD, + TXSD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT, + RL_MONI => open, + SER_MONI => SER_MONI + ); + + RBDTST : entity work.rbd_tst_rlink + port map ( + CLK => CLK, + RESET => RESET, + CE_USEC => CE_USEC, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_TST, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT, + RB_SRES_TOP => RB_SRES, + RXSD => RXD, + RXACT => SER_MONI.rxact, + STAT => STAT + ); + + RB_SRES_OR1 : rb_sres_or_2 + port map ( + RB_SRES_1 => RB_SRES_HIO, + RB_SRES_2 => RB_SRES_TST, + RB_SRES_OR => RB_SRES + ); + + DSP_DAT(31 downto 20) <= SER_MONI.abclkdiv(11 downto 0); + DSP_DAT(19) <= '0'; + DSP_DAT(18 downto 16) <= SER_MONI.abclkdiv_f; + DSP_DP(7 downto 4) <= "0010"; + + DSP_DAT(15 downto 0) <= (others=>'0'); + + DSP_DP(3) <= not SER_MONI.txok; + DSP_DP(2) <= SER_MONI.txact; + DSP_DP(1) <= not SER_MONI.rxok; + DSP_DP(0) <= SER_MONI.rxact; + + LED(15 downto 8) <= SWI(15 downto 8); + LED(7) <= SER_MONI.abact; + LED(6 downto 2) <= (others=>'0'); + LED(1) <= STAT(1); + LED(0) <= STAT(0); + + -- setup unused outputs in nexys4 + O_RGBLED0 <= (others=>'0'); + O_RGBLED1 <= (others=>not I_BTNRST_N); + +end syn; diff --git a/rtl/sys_gen/tst_rlink/nexys4/tb/.cvsignore b/rtl/sys_gen/tst_rlink/nexys4/tb/.cvsignore new file mode 100644 index 00000000..8912e778 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/nexys4/tb/.cvsignore @@ -0,0 +1,8 @@ +tb_tst_rlink_n4 +tb_tst_rlink_n4_[sft]sim +rlink_cext_fifo_rx +rlink_cext_fifo_tx +rlink_cext_conf +sys_tst_rlink_n4.ucf +*.dep_ucf_cpp +*.dep_* diff --git a/rtl/sys_gen/tst_rlink/nexys4/tb/Makefile b/rtl/sys_gen/tst_rlink/nexys4/tb/Makefile new file mode 100644 index 00000000..c149294a --- /dev/null +++ b/rtl/sys_gen/tst_rlink/nexys4/tb/Makefile @@ -0,0 +1,30 @@ +# $Id: Makefile 648 2015-02-20 20:16:21Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2015-02-18 648 1.0 Initial version +# +EXE_all = tb_tst_rlink_n4 +# +include $(RETROBASE)/rtl/make_viv/viv_default_nexys4.mk +# +.PHONY : all all_ssim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +# +clean : viv_clean ghdl_clean +# +#----- +# +include $(RETROBASE)/rtl/make_viv/generic_vivado.mk +include $(RETROBASE)/rtl/make_viv/generic_ghdl.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(wildcard *.o.dep_ghdl) +endif +# diff --git a/rtl/sys_gen/tst_rlink/nexys4/tb/Makefile.ise b/rtl/sys_gen/tst_rlink/nexys4/tb/Makefile.ise new file mode 100644 index 00000000..98ab374d --- /dev/null +++ b/rtl/sys_gen/tst_rlink/nexys4/tb/Makefile.ise @@ -0,0 +1,33 @@ +# -*- makefile-gmake -*- +# $Id: Makefile.ise 646 2015-02-15 12:04:55Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2013-09-28 535 1.0 Initial version +# +EXE_all = tb_tst_rlink_n4 +# +include $(RETROBASE)/rtl/make_ise/xflow_default_nexys4.mk +# +.PHONY : all all_ssim all_tsim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_tsim : $(EXE_all:=_tsim) +# +clean : ise_clean ghdl_clean + rm -f sys_tst_rlink_n4.ucf +# +#----- +# +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(wildcard *.o.dep_ghdl) +endif +# diff --git a/rtl/sys_gen/tst_rlink/nexys4/tb/sys_conf_sim.vhd b/rtl/sys_gen/tst_rlink/nexys4/tb/sys_conf_sim.vhd new file mode 100644 index 00000000..9a9cdda1 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/nexys4/tb/sys_conf_sim.vhd @@ -0,0 +1,58 @@ +-- $Id: sys_conf_sim.vhd 648 2015-02-20 20:16:21Z mueller $ +-- +-- Copyright 2013- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_rlink_n4 (for simulation) +-- +-- Dependencies: - +-- Tool versions: xst 14.5-14.7; viv 2014.4; ghdl 0.29-0.31 +-- Revision History: +-- Date Rev Version Comment +-- 2013-09-28 535 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 1; -- vco --- MHz + constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + -- single clock design, clkser = clksys + constant sys_conf_clkser_vcodivide : positive := sys_conf_clksys_vcodivide; + constant sys_conf_clkser_vcomultiply : positive := sys_conf_clksys_vcomultiply; + constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide; + constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype; + + constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim + + constant sys_conf_hio_debounce : boolean := false; -- no debouncers + + -- derived constants + + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_clkser : integer := + ((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) / + sys_conf_clkser_outdivide; + constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000; + +end package sys_conf; diff --git a/rtl/sys_gen/tst_rlink/nexys4/tb/sys_tst_rlink_n4.ucf_cpp b/rtl/sys_gen/tst_rlink/nexys4/tb/sys_tst_rlink_n4.ucf_cpp new file mode 120000 index 00000000..dfbb0b1b --- /dev/null +++ b/rtl/sys_gen/tst_rlink/nexys4/tb/sys_tst_rlink_n4.ucf_cpp @@ -0,0 +1 @@ +../sys_tst_rlink_n4.ucf_cpp \ No newline at end of file diff --git a/rtl/sys_gen/tst_rlink/nexys4/tb/tb_tst_rlink_n4.vbom b/rtl/sys_gen/tst_rlink/nexys4/tb/tb_tst_rlink_n4.vbom new file mode 100644 index 00000000..cd798a69 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/nexys4/tb/tb_tst_rlink_n4.vbom @@ -0,0 +1,7 @@ +# configure tb_nexsy4 with sys_tst_rlink_n4 target; +# use vhdl configure file (tb_tst_rlink_n4.vhd) to allow +# that all configurations will co-exist in work library +${nexys4_aif := ../sys_tst_rlink_n4.vbom} +sys_conf = sys_conf_sim.vhd +../../../../bplib/nexys4/tb/tb_nexys4.vbom +tb_tst_rlink_n4.vhd diff --git a/rtl/sys_gen/tst_rlink/nexys4/tb/tb_tst_rlink_n4.vhd b/rtl/sys_gen/tst_rlink/nexys4/tb/tb_tst_rlink_n4.vhd new file mode 100644 index 00000000..81d34f0f --- /dev/null +++ b/rtl/sys_gen/tst_rlink/nexys4/tb/tb_tst_rlink_n4.vhd @@ -0,0 +1,36 @@ +-- $Id: tb_tst_rlink_n4.vhd 648 2015-02-20 20:16:21Z mueller $ +-- +-- Copyright 2013-2015 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_tst_rlink_n4 +-- Description: Configuration for tb_tst_rlink_n4 for tb_nexys4 +-- +-- Dependencies: sys_tst_rlink_n4 +-- +-- To test: sys_tst_rlink_n4 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2015-02-01 641 1.1 use plain tb_nexys4 now +-- 2013-09-28 535 1.0 Initial version +------------------------------------------------------------------------------ + +configuration tb_tst_rlink_n4 of tb_nexys4 is + + for sim + for all : nexys4_aif + use entity work.sys_tst_rlink_n4; + end for; + end for; + +end tb_tst_rlink_n4; diff --git a/rtl/sys_gen/tst_rlink/nexys4/tb/tb_tst_rlink_n4_ssim.vbom b/rtl/sys_gen/tst_rlink/nexys4/tb/tb_tst_rlink_n4_ssim.vbom new file mode 100644 index 00000000..677efce2 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/nexys4/tb/tb_tst_rlink_n4_ssim.vbom @@ -0,0 +1,6 @@ +# configure for _*sim case +# Note: this tb uses sys_tst_rlink_n4.vbom in local directory +# (not in .. as usual) to allow a tb specific configure !!! +nexys4_aif = sys_tst_rlink_n4_ssim.vhd +tb_tst_rlink_n4.vbom +@top:tb_tst_rlink_n4 diff --git a/rtl/sys_gen/tst_rlink/nexys4/tb/tbw.dat b/rtl/sys_gen/tst_rlink/nexys4/tb/tbw.dat new file mode 100644 index 00000000..f91d9984 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/nexys4/tb/tbw.dat @@ -0,0 +1,6 @@ +# $Id: tbw.dat 535 2013-09-29 11:46:25Z mueller $ +# +[tb_tst_rlink_n4] +rlink_cext_fifo_rx = +rlink_cext_fifo_tx = +rlink_cext_conf = diff --git a/rtl/sys_gen/tst_rlink/s3board/Makefile b/rtl/sys_gen/tst_rlink/s3board/Makefile index 7fd792d0..c97d6392 100644 --- a/rtl/sys_gen/tst_rlink/s3board/Makefile +++ b/rtl/sys_gen/tst_rlink/s3board/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -7,7 +7,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make/xflow_default_s3board.mk +include $(RETROBASE)/rtl/make_ise/xflow_default_s3board.mk # .PHONY : all clean # @@ -18,8 +18,8 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make/generic_xflow.mk -include $(RETROBASE)/rtl/make/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_rlink/s3board/sys_conf.vhd b/rtl/sys_gen/tst_rlink/s3board/sys_conf.vhd index 326ce1e6..234e1c61 100644 --- a/rtl/sys_gen/tst_rlink/s3board/sys_conf.vhd +++ b/rtl/sys_gen/tst_rlink/s3board/sys_conf.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf.vhd 442 2011-12-23 10:03:28Z mueller $ +-- $Id: sys_conf.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Definitions for sys_tst_rlink_s3 (for synthesis) -- -- Dependencies: - --- Tool versions: xst 13.1; ghdl 0.29 +-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-12-22 442 1.0 Initial version diff --git a/rtl/sys_gen/tst_rlink/s3board/tb/Makefile b/rtl/sys_gen/tst_rlink/s3board/tb/Makefile index f6c161f5..7b9d801f 100644 --- a/rtl/sys_gen/tst_rlink/s3board/tb/Makefile +++ b/rtl/sys_gen/tst_rlink/s3board/tb/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -6,7 +6,7 @@ # EXE_all = tb_tst_rlink_s3 # -include $(RETROBASE)/rtl/make/xflow_default_s3board.mk +include $(RETROBASE)/rtl/make_ise/xflow_default_s3board.mk # .PHONY : all all_ssim all_tsim clean # @@ -19,8 +19,8 @@ clean : ise_clean ghdl_clean # #----- # -include $(RETROBASE)/rtl/make/generic_ghdl.mk -include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/sys_gen/tst_rlink/s3board/tb/sys_conf_sim.vhd b/rtl/sys_gen/tst_rlink/s3board/tb/sys_conf_sim.vhd index de72e052..64c18cf7 100644 --- a/rtl/sys_gen/tst_rlink/s3board/tb/sys_conf_sim.vhd +++ b/rtl/sys_gen/tst_rlink/s3board/tb/sys_conf_sim.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf_sim.vhd 442 2011-12-23 10:03:28Z mueller $ +-- $Id: sys_conf_sim.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Definitions for sys_tst_rlink_s3 (for simulation) -- -- Dependencies: - --- Tool versions: xst 13.1; ghdl 0.29 +-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-12-22 442 1.0 Initial version diff --git a/rtl/sys_gen/tst_rlink_cuff/Makefile b/rtl/sys_gen/tst_rlink_cuff/Makefile index 7c7b15d8..a769a652 100644 --- a/rtl/sys_gen/tst_rlink_cuff/Makefile +++ b/rtl/sys_gen/tst_rlink_cuff/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 602 2014-11-08 21:42:47Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -7,7 +7,7 @@ VBOM_all = $(wildcard *.vbom) NGC_all = $(VBOM_all:.vbom=.ngc) # -include $(RETROBASE)/rtl/make/xflow_default_nexys2.mk +include $(RETROBASE)/rtl/make_ise/xflow_default_nexys2.mk # .PHONY : all clean # @@ -18,8 +18,7 @@ clean : ise_clean # #---- # -include $(RETROBASE)/tools/make/dontincdep.mk -include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_rlink_cuff/atlys/ic/Makefile b/rtl/sys_gen/tst_rlink_cuff/atlys/ic/Makefile index 5ffd541c..e1235342 100644 --- a/rtl/sys_gen/tst_rlink_cuff/atlys/ic/Makefile +++ b/rtl/sys_gen/tst_rlink_cuff/atlys/ic/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -8,7 +8,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make/xflow_default_atlys.mk +include $(RETROBASE)/rtl/make_ise/xflow_default_atlys.mk FX2_FILE = nexys3_jtag_2fifo_ic.ihx # .PHONY : all clean @@ -20,8 +20,8 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make/generic_xflow.mk -include $(RETROBASE)/rtl/make/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_rlink_cuff/atlys/ic/sys_conf.vhd b/rtl/sys_gen/tst_rlink_cuff/atlys/ic/sys_conf.vhd index 1c54eec0..77b33be5 100644 --- a/rtl/sys_gen/tst_rlink_cuff/atlys/ic/sys_conf.vhd +++ b/rtl/sys_gen/tst_rlink_cuff/atlys/ic/sys_conf.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf.vhd 472 2013-01-06 14:39:10Z mueller $ +-- $Id: sys_conf.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2013- by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Definitions for sys_tst_rlink_cuff_ic_atlys (for synthesis) -- -- Dependencies: - --- Tool versions: xst 13.3; ghdl 0.29 +-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31 -- Revision History: -- Date Rev Version Comment -- 2013-01-06 472 1.0 Initial version diff --git a/rtl/sys_gen/tst_rlink_cuff/atlys/sys_tst_rlink_cuff_atlys.vbom b/rtl/sys_gen/tst_rlink_cuff/atlys/sys_tst_rlink_cuff_atlys.vbom index 8fae2a61..dd3d7625 100644 --- a/rtl/sys_gen/tst_rlink_cuff/atlys/sys_tst_rlink_cuff_atlys.vbom +++ b/rtl/sys_gen/tst_rlink_cuff/atlys/sys_tst_rlink_cuff_atlys.vbom @@ -1,6 +1,5 @@ # this is the vbom for the 'generic' top level entity # to be referenced in the vbom's of the specific systems -# ./as/sys_tst_rlink_cuff_as_atlys # ./ic/sys_tst_rlink_cuff_ic_atlys # ./ic3/sys_tst_rlink_cuff_ic3_atlys # @@ -14,12 +13,11 @@ ../../../bplib/fx2lib/fx2lib.vhd ${sys_conf} # components -[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom +[xst,vsyn,isim,vsim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom [ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom ../../../vlib/genlib/clkdivce.vbom ../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom ../../../bplib/bpgen/sn_humanio_demu_rbus.vbom -../../../bplib/fx2lib/fx2_2fifoctl_as.vbom ../../../bplib/fx2lib/fx2_2fifoctl_ic.vbom ../../../bplib/fx2lib/fx2_3fifoctl_ic.vbom ../tst_rlink_cuff.vbom diff --git a/rtl/sys_gen/tst_rlink_cuff/atlys/sys_tst_rlink_cuff_atlys.vhd b/rtl/sys_gen/tst_rlink_cuff/atlys/sys_tst_rlink_cuff_atlys.vhd index d11d1ec4..711865aa 100644 --- a/rtl/sys_gen/tst_rlink_cuff/atlys/sys_tst_rlink_cuff_atlys.vhd +++ b/rtl/sys_gen/tst_rlink_cuff/atlys/sys_tst_rlink_cuff_atlys.vhd @@ -1,6 +1,6 @@ --- $Id: sys_tst_rlink_cuff_atlys.vhd 620 2014-12-25 10:48:35Z mueller $ +-- $Id: sys_tst_rlink_cuff_atlys.vhd 638 2015-01-25 22:01:38Z mueller $ -- --- Copyright 2013-2014 by Walter F.J. Mueller +-- Copyright 2013-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -19,7 +19,6 @@ -- vlib/genlib/clkdivce -- bplib/bpgen/bp_rs232_2l4l_iob -- bplib/bpgen/sn_humanio_demu_rbus --- bplib/fx2lib/fx2_2fifoctl_as [sys_conf_fx2_type="as2"] -- bplib/fx2lib/fx2_2fifoctl_ic [sys_conf_fx2_type="ic2"] -- bplib/fx2lib/fx2_3fifoctl_ic [sys_conf_fx2_type="ic3"] -- tst_rlink_cuff @@ -35,6 +34,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2015-01-25 638 1.1.2 retire fx2_2fifoctl_as -- 2014-12-24 620 1.1.1 relocate hio rbus address -- 2014-08-15 583 1.1 rb_mreq addr now 16 bit -- 2013-01-06 472 1.0 Initial version; derived from sys_tst_rlink_cuff_n3 @@ -209,44 +209,6 @@ begin O_LED => O_HIO_LED ); - FX2_CNTL_AS : if sys_conf_fx2_type = "as2" generate - CNTL : fx2_2fifoctl_as - generic map ( - RXFAWIDTH => 5, - TXFAWIDTH => 5, - CCWIDTH => sys_conf_fx2_ccwidth, - RXAEMPTY_THRES => 1, - TXAFULL_THRES => 1, - PETOWIDTH => sys_conf_fx2_petowidth, - RDPWLDELAY => sys_conf_fx2_rdpwldelay, - RDPWHDELAY => sys_conf_fx2_rdpwhdelay, - WRPWLDELAY => sys_conf_fx2_wrpwldelay, - WRPWHDELAY => sys_conf_fx2_wrpwhdelay, - FLAGDELAY => sys_conf_fx2_flagdelay) - port map ( - CLK => CLK, - CE_USEC => CE_USEC, - RESET => RESET, - RXDATA => FX2_RXDATA, - RXVAL => FX2_RXVAL, - RXHOLD => FX2_RXHOLD, - RXAEMPTY => FX2_RXAEMPTY, - TXDATA => FX2_TXDATA, - TXENA => FX2_TXENA, - TXBUSY => FX2_TXBUSY, - TXAFULL => FX2_TXAFULL, - MONI => FX2_MONI, - I_FX2_IFCLK => I_FX2_IFCLK, - O_FX2_FIFO => O_FX2_FIFO, - I_FX2_FLAG => I_FX2_FLAG, - O_FX2_SLRD_N => O_FX2_SLRD_N, - O_FX2_SLWR_N => O_FX2_SLWR_N, - O_FX2_SLOE_N => O_FX2_SLOE_N, - O_FX2_PKTEND_N => O_FX2_PKTEND_N, - IO_FX2_DATA => IO_FX2_DATA - ); - end generate FX2_CNTL_AS; - FX2_CNTL_IC : if sys_conf_fx2_type = "ic2" generate CNTL : fx2_2fifoctl_ic generic map ( diff --git a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/Makefile b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/Makefile index 83a7500b..71130bca 100644 --- a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/Makefile +++ b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -8,7 +8,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make/xflow_default_nexys2.mk +include $(RETROBASE)/rtl/make_ise/xflow_default_nexys2.mk FX2_FILE = nexys2_jtag_2fifo_ic.ihx # .PHONY : all clean @@ -20,8 +20,8 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make/generic_xflow.mk -include $(RETROBASE)/rtl/make/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/sys_conf.vhd b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/sys_conf.vhd index dd9e3cc7..13307f13 100644 --- a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/sys_conf.vhd +++ b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/sys_conf.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf.vhd 466 2012-12-30 13:26:55Z mueller $ +-- $Id: sys_conf.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2012- by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Definitions for sys_tst_rlink_cuff_ic_n2 (for synthesis) -- -- Dependencies: - --- Tool versions: xst 13.3; ghdl 0.29 +-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31 -- Revision History: -- Date Rev Version Comment -- 2012-12-29 466 1.0 Initial version diff --git a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/Makefile b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/Makefile index cf7527e9..5c56d3ea 100644 --- a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/Makefile +++ b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -6,7 +6,7 @@ # EXE_all = tb_tst_rlink_cuff_ic_n2 # -include $(RETROBASE)/rtl/make/xflow_default_nexys2.mk +include $(RETROBASE)/rtl/make_ise/xflow_default_nexys2.mk # .PHONY : all all_ssim all_tsim clean # @@ -19,8 +19,8 @@ clean : ise_clean ghdl_clean # #----- # -include $(RETROBASE)/rtl/make/generic_ghdl.mk -include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/sys_conf_sim.vhd b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/sys_conf_sim.vhd index e06994af..6c5a1387 100644 --- a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/sys_conf_sim.vhd +++ b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/sys_conf_sim.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf_sim.vhd 467 2013-01-02 19:49:05Z mueller $ +-- $Id: sys_conf_sim.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2013- by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Definitions for sys_tst_rlink_cuff_ic_n2 (for simulation) -- -- Dependencies: - --- Tool versions: xst 13.3; ghdl 0.29 +-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31 -- Revision History: -- Date Rev Version Comment -- 2013-01-01 467 1.0 Initial version diff --git a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/Makefile b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/Makefile index aeaf7575..986e6338 100644 --- a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/Makefile +++ b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -8,7 +8,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make/xflow_default_nexys2.mk +include $(RETROBASE)/rtl/make_ise/xflow_default_nexys2.mk FX2_FILE = nexys2_jtag_3fifo_ic.ihx # .PHONY : all clean @@ -20,8 +20,8 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make/generic_xflow.mk -include $(RETROBASE)/rtl/make/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/sys_conf.vhd b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/sys_conf.vhd index fd59e828..056d440c 100644 --- a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/sys_conf.vhd +++ b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/sys_conf.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf.vhd 466 2012-12-30 13:26:55Z mueller $ +-- $Id: sys_conf.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2012- by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Definitions for sys_tst_rlink_cuff_ic3_n2 (for synthesis) -- -- Dependencies: - --- Tool versions: xst 13.3; ghdl 0.29 +-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31 -- Revision History: -- Date Rev Version Comment -- 2012-12-29 466 1.0 Initial version diff --git a/rtl/sys_gen/tst_rlink_cuff/nexys2/sys_tst_rlink_cuff_n2.vbom b/rtl/sys_gen/tst_rlink_cuff/nexys2/sys_tst_rlink_cuff_n2.vbom index 95be5712..34daca9d 100644 --- a/rtl/sys_gen/tst_rlink_cuff/nexys2/sys_tst_rlink_cuff_n2.vbom +++ b/rtl/sys_gen/tst_rlink_cuff/nexys2/sys_tst_rlink_cuff_n2.vbom @@ -1,6 +1,5 @@ # this is the vbom for the 'generic' top level entity # to be referenced in the vbom's of the specific systems -# ./as/sys_tst_rlink_cuff_as_n2 # ./ic/sys_tst_rlink_cuff_ic_n2 # ./ic3/sys_tst_rlink_cuff_ic3_n2 # @@ -15,12 +14,11 @@ ../../../bplib/nxcramlib/nxcramlib.vhd ${sys_conf} # components -[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom +[xst,vsyn,isim,vsim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom [ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom ../../../vlib/genlib/clkdivce.vbom ../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom ../../../bplib/bpgen/sn_humanio_rbus.vbom -../../../bplib/fx2lib/fx2_2fifoctl_as.vbom ../../../bplib/fx2lib/fx2_2fifoctl_ic.vbom ../../../bplib/fx2lib/fx2_3fifoctl_ic.vbom ../tst_rlink_cuff.vbom diff --git a/rtl/sys_gen/tst_rlink_cuff/nexys2/sys_tst_rlink_cuff_n2.vhd b/rtl/sys_gen/tst_rlink_cuff/nexys2/sys_tst_rlink_cuff_n2.vhd index 83caff15..f033ab32 100644 --- a/rtl/sys_gen/tst_rlink_cuff/nexys2/sys_tst_rlink_cuff_n2.vhd +++ b/rtl/sys_gen/tst_rlink_cuff/nexys2/sys_tst_rlink_cuff_n2.vhd @@ -1,6 +1,6 @@ --- $Id: sys_tst_rlink_cuff_n2.vhd 620 2014-12-25 10:48:35Z mueller $ +-- $Id: sys_tst_rlink_cuff_n2.vhd 638 2015-01-25 22:01:38Z mueller $ -- --- Copyright 2012-2014 by Walter F.J. Mueller +-- Copyright 2012-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -19,7 +19,6 @@ -- vlib/genlib/clkdivce -- bplib/bpgen/bp_rs232_2l4l_iob -- bplib/bpgen/sn_humanio_rbus --- bplib/fx2lib/fx2_2fifoctl_as [sys_conf_fx2_type="as2"] -- bplib/fx2lib/fx2_2fifoctl_ic [sys_conf_fx2_type="ic2"] -- bplib/fx2lib/fx2_3fifoctl_ic [sys_conf_fx2_type="ic3"] -- tst_rlink_cuff @@ -40,6 +39,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2015-01-25 638 1.1.2 retire fx2_2fifoctl_as -- 2014-12-24 620 1.1.1 relocate hio rbus address -- 2014-08-15 583 1.1 rb_mreq addr now 16 bit -- 2012-12-29 466 1.0 Initial version; derived from sys_tst_fx2loop_n2 @@ -230,44 +230,6 @@ begin O_SEG_N => O_SEG_N ); - FX2_CNTL_AS : if sys_conf_fx2_type = "as2" generate - CNTL : fx2_2fifoctl_as - generic map ( - RXFAWIDTH => 5, - TXFAWIDTH => 5, - CCWIDTH => sys_conf_fx2_ccwidth, - RXAEMPTY_THRES => 1, - TXAFULL_THRES => 1, - PETOWIDTH => sys_conf_fx2_petowidth, - RDPWLDELAY => sys_conf_fx2_rdpwldelay, - RDPWHDELAY => sys_conf_fx2_rdpwhdelay, - WRPWLDELAY => sys_conf_fx2_wrpwldelay, - WRPWHDELAY => sys_conf_fx2_wrpwhdelay, - FLAGDELAY => sys_conf_fx2_flagdelay) - port map ( - CLK => CLK, - CE_USEC => CE_USEC, - RESET => RESET, - RXDATA => FX2_RXDATA, - RXVAL => FX2_RXVAL, - RXHOLD => FX2_RXHOLD, - RXAEMPTY => FX2_RXAEMPTY, - TXDATA => FX2_TXDATA, - TXENA => FX2_TXENA, - TXBUSY => FX2_TXBUSY, - TXAFULL => FX2_TXAFULL, - MONI => FX2_MONI, - I_FX2_IFCLK => I_FX2_IFCLK, - O_FX2_FIFO => O_FX2_FIFO, - I_FX2_FLAG => I_FX2_FLAG, - O_FX2_SLRD_N => O_FX2_SLRD_N, - O_FX2_SLWR_N => O_FX2_SLWR_N, - O_FX2_SLOE_N => O_FX2_SLOE_N, - O_FX2_PKTEND_N => O_FX2_PKTEND_N, - IO_FX2_DATA => IO_FX2_DATA - ); - end generate FX2_CNTL_AS; - FX2_CNTL_IC : if sys_conf_fx2_type = "ic2" generate CNTL : fx2_2fifoctl_ic generic map ( diff --git a/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/Makefile b/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/Makefile index a1dbee51..215884ab 100644 --- a/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/Makefile +++ b/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -8,7 +8,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make/xflow_default_nexys3.mk +include $(RETROBASE)/rtl/make_ise/xflow_default_nexys3.mk FX2_FILE = nexys3_jtag_2fifo_ic.ihx # .PHONY : all clean @@ -20,8 +20,8 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make/generic_xflow.mk -include $(RETROBASE)/rtl/make/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/sys_conf.vhd b/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/sys_conf.vhd index 964376cb..c3292e2d 100644 --- a/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/sys_conf.vhd +++ b/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/sys_conf.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf.vhd 538 2013-10-06 17:21:25Z mueller $ +-- $Id: sys_conf.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2013- by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Definitions for sys_tst_rlink_cuff_ic_n3 (for synthesis) -- -- Dependencies: - --- Tool versions: xst 13.3, 14.6; ghdl 0.29 +-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31 -- Revision History: -- Date Rev Version Comment -- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect diff --git a/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/tb/Makefile b/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/tb/Makefile index 1cb06add..30c79884 100644 --- a/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/tb/Makefile +++ b/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/tb/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 512 2013-04-28 07:44:02Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -6,7 +6,7 @@ # EXE_all = tb_tst_rlink_cuff_ic_n3 # -include $(RETROBASE)/rtl/make/xflow_default_nexys3.mk +include $(RETROBASE)/rtl/make_ise/xflow_default_nexys3.mk # .PHONY : all all_ssim all_tsim clean # @@ -19,8 +19,8 @@ clean : ise_clean ghdl_clean # #----- # -include $(RETROBASE)/rtl/make/generic_ghdl.mk -include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/tb/sys_conf_sim.vhd b/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/tb/sys_conf_sim.vhd index 73d878a7..04913794 100644 --- a/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/tb/sys_conf_sim.vhd +++ b/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/tb/sys_conf_sim.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf_sim.vhd 538 2013-10-06 17:21:25Z mueller $ +-- $Id: sys_conf_sim.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2013- by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Definitions for sys_tst_rlink_cuff_ic_n3 (for simulation) -- -- Dependencies: - --- Tool versions: xst 13.3, 14.6; ghdl 0.29 +-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31 -- Revision History: -- Date Rev Version Comment -- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect diff --git a/rtl/sys_gen/tst_rlink_cuff/nexys3/sys_tst_rlink_cuff_n3.vbom b/rtl/sys_gen/tst_rlink_cuff/nexys3/sys_tst_rlink_cuff_n3.vbom index b401c16b..ffee41a2 100644 --- a/rtl/sys_gen/tst_rlink_cuff/nexys3/sys_tst_rlink_cuff_n3.vbom +++ b/rtl/sys_gen/tst_rlink_cuff/nexys3/sys_tst_rlink_cuff_n3.vbom @@ -1,6 +1,5 @@ # this is the vbom for the 'generic' top level entity # to be referenced in the vbom's of the specific systems -# ./as/sys_tst_rlink_cuff_as_n3 # ./ic/sys_tst_rlink_cuff_ic_n3 # ./ic3/sys_tst_rlink_cuff_ic3_n3 # @@ -15,12 +14,11 @@ ../../../bplib/nxcramlib/nxcramlib.vhd ${sys_conf} # components -[xst,isim]../../../vlib/xlib/s6_cmt_sfs_unisim.vbom +[xst,vsyn,isim,vsim]../../../vlib/xlib/s6_cmt_sfs_unisim.vbom [ghdl]../../../vlib/xlib/s6_cmt_sfs_gsim.vbom ../../../vlib/genlib/clkdivce.vbom ../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom ../../../bplib/bpgen/sn_humanio_rbus.vbom -../../../bplib/fx2lib/fx2_2fifoctl_as.vbom ../../../bplib/fx2lib/fx2_2fifoctl_ic.vbom ../../../bplib/fx2lib/fx2_3fifoctl_ic.vbom ../tst_rlink_cuff.vbom diff --git a/rtl/sys_gen/tst_rlink_cuff/nexys3/sys_tst_rlink_cuff_n3.vhd b/rtl/sys_gen/tst_rlink_cuff/nexys3/sys_tst_rlink_cuff_n3.vhd index 43c6b134..1b89c719 100644 --- a/rtl/sys_gen/tst_rlink_cuff/nexys3/sys_tst_rlink_cuff_n3.vhd +++ b/rtl/sys_gen/tst_rlink_cuff/nexys3/sys_tst_rlink_cuff_n3.vhd @@ -1,6 +1,6 @@ --- $Id: sys_tst_rlink_cuff_n3.vhd 620 2014-12-25 10:48:35Z mueller $ +-- $Id: sys_tst_rlink_cuff_n3.vhd 638 2015-01-25 22:01:38Z mueller $ -- --- Copyright 2013-2014 by Walter F.J. Mueller +-- Copyright 2013-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -19,7 +19,6 @@ -- vlib/genlib/clkdivce -- bplib/bpgen/bp_rs232_2l4l_iob -- bplib/bpgen/sn_humanio_rbus --- bplib/fx2lib/fx2_2fifoctl_as [sys_conf_fx2_type="as2"] -- bplib/fx2lib/fx2_2fifoctl_ic [sys_conf_fx2_type="ic2"] -- bplib/fx2lib/fx2_3fifoctl_ic [sys_conf_fx2_type="ic3"] -- tst_rlink_cuff @@ -36,6 +35,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2015-01-25 638 1.2.2 retire fx2_2fifoctl_as -- 2014-12-24 620 1.2.1 relocate hio rbus address -- 2014-08-15 583 1.2 rb_mreq addr now 16 bit -- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect @@ -233,44 +233,6 @@ begin O_SEG_N => O_SEG_N ); - FX2_CNTL_AS : if sys_conf_fx2_type = "as2" generate - CNTL : fx2_2fifoctl_as - generic map ( - RXFAWIDTH => 5, - TXFAWIDTH => 5, - CCWIDTH => sys_conf_fx2_ccwidth, - RXAEMPTY_THRES => 1, - TXAFULL_THRES => 1, - PETOWIDTH => sys_conf_fx2_petowidth, - RDPWLDELAY => sys_conf_fx2_rdpwldelay, - RDPWHDELAY => sys_conf_fx2_rdpwhdelay, - WRPWLDELAY => sys_conf_fx2_wrpwldelay, - WRPWHDELAY => sys_conf_fx2_wrpwhdelay, - FLAGDELAY => sys_conf_fx2_flagdelay) - port map ( - CLK => CLK, - CE_USEC => CE_USEC, - RESET => RESET, - RXDATA => FX2_RXDATA, - RXVAL => FX2_RXVAL, - RXHOLD => FX2_RXHOLD, - RXAEMPTY => FX2_RXAEMPTY, - TXDATA => FX2_TXDATA, - TXENA => FX2_TXENA, - TXBUSY => FX2_TXBUSY, - TXAFULL => FX2_TXAFULL, - MONI => FX2_MONI, - I_FX2_IFCLK => I_FX2_IFCLK, - O_FX2_FIFO => O_FX2_FIFO, - I_FX2_FLAG => I_FX2_FLAG, - O_FX2_SLRD_N => O_FX2_SLRD_N, - O_FX2_SLWR_N => O_FX2_SLWR_N, - O_FX2_SLOE_N => O_FX2_SLOE_N, - O_FX2_PKTEND_N => O_FX2_PKTEND_N, - IO_FX2_DATA => IO_FX2_DATA - ); - end generate FX2_CNTL_AS; - FX2_CNTL_IC : if sys_conf_fx2_type = "ic2" generate CNTL : fx2_2fifoctl_ic generic map ( diff --git a/rtl/sys_gen/tst_serloop/Makefile b/rtl/sys_gen/tst_serloop/Makefile index 84603070..d649f158 100644 --- a/rtl/sys_gen/tst_serloop/Makefile +++ b/rtl/sys_gen/tst_serloop/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 602 2014-11-08 21:42:47Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -8,7 +8,7 @@ VBOM_all = $(wildcard *.vbom) NGC_all = $(VBOM_all:.vbom=.ngc) # -include $(RETROBASE)/rtl/make/xflow_default_s3board.mk +include $(RETROBASE)/rtl/make_ise/xflow_default_s3board.mk # .PHONY : all clean distclean # @@ -21,8 +21,7 @@ distclean : # #---- # -include $(RETROBASE)/tools/make/dontincdep.mk -include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_serloop/nexys2/Makefile b/rtl/sys_gen/tst_serloop/nexys2/Makefile index e4824818..b08e216d 100644 --- a/rtl/sys_gen/tst_serloop/nexys2/Makefile +++ b/rtl/sys_gen/tst_serloop/nexys2/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -7,7 +7,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make/xflow_default_nexys2.mk +include $(RETROBASE)/rtl/make_ise/xflow_default_nexys2.mk # .PHONY : all clean # @@ -18,8 +18,8 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make/generic_xflow.mk -include $(RETROBASE)/rtl/make/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_serloop/nexys2/sys_conf1.vhd b/rtl/sys_gen/tst_serloop/nexys2/sys_conf1.vhd index 7b831a89..8debd817 100644 --- a/rtl/sys_gen/tst_serloop/nexys2/sys_conf1.vhd +++ b/rtl/sys_gen/tst_serloop/nexys2/sys_conf1.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf1.vhd 441 2011-12-20 17:01:16Z mueller $ +-- $Id: sys_conf1.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Definitions for sys_tst_serloop1_n2 (for synthesis) -- -- Dependencies: - --- Tool versions: xst 13.1; ghdl 0.29 +-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-11-16 439 1.0 Initial version diff --git a/rtl/sys_gen/tst_serloop/nexys2/sys_conf2.vhd b/rtl/sys_gen/tst_serloop/nexys2/sys_conf2.vhd index a4e4d55f..cb02ba2c 100644 --- a/rtl/sys_gen/tst_serloop/nexys2/sys_conf2.vhd +++ b/rtl/sys_gen/tst_serloop/nexys2/sys_conf2.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf2.vhd 441 2011-12-20 17:01:16Z mueller $ +-- $Id: sys_conf2.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Definitions for sys_tst_serloop2_n2 (for synthesis) -- -- Dependencies: - --- Tool versions: xst 13.1; ghdl 0.29 +-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-11-13 424 1.0 Initial version diff --git a/rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop1_n2.vhd b/rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop1_n2.vhd index 03d2c914..6eeedabb 100644 --- a/rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop1_n2.vhd +++ b/rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop1_n2.vhd @@ -1,4 +1,4 @@ --- $Id: sys_tst_serloop1_n2.vhd 476 2013-01-26 22:23:53Z mueller $ +-- $Id: sys_tst_serloop1_n2.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -26,7 +26,7 @@ -- Test bench: - -- -- Target Devices: generic --- Tool versions: xst 13.1; ghdl 0.29 +-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri diff --git a/rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop2_n2.vbom b/rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop2_n2.vbom index 5f3ac20a..37490503 100644 --- a/rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop2_n2.vbom +++ b/rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop2_n2.vbom @@ -8,7 +8,7 @@ ../../../bplib/nxcramlib/nxcramlib.vhd ${sys_conf := sys_conf2.vhd} # components -[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom +[xst,vsyn,isim,vsim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom [ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom ../../../vlib/genlib/clkdivce.vbom ../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom diff --git a/rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop2_n2.vhd b/rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop2_n2.vhd index c9feb43e..71589524 100644 --- a/rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop2_n2.vhd +++ b/rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop2_n2.vhd @@ -1,4 +1,4 @@ --- $Id: sys_tst_serloop2_n2.vhd 476 2013-01-26 22:23:53Z mueller $ +-- $Id: sys_tst_serloop2_n2.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -27,7 +27,7 @@ -- Test bench: - -- -- Target Devices: generic --- Tool versions: xst 13.1; ghdl 0.29 +-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri diff --git a/rtl/sys_gen/tst_serloop/nexys2/tb/Makefile b/rtl/sys_gen/tst_serloop/nexys2/tb/Makefile index 73ecc537..941e677b 100644 --- a/rtl/sys_gen/tst_serloop/nexys2/tb/Makefile +++ b/rtl/sys_gen/tst_serloop/nexys2/tb/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -7,7 +7,7 @@ EXE_all = tb_tst_serloop1_n2 EXE_all += tb_tst_serloop2_n2 # -include $(RETROBASE)/rtl/make/xflow_default_nexys2.mk +include $(RETROBASE)/rtl/make_ise/xflow_default_nexys2.mk # .PHONY : all all_ssim all_tsim clean # @@ -19,9 +19,9 @@ clean : ise_clean ghdl_clean isim_clean # #----- # -include $(RETROBASE)/rtl/make/generic_ghdl.mk -include $(RETROBASE)/rtl/make/generic_isim.mk -include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_isim.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/sys_gen/tst_serloop/nexys2/tb/sys_conf1_sim.vhd b/rtl/sys_gen/tst_serloop/nexys2/tb/sys_conf1_sim.vhd index 1f91b4fe..9e26293b 100644 --- a/rtl/sys_gen/tst_serloop/nexys2/tb/sys_conf1_sim.vhd +++ b/rtl/sys_gen/tst_serloop/nexys2/tb/sys_conf1_sim.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf1_sim.vhd 441 2011-12-20 17:01:16Z mueller $ +-- $Id: sys_conf1_sim.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Definitions for sys_tst_serloop1_n2 (for test bench) -- -- Dependencies: - --- Tool versions: xst 11.4; ghdl 0.26 +-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-12-16 439 1.0 Initial version diff --git a/rtl/sys_gen/tst_serloop/nexys2/tb/sys_conf2_sim.vhd b/rtl/sys_gen/tst_serloop/nexys2/tb/sys_conf2_sim.vhd index 02512d6f..e488e2d5 100644 --- a/rtl/sys_gen/tst_serloop/nexys2/tb/sys_conf2_sim.vhd +++ b/rtl/sys_gen/tst_serloop/nexys2/tb/sys_conf2_sim.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf2_sim.vhd 441 2011-12-20 17:01:16Z mueller $ +-- $Id: sys_conf2_sim.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Definitions for sys_tst_serloop2_n2 (for test bench) -- -- Dependencies: - --- Tool versions: xst 11.4; ghdl 0.26 +-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-11-13 424 1.0 Initial version diff --git a/rtl/sys_gen/tst_serloop/nexys3/Makefile b/rtl/sys_gen/tst_serloop/nexys3/Makefile index 7430a779..1b75a211 100644 --- a/rtl/sys_gen/tst_serloop/nexys3/Makefile +++ b/rtl/sys_gen/tst_serloop/nexys3/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -7,7 +7,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make/xflow_default_nexys3.mk +include $(RETROBASE)/rtl/make_ise/xflow_default_nexys3.mk # .PHONY : all clean # @@ -18,8 +18,8 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make/generic_xflow.mk -include $(RETROBASE)/rtl/make/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_serloop/nexys3/sys_conf1.vhd b/rtl/sys_gen/tst_serloop/nexys3/sys_conf1.vhd index 3da0a6e0..00c09664 100644 --- a/rtl/sys_gen/tst_serloop/nexys3/sys_conf1.vhd +++ b/rtl/sys_gen/tst_serloop/nexys3/sys_conf1.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf1.vhd 441 2011-12-20 17:01:16Z mueller $ +-- $Id: sys_conf1.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Definitions for sys_tst_serloop1_n3 (for synthesis) -- -- Dependencies: - --- Tool versions: xst 13.1; ghdl 0.29 +-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-12-09 438 1.0 Initial version diff --git a/rtl/sys_gen/tst_serloop/nexys3/sys_tst_serloop1_n3.vhd b/rtl/sys_gen/tst_serloop/nexys3/sys_tst_serloop1_n3.vhd index 8e38b1e9..66edad76 100644 --- a/rtl/sys_gen/tst_serloop/nexys3/sys_tst_serloop1_n3.vhd +++ b/rtl/sys_gen/tst_serloop/nexys3/sys_tst_serloop1_n3.vhd @@ -1,4 +1,4 @@ --- $Id: sys_tst_serloop1_n3.vhd 476 2013-01-26 22:23:53Z mueller $ +-- $Id: sys_tst_serloop1_n3.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -26,7 +26,7 @@ -- Test bench: - -- -- Target Devices: generic --- Tool versions: xst 13.1; ghdl 0.29 +-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri diff --git a/rtl/sys_gen/tst_serloop/nexys3/tb/Makefile b/rtl/sys_gen/tst_serloop/nexys3/tb/Makefile index ef77128b..2eeca478 100644 --- a/rtl/sys_gen/tst_serloop/nexys3/tb/Makefile +++ b/rtl/sys_gen/tst_serloop/nexys3/tb/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -7,7 +7,7 @@ # EXE_all = tb_tst_serloop1_n3 # -include $(RETROBASE)/rtl/make/xflow_default_nexys3.mk +include $(RETROBASE)/rtl/make_ise/xflow_default_nexys3.mk # .PHONY : all all_ssim all_tsim clean # @@ -19,9 +19,9 @@ clean : ise_clean ghdl_clean isim_clean # #----- # -include $(RETROBASE)/rtl/make/generic_ghdl.mk -include $(RETROBASE)/rtl/make/generic_isim.mk -include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_isim.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/sys_gen/tst_serloop/nexys3/tb/sys_conf1_sim.vhd b/rtl/sys_gen/tst_serloop/nexys3/tb/sys_conf1_sim.vhd index de1c166b..e10511f7 100644 --- a/rtl/sys_gen/tst_serloop/nexys3/tb/sys_conf1_sim.vhd +++ b/rtl/sys_gen/tst_serloop/nexys3/tb/sys_conf1_sim.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf1_sim.vhd 441 2011-12-20 17:01:16Z mueller $ +-- $Id: sys_conf1_sim.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Definitions for sys_tst_serloop1_n3 (for test bench) -- -- Dependencies: - --- Tool versions: xst 13.1; ghdl 0.29 +-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-12-11 438 1.0 Initial version diff --git a/rtl/sys_gen/tst_serloop/nexys4/.cvsignore b/rtl/sys_gen/tst_serloop/nexys4/.cvsignore new file mode 100644 index 00000000..bcfb2aa7 --- /dev/null +++ b/rtl/sys_gen/tst_serloop/nexys4/.cvsignore @@ -0,0 +1,7 @@ +.Xil +project_mflow +*.jou +*.log +*.rpt +*.dcp +*.dep_* diff --git a/rtl/sys_gen/tst_serloop/nexys4/Makefile b/rtl/sys_gen/tst_serloop/nexys4/Makefile new file mode 100644 index 00000000..4835aa3c --- /dev/null +++ b/rtl/sys_gen/tst_serloop/nexys4/Makefile @@ -0,0 +1,25 @@ +# $Id: Makefile 646 2015-02-15 12:04:55Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2015-02-01 641 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +include $(RETROBASE)/rtl/make_viv/viv_default_nexys4.mk +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : viv_clean +# +#---- +# +include $(RETROBASE)/rtl/make_viv/generic_vivado.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +endif +# diff --git a/rtl/sys_gen/tst_serloop/nexys4/sys_conf1.vhd b/rtl/sys_gen/tst_serloop/nexys4/sys_conf1.vhd new file mode 100644 index 00000000..da2ff81f --- /dev/null +++ b/rtl/sys_gen/tst_serloop/nexys4/sys_conf1.vhd @@ -0,0 +1,37 @@ +-- $Id: sys_conf1.vhd 646 2015-02-15 12:04:55Z mueller $ +-- +-- Copyright 2015- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_serloop1_n4 (for synthesis) +-- +-- Dependencies: - +-- Tool versions: viv 2014.4; ghdl 0.31 +-- Revision History: +-- Date Rev Version Comment +-- 2015-02-01 641 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_clkdiv_usecdiv : integer := 100; -- default usec + constant sys_conf_clkdiv_msecdiv : integer := 1000; -- default msec + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + constant sys_conf_uart_cdinit : integer := 868-1; -- 100000000/115200 + +end package sys_conf; diff --git a/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop1_n4.vbom b/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop1_n4.vbom new file mode 100644 index 00000000..9fa849f9 --- /dev/null +++ b/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop1_n4.vbom @@ -0,0 +1,19 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/xlib/xlib.vhd +../../../vlib/genlib/genlib.vhd +../../../bplib/bpgen/bpgenlib.vbom +../tst_serlooplib.vbom +../../../vlib/serport/serportlib.vbom +${sys_conf := sys_conf1.vhd} +# components +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/bp_rs232_4line_iob.vbom +../../../bplib/bpgen/sn_humanio.vbom +../tst_serloop_hiomap.vbom +../../../vlib/serport/serport_1clock.vbom +../tst_serloop.vbom +# design +sys_tst_serloop1_n4.vhd +@xdc:../../../bplib/nexys4/nexys4_pclk.xdc +@xdc:../../../bplib/nexys4/nexys4_pins.xdc diff --git a/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop1_n4.vhd b/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop1_n4.vhd new file mode 100644 index 00000000..946f6bfc --- /dev/null +++ b/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop1_n4.vhd @@ -0,0 +1,223 @@ +-- $Id: sys_tst_serloop1_n4.vhd 646 2015-02-15 12:04:55Z mueller $ +-- +-- Copyright 2015- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_tst_serloop1_n4 - syn +-- Description: Tester serial link for nexys3 (serport_1clock case) +-- +-- Dependencies: genlib/clkdivce +-- bpgen/bp_rs232_4line_iob +-- bpgen/sn_humanio +-- tst_serloop_hiomap +-- vlib/serport/serport_1clock +-- tst_serloop +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: viv 2014.4; ghdl 0.31 +-- +-- Synthesized: +-- Date Rev viv Target flop lutl lutm bram slic +-- 2015-02-01 641 2014.4 xc7a100t-1 xxx xxxx xx x xxx +-- +-- Revision History: +-- Date Rev Version Comment +-- 2015-02-06 643 1.1 factor out memory +-- 2015-02-01 641 1.0 Initial version (derived from sys_tst_serloop1_n3) +------------------------------------------------------------------------------ +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.genlib.all; +use work.bpgenlib.all; +use work.tst_serlooplib.all; +use work.serportlib.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_tst_serloop1_n4 is -- top level + -- implements nexys4_aif + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + O_RTS_N : out slbit; -- rx rts (board view; act.low) + I_CTS_N : in slbit; -- tx cts (board view; act.low) + I_SWI : in slv16; -- n4 switches + I_BTN : in slv5; -- n4 buttons + I_BTNRST_N : in slbit; -- n4 reset button + O_LED : out slv16; -- n4 leds + O_RGBLED0 : out slv3; -- n4 rgb-led 0 + O_RGBLED1 : out slv3; -- n4 rgb-led 1 + O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8 -- 7 segment disp: segments (act.low) + ); +end sys_tst_serloop1_n4; + +architecture syn of sys_tst_serloop1_n4 is + + signal CLK : slbit := '0'; + signal RESET : slbit := '0'; + + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal RXD : slbit := '0'; + signal TXD : slbit := '0'; + signal CTS_N : slbit := '0'; + signal RTS_N : slbit := '0'; + + signal SWI : slv16 := (others=>'0'); + signal BTN : slv5 := (others=>'0'); + signal LED : slv16 := (others=>'0'); + signal DSP_DAT : slv32 := (others=>'0'); + signal DSP_DP : slv8 := (others=>'0'); + + signal HIO_CNTL : hio_cntl_type := hio_cntl_init; + signal HIO_STAT : hio_stat_type := hio_stat_init; + + signal RXDATA : slv8 := (others=>'0'); + signal RXVAL : slbit := '0'; + signal RXHOLD : slbit := '0'; + signal TXDATA : slv8 := (others=>'0'); + signal TXENA : slbit := '0'; + signal TXBUSY : slbit := '0'; + + signal SER_MONI : serport_moni_type := serport_moni_init; + +begin + + CLK <= I_CLK100; + + CLKDIV : clkdivce + generic map ( + CDUWIDTH => 8, + USECDIV => sys_conf_clkdiv_usecdiv, -- syn: 100 sim: 20 + MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5 + port map ( + CLK => CLK, + CE_USEC => open, + CE_MSEC => CE_MSEC + ); + + HIO : sn_humanio + generic map ( + SWIDTH => 16, + BWIDTH => 5, + LWIDTH => 16, + DCWIDTH => 3, + DEBOUNCE => sys_conf_hio_debounce) + port map ( + CLK => CLK, + RESET => '0', + CE_MSEC => CE_MSEC, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + RESET <= BTN(0); -- BTN(0) will reset tester !! + + HIOMAP : tst_serloop_hiomap + port map ( + CLK => CLK, + RESET => RESET, + HIO_CNTL => HIO_CNTL, + HIO_STAT => HIO_STAT, + SER_MONI => SER_MONI, + SWI => SWI(7 downto 0), + BTN => BTN(3 downto 0), + LED => LED(7 downto 0), + DSP_DAT => DSP_DAT(15 downto 0), + DSP_DP => DSP_DP(3 downto 0) + ); + + IOB_RS232 : bp_rs232_4line_iob + port map ( + CLK => CLK, + RXD => RXD, + TXD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + I_RXD => I_RXD, + O_TXD => O_TXD, + I_CTS_N => I_CTS_N, + O_RTS_N => O_RTS_N + ); + + SERPORT : serport_1clock + generic map ( + CDWIDTH => 15, + CDINIT => sys_conf_uart_cdinit, + RXFAWIDTH => 5, + TXFAWIDTH => 5) + port map ( + CLK => CLK, + CE_MSEC => CE_MSEC, + RESET => RESET, + ENAXON => HIO_CNTL.enaxon, + ENAESC => HIO_CNTL.enaesc, + RXDATA => RXDATA, + RXVAL => RXVAL, + RXHOLD => RXHOLD, + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY, + MONI => SER_MONI, + RXSD => RXD, + TXSD => TXD, + RXRTS_N => RTS_N, + TXCTS_N => CTS_N + ); + + TESTER : tst_serloop + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + HIO_CNTL => HIO_CNTL, + HIO_STAT => HIO_STAT, + SER_MONI => SER_MONI, + RXDATA => RXDATA, + RXVAL => RXVAL, + RXHOLD => RXHOLD, + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY + ); + + -- show autobauder clock divisor on msb of display + DSP_DAT(31 downto 20) <= SER_MONI.abclkdiv(11 downto 0); + DSP_DAT(19) <= '0'; + DSP_DAT(18 downto 16) <= SER_MONI.abclkdiv_f; + DSP_DP(7 downto 4) <= "0010"; + + -- setup unused outputs in nexys4 + O_RGBLED0 <= (others=>'0'); + O_RGBLED1 <= (others=>not I_BTNRST_N); + +end syn; diff --git a/rtl/sys_gen/tst_serloop/nexys4/tb/.cvsignore b/rtl/sys_gen/tst_serloop/nexys4/tb/.cvsignore new file mode 100644 index 00000000..e1cd7d9a --- /dev/null +++ b/rtl/sys_gen/tst_serloop/nexys4/tb/.cvsignore @@ -0,0 +1,4 @@ +tb_tst_serloop1_n4 +tb_tst_serloop1_n4_[so]sim +tb_tst_serloop_stim +*.dep_* diff --git a/rtl/sys_gen/tst_serloop/nexys4/tb/Makefile b/rtl/sys_gen/tst_serloop/nexys4/tb/Makefile new file mode 100644 index 00000000..f1516384 --- /dev/null +++ b/rtl/sys_gen/tst_serloop/nexys4/tb/Makefile @@ -0,0 +1,30 @@ +# $Id: Makefile 649 2015-02-21 21:10:16Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2015-02-21 649 1.0 Initial version +# +EXE_all = tb_tst_serloop1_n4 +# +include $(RETROBASE)/rtl/make_viv/viv_default_nexys4.mk +# +.PHONY : all all_ssim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +# +clean : viv_clean ghdl_clean +# +#----- +# +include $(RETROBASE)/rtl/make_viv/generic_vivado.mk +include $(RETROBASE)/rtl/make_viv/generic_ghdl.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(wildcard *.o.dep_ghdl) +endif +# diff --git a/rtl/sys_gen/tst_serloop/nexys4/tb/sys_conf1_sim.vhd b/rtl/sys_gen/tst_serloop/nexys4/tb/sys_conf1_sim.vhd new file mode 100644 index 00000000..5b4f1b88 --- /dev/null +++ b/rtl/sys_gen/tst_serloop/nexys4/tb/sys_conf1_sim.vhd @@ -0,0 +1,43 @@ +-- $Id: sys_conf1_sim.vhd 649 2015-02-21 21:10:16Z mueller $ +-- +-- Copyright 2015- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_serloop1_n4 (for test bench) +-- +-- Dependencies: - +-- Tool versions: viv 2014.4; ghdl 0.31 +-- Revision History: +-- Date Rev Version Comment +-- 2015-02-21 649 1.0 Initial version (cloned from sys_tst_serloop1_n3) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + -- in simulation a usec is shortened to 20 cycles (0.2 usec) and a msec + -- to 100 cycles (1 usec). This affects the pulse generators (usec) and + -- mainly the autobauder. A break will be detected after 128 msec periods, + -- this in simulation after 128 usec or 6400 cycles. This is compatible with + -- bitrates of 115200 baud or higher (115200 <-> 8.68 usec <-> 521 cycles) + + constant sys_conf_clkdiv_usecdiv : integer := 20; -- default usec + constant sys_conf_clkdiv_msecdiv : integer := 5; -- shortened ! + constant sys_conf_hio_debounce : boolean := false; -- no debouncers + constant sys_conf_uart_cdinit : integer := 1-1; -- 1 cycle/bit in sim + +end package sys_conf; diff --git a/rtl/sys_gen/tst_serloop/nexys4/tb/tb_tst_serloop1_n4.vbom b/rtl/sys_gen/tst_serloop/nexys4/tb/tb_tst_serloop1_n4.vbom new file mode 100644 index 00000000..4653012a --- /dev/null +++ b/rtl/sys_gen/tst_serloop/nexys4/tb/tb_tst_serloop1_n4.vbom @@ -0,0 +1,11 @@ +# conf +sys_conf = sys_conf1_sim.vhd +# libs +../../../../vlib/slvtypes.vhd +../../../../vlib/simlib/simlib.vhd +# components +../../../../vlib/simlib/simclk.vbom +../sys_tst_serloop1_n4.vbom +../../tb/tb_tst_serloop.vbom +# design +tb_tst_serloop1_n4.vhd diff --git a/rtl/sys_gen/tst_serloop/nexys4/tb/tb_tst_serloop1_n4.vhd b/rtl/sys_gen/tst_serloop/nexys4/tb/tb_tst_serloop1_n4.vhd new file mode 100644 index 00000000..74a8fd9e --- /dev/null +++ b/rtl/sys_gen/tst_serloop/nexys4/tb/tb_tst_serloop1_n4.vhd @@ -0,0 +1,119 @@ +-- $Id: tb_tst_serloop1_n4.vhd 649 2015-02-21 21:10:16Z mueller $ +-- +-- Copyright 2015- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_tst_serloop1_n4 - sim +-- Description: Test bench for sys_tst_serloop1_n4 +-- +-- Dependencies: simlib/simclk +-- sys_tst_serloop1_n4 [UUT] +-- tb/tb_tst_serloop +-- +-- To test: sys_tst_serloop1_n4 +-- +-- Target Devices: generic +-- +-- Revision History: +-- Date Rev Version Comment +-- 2015-02-21 438 1.0 Initial version (cloned from tb_tst_serloop1_n3) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.simlib.all; + +entity tb_tst_serloop1_n4 is +end tb_tst_serloop1_n4; + +architecture sim of tb_tst_serloop1_n4 is + + signal CLK100 : slbit := '0'; + signal CLK_STOP : slbit := '0'; + + signal I_RXD : slbit := '1'; + signal O_TXD : slbit := '1'; + signal O_RTS_N : slbit := '0'; + signal I_CTS_N : slbit := '0'; + signal I_SWI : slv16 := (others=>'0'); + signal I_BTN : slv5 := (others=>'0'); + + signal RXD : slbit := '1'; + signal TXD : slbit := '1'; + signal RTS_N : slbit := '0'; + signal CTS_N : slbit := '0'; + signal SWI : slv16 := (others=>'0'); + signal BTN : slv5 := (others=>'0'); + + constant clock_period : time := 10 ns; + constant clock_offset : time := 200 ns; + constant delay_time : time := 2 ns; + +begin + + SYSCLK : simclk + generic map ( + PERIOD => clock_period, + OFFSET => clock_offset) + port map ( + CLK => CLK100, + CLK_STOP => CLK_STOP + ); + + UUT : entity work.sys_tst_serloop1_n4 + port map ( + I_CLK100 => CLK100, + I_RXD => I_RXD, + O_TXD => O_TXD, + O_RTS_N => O_RTS_N, + I_CTS_N => I_CTS_N, + I_SWI => I_SWI, + I_BTN => I_BTN, + I_BTNRST_N => '1', + O_LED => open, + O_RGBLED0 => open, + O_RGBLED1 => open, + O_ANO_N => open, + O_SEG_N => open + ); + + GENTB : entity work.tb_tst_serloop + port map ( + CLKS => CLK100, + CLKH => CLK100, + CLK_STOP => CLK_STOP, + P0_RXD => RXD, + P0_TXD => TXD, + P0_RTS_N => RTS_N, + P0_CTS_N => CTS_N, + P1_RXD => RXD, + P1_TXD => TXD, + P1_RTS_N => RTS_N, + P1_CTS_N => CTS_N, + SWI => SWI(7 downto 0), + BTN => BTN(3 downto 0) + ); + + I_RXD <= RXD after delay_time; + TXD <= O_TXD after delay_time; + RTS_N <= O_RTS_N after delay_time; + I_CTS_N <= CTS_N after delay_time; + + I_SWI <= SWI after delay_time; + I_BTN <= BTN after delay_time; + +end sim; diff --git a/rtl/sys_gen/tst_serloop/nexys4/tb/tbw.dat b/rtl/sys_gen/tst_serloop/nexys4/tb/tbw.dat new file mode 100644 index 00000000..94b47535 --- /dev/null +++ b/rtl/sys_gen/tst_serloop/nexys4/tb/tbw.dat @@ -0,0 +1,6 @@ +# $Id: tbw.dat 649 2015-02-21 21:10:16Z mueller $ +# +[tb_tst_serloop1_n4] +tb_tst_serloop_stim = ../../tb/tb_tst_serloop_stim.dat +[tb_tst_serloop2_n4] +tb_tst_serloop_stim = ../../tb/tb_tst_serloop_stim.dat diff --git a/rtl/sys_gen/tst_serloop/s3board/Makefile b/rtl/sys_gen/tst_serloop/s3board/Makefile index 3d02f4c7..70d13b25 100644 --- a/rtl/sys_gen/tst_serloop/s3board/Makefile +++ b/rtl/sys_gen/tst_serloop/s3board/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -7,7 +7,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make/xflow_default_s3board.mk +include $(RETROBASE)/rtl/make_ise/xflow_default_s3board.mk # .PHONY : all clean # @@ -18,8 +18,8 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make/generic_xflow.mk -include $(RETROBASE)/rtl/make/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_serloop/s3board/sys_conf.vhd b/rtl/sys_gen/tst_serloop/s3board/sys_conf.vhd index 3c39260c..8ec29cf3 100644 --- a/rtl/sys_gen/tst_serloop/s3board/sys_conf.vhd +++ b/rtl/sys_gen/tst_serloop/s3board/sys_conf.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf.vhd 441 2011-12-20 17:01:16Z mueller $ +-- $Id: sys_conf.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Definitions for sys_tst_serloop_s3 (for synthesis) -- -- Dependencies: - --- Tool versions: xst 13.1; ghdl 0.29 +-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-11-13 424 1.0 Initial version diff --git a/rtl/sys_gen/tst_serloop/s3board/sys_tst_serloop_s3.vbom b/rtl/sys_gen/tst_serloop/s3board/sys_tst_serloop_s3.vbom index 64a123f6..faa1b30d 100644 --- a/rtl/sys_gen/tst_serloop/s3board/sys_tst_serloop_s3.vbom +++ b/rtl/sys_gen/tst_serloop/s3board/sys_tst_serloop_s3.vbom @@ -8,7 +8,7 @@ ../../../bplib/s3board/s3boardlib.vbom ${sys_conf := sys_conf.vhd} # components -[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3.vbom +[xst,vsyn,isim,vsim]../../../vlib/xlib/dcm_sfs_unisim_s3.vbom [ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom ../../../vlib/genlib/clkdivce.vbom ../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom diff --git a/rtl/sys_gen/tst_serloop/s3board/sys_tst_serloop_s3.vhd b/rtl/sys_gen/tst_serloop/s3board/sys_tst_serloop_s3.vhd index ee2bef9d..8b3a3bee 100644 --- a/rtl/sys_gen/tst_serloop/s3board/sys_tst_serloop_s3.vhd +++ b/rtl/sys_gen/tst_serloop/s3board/sys_tst_serloop_s3.vhd @@ -1,4 +1,4 @@ --- $Id: sys_tst_serloop_s3.vhd 476 2013-01-26 22:23:53Z mueller $ +-- $Id: sys_tst_serloop_s3.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -27,7 +27,7 @@ -- Test bench: - -- -- Target Devices: generic --- Tool versions: xst 13.1; ghdl 0.29 +-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri diff --git a/rtl/sys_gen/tst_serloop/s3board/tb/Makefile b/rtl/sys_gen/tst_serloop/s3board/tb/Makefile index daaba848..384af1b2 100644 --- a/rtl/sys_gen/tst_serloop/s3board/tb/Makefile +++ b/rtl/sys_gen/tst_serloop/s3board/tb/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -6,7 +6,7 @@ # EXE_all = tb_tst_serloop_s3 # -include $(RETROBASE)/rtl/make/xflow_default_s3board.mk +include $(RETROBASE)/rtl/make_ise/xflow_default_s3board.mk # .PHONY : all all_ssim all_tsim clean # @@ -18,9 +18,9 @@ clean : ise_clean ghdl_clean isim_clean # #----- # -include $(RETROBASE)/rtl/make/generic_ghdl.mk -include $(RETROBASE)/rtl/make/generic_isim.mk -include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_isim.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/sys_gen/tst_serloop/s3board/tb/sys_conf_sim.vhd b/rtl/sys_gen/tst_serloop/s3board/tb/sys_conf_sim.vhd index 9b19c4ca..e4c89d58 100644 --- a/rtl/sys_gen/tst_serloop/s3board/tb/sys_conf_sim.vhd +++ b/rtl/sys_gen/tst_serloop/s3board/tb/sys_conf_sim.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf_sim.vhd 441 2011-12-20 17:01:16Z mueller $ +-- $Id: sys_conf_sim.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Definitions for sys_tst_serloop_s3 (for test bench) -- -- Dependencies: - --- Tool versions: xst 11.4; ghdl 0.26 +-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-11-05 420 1.0 Initial version diff --git a/rtl/sys_gen/tst_serloop/tst_serloop.vhd b/rtl/sys_gen/tst_serloop/tst_serloop.vhd index 477ca50f..678cb590 100644 --- a/rtl/sys_gen/tst_serloop/tst_serloop.vhd +++ b/rtl/sys_gen/tst_serloop/tst_serloop.vhd @@ -1,4 +1,4 @@ --- $Id: tst_serloop.vhd 476 2013-01-26 22:23:53Z mueller $ +-- $Id: tst_serloop.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -19,7 +19,7 @@ -- Test bench: - -- -- Target Devices: generic --- Tool versions: xst 13.1; ghdl 0.29 +-- Tool versions: ise 13.1-14.7; viv 2014.4; ghdl 0.29-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/sys_gen/tst_serloop/tst_serloop_hiomap.vhd b/rtl/sys_gen/tst_serloop/tst_serloop_hiomap.vhd index 71daa637..da101fb4 100644 --- a/rtl/sys_gen/tst_serloop/tst_serloop_hiomap.vhd +++ b/rtl/sys_gen/tst_serloop/tst_serloop_hiomap.vhd @@ -1,4 +1,4 @@ --- $Id: tst_serloop_hiomap.vhd 476 2013-01-26 22:23:53Z mueller $ +-- $Id: tst_serloop_hiomap.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -19,7 +19,7 @@ -- Test bench: - -- -- Target Devices: generic --- Tool versions: xst 13.1; ghdl 0.29 +-- Tool versions: ise 13.1-14.7; viv 2014.4; ghdl 0.29-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/sys_gen/tst_serloop/tst_serlooplib.vhd b/rtl/sys_gen/tst_serloop/tst_serlooplib.vhd index 83cbbfcb..9e8543fd 100644 --- a/rtl/sys_gen/tst_serloop/tst_serlooplib.vhd +++ b/rtl/sys_gen/tst_serloop/tst_serlooplib.vhd @@ -1,4 +1,4 @@ --- $Id: tst_serlooplib.vhd 476 2013-01-26 22:23:53Z mueller $ +-- $Id: tst_serlooplib.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Definitions for tst_serloop records and helpers -- -- Dependencies: - --- Tool versions: xst 13.1; ghdl 0.29 +-- Tool versions: ise 13.1-14.7; viv 2014.7; ghdl 0.29-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-12-10 438 1.0.2 add rxui(cnt|dat) fields in hio_stat_type diff --git a/rtl/sys_gen/tst_snhumanio/Makefile b/rtl/sys_gen/tst_snhumanio/Makefile index 0f685d42..d413b6a3 100644 --- a/rtl/sys_gen/tst_snhumanio/Makefile +++ b/rtl/sys_gen/tst_snhumanio/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -7,7 +7,7 @@ VBOM_all = $(wildcard *.vbom) NGC_all = $(VBOM_all:.vbom=.ngc) # -include $(RETROBASE)/rtl/make/xflow_default_s3board.mk +include $(RETROBASE)/rtl/make_ise/xflow_default_s3board.mk # .PHONY : all clean # @@ -17,7 +17,7 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_snhumanio/atlys/Makefile b/rtl/sys_gen/tst_snhumanio/atlys/Makefile index de97a319..1c31f539 100644 --- a/rtl/sys_gen/tst_snhumanio/atlys/Makefile +++ b/rtl/sys_gen/tst_snhumanio/atlys/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -7,7 +7,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make/xflow_default_atlys.mk +include $(RETROBASE)/rtl/make_ise/xflow_default_atlys.mk # .PHONY : all clean # @@ -18,8 +18,8 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make/generic_xflow.mk -include $(RETROBASE)/rtl/make/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_snhumanio/atlys/sys_conf.vhd b/rtl/sys_gen/tst_snhumanio/atlys/sys_conf.vhd index a71ea8e6..d1fa4057 100644 --- a/rtl/sys_gen/tst_snhumanio/atlys/sys_conf.vhd +++ b/rtl/sys_gen/tst_snhumanio/atlys/sys_conf.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf.vhd 414 2011-10-11 19:38:12Z mueller $ +-- $Id: sys_conf.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Definitions for sys_tst_snhumanio_atlys (for synthesis) -- -- Dependencies: - --- Tool versions: xst 13.1; ghdl 0.29 +-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-10-11 414 1.0 Initial version diff --git a/rtl/sys_gen/tst_snhumanio/atlys/sys_tst_snhumanio_atlys.vhd b/rtl/sys_gen/tst_snhumanio/atlys/sys_tst_snhumanio_atlys.vhd index a26bacd9..3d0993c7 100644 --- a/rtl/sys_gen/tst_snhumanio/atlys/sys_tst_snhumanio_atlys.vhd +++ b/rtl/sys_gen/tst_snhumanio/atlys/sys_tst_snhumanio_atlys.vhd @@ -1,4 +1,4 @@ --- $Id: sys_tst_snhumanio_atlys.vhd 439 2011-12-16 21:56:04Z mueller $ +-- $Id: sys_tst_snhumanio_atlys.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -22,7 +22,7 @@ -- Test bench: - -- -- Target Devices: generic --- Tool versions: xst 13.1; ghdl 0.29 +-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri diff --git a/rtl/sys_gen/tst_snhumanio/basys3/.cvsignore b/rtl/sys_gen/tst_snhumanio/basys3/.cvsignore new file mode 100644 index 00000000..bcfb2aa7 --- /dev/null +++ b/rtl/sys_gen/tst_snhumanio/basys3/.cvsignore @@ -0,0 +1,7 @@ +.Xil +project_mflow +*.jou +*.log +*.rpt +*.dcp +*.dep_* diff --git a/rtl/sys_gen/tst_snhumanio/basys3/Makefile b/rtl/sys_gen/tst_snhumanio/basys3/Makefile new file mode 100644 index 00000000..540f0167 --- /dev/null +++ b/rtl/sys_gen/tst_snhumanio/basys3/Makefile @@ -0,0 +1,26 @@ +# $Id: Makefile 646 2015-02-15 12:04:55Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2015-01-25 637 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +include $(RETROBASE)/rtl/make_viv/viv_default_basys3.mk +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : viv_clean + rm -f $(VBOM_all:.vbom=.ucf) +# +#---- +# +include $(RETROBASE)/rtl/make_viv/generic_vivado.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +endif +# diff --git a/rtl/sys_gen/tst_snhumanio/basys3/sys_conf.vhd b/rtl/sys_gen/tst_snhumanio/basys3/sys_conf.vhd new file mode 100644 index 00000000..57b71d4f --- /dev/null +++ b/rtl/sys_gen/tst_snhumanio/basys3/sys_conf.vhd @@ -0,0 +1,35 @@ +-- $Id: sys_conf.vhd 636 2015-01-16 22:22:25Z mueller $ +-- +-- Copyright 2015- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_snhumanio_b3 (for synthesis) +-- +-- Dependencies: - +-- Tool versions: viv 2014.4; ghdl 0.31 +-- Revision History: +-- Date Rev Version Comment +-- 2015-01-16 636 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + +end package sys_conf; + diff --git a/rtl/sys_gen/tst_snhumanio/basys3/sys_tst_snhumanio_b3.vbom b/rtl/sys_gen/tst_snhumanio/basys3/sys_tst_snhumanio_b3.vbom new file mode 100644 index 00000000..3805bc86 --- /dev/null +++ b/rtl/sys_gen/tst_snhumanio/basys3/sys_tst_snhumanio_b3.vbom @@ -0,0 +1,13 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/genlib/genlib.vhd +../../../bplib/bpgen/bpgenlib.vbom +${sys_conf := sys_conf.vhd} +# components +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/sn_humanio.vbom +../tst_snhumanio.vbom +# design +sys_tst_snhumanio_b3.vhd +@xdc:../../../bplib/basys3/basys3_pclk.xdc +@xdc:../../../bplib/basys3/basys3_pins.xdc diff --git a/rtl/sys_gen/tst_snhumanio/basys3/sys_tst_snhumanio_b3.vhd b/rtl/sys_gen/tst_snhumanio/basys3/sys_tst_snhumanio_b3.vhd new file mode 100644 index 00000000..5b19719c --- /dev/null +++ b/rtl/sys_gen/tst_snhumanio/basys3/sys_tst_snhumanio_b3.vhd @@ -0,0 +1,129 @@ +-- $Id: sys_tst_snhumanio_b3.vhd 640 2015-02-01 09:56:53Z mueller $ +-- +-- Copyright 2015- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_tst_snhumanio_b3 - syn +-- Description: snhumanio tester design for basys3 +-- +-- Dependencies: vlib/genlib/clkdivce +-- bplib/bpgen/sn_humanio +-- tst_snhumanio +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: viv 2014.4; ghdl 0.31 +-- +-- Synthesized (xst): +-- Date Rev viv Target flop lutl lutm bram slic +-- 2015-01-30 636 2014.4 xc7a35t-1 154 133 0 0 63 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2015-01-16 636 1.0 Initial version +------------------------------------------------------------------------------ +-- Usage of Basys 3 Switches, Buttons, LEDs: +-- + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.genlib.all; +use work.bpgenlib.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_tst_snhumanio_b3 is -- top level + -- implements basys3_aif + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv16; -- b3 switches + I_BTN : in slv5; -- b3 buttons + O_LED : out slv16; -- b3 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8 -- 7 segment disp: segments (act.low) + ); +end sys_tst_snhumanio_b3; + +architecture syn of sys_tst_snhumanio_b3 is + + signal CLK : slbit := '0'; + + signal SWI : slv8 := (others=>'0'); + signal BTN : slv5 := (others=>'0'); + signal LED : slv8 := (others=>'0'); + signal DSP_DAT : slv16 := (others=>'0'); + signal DSP_DP : slv4 := (others=>'0'); + + signal RESET : slbit := '0'; + signal CE_MSEC : slbit := '0'; + +begin + + RESET <= '0'; -- so far not used + + CLK <= I_CLK100; + + CLKDIV : clkdivce + generic map ( + CDUWIDTH => 7, + USECDIV => 100, + MSECDIV => 1000) + port map ( + CLK => CLK, + CE_USEC => open, + CE_MSEC => CE_MSEC + ); + + HIO : sn_humanio + generic map ( + BWIDTH => 5, + DEBOUNCE => sys_conf_hio_debounce) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI(7 downto 0), + I_BTN => I_BTN, + O_LED => O_LED(7 downto 0), + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + HIOTEST : entity work.tst_snhumanio + generic map ( + BWIDTH => 5) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP + ); + + O_TXD <= I_RXD; + O_LED(15 downto 8) <= not I_SWI(15 downto 8); + +end syn; diff --git a/rtl/sys_gen/tst_snhumanio/nexys2/Makefile b/rtl/sys_gen/tst_snhumanio/nexys2/Makefile index cf224cad..25c1ed7d 100644 --- a/rtl/sys_gen/tst_snhumanio/nexys2/Makefile +++ b/rtl/sys_gen/tst_snhumanio/nexys2/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -7,7 +7,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make/xflow_default_nexys2.mk +include $(RETROBASE)/rtl/make_ise/xflow_default_nexys2.mk # .PHONY : all clean # @@ -18,8 +18,8 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make/generic_xflow.mk -include $(RETROBASE)/rtl/make/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_snhumanio/nexys2/sys_conf.vhd b/rtl/sys_gen/tst_snhumanio/nexys2/sys_conf.vhd index e3a2b939..b86d6409 100644 --- a/rtl/sys_gen/tst_snhumanio/nexys2/sys_conf.vhd +++ b/rtl/sys_gen/tst_snhumanio/nexys2/sys_conf.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf.vhd 410 2011-09-18 11:23:09Z mueller $ +-- $Id: sys_conf.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Definitions for sys_tst_snhumanio_n2 (for synthesis) -- -- Dependencies: - --- Tool versions: xst 13.1; ghdl 0.29 +-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-09-17 410 1.0 Initial version diff --git a/rtl/sys_gen/tst_snhumanio/nexys2/sys_tst_snhumanio_n2.vhd b/rtl/sys_gen/tst_snhumanio/nexys2/sys_tst_snhumanio_n2.vhd index 0571b174..ba5a7931 100644 --- a/rtl/sys_gen/tst_snhumanio/nexys2/sys_tst_snhumanio_n2.vhd +++ b/rtl/sys_gen/tst_snhumanio/nexys2/sys_tst_snhumanio_n2.vhd @@ -1,4 +1,4 @@ --- $Id: sys_tst_snhumanio_n2.vhd 444 2011-12-25 10:04:58Z mueller $ +-- $Id: sys_tst_snhumanio_n2.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -23,7 +23,7 @@ -- Test bench: - -- -- Target Devices: generic --- Tool versions: xst 13.1; ghdl 0.29 +-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri diff --git a/rtl/sys_gen/tst_snhumanio/nexys3/Makefile b/rtl/sys_gen/tst_snhumanio/nexys3/Makefile index 7430a779..1b75a211 100644 --- a/rtl/sys_gen/tst_snhumanio/nexys3/Makefile +++ b/rtl/sys_gen/tst_snhumanio/nexys3/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -7,7 +7,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make/xflow_default_nexys3.mk +include $(RETROBASE)/rtl/make_ise/xflow_default_nexys3.mk # .PHONY : all clean # @@ -18,8 +18,8 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make/generic_xflow.mk -include $(RETROBASE)/rtl/make/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_snhumanio/nexys3/sys_conf.vhd b/rtl/sys_gen/tst_snhumanio/nexys3/sys_conf.vhd index adf7372a..6f751454 100644 --- a/rtl/sys_gen/tst_snhumanio/nexys3/sys_conf.vhd +++ b/rtl/sys_gen/tst_snhumanio/nexys3/sys_conf.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf.vhd 433 2011-11-27 22:04:39Z mueller $ +-- $Id: sys_conf.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Definitions for sys_tst_snhumanio_n3 (for synthesis) -- -- Dependencies: - --- Tool versions: xst 13.1; ghdl 0.29 +-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-11-27 433 1.0 Initial version diff --git a/rtl/sys_gen/tst_snhumanio/nexys3/sys_tst_snhumanio_n3.vhd b/rtl/sys_gen/tst_snhumanio/nexys3/sys_tst_snhumanio_n3.vhd index c038b99d..0b58e376 100644 --- a/rtl/sys_gen/tst_snhumanio/nexys3/sys_tst_snhumanio_n3.vhd +++ b/rtl/sys_gen/tst_snhumanio/nexys3/sys_tst_snhumanio_n3.vhd @@ -1,4 +1,4 @@ --- $Id: sys_tst_snhumanio_n3.vhd 433 2011-11-27 22:04:39Z mueller $ +-- $Id: sys_tst_snhumanio_n3.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -23,7 +23,7 @@ -- Test bench: - -- -- Target Devices: generic --- Tool versions: xst 13.1; ghdl 0.29 +-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri @@ -33,7 +33,7 @@ -- Date Rev Version Comment -- 2011-11-27 433 1.0 Initial version ------------------------------------------------------------------------------ --- Usage of Nexys 2 Switches, Buttons, LEDs: +-- Usage of Nexys 3 Switches, Buttons, LEDs: -- library ieee; diff --git a/rtl/sys_gen/tst_snhumanio/nexys4/.cvsignore b/rtl/sys_gen/tst_snhumanio/nexys4/.cvsignore new file mode 100644 index 00000000..bcfb2aa7 --- /dev/null +++ b/rtl/sys_gen/tst_snhumanio/nexys4/.cvsignore @@ -0,0 +1,7 @@ +.Xil +project_mflow +*.jou +*.log +*.rpt +*.dcp +*.dep_* diff --git a/rtl/sys_gen/tst_snhumanio/nexys4/Makefile b/rtl/sys_gen/tst_snhumanio/nexys4/Makefile new file mode 100644 index 00000000..c5741c41 --- /dev/null +++ b/rtl/sys_gen/tst_snhumanio/nexys4/Makefile @@ -0,0 +1,26 @@ +# $Id: Makefile 646 2015-02-15 12:04:55Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2015-01-31 640 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +include $(RETROBASE)/rtl/make_viv/viv_default_nexys4.mk +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : viv_clean + rm -f $(VBOM_all:.vbom=.ucf) +# +#---- +# +include $(RETROBASE)/rtl/make_viv/generic_vivado.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +endif +# diff --git a/rtl/sys_gen/tst_snhumanio/nexys4/sys_conf.vhd b/rtl/sys_gen/tst_snhumanio/nexys4/sys_conf.vhd new file mode 100644 index 00000000..36f0e08a --- /dev/null +++ b/rtl/sys_gen/tst_snhumanio/nexys4/sys_conf.vhd @@ -0,0 +1,35 @@ +-- $Id: sys_conf.vhd 640 2015-02-01 09:56:53Z mueller $ +-- +-- Copyright 2015- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_snhumanio_n4 (for synthesis) +-- +-- Dependencies: - +-- Tool versions: viv 2014.4; ghdl 0.31 +-- Revision History: +-- Date Rev Version Comment +-- 2015-01-31 640 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + +end package sys_conf; + diff --git a/rtl/sys_gen/tst_snhumanio/nexys4/sys_tst_snhumanio_n4.vbom b/rtl/sys_gen/tst_snhumanio/nexys4/sys_tst_snhumanio_n4.vbom new file mode 100644 index 00000000..d572729f --- /dev/null +++ b/rtl/sys_gen/tst_snhumanio/nexys4/sys_tst_snhumanio_n4.vbom @@ -0,0 +1,13 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/genlib/genlib.vhd +../../../bplib/bpgen/bpgenlib.vbom +${sys_conf := sys_conf.vhd} +# components +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/sn_humanio.vbom +../tst_snhumanio.vbom +# design +sys_tst_snhumanio_n4.vhd +@xdc:../../../bplib/nexys4/nexys4_pclk.xdc +@xdc:../../../bplib/nexys4/nexys4_pins.xdc diff --git a/rtl/sys_gen/tst_snhumanio/nexys4/sys_tst_snhumanio_n4.vhd b/rtl/sys_gen/tst_snhumanio/nexys4/sys_tst_snhumanio_n4.vhd new file mode 100644 index 00000000..549b0585 --- /dev/null +++ b/rtl/sys_gen/tst_snhumanio/nexys4/sys_tst_snhumanio_n4.vhd @@ -0,0 +1,142 @@ +-- $Id: sys_tst_snhumanio_n4.vhd 643 2015-02-07 17:41:53Z mueller $ +-- +-- Copyright 2015- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_tst_snhumanio_n4 - syn +-- Description: snhumanio tester design for nexys4 +-- +-- Dependencies: vlib/genlib/clkdivce +-- bplib/bpgen/sn_humanio +-- tst_snhumanio +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: viv 2014.4; ghdl 0.31 +-- +-- Synthesized: +-- Date Rev viv Target flop lutl lutm bram slic +-- 2015-01-31 640 2014.4 xc7a100t-1 154 133 0 0 56 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2015-02-06 643 1.1 factor out memory +-- 2015-02-01 641 1.0.1 separate I_BTNRST_N +-- 2015-01-31 640 1.0 Initial version +------------------------------------------------------------------------------ +-- Usage of Nexys 4 Switches, Buttons, LEDs: +-- + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.genlib.all; +use work.bpgenlib.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_tst_snhumanio_n4 is -- top level + -- implements nexys4_aif + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + O_RTS_N : out slbit; -- rx rts (board view; act.low) + I_CTS_N : in slbit; -- tx cts (board view; act.low) + I_SWI : in slv16; -- n4 switches + I_BTN : in slv5; -- n4 buttons + I_BTNRST_N : in slbit; -- n4 reset button + O_LED : out slv16; -- n4 leds + O_RGBLED0 : out slv3; -- n4 rgb-led 0 + O_RGBLED1 : out slv3; -- n4 rgb-led 1 + O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8 -- 7 segment disp: segments (act.low) + ); +end sys_tst_snhumanio_n4; + +architecture syn of sys_tst_snhumanio_n4 is + + signal CLK : slbit := '0'; + + signal SWI : slv8 := (others=>'0'); + signal BTN : slv5 := (others=>'0'); + signal LED : slv8 := (others=>'0'); + signal DSP_DAT : slv16 := (others=>'0'); + signal DSP_DP : slv4 := (others=>'0'); + + signal RESET : slbit := '0'; + signal CE_MSEC : slbit := '0'; + +begin + + RESET <= '0'; -- so far not used + + CLK <= I_CLK100; + + CLKDIV : clkdivce + generic map ( + CDUWIDTH => 7, + USECDIV => 100, + MSECDIV => 1000) + port map ( + CLK => CLK, + CE_USEC => open, + CE_MSEC => CE_MSEC + ); + + HIO : sn_humanio + generic map ( + BWIDTH => 5, + DEBOUNCE => sys_conf_hio_debounce) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI(7 downto 0), + I_BTN => I_BTN, + O_LED => O_LED(7 downto 0), + O_ANO_N => O_ANO_N(3 downto 0), + O_SEG_N => O_SEG_N + ); + + HIOTEST : entity work.tst_snhumanio + generic map ( + BWIDTH => 5) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP + ); + + O_TXD <= I_RXD; + O_RTS_N <= I_CTS_N; + + O_LED(15 downto 8) <= not I_SWI(15 downto 8); + O_ANO_N(7 downto 4) <= (others=>'1'); + + O_RGBLED0 <= (others=>'0'); + O_RGBLED1 <= (others=>not I_BTNRST_N); + +end syn; diff --git a/rtl/sys_gen/tst_snhumanio/s3board/Makefile b/rtl/sys_gen/tst_snhumanio/s3board/Makefile index cb71cff2..39047041 100644 --- a/rtl/sys_gen/tst_snhumanio/s3board/Makefile +++ b/rtl/sys_gen/tst_snhumanio/s3board/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -7,7 +7,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make/xflow_default_s3board.mk +include $(RETROBASE)/rtl/make_ise/xflow_default_s3board.mk # .PHONY : all clean # @@ -18,8 +18,8 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make/generic_xflow.mk -include $(RETROBASE)/rtl/make/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/tst_snhumanio/s3board/sys_conf.vhd b/rtl/sys_gen/tst_snhumanio/s3board/sys_conf.vhd index 9bf198e5..2f3c6415 100644 --- a/rtl/sys_gen/tst_snhumanio/s3board/sys_conf.vhd +++ b/rtl/sys_gen/tst_snhumanio/s3board/sys_conf.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf.vhd 410 2011-09-18 11:23:09Z mueller $ +-- $Id: sys_conf.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Definitions for sys_tst_snhumanio_n2 (for synthesis) -- -- Dependencies: - --- Tool versions: xst 13.1; ghdl 0.29 +-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-09-18 410 1.0 Initial version diff --git a/rtl/sys_gen/tst_snhumanio/s3board/sys_tst_snhumanio_s3.vhd b/rtl/sys_gen/tst_snhumanio/s3board/sys_tst_snhumanio_s3.vhd index b45efa24..f862211b 100644 --- a/rtl/sys_gen/tst_snhumanio/s3board/sys_tst_snhumanio_s3.vhd +++ b/rtl/sys_gen/tst_snhumanio/s3board/sys_tst_snhumanio_s3.vhd @@ -1,4 +1,4 @@ --- $Id: sys_tst_snhumanio_s3.vhd 419 2011-11-01 19:42:30Z mueller $ +-- $Id: sys_tst_snhumanio_s3.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -23,7 +23,7 @@ -- Test bench: - -- -- Target Devices: generic --- Tool versions: xst 13.1; ghdl 0.29 +-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri diff --git a/rtl/sys_gen/tst_snhumanio/tst_snhumanio.vhd b/rtl/sys_gen/tst_snhumanio/tst_snhumanio.vhd index 2331ab78..53218d1e 100644 --- a/rtl/sys_gen/tst_snhumanio/tst_snhumanio.vhd +++ b/rtl/sys_gen/tst_snhumanio/tst_snhumanio.vhd @@ -1,4 +1,4 @@ --- $Id: tst_snhumanio.vhd 416 2011-10-15 13:32:57Z mueller $ +-- $Id: tst_snhumanio.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -19,7 +19,7 @@ -- Test bench: - -- -- Target Devices: generic --- Tool versions: xst 13.1; ghdl 0.29 +-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/sys_gen/w11a/basys3/.cvsignore b/rtl/sys_gen/w11a/basys3/.cvsignore new file mode 100644 index 00000000..bcfb2aa7 --- /dev/null +++ b/rtl/sys_gen/w11a/basys3/.cvsignore @@ -0,0 +1,7 @@ +.Xil +project_mflow +*.jou +*.log +*.rpt +*.dcp +*.dep_* diff --git a/rtl/sys_gen/w11a/basys3/Makefile b/rtl/sys_gen/w11a/basys3/Makefile new file mode 100644 index 00000000..13065b8e --- /dev/null +++ b/rtl/sys_gen/w11a/basys3/Makefile @@ -0,0 +1,25 @@ +# $Id: Makefile 646 2015-02-15 12:04:55Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2015-02-08 644 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +include $(RETROBASE)/rtl/make_viv/viv_default_basys3.mk +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : viv_clean +# +#---- +# +include $(RETROBASE)/rtl/make_viv/generic_vivado.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +endif +# diff --git a/rtl/sys_gen/w11a/basys3/sys_conf.vhd b/rtl/sys_gen/w11a/basys3/sys_conf.vhd new file mode 100644 index 00000000..f159ab07 --- /dev/null +++ b/rtl/sys_gen/w11a/basys3/sys_conf.vhd @@ -0,0 +1,82 @@ +-- $Id: sys_conf.vhd 649 2015-02-21 21:10:16Z mueller $ +-- +-- Copyright 2015- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_w11a_b3 (for synthesis) +-- +-- Dependencies: - +-- Tool versions: viv 2014.4; ghdl 0.31 +-- Revision History: +-- Date Rev Version Comment +-- 2015-02-08 644 1.0 Initial version (derived from _n4 version) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz + constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + -- single clock design, clkser = clksys + constant sys_conf_clkser_vcodivide : positive := sys_conf_clksys_vcodivide; + constant sys_conf_clkser_vcomultiply : positive := sys_conf_clksys_vcomultiply; + constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide; + constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype; + + constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud + + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + + constant sys_conf_memctl_mawidth : positive := 4; + constant sys_conf_memctl_nblock : positive := 11; + + -- sys_conf_mem_losize is highest 64 byte MMU block number + -- the bram_memcnt uses 4*4kB memory blocks => 1 MEM block = 256 MMU blocks + constant sys_conf_mem_losize : integer := 256*sys_conf_memctl_nblock-1; + + constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled + + -- derived constants + + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_clkser : integer := + ((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) / + sys_conf_clkser_outdivide; + constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000; + + constant sys_conf_ser2rri_cdinit : integer := + (sys_conf_clkser/sys_conf_ser2rri_defbaud)-1; + +end package sys_conf; + +-- Note: mem_losize holds 16 MSB of the PA of the addressable memory +-- 2 211 111 111 110 000 000 000 +-- 1 098 765 432 109 876 543 210 +-- +-- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte +-- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte +-- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte +-- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte +-- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte +-- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte +-- upper 256 kB excluded for 11/70 UB diff --git a/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vbom b/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vbom new file mode 100644 index 00000000..174a0725 --- /dev/null +++ b/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vbom @@ -0,0 +1,37 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/xlib/xlib.vhd +../../../vlib/genlib/genlib.vhd +../../../vlib/serport/serportlib.vbom +../../../vlib/rbus/rblib.vhd +../../../vlib/rlink/rlinklib.vbom +../../../bplib/bpgen/bpgenlib.vbom +../../../bplib/bpgen/bpgenrbuslib.vbom +../../../ibus/iblib.vhd +../../../ibus/ibdlib.vhd +../../../w11a/pdp11.vhd +sys_conf = sys_conf.vhd +# components +[xst,vsyn,isim,vsim]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom +[ghdl]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/bp_rs232_2line_iob.vbom +../../../bplib/bpgen/sn_humanio_rbus.vbom +../../../vlib/rlink/rlink_sp1c.vbom +../../../vlib/rbus/rb_sres_or_3.vbom +../../../w11a/pdp11_core_rbus.vbom +../../../w11a/pdp11_core.vbom +../../../w11a/pdp11_cache.vbom +../../../w11a/pdp11_mem70.vbom +../../../w11a/pdp11_bram_memctl.vbom +../../../ibus/ib_sres_or_2.vbom +../../../ibus/ibdr_maxisys.vbom +../../../vlib/rlink/ioleds_sp1c.vbom +../../../w11a/pdp11_statleds.vbom +../../../w11a/pdp11_ledmux.vbom +../../../w11a/pdp11_dspmux.vbom +[sim]../../../w11a/pdp11_tmu_sb.vbom +# design +sys_w11a_b3.vhd +@xdc:../../../bplib/basys3/basys3_pclk.xdc +@xdc:../../../bplib/basys3/basys3_pins.xdc diff --git a/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd b/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd new file mode 100644 index 00000000..7abd95e7 --- /dev/null +++ b/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd @@ -0,0 +1,484 @@ +-- $Id: sys_w11a_b3.vhd 652 2015-02-28 12:18:08Z mueller $ +-- +-- Copyright 2015- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_w11a_b3 - syn +-- Description: w11a test design for basys3 +-- +-- Dependencies: vlib/xlib/s7_cmt_sfs +-- vlib/genlib/clkdivce +-- bplib/bpgen/bp_rs232_2line_iob +-- bplib/bpgen/sn_humanio_rbus +-- vlib/rlink/rlink_sp1c +-- vlib/rbus/rb_sres_or_3 +-- w11a/pdp11_core_rbus +-- w11a/pdp11_core +-- w11a/pdp11_cache +-- w11a/pdp11_mem70 +-- w11a/pdp11_bram_memctl +-- ibus/ib_sres_or_2 +-- ibus/ibdr_maxisys +-- vlib/rlink/ioleds_sp1c +-- w11a/pdp11_statleds +-- w11a/pdp11_ledmux +-- w11a/pdp11_dspmux +-- w11a/pdp11_tmu_sb [sim only] +-- +-- Test bench: tb/tb_sys_w11a_b3 +-- +-- Target Devices: generic +-- Tool versions: viv 2014.4; ghdl 0.31 +-- +-- Synthesized: +-- Date Rev viv Target flop lutl lutm bram slic +-- 2015-02-21 649 2014.4 xc7a35t-1 1637 3767 146 47.5 1195 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2015-02-21 649 1.1 use ioleds_sp1c,pdp11_(statleds,ledmux,dspmux) +-- 2015-02-08 644 1.0 Initial version (derived from sys_w11a_n4) +------------------------------------------------------------------------------ +-- +-- w11a test design for basys3 +-- w11a + rlink + serport +-- +-- Usage of Basys 3 Switches, Buttons, LEDs +-- +-- SWI(15:6): no function (only connected to sn_humanio_rbus) +-- SWI(5:4): select DSP +-- 00 abclkdiv & abclkdiv_f +-- 01 PC +-- 10 DISPREG +-- 11 DR emulation +-- SWI(3): select LED display +-- 0 overall status +-- 1 DR emulation +-- SWI(2): unused-reserved (USB port select) +-- SWI(1): 1 enable XON +-- SWI(0): unused-reserved (serial port select) +-- +-- LEDs if SWI(3) = 1 +-- (15:0) DR emulation; shows R0 during wait like 11/45+70 +-- +-- LEDs if SWI(3) = 0 +-- (7) MEM_ACT_W +-- (6) MEM_ACT_R +-- (5) cmdbusy (all rlink access, mostly rdma) +-- (4:0) if cpugo=1 show cpu mode activity +-- (4) kernel mode, pri>0 +-- (3) kernel mode, pri=0 +-- (2) kernel mode, wait +-- (1) supervisor mode +-- (0) user mode +-- if cpugo=0 shows cpurust +-- (4) '1' +-- (3:0) cpurust code +-- +-- DSP(7:4) shows abclkdiv & abclkdiv_f or PS depending on SWI(4) +-- DSP(3:0) shows DISPREG +-- DP(3:0) shows IO activity +-- (3) not SER_MONI.txok (shows tx back preasure) +-- (2) SER_MONI.txact (shows tx activity) +-- (1) not SER_MONI.rxok (shows rx back preasure) +-- (0) SER_MONI.rxact (shows rx activity) +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.genlib.all; +use work.serportlib.all; +use work.rblib.all; +use work.rlinklib.all; +use work.bpgenlib.all; +use work.bpgenrbuslib.all; +use work.iblib.all; +use work.ibdlib.all; +use work.pdp11.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_w11a_b3 is -- top level + -- implements basys3_aif + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv16; -- b3 switches + I_BTN : in slv5; -- b3 buttons + O_LED : out slv16; -- b3 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8 -- 7 segment disp: segments (act.low) + ); +end sys_w11a_b3; + +architecture syn of sys_w11a_b3 is + + signal CLK : slbit := '0'; + + signal RXD : slbit := '1'; + signal TXD : slbit := '0'; + + signal SWI : slv16 := (others=>'0'); + signal BTN : slv5 := (others=>'0'); + signal LED : slv16 := (others=>'0'); + signal DSP_DAT : slv16 := (others=>'0'); + signal DSP_DP : slv4 := (others=>'0'); + + signal RB_LAM : slv16 := (others=>'0'); + signal RB_STAT : slv4 := (others=>'0'); + + signal SER_MONI : serport_moni_type := serport_moni_init; + + signal RB_MREQ : rb_mreq_type := rb_mreq_init; + signal RB_SRES : rb_sres_type := rb_sres_init; + signal RB_SRES_CPU : rb_sres_type := rb_sres_init; + signal RB_SRES_IBD : rb_sres_type := rb_sres_init; + signal RB_SRES_HIO : rb_sres_type := rb_sres_init; + + signal RESET : slbit := '0'; + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal CPU_RESET : slbit := '0'; + signal CP_CNTL : cp_cntl_type := cp_cntl_init; + signal CP_ADDR : cp_addr_type := cp_addr_init; + signal CP_DIN : slv16 := (others=>'0'); + signal CP_STAT : cp_stat_type := cp_stat_init; + signal CP_DOUT : slv16 := (others=>'0'); + + signal EI_PRI : slv3 := (others=>'0'); + signal EI_VECT : slv9_2 := (others=>'0'); + signal EI_ACKM : slbit := '0'; + + signal EM_MREQ : em_mreq_type := em_mreq_init; + signal EM_SRES : em_sres_type := em_sres_init; + + signal HM_ENA : slbit := '0'; + signal MEM70_FMISS : slbit := '0'; + signal CACHE_FMISS : slbit := '0'; + signal CACHE_CHIT : slbit := '0'; + + signal MEM_REQ : slbit := '0'; + signal MEM_WE : slbit := '0'; + signal MEM_BUSY : slbit := '0'; + signal MEM_ACK_R : slbit := '0'; + signal MEM_ACT_R : slbit := '0'; + signal MEM_ACT_W : slbit := '0'; + signal MEM_ADDR : slv20 := (others=>'0'); + signal MEM_BE : slv4 := (others=>'0'); + signal MEM_DI : slv32 := (others=>'0'); + signal MEM_DO : slv32 := (others=>'0'); + + signal BRESET : slbit := '0'; + signal IB_MREQ : ib_mreq_type := ib_mreq_init; + signal IB_SRES : ib_sres_type := ib_sres_init; + + signal IB_SRES_MEM70 : ib_sres_type := ib_sres_init; + signal IB_SRES_IBDR : ib_sres_type := ib_sres_init; + + signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init; + signal DM_STAT_VM : dm_stat_vm_type := dm_stat_vm_init; + signal DM_STAT_CO : dm_stat_co_type := dm_stat_co_init; + signal DM_STAT_SY : dm_stat_sy_type := dm_stat_sy_init; + + signal DISPREG : slv16 := (others=>'0'); + signal STATLEDS : slv8 := (others=>'0'); + signal ABCLKDIV : slv16 := (others=>'0'); + + constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0004: 1111 1110 1111 00xx + constant rbaddr_ibus0 : slv16 := x"4000"; -- 4000/1000: 0100 xxxx xxxx xxxx + constant rbaddr_core0 : slv16 := x"0000"; -- 0000/0020: 0000 0000 000x xxxx + +begin + + assert (sys_conf_clksys mod 1000000) = 0 + report "assert sys_conf_clksys on MHz grid" + severity failure; + + GEN_CLKSYS : s7_cmt_sfs + generic map ( + VCO_DIVIDE => sys_conf_clksys_vcodivide, + VCO_MULTIPLY => sys_conf_clksys_vcomultiply, + OUT_DIVIDE => sys_conf_clksys_outdivide, + CLKIN_PERIOD => 10.0, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clksys_gentype) + port map ( + CLKIN => I_CLK100, + CLKFX => CLK, + LOCKED => open + ); + + CLKDIV : clkdivce + generic map ( + CDUWIDTH => 7, + USECDIV => sys_conf_clksys_mhz, + MSECDIV => 1000) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC + ); + + IOB_RS232 : bp_rs232_2line_iob + port map ( + CLK => CLK, + RXD => RXD, + TXD => TXD, + I_RXD => I_RXD, + O_TXD => O_TXD + ); + + HIO : sn_humanio_rbus + generic map ( + SWIDTH => 16, + BWIDTH => 5, + LWIDTH => 16, + DCWIDTH => 2, + DEBOUNCE => sys_conf_hio_debounce, + RB_ADDR => rbaddr_hio) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_HIO, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + RLINK : rlink_sp1c + generic map ( + BTOWIDTH => 7, -- 128 cycles access timeout + RTAWIDTH => 12, + SYSID => (others=>'0'), + IFAWIDTH => 5, -- 32 word input fifo + OFAWIDTH => 5, -- 32 word output fifo + ENAPIN_RLMON => sbcntl_sbf_rlmon, + ENAPIN_RBMON => sbcntl_sbf_rbmon, + CDWIDTH => 13, + CDINIT => sys_conf_ser2rri_cdinit) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + CE_INT => CE_MSEC, + RESET => RESET, + ENAXON => SWI(1), + ENAESC => SWI(1), + RXSD => RXD, + TXSD => TXD, + CTS_N => '0', + RTS_N => open, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT, + RL_MONI => open, + SER_MONI => SER_MONI + ); + + RB_SRES_OR : rb_sres_or_3 + port map ( + RB_SRES_1 => RB_SRES_CPU, + RB_SRES_2 => RB_SRES_IBD, + RB_SRES_3 => RB_SRES_HIO, + RB_SRES_OR => RB_SRES + ); + + RB2CP : pdp11_core_rbus + generic map ( + RB_ADDR_CORE => rbaddr_core0, + RB_ADDR_IBUS => rbaddr_ibus0) + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_CPU, + RB_STAT => RB_STAT, + RB_LAM => RB_LAM(0), + CPU_RESET => CPU_RESET, + CP_CNTL => CP_CNTL, + CP_ADDR => CP_ADDR, + CP_DIN => CP_DIN, + CP_STAT => CP_STAT, + CP_DOUT => CP_DOUT + ); + + W11A : pdp11_core + port map ( + CLK => CLK, + RESET => CPU_RESET, + CP_CNTL => CP_CNTL, + CP_ADDR => CP_ADDR, + CP_DIN => CP_DIN, + CP_STAT => CP_STAT, + CP_DOUT => CP_DOUT, + EI_PRI => EI_PRI, + EI_VECT => EI_VECT, + EI_ACKM => EI_ACKM, + EM_MREQ => EM_MREQ, + EM_SRES => EM_SRES, + BRESET => BRESET, + IB_MREQ_M => IB_MREQ, + IB_SRES_M => IB_SRES, + DM_STAT_DP => DM_STAT_DP, + DM_STAT_VM => DM_STAT_VM, + DM_STAT_CO => DM_STAT_CO + ); + + CACHE: pdp11_cache + port map ( + CLK => CLK, + GRESET => CPU_RESET, + EM_MREQ => EM_MREQ, + EM_SRES => EM_SRES, + FMISS => CACHE_FMISS, + CHIT => CACHE_CHIT, + MEM_REQ => MEM_REQ, + MEM_WE => MEM_WE, + MEM_BUSY => MEM_BUSY, + MEM_ACK_R => MEM_ACK_R, + MEM_ADDR => MEM_ADDR, + MEM_BE => MEM_BE, + MEM_DI => MEM_DI, + MEM_DO => MEM_DO + ); + + MEM70: pdp11_mem70 + port map ( + CLK => CLK, + CRESET => BRESET, + HM_ENA => HM_ENA, + HM_VAL => CACHE_CHIT, + CACHE_FMISS => MEM70_FMISS, + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_MEM70 + ); + + HM_ENA <= EM_SRES.ack_r or EM_SRES.ack_w; + CACHE_FMISS <= MEM70_FMISS or sys_conf_cache_fmiss; + + BRAM_CTL: pdp11_bram_memctl + generic map ( + MAWIDTH => sys_conf_memctl_mawidth, + NBLOCK => sys_conf_memctl_nblock) + port map ( + CLK => CLK, + RESET => CPU_RESET, + REQ => MEM_REQ, + WE => MEM_WE, + BUSY => MEM_BUSY, + ACK_R => MEM_ACK_R, + ACK_W => open, + ACT_R => MEM_ACT_R, + ACT_W => MEM_ACT_W, + ADDR => MEM_ADDR, + BE => MEM_BE, + DI => MEM_DI, + DO => MEM_DO + ); + + IB_SRES_OR : ib_sres_or_2 + port map ( + IB_SRES_1 => IB_SRES_MEM70, + IB_SRES_2 => IB_SRES_IBDR, + IB_SRES_OR => IB_SRES + ); + + IBDR_SYS : ibdr_maxisys + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + RESET => CPU_RESET, + BRESET => BRESET, + RB_LAM => RB_LAM(15 downto 1), + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_IBDR, + EI_ACKM => EI_ACKM, + EI_PRI => EI_PRI, + EI_VECT => EI_VECT, + DISPREG => DISPREG + ); + + LED_IO : ioleds_sp1c + port map ( + SER_MONI => SER_MONI, + IOLEDS => DSP_DP + ); + + LED_CPU : pdp11_statleds + port map ( + MEM_ACT_R => MEM_ACT_R, + MEM_ACT_W => MEM_ACT_W, + CP_STAT => CP_STAT, + DM_STAT_DP => DM_STAT_DP, + STATLEDS => STATLEDS + ); + + LED_MUX : pdp11_ledmux + generic map ( + LWIDTH => LED'length) + port map ( + SEL => SWI(3), + STATLEDS => STATLEDS, + DM_STAT_DP => DM_STAT_DP, + LED => LED + ); + + ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f; + + DSP_MUX : pdp11_dspmux + generic map ( + DCWIDTH => 2) + port map ( + SEL => SWI(5 downto 4), + ABCLKDIV => ABCLKDIV, + DM_STAT_DP => DM_STAT_DP, + DISPREG => DISPREG, + DSP_DAT => DSP_DAT + ); + +-- synthesis translate_off + DM_STAT_SY.emmreq <= EM_MREQ; + DM_STAT_SY.emsres <= EM_SRES; + DM_STAT_SY.chit <= CACHE_CHIT; + + TMU : pdp11_tmu_sb + generic map ( + ENAPIN => 13) + port map ( + CLK => CLK, + DM_STAT_DP => DM_STAT_DP, + DM_STAT_VM => DM_STAT_VM, + DM_STAT_CO => DM_STAT_CO, + DM_STAT_SY => DM_STAT_SY + ); +-- synthesis translate_on + +end syn; diff --git a/rtl/sys_gen/w11a/basys3/tb/.cvsignore b/rtl/sys_gen/w11a/basys3/tb/.cvsignore new file mode 100644 index 00000000..9229a836 --- /dev/null +++ b/rtl/sys_gen/w11a/basys3/tb/.cvsignore @@ -0,0 +1,6 @@ +tb_w11a_b3 +tb_w11a_b3_[so]sim +rlink_cext_fifo_rx +rlink_cext_fifo_tx +rlink_cext_conf +*.dep_* diff --git a/rtl/sys_gen/w11a/basys3/tb/Makefile b/rtl/sys_gen/w11a/basys3/tb/Makefile new file mode 100644 index 00000000..77d5f2d1 --- /dev/null +++ b/rtl/sys_gen/w11a/basys3/tb/Makefile @@ -0,0 +1,30 @@ +# $Id: Makefile 649 2015-02-21 21:10:16Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2015-02-21 649 1.0 Initial version +# +EXE_all = tb_w11a_b3 +# +include $(RETROBASE)/rtl/make_viv/viv_default_basys3.mk +# +.PHONY : all all_ssim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +# +clean : viv_clean ghdl_clean +# +#----- +# +include $(RETROBASE)/rtl/make_viv/generic_vivado.mk +include $(RETROBASE)/rtl/make_viv/generic_ghdl.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(wildcard *.o.dep_ghdl) +endif +# diff --git a/rtl/sys_gen/w11a/basys3/tb/sys_conf_sim.vhd b/rtl/sys_gen/w11a/basys3/tb/sys_conf_sim.vhd new file mode 100644 index 00000000..483c358c --- /dev/null +++ b/rtl/sys_gen/w11a/basys3/tb/sys_conf_sim.vhd @@ -0,0 +1,67 @@ +-- $Id: sys_conf_sim.vhd 649 2015-02-21 21:10:16Z mueller $ +-- +-- Copyright 2015- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_w11a_b3 (for simulation) +-- +-- Dependencies: - +-- Tool versions: viv 2014.4; ghdl 0.31 +-- Revision History: +-- Date Rev Version Comment +-- 2015-02-21 649 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 1; -- vco --- MHz + constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + -- single clock design, clkser = clksys + constant sys_conf_clkser_vcodivide : positive := sys_conf_clksys_vcodivide; + constant sys_conf_clkser_vcomultiply : positive := sys_conf_clksys_vcomultiply; + constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide; + constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype; + + constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim + + constant sys_conf_hio_debounce : boolean := false; -- no debouncers + + constant sys_conf_memctl_mawidth : positive := 4; + constant sys_conf_memctl_nblock : positive := 11; + + -- sys_conf_mem_losize is highest 64 byte MMU block number + -- the bram_memcnt uses 4*4kB memory blocks => 1 MEM block = 256 MMU blocks + constant sys_conf_mem_losize : integer := 256*sys_conf_memctl_nblock-1; + + constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled + + -- derived constants + + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_clkser : integer := + ((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) / + sys_conf_clkser_outdivide; + constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000; + +end package sys_conf; diff --git a/rtl/sys_gen/w11a/basys3/tb/tb_w11a_b3.vbom b/rtl/sys_gen/w11a/basys3/tb/tb_w11a_b3.vbom new file mode 100644 index 00000000..17491049 --- /dev/null +++ b/rtl/sys_gen/w11a/basys3/tb/tb_w11a_b3.vbom @@ -0,0 +1,7 @@ +# configure tb_basys3 with sys_w11a_b3 target; +# use vhdl configure file (tb_w11a_b3.vhd) to allow +# that all configurations will co-exist in work library +${basys3_aif := ../sys_w11a_b3.vbom} +sys_conf = sys_conf_sim.vhd +../../../../bplib/basys3/tb/tb_basys3.vbom +tb_w11a_b3.vhd diff --git a/rtl/sys_gen/w11a/basys3/tb/tb_w11a_b3.vhd b/rtl/sys_gen/w11a/basys3/tb/tb_w11a_b3.vhd new file mode 100644 index 00000000..b941a1e9 --- /dev/null +++ b/rtl/sys_gen/w11a/basys3/tb/tb_w11a_b3.vhd @@ -0,0 +1,35 @@ +-- $Id: tb_w11a_b3.vhd 649 2015-02-21 21:10:16Z mueller $ +-- +-- Copyright 2015- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_w11a_b3 +-- Description: Configuration for tb_w11a_b3 for tb_basys3 +-- +-- Dependencies: sys_w11a_b3 +-- +-- To test: sys_w11a_b3 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2015-02-21 649 1.0 Initial version +------------------------------------------------------------------------------ + +configuration tb_w11a_b3 of tb_basys3 is + + for sim + for all : basys3_aif + use entity work.sys_w11a_b3; + end for; + end for; + +end tb_w11a_b3; diff --git a/rtl/sys_gen/w11a/basys3/tb/tb_w11a_b3_ssim.vbom b/rtl/sys_gen/w11a/basys3/tb/tb_w11a_b3_ssim.vbom new file mode 100644 index 00000000..cc6aea6f --- /dev/null +++ b/rtl/sys_gen/w11a/basys3/tb/tb_w11a_b3_ssim.vbom @@ -0,0 +1,6 @@ +# configure for _*sim case +# Note: this tb uses sys_w11a_b3.vbom in local directory +# (not in .. as usual) to allow a tb specific configure !!! +basys3_aif = sys_w11a_b3_ssim.vhd +tb_w11a_b3.vbom +@top:tb_w11a_b3 diff --git a/rtl/sys_gen/w11a/basys3/tb/tbw.dat b/rtl/sys_gen/w11a/basys3/tb/tbw.dat new file mode 100644 index 00000000..ed5fb2b8 --- /dev/null +++ b/rtl/sys_gen/w11a/basys3/tb/tbw.dat @@ -0,0 +1,6 @@ +# $Id: tbw.dat 649 2015-02-21 21:10:16Z mueller $ +# +[tb_w11a_b3] +rlink_cext_fifo_rx = +rlink_cext_fifo_tx = +rlink_cext_conf = diff --git a/rtl/sys_gen/w11a/nexys2/Makefile b/rtl/sys_gen/w11a/nexys2/Makefile index 495b7f86..fc15f3a3 100644 --- a/rtl/sys_gen/w11a/nexys2/Makefile +++ b/rtl/sys_gen/w11a/nexys2/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 509 2013-04-21 20:46:20Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -9,7 +9,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make/xflow_default_nexys2.mk +include $(RETROBASE)/rtl/make_ise/xflow_default_nexys2.mk FX2_FILE = nexys2_jtag_2fifo_ic.ihx # .PHONY : all clean @@ -26,8 +26,8 @@ sys_w11a_n2.mcs : sys_w11a_n2.bit # #---- # -include $(RETROBASE)/rtl/make/generic_xflow.mk -include $(RETROBASE)/rtl/make/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/w11a/nexys2/sys_conf.vhd b/rtl/sys_gen/w11a/nexys2/sys_conf.vhd index ab4c7f08..ba71559e 100644 --- a/rtl/sys_gen/w11a/nexys2/sys_conf.vhd +++ b/rtl/sys_gen/w11a/nexys2/sys_conf.vhd @@ -1,6 +1,6 @@ --- $Id: sys_conf.vhd 619 2014-12-23 13:17:41Z mueller $ +-- $Id: sys_conf.vhd 647 2015-02-17 22:35:36Z mueller $ -- --- Copyright 2010-2014 by Walter F.J. Mueller +-- Copyright 2010-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -19,6 +19,8 @@ -- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31 -- Revision History: -- Date Rev Version Comment +-- 2015-02-15 647 1.3 drop bram and minisys options +-- 2015-01-04 630 1.2.2 use clksys=54 (no closure after rlink r4 + RL11) -- 2014-12-22 619 1.2.1 add _rbmon_awidth -- 2013-04-21 509 1.2 add fx2 settings -- 2011-11-19 428 1.1.1 use clksys=56 (58 no closure after numeric_std...) @@ -40,7 +42,7 @@ use work.slvtypes.all; package sys_conf is constant sys_conf_clkfx_divide : positive := 25; - constant sys_conf_clkfx_multiply : positive := 28; -- ==> 56 MHz + constant sys_conf_clkfx_multiply : positive := 27; -- ==> 54 MHz constant sys_conf_memctl_read0delay : positive := 3; constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay; @@ -56,15 +58,9 @@ package sys_conf is constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers - constant sys_conf_bram : integer := 0; -- no bram, use cache - constant sys_conf_bram_awidth : integer := 14; -- bram size (16 kB) constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte --constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug) --- constant sys_conf_bram : integer := 1; -- bram only --- constant sys_conf_bram_awidth : integer := 15; -- bram size (32 kB) --- constant sys_conf_mem_losize : integer := 8#000777#; -- 32 kByte - constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled -- derived constants diff --git a/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vbom b/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vbom index ff655560..488ce852 100644 --- a/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vbom +++ b/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vbom @@ -16,26 +16,26 @@ ../../../w11a/pdp11.vhd sys_conf = sys_conf.vhd # components -[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom +[xst,vsyn,isim,vsim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom [ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom ../../../vlib/genlib/clkdivce.vbom ../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom ../../../bplib/bpgen/sn_humanio_rbus.vbom ../../../bplib/fx2rlink/rlink_sp1c_fx2.vbom -../../../bplib/fx2rlink/ioleds_sp1c_fx2.vbom ../../../vlib/rbus/rb_sres_or_4.vbom ../../../vlib/rbus/rbd_rbmon.vbom ../../../w11a/pdp11_core_rbus.vbom ../../../w11a/pdp11_core.vbom -../../../w11a/pdp11_bram.vbom -../../../bplib/nxcramlib/nx_cram_dummy.vbom ../../../w11a/pdp11_cache.vbom ../../../w11a/pdp11_mem70.vbom ../../../bplib/nxcramlib/nx_cram_memctl_as.vbom ../../../ibus/ib_sres_or_2.vbom -../../../ibus/ibdr_minisys.vbom ../../../ibus/ibdr_maxisys.vbom -[ghdl,isim]../../../w11a/pdp11_tmu_sb.vbom +../../../bplib/fx2rlink/ioleds_sp1c_fx2.vbom +../../../w11a/pdp11_statleds.vbom +../../../w11a/pdp11_ledmux.vbom +../../../w11a/pdp11_dspmux.vbom +[sim]../../../w11a/pdp11_tmu_sb.vbom # design sys_w11a_n2.vhd @ucf_cpp: sys_w11a_n2.ucf diff --git a/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd b/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd index 9493751b..d8a01d86 100644 --- a/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd +++ b/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd @@ -1,6 +1,6 @@ --- $Id: sys_w11a_n2.vhd 620 2014-12-25 10:48:35Z mueller $ +-- $Id: sys_w11a_n2.vhd 652 2015-02-28 12:18:08Z mueller $ -- --- Copyright 2010-2014 by Walter F.J. Mueller +-- Copyright 2010-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -20,19 +20,19 @@ -- bplib/bpgen/bp_rs232_2l4l_iob -- bplib/bpgen/sn_humanio_rbus -- bplib/fx2rlink/rlink_sp1c_fx2 --- bplib/fx2rlink/ioleds_sp1c_fx2 -- vlib/rbus/rb_sres_or_4 -- vlib/rbus/rbd_rbmon -- w11a/pdp11_core_rbus -- w11a/pdp11_core --- w11a/pdp11_bram --- vlib/nxcramlib/nx_cram_dummy -- w11a/pdp11_cache -- w11a/pdp11_mem70 -- bplib/nxcramlib/nx_cram_memctl_as -- ibus/ib_sres_or_2 --- ibus/ibdr_minisys -- ibus/ibdr_maxisys +-- bplib/fx2rlink/ioleds_sp1c_fx2 +-- w11a/pdp11_statleds +-- w11a/pdp11_ledmux +-- w11a/pdp11_dspmux -- w11a/pdp11_tmu_sb [sim only] -- -- Test bench: tb/tb_sys_w11a_n2 @@ -42,6 +42,7 @@ -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri +-- 2015-02-21 649 14.7 131013 xc3s1200e-4 1903 5512 382 3483 ok: +RL11 -- 2014-12-22 619 14.7 131013 xc3s1200e-4 1828 5131 366 3263 ok: +rbmon -- 2014-12-20 614 14.7 131013 xc3s1200e-4 1714 4896 366 3125 ok: -RL11,rlv4 -- 2014-06-08 561 14.7 131013 xc3s1200e-4 1626 4821 360 3052 ok: +RL11 @@ -71,6 +72,8 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2015-02-21 649 1.7.1 use ioleds_sp1c,pdp11_(statleds,ledmux,dspmux) +-- 2015-02-15 647 1.7 drop bram and minisys options -- 2014-12-24 620 1.6.2 relocate ibus window and hio rbus address -- 2014-12-22 619 1.6.1 add rbus monitor rbd_rbmon -- 2014-08-28 588 1.6 use new rlink v4 iface generics and 4 bit STAT @@ -108,25 +111,37 @@ -- -- Usage of Nexys 2 Switches, Buttons, LEDs: -- --- SWI(7:3): no function (only connected to sn_humanio_rbus) +-- SWI(7:6): no function (only connected to sn_humanio_rbus) +-- (5:4): select DSP +-- 00 abclkdiv & abclkdiv_f +-- 01 PC +-- 10 DISPREG +-- 11 DR emulation +-- (3): select LED display +-- 0 overall status +-- 1 DR emulation -- (2) 0 -> int/ext RS242 port for rlink -- 1 -> use USB interface for rlink -- (1): 1 enable XON -- (0): 0 -> main board RS232 port -- 1 -> Pmod B/top RS232 port --- --- LED(7) MEM_ACT_W --- (6) MEM_ACT_R --- (5) cmdbusy (all rlink access, mostly rdma) --- (4:0): if cpugo=1 show cpu mode activity +-- +-- LEDs if SWI(3) = 1 +-- (7:0) DR emulation; shows R0(lower 8 bits) during wait like 11/45+70 +-- +-- LEDs if SWI(3) = 0 +-- (7) MEM_ACT_W +-- (6) MEM_ACT_R +-- (5) cmdbusy (all rlink access, mostly rdma) +-- (4:0) if cpugo=1 show cpu mode activity -- (4) kernel mode, pri>0 -- (3) kernel mode, pri=0 -- (2) kernel mode, wait -- (1) supervisor mode -- (0) user mode -- if cpugo=0 shows cpurust --- (3:0) cpurust code -- (4) '1' +-- (3:0) cpurust code -- -- DP(3:0) shows IO activity -- if SWI(2)=0 (serport) @@ -279,6 +294,8 @@ architecture syn of sys_w11a_n2 is signal DM_STAT_SY : dm_stat_sy_type := dm_stat_sy_init; signal DISPREG : slv16 := (others=>'0'); + signal STATLEDS : slv8 := (others=>'0'); + signal ABCLKDIV : slv16 := (others=>'0'); constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0004: 1111 1110 1111 00xx @@ -439,7 +456,7 @@ begin CP_DOUT => CP_DOUT ); - CORE : pdp11_core + W11A : pdp11_core port map ( CLK => CLK, RESET => CPU_RESET, @@ -461,122 +478,73 @@ begin DM_STAT_CO => DM_STAT_CO ); - MEM_BRAM: if sys_conf_bram > 0 generate - signal HM_VAL_BRAM : slbit := '0'; - begin - - MEM : pdp11_bram - generic map ( - AWIDTH => sys_conf_bram_awidth) - port map ( - CLK => CLK, - GRESET => CPU_RESET, - EM_MREQ => EM_MREQ, - EM_SRES => EM_SRES - ); + CACHE: pdp11_cache + port map ( + CLK => CLK, + GRESET => CPU_RESET, + EM_MREQ => EM_MREQ, + EM_SRES => EM_SRES, + FMISS => CACHE_FMISS, + CHIT => CACHE_CHIT, + MEM_REQ => MEM_REQ, + MEM_WE => MEM_WE, + MEM_BUSY => MEM_BUSY, + MEM_ACK_R => MEM_ACK_R, + MEM_ADDR => MEM_ADDR, + MEM_BE => MEM_BE, + MEM_DI => MEM_DI, + MEM_DO => MEM_DO + ); - HM_VAL_BRAM <= not EM_MREQ.we; -- assume hit if read, miss if write - - MEM70: pdp11_mem70 - port map ( - CLK => CLK, - CRESET => BRESET, - HM_ENA => EM_MREQ.req, - HM_VAL => HM_VAL_BRAM, - CACHE_FMISS => MEM70_FMISS, - IB_MREQ => IB_MREQ, - IB_SRES => IB_SRES_MEM70 - ); + MEM70: pdp11_mem70 + port map ( + CLK => CLK, + CRESET => BRESET, + HM_ENA => HM_ENA, + HM_VAL => CACHE_CHIT, + CACHE_FMISS => MEM70_FMISS, + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_MEM70 + ); - SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy - port map ( - O_MEM_CE_N => O_MEM_CE_N, - O_MEM_BE_N => O_MEM_BE_N, - O_MEM_WE_N => O_MEM_WE_N, - O_MEM_OE_N => O_MEM_OE_N, - O_MEM_ADV_N => O_MEM_ADV_N, - O_MEM_CLK => O_MEM_CLK, - O_MEM_CRE => O_MEM_CRE, - I_MEM_WAIT => I_MEM_WAIT, - O_MEM_ADDR => O_MEM_ADDR, - IO_MEM_DATA => IO_MEM_DATA - ); - - O_FLA_CE_N <= '1'; -- keep Flash memory disabled - - end generate MEM_BRAM; - - MEM_SRAM: if sys_conf_bram = 0 generate - - CACHE: pdp11_cache - port map ( - CLK => CLK, - GRESET => CPU_RESET, - EM_MREQ => EM_MREQ, - EM_SRES => EM_SRES, - FMISS => CACHE_FMISS, - CHIT => CACHE_CHIT, - MEM_REQ => MEM_REQ, - MEM_WE => MEM_WE, - MEM_BUSY => MEM_BUSY, - MEM_ACK_R => MEM_ACK_R, - MEM_ADDR => MEM_ADDR, - MEM_BE => MEM_BE, - MEM_DI => MEM_DI, - MEM_DO => MEM_DO - ); - - MEM70: pdp11_mem70 - port map ( - CLK => CLK, - CRESET => BRESET, - HM_ENA => HM_ENA, - HM_VAL => CACHE_CHIT, - CACHE_FMISS => MEM70_FMISS, - IB_MREQ => IB_MREQ, - IB_SRES => IB_SRES_MEM70 - ); - - HM_ENA <= EM_SRES.ack_r or EM_SRES.ack_w; - CACHE_FMISS <= MEM70_FMISS or sys_conf_cache_fmiss; - - MEM_ADDR_EXT <= "00" & MEM_ADDR; -- just use lower 4 MB (of 16 MB) - - SRAM_CTL: nx_cram_memctl_as - generic map ( - READ0DELAY => sys_conf_memctl_read0delay, - READ1DELAY => sys_conf_memctl_read1delay, - WRITEDELAY => sys_conf_memctl_writedelay) - port map ( - CLK => CLK, - RESET => CPU_RESET, - REQ => MEM_REQ, - WE => MEM_WE, - BUSY => MEM_BUSY, - ACK_R => MEM_ACK_R, - ACK_W => open, - ACT_R => MEM_ACT_R, - ACT_W => MEM_ACT_W, - ADDR => MEM_ADDR_EXT, - BE => MEM_BE, - DI => MEM_DI, - DO => MEM_DO, - O_MEM_CE_N => O_MEM_CE_N, - O_MEM_BE_N => O_MEM_BE_N, - O_MEM_WE_N => O_MEM_WE_N, - O_MEM_OE_N => O_MEM_OE_N, - O_MEM_ADV_N => O_MEM_ADV_N, - O_MEM_CLK => O_MEM_CLK, - O_MEM_CRE => O_MEM_CRE, - I_MEM_WAIT => I_MEM_WAIT, - O_MEM_ADDR => O_MEM_ADDR, - IO_MEM_DATA => IO_MEM_DATA - ); - - O_FLA_CE_N <= '1'; -- keep Flash memory disabled - - end generate MEM_SRAM; + HM_ENA <= EM_SRES.ack_r or EM_SRES.ack_w; + CACHE_FMISS <= MEM70_FMISS or sys_conf_cache_fmiss; + MEM_ADDR_EXT <= "00" & MEM_ADDR; -- just use lower 4 MB (of 16 MB) + + SRAM_CTL: nx_cram_memctl_as + generic map ( + READ0DELAY => sys_conf_memctl_read0delay, + READ1DELAY => sys_conf_memctl_read1delay, + WRITEDELAY => sys_conf_memctl_writedelay) + port map ( + CLK => CLK, + RESET => CPU_RESET, + REQ => MEM_REQ, + WE => MEM_WE, + BUSY => MEM_BUSY, + ACK_R => MEM_ACK_R, + ACK_W => open, + ACT_R => MEM_ACT_R, + ACT_W => MEM_ACT_W, + ADDR => MEM_ADDR_EXT, + BE => MEM_BE, + DI => MEM_DI, + DO => MEM_DO, + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + O_FLA_CE_N <= '1'; -- keep Flash memory disabled + IB_SRES_OR : ib_sres_or_2 port map ( IB_SRES_1 => IB_SRES_MEM70, @@ -584,45 +552,23 @@ begin IB_SRES_OR => IB_SRES ); - IBD_MINI : if false generate - begin - IBDR_SYS : ibdr_minisys - port map ( - CLK => CLK, - CE_USEC => CE_USEC, - CE_MSEC => CE_MSEC, - RESET => CPU_RESET, - BRESET => BRESET, - RB_LAM => RB_LAM(15 downto 1), - IB_MREQ => IB_MREQ, - IB_SRES => IB_SRES_IBDR, - EI_ACKM => EI_ACKM, + IBDR_SYS : ibdr_maxisys + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + RESET => CPU_RESET, + BRESET => BRESET, + RB_LAM => RB_LAM(15 downto 1), + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_IBDR, + EI_ACKM => EI_ACKM, EI_PRI => EI_PRI, - EI_VECT => EI_VECT, - DISPREG => DISPREG - ); - end generate IBD_MINI; - - IBD_MAXI : if true generate - begin - IBDR_SYS : ibdr_maxisys - port map ( - CLK => CLK, - CE_USEC => CE_USEC, - CE_MSEC => CE_MSEC, - RESET => CPU_RESET, - BRESET => BRESET, - RB_LAM => RB_LAM(15 downto 1), - IB_MREQ => IB_MREQ, - IB_SRES => IB_SRES_IBDR, - EI_ACKM => EI_ACKM, - EI_PRI => EI_PRI, - EI_VECT => EI_VECT, - DISPREG => DISPREG - ); - end generate IBD_MAXI; + EI_VECT => EI_VECT, + DISPREG => DISPREG + ); - IOLEDS : ioleds_sp1c_fx2 + LED_IO : ioleds_sp1c_fx2 port map ( CLK => CLK, CE_USEC => CE_USEC, @@ -634,37 +580,37 @@ begin IOLEDS => DSP_DP ); - DSP_DAT(15 downto 0) <= DISPREG; + LED_CPU : pdp11_statleds + port map ( + MEM_ACT_R => MEM_ACT_R, + MEM_ACT_W => MEM_ACT_W, + CP_STAT => CP_STAT, + DM_STAT_DP => DM_STAT_DP, + STATLEDS => STATLEDS + ); + + LED_MUX : pdp11_ledmux + generic map ( + LWIDTH => LED'length) + port map ( + SEL => SWI(3), + STATLEDS => STATLEDS, + DM_STAT_DP => DM_STAT_DP, + LED => LED + ); + + ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f; - proc_led: process (MEM_ACT_W, MEM_ACT_R, CP_STAT, DM_STAT_DP.psw) - variable iled : slv8 := (others=>'0'); - begin - iled := (others=>'0'); - iled(7) := MEM_ACT_W; - iled(6) := MEM_ACT_R; - iled(5) := CP_STAT.cmdbusy; - if CP_STAT.cpugo = '1' then - case DM_STAT_DP.psw.cmode is - when c_psw_kmode => - if CP_STAT.cpuwait = '1' then - iled(2) := '1'; - elsif unsigned(DM_STAT_DP.psw.pri) = 0 then - iled(3) := '1'; - else - iled(4) := '1'; - end if; - when c_psw_smode => - iled(1) := '1'; - when c_psw_umode => - iled(0) := '1'; - when others => null; - end case; - else - iled(4) := '1'; - iled(3 downto 0) := CP_STAT.cpurust; - end if; - LED <= iled; - end process; + DSP_MUX : pdp11_dspmux + generic map ( + DCWIDTH => 2) + port map ( + SEL => SWI(5 downto 4), + ABCLKDIV => ABCLKDIV, + DM_STAT_DP => DM_STAT_DP, + DISPREG => DISPREG, + DSP_DAT => DSP_DAT + ); -- synthesis translate_off DM_STAT_SY.emmreq <= EM_MREQ; diff --git a/rtl/sys_gen/w11a/nexys2/tb/Makefile b/rtl/sys_gen/w11a/nexys2/tb/Makefile index 95d57d98..bcfa09a4 100644 --- a/rtl/sys_gen/w11a/nexys2/tb/Makefile +++ b/rtl/sys_gen/w11a/nexys2/tb/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -7,7 +7,7 @@ # EXE_all = tb_w11a_n2 # -include $(RETROBASE)/rtl/make/xflow_default_nexys2.mk +include $(RETROBASE)/rtl/make_ise/xflow_default_nexys2.mk # .PHONY : all all_ssim all_tsim clean # @@ -19,8 +19,8 @@ clean : ise_clean ghdl_clean # #----- # -include $(RETROBASE)/rtl/make/generic_ghdl.mk -include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/sys_gen/w11a/nexys2/tb/sys_conf_sim.vhd b/rtl/sys_gen/w11a/nexys2/tb/sys_conf_sim.vhd index c02a0d40..fe33bc83 100644 --- a/rtl/sys_gen/w11a/nexys2/tb/sys_conf_sim.vhd +++ b/rtl/sys_gen/w11a/nexys2/tb/sys_conf_sim.vhd @@ -1,6 +1,6 @@ --- $Id: sys_conf_sim.vhd 619 2014-12-23 13:17:41Z mueller $ +-- $Id: sys_conf_sim.vhd 647 2015-02-17 22:35:36Z mueller $ -- --- Copyright 2010-2014 by Walter F.J. Mueller +-- Copyright 2010-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -19,6 +19,7 @@ -- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31 -- Revision History: -- Date Rev Version Comment +-- 2015-02-07 643 1.3 drop bram and minisys options -- 2014-12-22 619 1.2.1 add _rbmon_awidth -- 2013-04-21 509 1.2 add fx2 settings -- 2011-11-27 433 1.1.1 use /1*1 to skip dcm in sim, _ssim fails with dcm @@ -52,15 +53,9 @@ package sys_conf is constant sys_conf_hio_debounce : boolean := false; -- no debouncers - constant sys_conf_bram : integer := 0; -- no bram, use cache - constant sys_conf_bram_awidth : integer := 14; -- bram size (16 kB) constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte --constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug) --- constant sys_conf_bram : integer := 1; -- bram only --- constant sys_conf_bram_awidth : integer := 16; -- bram size (64 kB) --- constant sys_conf_mem_losize : integer := 8#001777#; -- 64 kByte - constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled -- derived constants diff --git a/rtl/sys_gen/w11a/nexys3/Makefile b/rtl/sys_gen/w11a/nexys3/Makefile index 0f1bc885..25b8f9be 100644 --- a/rtl/sys_gen/w11a/nexys3/Makefile +++ b/rtl/sys_gen/w11a/nexys3/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 509 2013-04-21 20:46:20Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -8,7 +8,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make/xflow_default_nexys3.mk +include $(RETROBASE)/rtl/make_ise/xflow_default_nexys3.mk FX2_FILE = nexys3_jtag_2fifo_ic.ihx # .PHONY : all clean @@ -20,8 +20,8 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make/generic_xflow.mk -include $(RETROBASE)/rtl/make/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/w11a/nexys3/sys_conf.vhd b/rtl/sys_gen/w11a/nexys3/sys_conf.vhd index b2ef5990..ff209063 100644 --- a/rtl/sys_gen/w11a/nexys3/sys_conf.vhd +++ b/rtl/sys_gen/w11a/nexys3/sys_conf.vhd @@ -1,6 +1,6 @@ --- $Id: sys_conf.vhd 621 2014-12-26 21:20:05Z mueller $ +-- $Id: sys_conf.vhd 647 2015-02-17 22:35:36Z mueller $ -- --- Copyright 2011-2014 by Walter F.J. Mueller +-- Copyright 2011-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -19,6 +19,7 @@ -- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 -- Revision History: -- Date Rev Version Comment +-- 2015-02-15 647 1.3 drop bram and minisys options -- 2014-12-26 621 1.2.2 use 68 MHz, get occasional problems with 72 MHz -- 2014-12-22 619 1.2.1 add _rbmon_awidth -- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect @@ -63,15 +64,9 @@ package sys_conf is constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers - constant sys_conf_bram : integer := 0; -- no bram, use cache - constant sys_conf_bram_awidth : integer := 14; -- bram size (16 kB) constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte --constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug) --- constant sys_conf_bram : integer := 1; -- bram only --- constant sys_conf_bram_awidth : integer := 15; -- bram size (32 kB) --- constant sys_conf_mem_losize : integer := 8#000777#; -- 32 kByte - constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled -- derived constants diff --git a/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vbom b/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vbom index 6e7c7e0e..096fa16d 100644 --- a/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vbom +++ b/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vbom @@ -16,26 +16,26 @@ ../../../w11a/pdp11.vhd sys_conf = sys_conf.vhd # components -[xst,isim]../../../vlib/xlib/s6_cmt_sfs_unisim.vbom +[xst,vsyn,isim,vsim]../../../vlib/xlib/s6_cmt_sfs_unisim.vbom [ghdl]../../../vlib/xlib/s6_cmt_sfs_gsim.vbom ../../../vlib/genlib/clkdivce.vbom ../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom ../../../bplib/bpgen/sn_humanio_rbus.vbom ../../../bplib/fx2rlink/rlink_sp1c_fx2.vbom -../../../bplib/fx2rlink/ioleds_sp1c_fx2.vbom ../../../vlib/rbus/rb_sres_or_4.vbom ../../../vlib/rbus/rbd_rbmon.vbom ../../../w11a/pdp11_core_rbus.vbom ../../../w11a/pdp11_core.vbom -../../../w11a/pdp11_bram.vbom -../../../bplib/nxcramlib/nx_cram_dummy.vbom ../../../w11a/pdp11_cache.vbom ../../../w11a/pdp11_mem70.vbom ../../../bplib/nxcramlib/nx_cram_memctl_as.vbom ../../../ibus/ib_sres_or_2.vbom -../../../ibus/ibdr_minisys.vbom ../../../ibus/ibdr_maxisys.vbom -[ghdl,isim]../../../w11a/pdp11_tmu_sb.vbom +../../../bplib/fx2rlink/ioleds_sp1c_fx2.vbom +../../../w11a/pdp11_statleds.vbom +../../../w11a/pdp11_ledmux.vbom +../../../w11a/pdp11_dspmux.vbom +[sim]../../../w11a/pdp11_tmu_sb.vbom # design sys_w11a_n3.vhd @ucf_cpp: sys_w11a_n3.ucf diff --git a/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd b/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd index 39d7b882..e68ea80a 100644 --- a/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd +++ b/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd @@ -1,6 +1,6 @@ --- $Id: sys_w11a_n3.vhd 620 2014-12-25 10:48:35Z mueller $ +-- $Id: sys_w11a_n3.vhd 652 2015-02-28 12:18:08Z mueller $ -- --- Copyright 2011-2014 by Walter F.J. Mueller +-- Copyright 2011-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -20,19 +20,19 @@ -- bplib/bpgen/bp_rs232_2l4l_iob -- bplib/bpgen/sn_humanio_rbus -- bplib/fx2rlink/rlink_sp1c_fx2 --- bplib/fx2rlink/ioleds_sp1c_fx2 -- vlib/rbus/rb_sres_or_4 -- vlib/rbus/rbd_rbmon -- w11a/pdp11_core_rbus -- w11a/pdp11_core --- w11a/pdp11_bram --- vlib/nxcramlib/nx_cram_dummy -- w11a/pdp11_cache -- w11a/pdp11_mem70 -- bplib/nxcramlib/nx_cram_memctl_as -- ibus/ib_sres_or_2 --- ibus/ibdr_minisys -- ibus/ibdr_maxisys +-- bplib/fx2rlink/ioleds_sp1c_fx2 +-- w11a/pdp11_statleds +-- w11a/pdp11_ledmux +-- w11a/pdp11_dspmux -- w11a/pdp11_tmu_sb [sim only] -- -- Test bench: tb/tb_sys_w11a_n3 @@ -42,6 +42,7 @@ -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri +-- 2014-02-21 649 14.7 131013 xc6slx16-2 1819 3905 160 1380 ok: +RL11 -- 2014-12-22 619 14.7 131013 xc6slx16-2 1742 3767 150 1350 ok: +rbmon -- 2014-12-20 614 14.7 131013 xc6slx16-2 1640 3692 150 1297 ok: -RL11,rlv4 -- 2014-06-08 561 14.7 131013 xc6slx16-2 1531 3500 142 1165 ok: +RL11 @@ -52,6 +53,8 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2015-02-21 649 1.8.1 use ioleds_sp1c,pdp11_(statleds,ledmux,dspmux) +-- 2015-02-15 647 1.8 drop bram and minisys options -- 2014-12-24 620 1.7.2 relocate ibus window and hio rbus address -- 2014-12-22 619 1.7.1 add rbus monitor rbd_rbmon -- 2014-08-28 588 1.7 use new rlink v4 iface generics and 4 bit STAT @@ -70,25 +73,37 @@ -- -- Usage of Nexys 3 Switches, Buttons, LEDs: -- --- SWI(7:3): no function (only connected to sn_humanio_rbus) +-- SWI(7:6): no function (only connected to sn_humanio_rbus) +-- (5:4): select DSP +-- 00 abclkdiv & abclkdiv_f +-- 01 PC +-- 10 DISPREG +-- 11 DR emulation +-- (3): select LED display +-- 0 overall status +-- 1 DR emulation -- (2) 0 -> int/ext RS242 port for rlink -- 1 -> use USB interface for rlink --- SWI(1): 1 enable XON --- SWI(0): 0 -> main board RS232 port +-- (1): 1 enable XON +-- (0): 0 -> main board RS232 port -- 1 -> Pmod B/top RS232 port -- --- LED(7) MEM_ACT_W --- (6) MEM_ACT_R --- (5) cmdbusy (all rlink access, mostly rdma) --- (4:0): if cpugo=1 show cpu mode activity +-- LEDs if SWI(3) = 1 +-- (7:0) DR emulation; shows R0(lower 8 bits) during wait like 11/45+70 +-- +-- LEDs if SWI(3) = 0 +-- (7) MEM_ACT_W +-- (6) MEM_ACT_R +-- (5) cmdbusy (all rlink access, mostly rdma) +-- (4:0) if cpugo=1 show cpu mode activity -- (4) kernel mode, pri>0 -- (3) kernel mode, pri=0 -- (2) kernel mode, wait -- (1) supervisor mode -- (0) user mode -- if cpugo=0 shows cpurust --- (3:0) cpurust code -- (4) '1' +-- (3:0) cpurust code -- -- DP(3:0) shows IO activity -- if SWI(2)=0 (serport) @@ -242,6 +257,8 @@ architecture syn of sys_w11a_n3 is signal DM_STAT_SY : dm_stat_sy_type := dm_stat_sy_init; signal DISPREG : slv16 := (others=>'0'); + signal STATLEDS : slv8 := (others=>'0'); + signal ABCLKDIV : slv16 := (others=>'0'); constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0004: 1111 1110 1111 00xx @@ -407,7 +424,7 @@ begin CP_DOUT => CP_DOUT ); - CORE : pdp11_core + W11A : pdp11_core port map ( CLK => CLK, RESET => CPU_RESET, @@ -429,123 +446,73 @@ begin DM_STAT_CO => DM_STAT_CO ); - MEM_BRAM: if sys_conf_bram > 0 generate - signal HM_VAL_BRAM : slbit := '0'; - begin - - MEM : pdp11_bram - generic map ( - AWIDTH => sys_conf_bram_awidth) - port map ( - CLK => CLK, - GRESET => CPU_RESET, - EM_MREQ => EM_MREQ, - EM_SRES => EM_SRES - ); + CACHE: pdp11_cache + port map ( + CLK => CLK, + GRESET => CPU_RESET, + EM_MREQ => EM_MREQ, + EM_SRES => EM_SRES, + FMISS => CACHE_FMISS, + CHIT => CACHE_CHIT, + MEM_REQ => MEM_REQ, + MEM_WE => MEM_WE, + MEM_BUSY => MEM_BUSY, + MEM_ACK_R => MEM_ACK_R, + MEM_ADDR => MEM_ADDR, + MEM_BE => MEM_BE, + MEM_DI => MEM_DI, + MEM_DO => MEM_DO + ); - HM_VAL_BRAM <= not EM_MREQ.we; -- assume hit if read, miss if write - - MEM70: pdp11_mem70 - port map ( - CLK => CLK, - CRESET => BRESET, - HM_ENA => EM_MREQ.req, - HM_VAL => HM_VAL_BRAM, - CACHE_FMISS => MEM70_FMISS, - IB_MREQ => IB_MREQ, - IB_SRES => IB_SRES_MEM70 - ); + MEM70: pdp11_mem70 + port map ( + CLK => CLK, + CRESET => BRESET, + HM_ENA => HM_ENA, + HM_VAL => CACHE_CHIT, + CACHE_FMISS => MEM70_FMISS, + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_MEM70 + ); - SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy - port map ( - O_MEM_CE_N => O_MEM_CE_N, - O_MEM_BE_N => O_MEM_BE_N, - O_MEM_WE_N => O_MEM_WE_N, - O_MEM_OE_N => O_MEM_OE_N, - O_MEM_ADV_N => O_MEM_ADV_N, - O_MEM_CLK => O_MEM_CLK, - O_MEM_CRE => O_MEM_CRE, - I_MEM_WAIT => I_MEM_WAIT, - O_MEM_ADDR => O_MEM_ADDR, - IO_MEM_DATA => IO_MEM_DATA - ); + HM_ENA <= EM_SRES.ack_r or EM_SRES.ack_w; + CACHE_FMISS <= MEM70_FMISS or sys_conf_cache_fmiss; + + MEM_ADDR_EXT <= "00" & MEM_ADDR; -- just use lower 4 MB (of 16 MB) - O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled - O_PPCM_RST_N <= '1'; -- - - end generate MEM_BRAM; + SRAM_CTL: nx_cram_memctl_as + generic map ( + READ0DELAY => sys_conf_memctl_read0delay, + READ1DELAY => sys_conf_memctl_read1delay, + WRITEDELAY => sys_conf_memctl_writedelay) + port map ( + CLK => CLK, + RESET => CPU_RESET, + REQ => MEM_REQ, + WE => MEM_WE, + BUSY => MEM_BUSY, + ACK_R => MEM_ACK_R, + ACK_W => open, + ACT_R => MEM_ACT_R, + ACT_W => MEM_ACT_W, + ADDR => MEM_ADDR_EXT, + BE => MEM_BE, + DI => MEM_DI, + DO => MEM_DO, + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); - MEM_SRAM: if sys_conf_bram = 0 generate - - CACHE: pdp11_cache - port map ( - CLK => CLK, - GRESET => CPU_RESET, - EM_MREQ => EM_MREQ, - EM_SRES => EM_SRES, - FMISS => CACHE_FMISS, - CHIT => CACHE_CHIT, - MEM_REQ => MEM_REQ, - MEM_WE => MEM_WE, - MEM_BUSY => MEM_BUSY, - MEM_ACK_R => MEM_ACK_R, - MEM_ADDR => MEM_ADDR, - MEM_BE => MEM_BE, - MEM_DI => MEM_DI, - MEM_DO => MEM_DO - ); - - MEM70: pdp11_mem70 - port map ( - CLK => CLK, - CRESET => BRESET, - HM_ENA => HM_ENA, - HM_VAL => CACHE_CHIT, - CACHE_FMISS => MEM70_FMISS, - IB_MREQ => IB_MREQ, - IB_SRES => IB_SRES_MEM70 - ); - - HM_ENA <= EM_SRES.ack_r or EM_SRES.ack_w; - CACHE_FMISS <= MEM70_FMISS or sys_conf_cache_fmiss; - - MEM_ADDR_EXT <= "00" & MEM_ADDR; -- just use lower 4 MB (of 16 MB) - - SRAM_CTL: nx_cram_memctl_as - generic map ( - READ0DELAY => sys_conf_memctl_read0delay, - READ1DELAY => sys_conf_memctl_read1delay, - WRITEDELAY => sys_conf_memctl_writedelay) - port map ( - CLK => CLK, - RESET => CPU_RESET, - REQ => MEM_REQ, - WE => MEM_WE, - BUSY => MEM_BUSY, - ACK_R => MEM_ACK_R, - ACK_W => open, - ACT_R => MEM_ACT_R, - ACT_W => MEM_ACT_W, - ADDR => MEM_ADDR_EXT, - BE => MEM_BE, - DI => MEM_DI, - DO => MEM_DO, - O_MEM_CE_N => O_MEM_CE_N, - O_MEM_BE_N => O_MEM_BE_N, - O_MEM_WE_N => O_MEM_WE_N, - O_MEM_OE_N => O_MEM_OE_N, - O_MEM_ADV_N => O_MEM_ADV_N, - O_MEM_CLK => O_MEM_CLK, - O_MEM_CRE => O_MEM_CRE, - I_MEM_WAIT => I_MEM_WAIT, - O_MEM_ADDR => O_MEM_ADDR, - IO_MEM_DATA => IO_MEM_DATA - ); - - O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled - O_PPCM_RST_N <= '1'; -- - - end generate MEM_SRAM; + O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled + O_PPCM_RST_N <= '1'; -- IB_SRES_OR : ib_sres_or_2 port map ( @@ -554,45 +521,23 @@ begin IB_SRES_OR => IB_SRES ); - IBD_MINI : if false generate - begin - IBDR_SYS : ibdr_minisys - port map ( - CLK => CLK, - CE_USEC => CE_USEC, - CE_MSEC => CE_MSEC, - RESET => CPU_RESET, - BRESET => BRESET, - RB_LAM => RB_LAM(15 downto 1), - IB_MREQ => IB_MREQ, - IB_SRES => IB_SRES_IBDR, - EI_ACKM => EI_ACKM, - EI_PRI => EI_PRI, - EI_VECT => EI_VECT, - DISPREG => DISPREG - ); - end generate IBD_MINI; - - IBD_MAXI : if true generate - begin - IBDR_SYS : ibdr_maxisys - port map ( - CLK => CLK, - CE_USEC => CE_USEC, - CE_MSEC => CE_MSEC, - RESET => CPU_RESET, - BRESET => BRESET, - RB_LAM => RB_LAM(15 downto 1), - IB_MREQ => IB_MREQ, - IB_SRES => IB_SRES_IBDR, - EI_ACKM => EI_ACKM, - EI_PRI => EI_PRI, - EI_VECT => EI_VECT, - DISPREG => DISPREG - ); - end generate IBD_MAXI; + IBDR_SYS : ibdr_maxisys + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + RESET => CPU_RESET, + BRESET => BRESET, + RB_LAM => RB_LAM(15 downto 1), + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_IBDR, + EI_ACKM => EI_ACKM, + EI_PRI => EI_PRI, + EI_VECT => EI_VECT, + DISPREG => DISPREG + ); - IOLEDS : ioleds_sp1c_fx2 + LED_IO : ioleds_sp1c_fx2 port map ( CLK => CLK, CE_USEC => CE_USEC, @@ -603,38 +548,38 @@ begin SER_MONI => SER_MONI, IOLEDS => DSP_DP ); + + LED_CPU : pdp11_statleds + port map ( + MEM_ACT_R => MEM_ACT_R, + MEM_ACT_W => MEM_ACT_W, + CP_STAT => CP_STAT, + DM_STAT_DP => DM_STAT_DP, + STATLEDS => STATLEDS + ); + + LED_MUX : pdp11_ledmux + generic map ( + LWIDTH => LED'length) + port map ( + SEL => SWI(3), + STATLEDS => STATLEDS, + DM_STAT_DP => DM_STAT_DP, + LED => LED + ); + + ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f; - DSP_DAT(15 downto 0) <= DISPREG; - - proc_led: process (MEM_ACT_W, MEM_ACT_R, CP_STAT, DM_STAT_DP.psw) - variable iled : slv8 := (others=>'0'); - begin - iled := (others=>'0'); - iled(7) := MEM_ACT_W; - iled(6) := MEM_ACT_R; - iled(5) := CP_STAT.cmdbusy; - if CP_STAT.cpugo = '1' then - case DM_STAT_DP.psw.cmode is - when c_psw_kmode => - if CP_STAT.cpuwait = '1' then - iled(2) := '1'; - elsif unsigned(DM_STAT_DP.psw.pri) = 0 then - iled(3) := '1'; - else - iled(4) := '1'; - end if; - when c_psw_smode => - iled(1) := '1'; - when c_psw_umode => - iled(0) := '1'; - when others => null; - end case; - else - iled(4) := '1'; - iled(3 downto 0) := CP_STAT.cpurust; - end if; - LED <= iled; - end process; + DSP_MUX : pdp11_dspmux + generic map ( + DCWIDTH => 2) + port map ( + SEL => SWI(5 downto 4), + ABCLKDIV => ABCLKDIV, + DM_STAT_DP => DM_STAT_DP, + DISPREG => DISPREG, + DSP_DAT => DSP_DAT + ); -- synthesis translate_off DM_STAT_SY.emmreq <= EM_MREQ; diff --git a/rtl/sys_gen/w11a/nexys3/tb/Makefile b/rtl/sys_gen/w11a/nexys3/tb/Makefile index 9dcfb7d9..80cc2e3d 100644 --- a/rtl/sys_gen/w11a/nexys3/tb/Makefile +++ b/rtl/sys_gen/w11a/nexys3/tb/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -6,7 +6,7 @@ # EXE_all = tb_w11a_n3 # -include $(RETROBASE)/rtl/make/xflow_default_nexys3.mk +include $(RETROBASE)/rtl/make_ise/xflow_default_nexys3.mk # .PHONY : all all_ssim all_tsim clean # @@ -18,8 +18,8 @@ clean : ise_clean ghdl_clean # #----- # -include $(RETROBASE)/rtl/make/generic_ghdl.mk -include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/sys_gen/w11a/nexys3/tb/sys_conf_sim.vhd b/rtl/sys_gen/w11a/nexys3/tb/sys_conf_sim.vhd index c4b6e702..9afece5e 100644 --- a/rtl/sys_gen/w11a/nexys3/tb/sys_conf_sim.vhd +++ b/rtl/sys_gen/w11a/nexys3/tb/sys_conf_sim.vhd @@ -1,6 +1,6 @@ --- $Id: sys_conf_sim.vhd 619 2014-12-23 13:17:41Z mueller $ +-- $Id: sys_conf_sim.vhd 647 2015-02-17 22:35:36Z mueller $ -- --- Copyright 2011-2014 by Walter F.J. Mueller +-- Copyright 2011-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -19,6 +19,7 @@ -- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 -- Revision History: -- Date Rev Version Comment +-- 2015-02-15 647 1.4 drop bram and minisys options -- 2014-12-22 619 1.3.1 add _rbmon_awidth -- 2013-10-06 538 1.3 pll support, use clksys_vcodivide ect -- 2013-04-21 509 1.2 add fx2 settings @@ -51,15 +52,9 @@ package sys_conf is constant sys_conf_hio_debounce : boolean := false; -- no debouncers - constant sys_conf_bram : integer := 0; -- no bram, use cache - constant sys_conf_bram_awidth : integer := 14; -- bram size (16 kB) constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte --constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug) --- constant sys_conf_bram : integer := 1; -- bram only --- constant sys_conf_bram_awidth : integer := 16; -- bram size (64 kB) --- constant sys_conf_mem_losize : integer := 8#001777#; -- 64 kByte - constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled -- derived constants diff --git a/rtl/sys_gen/w11a/nexys4/.cvsignore b/rtl/sys_gen/w11a/nexys4/.cvsignore new file mode 100644 index 00000000..1e3b6be4 --- /dev/null +++ b/rtl/sys_gen/w11a/nexys4/.cvsignore @@ -0,0 +1,12 @@ +sys_w11a_n4.ucf +*.dep_ucf_cpp +log_* +_impact* +*.svf +.Xil +project_mflow +*.jou +*.log +*.rpt +*.dcp +*.dep_* diff --git a/rtl/sys_gen/w11a/nexys4/Makefile b/rtl/sys_gen/w11a/nexys4/Makefile new file mode 100644 index 00000000..208c9637 --- /dev/null +++ b/rtl/sys_gen/w11a/nexys4/Makefile @@ -0,0 +1,25 @@ +# $Id: Makefile 646 2015-02-15 12:04:55Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2015-01-25 637 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +include $(RETROBASE)/rtl/make_viv/viv_default_nexys4.mk +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : viv_clean +# +#---- +# +include $(RETROBASE)/rtl/make_viv/generic_vivado.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +endif +# diff --git a/rtl/sys_gen/w11a/nexys4/Makefile.ise b/rtl/sys_gen/w11a/nexys4/Makefile.ise new file mode 100644 index 00000000..70f997f1 --- /dev/null +++ b/rtl/sys_gen/w11a/nexys4/Makefile.ise @@ -0,0 +1,29 @@ +# -*- makefile-gmake -*- +# $Id: Makefile.ise 646 2015-02-15 12:04:55Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2013-09-22 534 1.0 Initial version (derived from _n3 version) +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +include $(RETROBASE)/rtl/make_ise/xflow_default_nexys4.mk +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : ise_clean + rm -f $(VBOM_all:.vbom=.ucf) +# +#---- +# +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +endif +# diff --git a/rtl/sys_gen/w11a/nexys4/sys_conf.vhd b/rtl/sys_gen/w11a/nexys4/sys_conf.vhd new file mode 100644 index 00000000..646d7c26 --- /dev/null +++ b/rtl/sys_gen/w11a/nexys4/sys_conf.vhd @@ -0,0 +1,92 @@ +-- $Id: sys_conf.vhd 643 2015-02-07 17:41:53Z mueller $ +-- +-- Copyright 2013-2015 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_w11a_n4 (for synthesis) +-- +-- Dependencies: - +-- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31 +-- Revision History: +-- Date Rev Version Comment +-- 2015-02-07 643 1.1 drop bram and minisys options +-- 2013-09-22 534 1.0 Initial version (derived from _n3 version) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +-- valid system clock / delay combinations (see n2_cram_memctl_as.vhd): +-- div mul clksys read0 read1 write +-- 2 1 50.0 2 2 3 +-- 4 3 75.0 4 4 5 (also 70 MHz) +-- 5 4 80.0 5 5 5 +-- 20 17 85.0 5 5 6 +-- 10 9 90.0 6 6 6 (also 95 MHz) +-- 1 1 100.0 6 6 7 + +package sys_conf is + + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz + constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + -- single clock design, clkser = clksys + constant sys_conf_clkser_vcodivide : positive := sys_conf_clksys_vcodivide; + constant sys_conf_clkser_vcomultiply : positive := sys_conf_clksys_vcomultiply; + constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide; + constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype; + + constant sys_conf_memctl_read0delay : positive := 5; + constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay; + constant sys_conf_memctl_writedelay : positive := 5; + + constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud + + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + + constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte +--constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug) + + constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled + + -- derived constants + + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_clkser : integer := + ((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) / + sys_conf_clkser_outdivide; + constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000; + + constant sys_conf_ser2rri_cdinit : integer := + (sys_conf_clkser/sys_conf_ser2rri_defbaud)-1; + +end package sys_conf; + +-- Note: mem_losize holds 16 MSB of the PA of the addressable memory +-- 2 211 111 111 110 000 000 000 +-- 1 098 765 432 109 876 543 210 +-- +-- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte +-- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte +-- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte +-- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte +-- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte +-- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte +-- upper 256 kB excluded for 11/70 UB diff --git a/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.ucf_cpp b/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.ucf_cpp new file mode 100644 index 00000000..d135b92f --- /dev/null +++ b/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.ucf_cpp @@ -0,0 +1,21 @@ +## $Id: sys_w11a_n4.ucf_cpp 643 2015-02-07 17:41:53Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2013-10-13 540 1.1 add pad->clk constraints +## 2013-09-22 534 1.0 Initial version +## + +NET "I_CLK100" TNM_NET = "I_CLK100"; +TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %; +OFFSET = IN 10 ns BEFORE "I_CLK100"; +OFFSET = OUT 20 ns AFTER "I_CLK100"; + +## constrain pad->net clock delay +NET CLK TNM = TNM_CLK; +TIMESPEC TS_PAD_CLK=FROM PADS(I_CLK100) TO TNM_CLK 10 ns; + +## std board +## +#include "bplib/nexys4/nexys4_pins.ucf" +#include "bplib/nexys4/nexys4_pins_cram.ucf" diff --git a/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vbom b/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vbom new file mode 100644 index 00000000..304d7ade --- /dev/null +++ b/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vbom @@ -0,0 +1,41 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/xlib/xlib.vhd +../../../vlib/genlib/genlib.vhd +../../../vlib/serport/serportlib.vbom +../../../vlib/rbus/rblib.vhd +../../../vlib/rlink/rlinklib.vbom +../../../bplib/bpgen/bpgenlib.vbom +../../../bplib/bpgen/bpgenrbuslib.vbom +../../../bplib/nxcramlib/nxcramlib.vhd +../../../ibus/iblib.vhd +../../../ibus/ibdlib.vhd +../../../w11a/pdp11.vhd +sys_conf = sys_conf.vhd +# components +[xst,vsyn,isim,vsim]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom +[ghdl]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/bp_rs232_4line_iob.vbom +../../../bplib/bpgen/sn_humanio_rbus.vbom +../../../vlib/rlink/rlink_sp1c.vbom +../../../vlib/rbus/rb_sres_or_3.vbom +../../../w11a/pdp11_core_rbus.vbom +../../../w11a/pdp11_core.vbom +../../../w11a/pdp11_cache.vbom +../../../w11a/pdp11_mem70.vbom +../../../bplib/nxcramlib/nx_cram_memctl_as.vbom +../../../ibus/ib_sres_or_2.vbom +../../../ibus/ibdr_maxisys.vbom +../../../vlib/rlink/ioleds_sp1c.vbom +../../../w11a/pdp11_statleds.vbom +../../../w11a/pdp11_ledmux.vbom +../../../w11a/pdp11_dspmux.vbom +[sim]../../../w11a/pdp11_tmu_sb.vbom +# design +sys_w11a_n4.vhd +# constraints +@ucf_cpp: sys_w11a_n4.ucf +@xdc:../../../bplib/nexys4/nexys4_pclk.xdc +@xdc:../../../bplib/nexys4/nexys4_pins.xdc +@xdc:../../../bplib/nexys4/nexys4_pins_cram.xdc diff --git a/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vhd b/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vhd new file mode 100644 index 00000000..02708fee --- /dev/null +++ b/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vhd @@ -0,0 +1,536 @@ +-- $Id: sys_w11a_n4.vhd 650 2015-02-22 21:39:47Z mueller $ +-- +-- Copyright 2013-2015 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_w11a_n4 - syn +-- Description: w11a test design for nexys4 +-- +-- Dependencies: vlib/xlib/s7_cmt_sfs +-- vlib/genlib/clkdivce +-- bplib/bpgen/bp_rs232_4line_iob +-- bplib/bpgen/sn_humanio_rbus +-- vlib/rlink/rlink_sp1c +-- vlib/rbus/rb_sres_or_3 +-- w11a/pdp11_core_rbus +-- w11a/pdp11_core +-- w11a/pdp11_cache +-- w11a/pdp11_mem70 +-- bplib/nxcramlib/nx_cram_memctl_as +-- ibus/ib_sres_or_2 +-- ibus/ibdr_maxisys +-- vlib/rlink/ioleds_sp1c +-- w11a/pdp11_statleds +-- w11a/pdp11_ledmux +-- w11a/pdp11_dspmux +-- w11a/pdp11_tmu_sb [sim only] +-- +-- Test bench: tb/tb_sys_w11a_n4 +-- +-- Target Devices: generic +-- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31 +-- +-- Synthesized: +-- Date Rev viv Target flop lutl lutm bram slic +-- 2015-02-22 650 2014.4 xc7a100t-1 1606 3652 146 3.5 1158 80 MHz +-- 2015-02-22 650 i 17.7 xc7a100t-1 1670 3564 124 1508 80 MHz +-- +-- Revision History: +-- Date Rev Version Comment +-- 2015-02-21 649 1.4.1 use ioleds_sp1c,pdp11_(statleds,ledmux,dspmux) +-- 2015-02-07 643 1.4 new DSP+LED layout, use pdp11_dr; drop bram and +-- minisys options; +-- 2015-02-01 641 1.3.1 separate I_BTNRST_N; autobaud on msb of display +-- 2015-01-31 640 1.3 drop fusp iface; use new sn_hio +-- 2014-12-24 620 1.2.1 relocate ibus window and hio rbus address +-- 2014-08-28 588 1.2 use new rlink v4 iface and 4 bit STAT +-- 2014-08-15 583 1.1 rb_mreq addr now 16 bit +-- 2013-09-28 535 1.0.1 use proper clock manager +-- 2013-09-22 543 1.0 Initial version (derived from sys_w11a_n3) +------------------------------------------------------------------------------ +-- +-- w11a test design for nexys4 +-- w11a + rlink + serport +-- +-- Usage of Nexys 4 Switches, Buttons, LEDs +-- +-- SWI(15:5): no function (only connected to sn_humanio_rbus) +-- (5): select DSP(7:4) display +-- 0 abclkdiv & abclkdiv_f +-- 1 PC +-- (4): select DSP(3:0) display +-- 0 DISPREG +-- 1 DR emulation +-- (3): select LED display +-- 0 overall status +-- 1 DR emulation +-- (2): unused-reserved (USB port select) +-- (1): 1 enable XON +-- (0): unused-reserved (serial port select) +-- +-- LEDs if SWI(3) = 1 +-- (15:0) DR emulation; shows R0 during wait like 11/45+70 +-- +-- LEDs if SWI(3) = 0 +-- (7) MEM_ACT_W +-- (6) MEM_ACT_R +-- (5) cmdbusy (all rlink access, mostly rdma) +-- (4:0) if cpugo=1 show cpu mode activity +-- (4) kernel mode, pri>0 +-- (3) kernel mode, pri=0 +-- (2) kernel mode, wait +-- (1) supervisor mode +-- (0) user mode +-- if cpugo=0 shows cpurust +-- (4) '1' +-- (3:0) cpurust code +-- +-- DSP(7:4) shows abclkdiv & abclkdiv_f or PS, depending on SWI(5) +-- DSP(3:0) shows DISPREG or DR emulation, depending on SWI(4) +-- DP(3:0) shows IO activity +-- (3) not SER_MONI.txok (shows tx back preasure) +-- (2) SER_MONI.txact (shows tx activity) +-- (1) not SER_MONI.rxok (shows rx back preasure) +-- (0) SER_MONI.rxact (shows rx activity) +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.genlib.all; +use work.serportlib.all; +use work.rblib.all; +use work.rlinklib.all; +use work.bpgenlib.all; +use work.bpgenrbuslib.all; +use work.nxcramlib.all; +use work.iblib.all; +use work.ibdlib.all; +use work.pdp11.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_w11a_n4 is -- top level + -- implements nexys4_cram_aif + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + O_RTS_N : out slbit; -- rx rts (board view; act.low) + I_CTS_N : in slbit; -- tx cts (board view; act.low) + I_SWI : in slv16; -- n4 switches + I_BTN : in slv5; -- n4 buttons + I_BTNRST_N : in slbit; -- n4 reset button + O_LED : out slv16; -- n4 leds + O_RGBLED0 : out slv3; -- n4 rgb-led 0 + O_RGBLED1 : out slv3; -- n4 rgb-led 1 + O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16 -- cram: data lines + ); +end sys_w11a_n4; + +architecture syn of sys_w11a_n4 is + + signal CLK : slbit := '0'; + + signal RXD : slbit := '1'; + signal TXD : slbit := '0'; + signal RTS_N : slbit := '0'; + signal CTS_N : slbit := '0'; + + signal SWI : slv16 := (others=>'0'); + signal BTN : slv5 := (others=>'0'); + signal LED : slv16 := (others=>'0'); + signal DSP_DAT : slv32 := (others=>'0'); + signal DSP_DP : slv8 := (others=>'0'); + + signal RB_LAM : slv16 := (others=>'0'); + signal RB_STAT : slv4 := (others=>'0'); + + signal SER_MONI : serport_moni_type := serport_moni_init; + + signal RB_MREQ : rb_mreq_type := rb_mreq_init; + signal RB_SRES : rb_sres_type := rb_sres_init; + signal RB_SRES_CPU : rb_sres_type := rb_sres_init; + signal RB_SRES_IBD : rb_sres_type := rb_sres_init; + signal RB_SRES_HIO : rb_sres_type := rb_sres_init; + + signal RESET : slbit := '0'; + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal CPU_RESET : slbit := '0'; + signal CP_CNTL : cp_cntl_type := cp_cntl_init; + signal CP_ADDR : cp_addr_type := cp_addr_init; + signal CP_DIN : slv16 := (others=>'0'); + signal CP_STAT : cp_stat_type := cp_stat_init; + signal CP_DOUT : slv16 := (others=>'0'); + + signal EI_PRI : slv3 := (others=>'0'); + signal EI_VECT : slv9_2 := (others=>'0'); + signal EI_ACKM : slbit := '0'; + + signal EM_MREQ : em_mreq_type := em_mreq_init; + signal EM_SRES : em_sres_type := em_sres_init; + + signal HM_ENA : slbit := '0'; + signal MEM70_FMISS : slbit := '0'; + signal CACHE_FMISS : slbit := '0'; + signal CACHE_CHIT : slbit := '0'; + + signal MEM_REQ : slbit := '0'; + signal MEM_WE : slbit := '0'; + signal MEM_BUSY : slbit := '0'; + signal MEM_ACK_R : slbit := '0'; + signal MEM_ACT_R : slbit := '0'; + signal MEM_ACT_W : slbit := '0'; + signal MEM_ADDR : slv20 := (others=>'0'); + signal MEM_BE : slv4 := (others=>'0'); + signal MEM_DI : slv32 := (others=>'0'); + signal MEM_DO : slv32 := (others=>'0'); + + signal MEM_ADDR_EXT : slv22 := (others=>'0'); + + signal BRESET : slbit := '0'; + signal IB_MREQ : ib_mreq_type := ib_mreq_init; + signal IB_SRES : ib_sres_type := ib_sres_init; + + signal IB_SRES_MEM70 : ib_sres_type := ib_sres_init; + signal IB_SRES_IBDR : ib_sres_type := ib_sres_init; + + signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init; + signal DM_STAT_VM : dm_stat_vm_type := dm_stat_vm_init; + signal DM_STAT_CO : dm_stat_co_type := dm_stat_co_init; + signal DM_STAT_SY : dm_stat_sy_type := dm_stat_sy_init; + + signal DISPREG : slv16 := (others=>'0'); + signal STATLEDS : slv8 := (others=>'0'); + signal ABCLKDIV : slv16 := (others=>'0'); + + constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0004: 1111 1110 1111 00xx + constant rbaddr_ibus0 : slv16 := x"4000"; -- 4000/1000: 0100 xxxx xxxx xxxx + constant rbaddr_core0 : slv16 := x"0000"; -- 0000/0020: 0000 0000 000x xxxx + +begin + + assert (sys_conf_clksys mod 1000000) = 0 + report "assert sys_conf_clksys on MHz grid" + severity failure; + + GEN_CLKSYS : s7_cmt_sfs + generic map ( + VCO_DIVIDE => sys_conf_clksys_vcodivide, + VCO_MULTIPLY => sys_conf_clksys_vcomultiply, + OUT_DIVIDE => sys_conf_clksys_outdivide, + CLKIN_PERIOD => 10.0, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clksys_gentype) + port map ( + CLKIN => I_CLK100, + CLKFX => CLK, + LOCKED => open + ); + + CLKDIV : clkdivce + generic map ( + CDUWIDTH => 7, + USECDIV => sys_conf_clksys_mhz, + MSECDIV => 1000) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC + ); + + IOB_RS232 : bp_rs232_4line_iob + port map ( + CLK => CLK, + RXD => RXD, + TXD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + I_RXD => I_RXD, + O_TXD => O_TXD, + I_CTS_N => I_CTS_N, + O_RTS_N => O_RTS_N + ); + + HIO : sn_humanio_rbus + generic map ( + SWIDTH => 16, + BWIDTH => 5, + LWIDTH => 16, + DCWIDTH => 3, + DEBOUNCE => sys_conf_hio_debounce, + RB_ADDR => rbaddr_hio) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_HIO, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + RLINK : rlink_sp1c + generic map ( + BTOWIDTH => 7, -- 128 cycles access timeout + RTAWIDTH => 12, + SYSID => (others=>'0'), + IFAWIDTH => 5, -- 32 word input fifo + OFAWIDTH => 5, -- 32 word output fifo + ENAPIN_RLMON => sbcntl_sbf_rlmon, + ENAPIN_RBMON => sbcntl_sbf_rbmon, + CDWIDTH => 13, + CDINIT => sys_conf_ser2rri_cdinit) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + CE_INT => CE_MSEC, + RESET => RESET, + ENAXON => SWI(1), + ENAESC => SWI(1), + RXSD => RXD, + TXSD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT, + RL_MONI => open, + SER_MONI => SER_MONI + ); + + RB_SRES_OR : rb_sres_or_3 + port map ( + RB_SRES_1 => RB_SRES_CPU, + RB_SRES_2 => RB_SRES_IBD, + RB_SRES_3 => RB_SRES_HIO, + RB_SRES_OR => RB_SRES + ); + + RB2CP : pdp11_core_rbus + generic map ( + RB_ADDR_CORE => rbaddr_core0, + RB_ADDR_IBUS => rbaddr_ibus0) + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_CPU, + RB_STAT => RB_STAT, + RB_LAM => RB_LAM(0), + CPU_RESET => CPU_RESET, + CP_CNTL => CP_CNTL, + CP_ADDR => CP_ADDR, + CP_DIN => CP_DIN, + CP_STAT => CP_STAT, + CP_DOUT => CP_DOUT + ); + + W11A : pdp11_core + port map ( + CLK => CLK, + RESET => CPU_RESET, + CP_CNTL => CP_CNTL, + CP_ADDR => CP_ADDR, + CP_DIN => CP_DIN, + CP_STAT => CP_STAT, + CP_DOUT => CP_DOUT, + EI_PRI => EI_PRI, + EI_VECT => EI_VECT, + EI_ACKM => EI_ACKM, + EM_MREQ => EM_MREQ, + EM_SRES => EM_SRES, + BRESET => BRESET, + IB_MREQ_M => IB_MREQ, + IB_SRES_M => IB_SRES, + DM_STAT_DP => DM_STAT_DP, + DM_STAT_VM => DM_STAT_VM, + DM_STAT_CO => DM_STAT_CO + ); + + CACHE: pdp11_cache + port map ( + CLK => CLK, + GRESET => CPU_RESET, + EM_MREQ => EM_MREQ, + EM_SRES => EM_SRES, + FMISS => CACHE_FMISS, + CHIT => CACHE_CHIT, + MEM_REQ => MEM_REQ, + MEM_WE => MEM_WE, + MEM_BUSY => MEM_BUSY, + MEM_ACK_R => MEM_ACK_R, + MEM_ADDR => MEM_ADDR, + MEM_BE => MEM_BE, + MEM_DI => MEM_DI, + MEM_DO => MEM_DO + ); + + MEM70: pdp11_mem70 + port map ( + CLK => CLK, + CRESET => BRESET, + HM_ENA => HM_ENA, + HM_VAL => CACHE_CHIT, + CACHE_FMISS => MEM70_FMISS, + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_MEM70 + ); + + HM_ENA <= EM_SRES.ack_r or EM_SRES.ack_w; + CACHE_FMISS <= MEM70_FMISS or sys_conf_cache_fmiss; + + MEM_ADDR_EXT <= "00" & MEM_ADDR; -- just use lower 4 MB (of 16 MB) + + CRAM_CTL: nx_cram_memctl_as + generic map ( + READ0DELAY => sys_conf_memctl_read0delay, + READ1DELAY => sys_conf_memctl_read1delay, + WRITEDELAY => sys_conf_memctl_writedelay) + port map ( + CLK => CLK, + RESET => CPU_RESET, + REQ => MEM_REQ, + WE => MEM_WE, + BUSY => MEM_BUSY, + ACK_R => MEM_ACK_R, + ACK_W => open, + ACT_R => MEM_ACT_R, + ACT_W => MEM_ACT_W, + ADDR => MEM_ADDR_EXT, + BE => MEM_BE, + DI => MEM_DI, + DO => MEM_DO, + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + IB_SRES_OR : ib_sres_or_2 + port map ( + IB_SRES_1 => IB_SRES_MEM70, + IB_SRES_2 => IB_SRES_IBDR, + IB_SRES_OR => IB_SRES + ); + + IBDR_SYS : ibdr_maxisys + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + RESET => CPU_RESET, + BRESET => BRESET, + RB_LAM => RB_LAM(15 downto 1), + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_IBDR, + EI_ACKM => EI_ACKM, + EI_PRI => EI_PRI, + EI_VECT => EI_VECT, + DISPREG => DISPREG + ); + + LED_IO : ioleds_sp1c + port map ( + SER_MONI => SER_MONI, + IOLEDS => DSP_DP(3 downto 0) + ); + DSP_DP(7 downto 4) <= "0010"; + + LED_CPU : pdp11_statleds + port map ( + MEM_ACT_R => MEM_ACT_R, + MEM_ACT_W => MEM_ACT_W, + CP_STAT => CP_STAT, + DM_STAT_DP => DM_STAT_DP, + STATLEDS => STATLEDS + ); + + LED_MUX : pdp11_ledmux + generic map ( + LWIDTH => LED'length) + port map ( + SEL => SWI(3), + STATLEDS => STATLEDS, + DM_STAT_DP => DM_STAT_DP, + LED => LED + ); + + ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f; + + DSP_MUX : pdp11_dspmux + generic map ( + DCWIDTH => 3) + port map ( + SEL => SWI(5 downto 4), + ABCLKDIV => ABCLKDIV, + DM_STAT_DP => DM_STAT_DP, + DISPREG => DISPREG, + DSP_DAT => DSP_DAT + ); + + -- setup unused outputs in nexys4 + O_RGBLED0 <= (others=>'0'); + O_RGBLED1 <= (others=>not I_BTNRST_N); + +-- synthesis translate_off + DM_STAT_SY.emmreq <= EM_MREQ; + DM_STAT_SY.emsres <= EM_SRES; + DM_STAT_SY.chit <= CACHE_CHIT; + + TMU : pdp11_tmu_sb + generic map ( + ENAPIN => 13) + port map ( + CLK => CLK, + DM_STAT_DP => DM_STAT_DP, + DM_STAT_VM => DM_STAT_VM, + DM_STAT_CO => DM_STAT_CO, + DM_STAT_SY => DM_STAT_SY + ); +-- synthesis translate_on + +end syn; diff --git a/rtl/sys_gen/w11a/nexys4/tb/.cvsignore b/rtl/sys_gen/w11a/nexys4/tb/.cvsignore new file mode 100644 index 00000000..eb0f2a2c --- /dev/null +++ b/rtl/sys_gen/w11a/nexys4/tb/.cvsignore @@ -0,0 +1,9 @@ +tb_w11a_n4 +tb_w11a_n4_[sft]sim +rlink_cext_fifo_rx +rlink_cext_fifo_tx +rlink_cext_conf +tmu_ofile +sys_w11a_n4.ucf +*.dep_ucf_cpp +*.dep_* diff --git a/rtl/sys_gen/w11a/nexys4/tb/Makefile b/rtl/sys_gen/w11a/nexys4/tb/Makefile new file mode 100644 index 00000000..bdc3e6c7 --- /dev/null +++ b/rtl/sys_gen/w11a/nexys4/tb/Makefile @@ -0,0 +1,31 @@ +# $Id: Makefile 646 2015-02-15 12:04:55Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2015-02-14 646 1.0 Initial version +# 2015-02-01 640 0.1 First draft +# +EXE_all = tb_w11a_n4 +# +include $(RETROBASE)/rtl/make_viv/viv_default_nexys4.mk +# +.PHONY : all all_ssim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +# +clean : viv_clean ghdl_clean +# +#----- +# +include $(RETROBASE)/rtl/make_viv/generic_vivado.mk +include $(RETROBASE)/rtl/make_viv/generic_ghdl.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(wildcard *.o.dep_ghdl) +endif +# diff --git a/rtl/sys_gen/w11a/nexys4/tb/Makefile.ise b/rtl/sys_gen/w11a/nexys4/tb/Makefile.ise new file mode 100644 index 00000000..1ee8fa81 --- /dev/null +++ b/rtl/sys_gen/w11a/nexys4/tb/Makefile.ise @@ -0,0 +1,32 @@ +# -*- makefile-gmake -*- +# $Id: Makefile.ise 646 2015-02-15 12:04:55Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2013-09-22 534 1.0 Initial version +# +EXE_all = tb_w11a_n4 +# +include $(RETROBASE)/rtl/make_ise/xflow_default_nexys4.mk +# +.PHONY : all all_ssim all_tsim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_tsim : $(EXE_all:=_tsim) +# +clean : ise_clean ghdl_clean +# +#----- +# +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(wildcard *.o.dep_ghdl) +endif +# diff --git a/rtl/sys_gen/w11a/nexys4/tb/sys_conf_sim.vhd b/rtl/sys_gen/w11a/nexys4/tb/sys_conf_sim.vhd new file mode 100644 index 00000000..0f96416b --- /dev/null +++ b/rtl/sys_gen/w11a/nexys4/tb/sys_conf_sim.vhd @@ -0,0 +1,80 @@ +-- $Id: sys_conf_sim.vhd 647 2015-02-17 22:35:36Z mueller $ +-- +-- Copyright 2013-2015 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_w11a_n4 (for simulation) +-- +-- Dependencies: - +-- Tool versions: xst 14.5-14.7; ghdl 0.29-0.31 +-- Revision History: +-- Date Rev Version Comment +-- 2015-02-07 643 1.1 drop bram and minisys options +-- 2013-09-34 534 1.0 Initial version (cloned from _n3) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz + constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + -- single clock design, clkser = clksys + constant sys_conf_clkser_vcodivide : positive := sys_conf_clksys_vcodivide; + constant sys_conf_clkser_vcomultiply : positive := sys_conf_clksys_vcomultiply; + constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide; + constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype; + + constant sys_conf_memctl_read0delay : positive := 6; -- for 100 MHz + constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay; + constant sys_conf_memctl_writedelay : positive := 7; + + constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim + + constant sys_conf_hio_debounce : boolean := false; -- no debouncers + + constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte +--constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug) + + constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled + + -- derived constants + + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_clkser : integer := + ((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) / + sys_conf_clkser_outdivide; + constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000; + +end package sys_conf; + +-- Note: mem_losize holds 16 MSB of the PA of the addressable memory +-- 2 211 111 111 110 000 000 000 +-- 1 098 765 432 109 876 543 210 +-- +-- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte +-- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte +-- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte +-- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte +-- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte +-- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte +-- upper 256 kB excluded for 11/70 UB diff --git a/rtl/sys_gen/w11a/nexys4/tb/sys_w11a_n4.ucf_cpp b/rtl/sys_gen/w11a/nexys4/tb/sys_w11a_n4.ucf_cpp new file mode 120000 index 00000000..6162da34 --- /dev/null +++ b/rtl/sys_gen/w11a/nexys4/tb/sys_w11a_n4.ucf_cpp @@ -0,0 +1 @@ +../sys_w11a_n4.ucf_cpp \ No newline at end of file diff --git a/rtl/sys_gen/w11a/nexys4/tb/tb_w11a_n4.vbom b/rtl/sys_gen/w11a/nexys4/tb/tb_w11a_n4.vbom new file mode 100644 index 00000000..555ad9f1 --- /dev/null +++ b/rtl/sys_gen/w11a/nexys4/tb/tb_w11a_n4.vbom @@ -0,0 +1,7 @@ +# configure tb_nexys4_cram with sys_w11a_n4 target; +# use vhdl configure file (tb_w11a_n4.vhd) to allow +# that all configurations will co-exist in work library +nexys4_cram_aif = ../sys_w11a_n4.vbom +sys_conf = sys_conf_sim.vhd +../../../../bplib/nexys4/tb/tb_nexys4_cram.vbom +tb_w11a_n4.vhd diff --git a/rtl/sys_gen/w11a/nexys4/tb/tb_w11a_n4.vhd b/rtl/sys_gen/w11a/nexys4/tb/tb_w11a_n4.vhd new file mode 100644 index 00000000..5b83ce4b --- /dev/null +++ b/rtl/sys_gen/w11a/nexys4/tb/tb_w11a_n4.vhd @@ -0,0 +1,41 @@ +-- $Id: tb_w11a_n4.vhd 644 2015-02-08 22:56:54Z mueller $ +-- +-- Copyright 2013-2015 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_w11a_n4 +-- Description: Configuration for tb_w11a_n4 for tb_nexys4_cram +-- +-- Dependencies: sys_w11a_n4 +-- +-- To test: sys_w11a_n4 +-- +-- Verified (with (#1) ../../tb/tb_rritba_pdp11core_stim.dat +-- (#2) ../../tb/tb_pdp11_core_stim.dat): +-- Date Rev Code ghdl ise Target Comment +-- 2011-11-25 295 - -.-- - - -:-- +-- +-- Revision History: +-- Date Rev Version Comment +-- 2015-02-06 643 1.1 use tb_nexys4_cram now +-- 2013-09-22 432 1.0 Initial version (cloned from _n3) +------------------------------------------------------------------------------ + +configuration tb_w11a_n4 of tb_nexys4_cram is + + for sim + for all : nexys4_cram_aif + use entity work.sys_w11a_n4; + end for; + end for; + +end tb_w11a_n4; diff --git a/rtl/sys_gen/w11a/nexys4/tb/tb_w11a_n4_ssim.vbom b/rtl/sys_gen/w11a/nexys4/tb/tb_w11a_n4_ssim.vbom new file mode 100644 index 00000000..5b80ea27 --- /dev/null +++ b/rtl/sys_gen/w11a/nexys4/tb/tb_w11a_n4_ssim.vbom @@ -0,0 +1,6 @@ +# configure for _*sim case +# Note: this tb uses sys_w11a_n4.vbom in local directory +# (not in .. as usual) to allow a tb specific configure !!! +nexys4_cram_aif = sys_w11a_n4_ssim.vhd +tb_w11a_n4.vbom +@top:tb_w11a_n4 diff --git a/rtl/sys_gen/w11a/nexys4/tb/tbw.dat b/rtl/sys_gen/w11a/nexys4/tb/tbw.dat new file mode 100644 index 00000000..60e323ef --- /dev/null +++ b/rtl/sys_gen/w11a/nexys4/tb/tbw.dat @@ -0,0 +1,6 @@ +# $Id: tbw.dat 535 2013-09-29 11:46:25Z mueller $ +# +[tb_w11a_n4] +rlink_cext_fifo_rx = +rlink_cext_fifo_tx = +rlink_cext_conf = diff --git a/rtl/sys_gen/w11a/s3board/Makefile b/rtl/sys_gen/w11a/s3board/Makefile index 7346ae69..2ed49bba 100644 --- a/rtl/sys_gen/w11a/s3board/Makefile +++ b/rtl/sys_gen/w11a/s3board/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -13,7 +13,7 @@ VBOM_all = $(wildcard *.vbom) BIT_all = $(VBOM_all:.vbom=.bit) # -include $(RETROBASE)/rtl/make/xflow_default_s3board.mk +include $(RETROBASE)/rtl/make_ise/xflow_default_s3board.mk # .PHONY : all clean # @@ -29,8 +29,8 @@ sys_w11a_s3.mcs : sys_w11a_s3.bit # #---- # -include $(RETROBASE)/rtl/make/generic_xflow.mk -include $(RETROBASE)/rtl/make/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vbom b/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vbom index 0ba13bac..2d4a9ce8 100644 --- a/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vbom +++ b/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vbom @@ -28,7 +28,11 @@ sys_conf = sys_conf.vhd ../../../ibus/ib_sres_or_2.vbom ../../../ibus/ibdr_minisys.vbom ../../../ibus/ibdr_maxisys.vbom -[ghdl,isim]../../../w11a/pdp11_tmu_sb.vbom +../../../vlib/rlink/ioleds_sp1c.vbom +../../../w11a/pdp11_statleds.vbom +../../../w11a/pdp11_ledmux.vbom +../../../w11a/pdp11_dspmux.vbom +[sim]../../../w11a/pdp11_tmu_sb.vbom # design sys_w11a_s3.vhd @ucf_cpp: sys_w11a_s3.ucf diff --git a/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd b/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd index acd5c620..05217f38 100644 --- a/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd +++ b/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd @@ -1,6 +1,6 @@ --- $Id: sys_w11a_s3.vhd 620 2014-12-25 10:48:35Z mueller $ +-- $Id: sys_w11a_s3.vhd 652 2015-02-28 12:18:08Z mueller $ -- --- Copyright 2007-2014 by Walter F.J. Mueller +-- Copyright 2007-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -31,6 +31,10 @@ -- ibus/ib_sres_or_2 -- ibus/ibdr_minisys -- ibus/ibdr_maxisys +-- vlib/rlink/ioleds_sp1c +-- w11a/pdp11_statleds +-- w11a/pdp11_ledmux +-- w11a/pdp11_dspmux -- w11a/pdp11_tmu_sb [sim only] -- -- Test bench: tb/tb_sys_w11a_s3 @@ -40,6 +44,7 @@ -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri +-- 2015-02-21 649 14.7 131013 xc3s1000-4 1643 5124 318 3176 OK: +RL11 -- 2014-12-22 619 14.7 131013 xc3s1000-4 1569 4768 302 2994 OK: +rbmon -- 2014-12-20 614 14.7 131013 xc3s1000-4 1455 4523 302 2807 OK: -RL11,rlv4 -- 2014-06-08 561 14.7 131013 xc3s1000-4 1374 4580 286 2776 OK: +RL11 @@ -78,6 +83,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2015-02-21 649 1.7 use ioleds_sp1c,pdp11_(statleds,ledmux,dspmux) -- 2014-12-24 620 1.6.2 relocate ibus window and hio rbus address -- 2014-12-22 619 1.6.1 add rbus monitor rbd_rbmon -- 2014-08-28 588 1.6 use new rlink v4 iface and 4 bit STAT @@ -134,23 +140,37 @@ -- -- Usage of S3BOARD Switches, Buttons, LEDs: -- --- SWI(7:2): no function (only connected to sn_humanio_rbus) --- SWI(1): 1 enable XON --- SWI(0): 0 -> main board RS232 port +-- SWI(7:6): no function (only connected to sn_humanio_rbus) +-- (5:4): select DSP +-- 00 abclkdiv & abclkdiv_f +-- 01 PC +-- 10 DISPREG +-- 11 DR emulation +-- (3): select LED display +-- 0 overall status +-- 1 DR emulation +-- (2) 0 -> int/ext RS242 port for rlink +-- 1 -> use USB interface for rlink +-- (1): 1 enable XON +-- (0): 0 -> main board RS232 port -- 1 -> Pmod B/top RS232 port --- --- LED(7) MEM_ACT_W --- (6) MEM_ACT_R --- (5) cmdbusy (all rlink access, mostly rdma) --- (4:0): if cpugo=1 show cpu mode activity +-- +-- LEDs if SWI(3) = 1 +-- (7:0) DR emulation; shows R0(lower 8 bits) during wait like 11/45+70 +-- +-- LEDs if SWI(3) = 0 +-- (7) MEM_ACT_W +-- (6) MEM_ACT_R +-- (5) cmdbusy (all rlink access, mostly rdma) +-- (4:0) if cpugo=1 show cpu mode activity -- (4) kernel mode, pri>0 -- (3) kernel mode, pri=0 -- (2) kernel mode, wait -- (1) supervisor mode -- (0) user mode -- if cpugo=0 shows cpurust --- (3:0) cpurust code -- (4) '1' +-- (3:0) cpurust code -- -- DP(3): not SER_MONI.txok (shows tx back preasure) -- DP(2): SER_MONI.txact (shows tx activity) @@ -274,6 +294,8 @@ architecture syn of sys_w11a_s3 is signal DM_STAT_SY : dm_stat_sy_type := dm_stat_sy_init; signal DISPREG : slv16 := (others=>'0'); + signal STATLEDS : slv8 := (others=>'0'); + signal ABCLKDIV : slv16 := (others=>'0'); constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0004: 1111 1110 1111 00xx @@ -404,7 +426,7 @@ begin CP_DOUT => CP_DOUT ); - CORE : pdp11_core + W11A : pdp11_core port map ( CLK => CLK, RESET => CPU_RESET, @@ -565,43 +587,44 @@ begin EI_VECT => EI_VECT, DISPREG => DISPREG); end generate IBD_MAXI; - - DSP_DAT(15 downto 0) <= DISPREG; - DSP_DP(3) <= not SER_MONI.txok; - DSP_DP(2) <= SER_MONI.txact; - DSP_DP(1) <= not SER_MONI.rxok; - DSP_DP(0) <= SER_MONI.rxact; + LED_IO : ioleds_sp1c + port map ( + SER_MONI => SER_MONI, + IOLEDS => DSP_DP + ); + + LED_CPU : pdp11_statleds + port map ( + MEM_ACT_R => MEM_ACT_R, + MEM_ACT_W => MEM_ACT_W, + CP_STAT => CP_STAT, + DM_STAT_DP => DM_STAT_DP, + STATLEDS => STATLEDS + ); - proc_led: process (MEM_ACT_W, MEM_ACT_R, CP_STAT, DM_STAT_DP.psw) - variable iled : slv8 := (others=>'0'); - begin - iled := (others=>'0'); - iled(7) := MEM_ACT_W; - iled(6) := MEM_ACT_R; - iled(5) := CP_STAT.cmdbusy; - if CP_STAT.cpugo = '1' then - case DM_STAT_DP.psw.cmode is - when c_psw_kmode => - if CP_STAT.cpuwait = '1' then - iled(2) := '1'; - elsif unsigned(DM_STAT_DP.psw.pri) = 0 then - iled(3) := '1'; - else - iled(4) := '1'; - end if; - when c_psw_smode => - iled(1) := '1'; - when c_psw_umode => - iled(0) := '1'; - when others => null; - end case; - else - iled(4) := '1'; - iled(3 downto 0) := CP_STAT.cpurust; - end if; - LED <= iled; - end process; + LED_MUX : pdp11_ledmux + generic map ( + LWIDTH => LED'length) + port map ( + SEL => SWI(3), + STATLEDS => STATLEDS, + DM_STAT_DP => DM_STAT_DP, + LED => LED + ); + + ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f; + + DSP_MUX : pdp11_dspmux + generic map ( + DCWIDTH => 2) + port map ( + SEL => SWI(5 downto 4), + ABCLKDIV => ABCLKDIV, + DM_STAT_DP => DM_STAT_DP, + DISPREG => DISPREG, + DSP_DAT => DSP_DAT + ); -- synthesis translate_off DM_STAT_SY.emmreq <= EM_MREQ; diff --git a/rtl/sys_gen/w11a/s3board/tb/Makefile b/rtl/sys_gen/w11a/s3board/tb/Makefile index 6e29026f..8812136b 100644 --- a/rtl/sys_gen/w11a/s3board/tb/Makefile +++ b/rtl/sys_gen/w11a/s3board/tb/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -9,7 +9,7 @@ # EXE_all = tb_w11a_s3 # -include $(RETROBASE)/rtl/make/xflow_default_s3board.mk +include $(RETROBASE)/rtl/make_ise/xflow_default_s3board.mk # .PHONY : all all_ssim all_tsim clean # @@ -21,8 +21,8 @@ clean : ise_clean ghdl_clean # #----- # -include $(RETROBASE)/rtl/make/generic_ghdl.mk -include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/vlib/comlib/Makefile b/rtl/vlib/comlib/Makefile index 8bdb06e1..e485ad29 100644 --- a/rtl/vlib/comlib/Makefile +++ b/rtl/vlib/comlib/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 575 2014-07-27 20:55:41Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -14,7 +14,7 @@ NGC_all = $(VBOM_all:.vbom=.ngc) ifndef XTW_BOARD XTW_BOARD=nexys3 endif -include $(RETROBASE)/rtl/make/xflow_default_$(XTW_BOARD).mk +include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # .PHONY : all clean # @@ -24,7 +24,7 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/vlib/comlib/byte2cdata.vhd b/rtl/vlib/comlib/byte2cdata.vhd index 7e4d58a5..2c7d558a 100644 --- a/rtl/vlib/comlib/byte2cdata.vhd +++ b/rtl/vlib/comlib/byte2cdata.vhd @@ -1,4 +1,4 @@ --- $Id: byte2cdata.vhd 596 2014-10-17 19:50:07Z mueller $ +-- $Id: byte2cdata.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2007-2014 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/vlib/comlib/byte2word.vhd b/rtl/vlib/comlib/byte2word.vhd index ab3a5618..58b18945 100644 --- a/rtl/vlib/comlib/byte2word.vhd +++ b/rtl/vlib/comlib/byte2word.vhd @@ -1,4 +1,4 @@ --- $Id: byte2word.vhd 432 2011-11-25 20:16:28Z mueller $ +-- $Id: byte2word.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 12.1; ghdl 0.29 +-- Tool versions: xst 12.1-14.7; ghdl 0.29-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/vlib/comlib/cdata2byte.vhd b/rtl/vlib/comlib/cdata2byte.vhd index a5da5798..be899e23 100644 --- a/rtl/vlib/comlib/cdata2byte.vhd +++ b/rtl/vlib/comlib/cdata2byte.vhd @@ -1,4 +1,4 @@ --- $Id: cdata2byte.vhd 596 2014-10-17 19:50:07Z mueller $ +-- $Id: cdata2byte.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2007-2014 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/vlib/comlib/comlib.vhd b/rtl/vlib/comlib/comlib.vhd index 88eb9bae..7bae519e 100644 --- a/rtl/vlib/comlib/comlib.vhd +++ b/rtl/vlib/comlib/comlib.vhd @@ -1,4 +1,4 @@ --- $Id: comlib.vhd 596 2014-10-17 19:50:07Z mueller $ +-- $Id: comlib.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2007-2014 by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: communication components -- -- Dependencies: - --- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2014-09-27 595 1.6 add crc16 (using CRC-CCITT polynomial) diff --git a/rtl/vlib/comlib/crc16.vhd b/rtl/vlib/comlib/crc16.vhd index 7c76063f..c9748424 100644 --- a/rtl/vlib/comlib/crc16.vhd +++ b/rtl/vlib/comlib/crc16.vhd @@ -1,4 +1,4 @@ --- $Id: crc16.vhd 595 2014-09-28 08:47:45Z mueller $ +-- $Id: crc16.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2014- by Walter F.J. Mueller -- @@ -20,7 +20,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 14.7; ghdl 0.31 +-- Tool versions: ise 14.7; viv 2014.4; ghdl 0.31 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri diff --git a/rtl/vlib/comlib/misc/Makefile b/rtl/vlib/comlib/misc/Makefile index f12ee764..39d27be3 100644 --- a/rtl/vlib/comlib/misc/Makefile +++ b/rtl/vlib/comlib/misc/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 595 2014-09-28 08:47:45Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -17,7 +17,7 @@ clean : ghdl_clean # #----- # -include $(RETROBASE)/rtl/make/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/vlib/comlib/tb/Makefile b/rtl/vlib/comlib/tb/Makefile index 645b2eef..19553ccb 100644 --- a/rtl/vlib/comlib/tb/Makefile +++ b/rtl/vlib/comlib/tb/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 596 2014-10-17 19:50:07Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -10,7 +10,7 @@ EXE_all = tb_cdata2byte ifndef XTW_BOARD XTW_BOARD=nexys3 endif -include $(RETROBASE)/rtl/make/xflow_default_$(XTW_BOARD).mk +include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # .PHONY : all all_ssim all_tsim clean # @@ -22,9 +22,9 @@ clean : ise_clean ghdl_clean isim_clean # #----- # -include $(RETROBASE)/rtl/make/generic_ghdl.mk -include $(RETROBASE)/rtl/make/generic_isim.mk -include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_isim.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/vlib/comlib/word2byte.vhd b/rtl/vlib/comlib/word2byte.vhd index cb0e4be7..715e367b 100644 --- a/rtl/vlib/comlib/word2byte.vhd +++ b/rtl/vlib/comlib/word2byte.vhd @@ -1,4 +1,4 @@ --- $Id: word2byte.vhd 432 2011-11-25 20:16:28Z mueller $ +-- $Id: word2byte.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 12.1; ghdl 0.29 +-- Tool versions: xst 12.1-14.7; ghdl 0.29-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/vlib/genlib/Makefile b/rtl/vlib/genlib/Makefile index f5dbbdc0..43a3a7c2 100644 --- a/rtl/vlib/genlib/Makefile +++ b/rtl/vlib/genlib/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 575 2014-07-27 20:55:41Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -15,7 +15,7 @@ NGC_all = $(VBOM_all:.vbom=.ngc) ifndef XTW_BOARD XTW_BOARD=nexys3 endif -include $(RETROBASE)/rtl/make/xflow_default_$(XTW_BOARD).mk +include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # .PHONY : all clean # @@ -25,7 +25,7 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/vlib/genlib/cdc_pulse.vhd b/rtl/vlib/genlib/cdc_pulse.vhd index 014ee0e9..4bf2b0d4 100644 --- a/rtl/vlib/genlib/cdc_pulse.vhd +++ b/rtl/vlib/genlib/cdc_pulse.vhd @@ -1,4 +1,4 @@ --- $Id: cdc_pulse.vhd 426 2011-11-18 18:14:08Z mueller $ +-- $Id: cdc_pulse.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 13.1; ghdl 0.29 +-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-11-09 422 1.0 Initial version diff --git a/rtl/vlib/genlib/clkdivce.vhd b/rtl/vlib/genlib/clkdivce.vhd index 75e9fed9..ce012bd8 100644 --- a/rtl/vlib/genlib/clkdivce.vhd +++ b/rtl/vlib/genlib/clkdivce.vhd @@ -1,4 +1,4 @@ --- $Id: clkdivce.vhd 418 2011-10-23 20:11:40Z mueller $ +-- $Id: clkdivce.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2007-2011 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-10-22 418 1.0.3 now numeric_std clean diff --git a/rtl/vlib/genlib/debounce_gen.vhd b/rtl/vlib/genlib/debounce_gen.vhd index fb86d190..8b7490d0 100644 --- a/rtl/vlib/genlib/debounce_gen.vhd +++ b/rtl/vlib/genlib/debounce_gen.vhd @@ -1,4 +1,4 @@ --- $Id: debounce_gen.vhd 418 2011-10-23 20:11:40Z mueller $ +-- $Id: debounce_gen.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2007-2011 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: tb/tb_debounce_gen -- Target Devices: generic --- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-10-22 418 1.0.3 now numeric_std clean diff --git a/rtl/vlib/genlib/genlib.vhd b/rtl/vlib/genlib/genlib.vhd index 206b23d1..94762984 100644 --- a/rtl/vlib/genlib/genlib.vhd +++ b/rtl/vlib/genlib/genlib.vhd @@ -1,4 +1,4 @@ --- $Id: genlib.vhd 466 2012-12-30 13:26:55Z mueller $ +-- $Id: genlib.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2007-2012 by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: some general purpose components -- -- Dependencies: - --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 13.3; ghdl 0.18-0.29 +-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2012-12-29 466 1.0.9 add led_pulse_stretch diff --git a/rtl/vlib/genlib/gray2bin_gen.vhd b/rtl/vlib/genlib/gray2bin_gen.vhd index 884ad14f..5619a72a 100644 --- a/rtl/vlib/genlib/gray2bin_gen.vhd +++ b/rtl/vlib/genlib/gray2bin_gen.vhd @@ -1,4 +1,4 @@ --- $Id: gray2bin_gen.vhd 418 2011-10-23 20:11:40Z mueller $ +-- $Id: gray2bin_gen.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2007- by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: tb/tb_debounce_gen -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2007-12-26 106 1.0 Initial version diff --git a/rtl/vlib/genlib/gray_cnt_4.vhd b/rtl/vlib/genlib/gray_cnt_4.vhd index 2d5cabaa..6dcdd2ef 100644 --- a/rtl/vlib/genlib/gray_cnt_4.vhd +++ b/rtl/vlib/genlib/gray_cnt_4.vhd @@ -1,4 +1,4 @@ --- $Id: gray_cnt_4.vhd 418 2011-10-23 20:11:40Z mueller $ +-- $Id: gray_cnt_4.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2007- by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2007-12-26 106 1.0 Initial version diff --git a/rtl/vlib/genlib/gray_cnt_5.vhd b/rtl/vlib/genlib/gray_cnt_5.vhd index d58a8b57..48b929c8 100644 --- a/rtl/vlib/genlib/gray_cnt_5.vhd +++ b/rtl/vlib/genlib/gray_cnt_5.vhd @@ -1,4 +1,4 @@ --- $Id: gray_cnt_5.vhd 418 2011-10-23 20:11:40Z mueller $ +-- $Id: gray_cnt_5.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2007- by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2007-12-26 106 1.0 Initial version diff --git a/rtl/vlib/genlib/gray_cnt_gen.vhd b/rtl/vlib/genlib/gray_cnt_gen.vhd index 036b04ec..49984112 100644 --- a/rtl/vlib/genlib/gray_cnt_gen.vhd +++ b/rtl/vlib/genlib/gray_cnt_gen.vhd @@ -1,4 +1,4 @@ --- $Id: gray_cnt_gen.vhd 418 2011-10-23 20:11:40Z mueller $ +-- $Id: gray_cnt_gen.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2007- by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2007-12-26 106 1.0 Initial version diff --git a/rtl/vlib/genlib/gray_cnt_n.vhd b/rtl/vlib/genlib/gray_cnt_n.vhd index abf859d7..b88906d2 100644 --- a/rtl/vlib/genlib/gray_cnt_n.vhd +++ b/rtl/vlib/genlib/gray_cnt_n.vhd @@ -1,4 +1,4 @@ --- $Id: gray_cnt_n.vhd 418 2011-10-23 20:11:40Z mueller $ +-- $Id: gray_cnt_n.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2007- by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: tb/tb_debounce_gen -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2007-12-26 106 1.0 Initial version diff --git a/rtl/vlib/genlib/led_pulse_stretch.vhd b/rtl/vlib/genlib/led_pulse_stretch.vhd index c75a58ce..c55bd1d0 100644 --- a/rtl/vlib/genlib/led_pulse_stretch.vhd +++ b/rtl/vlib/genlib/led_pulse_stretch.vhd @@ -1,4 +1,4 @@ --- $Id: led_pulse_stretch.vhd 466 2012-12-30 13:26:55Z mueller $ +-- $Id: led_pulse_stretch.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2012- by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 13.3; ghdl 0.29 +-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31 -- Revision History: -- Date Rev Version Comment -- 2012-12-29 466 1.0 Initial version diff --git a/rtl/vlib/memlib/Makefile b/rtl/vlib/memlib/Makefile index b9914607..40e69a25 100644 --- a/rtl/vlib/memlib/Makefile +++ b/rtl/vlib/memlib/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 575 2014-07-27 20:55:41Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -14,7 +14,7 @@ NGC_all = $(VBOM_all:.vbom=.ngc) ifndef XTW_BOARD XTW_BOARD=nexys3 endif -include $(RETROBASE)/rtl/make/xflow_default_$(XTW_BOARD).mk +include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # .PHONY : all clean # @@ -24,7 +24,7 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/vlib/memlib/fifo_1c_dram.vhd b/rtl/vlib/memlib/fifo_1c_dram.vhd index 70c86b49..7ef3d1ce 100644 --- a/rtl/vlib/memlib/fifo_1c_dram.vhd +++ b/rtl/vlib/memlib/fifo_1c_dram.vhd @@ -1,4 +1,4 @@ --- $Id: fifo_1c_dram.vhd 421 2011-11-07 21:23:50Z mueller $ +-- $Id: fifo_1c_dram.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2007- by Walter F.J. Mueller -- @@ -20,7 +20,7 @@ -- -- Test bench: tb/tb_fifo_1c_dram -- Target Devices: generic Spartan, Virtex --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2007-06-06 49 1.0 Initial version diff --git a/rtl/vlib/memlib/fifo_1c_dram_raw.vbom b/rtl/vlib/memlib/fifo_1c_dram_raw.vbom index 2f470174..8b308895 100644 --- a/rtl/vlib/memlib/fifo_1c_dram_raw.vbom +++ b/rtl/vlib/memlib/fifo_1c_dram_raw.vbom @@ -2,7 +2,7 @@ ../slvtypes.vhd memlib.vhd # components -[ghdl,isim]ram_1swar_1ar_gen.vbom -[xst]ram_1swar_1ar_gen_unisim.vbom +[sim]ram_1swar_1ar_gen.vbom +[xst,vsyn]ram_1swar_1ar_gen_unisim.vbom # design fifo_1c_dram_raw.vhd diff --git a/rtl/vlib/memlib/fifo_1c_dram_raw.vhd b/rtl/vlib/memlib/fifo_1c_dram_raw.vhd index de5ec030..9acd32fd 100644 --- a/rtl/vlib/memlib/fifo_1c_dram_raw.vhd +++ b/rtl/vlib/memlib/fifo_1c_dram_raw.vhd @@ -1,4 +1,4 @@ --- $Id: fifo_1c_dram_raw.vhd 421 2011-11-07 21:23:50Z mueller $ +-- $Id: fifo_1c_dram_raw.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2007-2011 by Walter F.J. Mueller -- @@ -20,7 +20,7 @@ -- -- Test bench: tb/tb_fifo_1c_dram -- Target Devices: generic Spartan, Virtex --- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-11-07 421 1.0.2 now numeric_std clean diff --git a/rtl/vlib/memlib/fifo_2c_dram.vbom b/rtl/vlib/memlib/fifo_2c_dram.vbom index 884fa514..acd26333 100644 --- a/rtl/vlib/memlib/fifo_2c_dram.vbom +++ b/rtl/vlib/memlib/fifo_2c_dram.vbom @@ -3,8 +3,8 @@ ../genlib/genlib.vhd memlib.vhd # components -[ghdl,isim]ram_1swar_1ar_gen.vbom -[xst]ram_1swar_1ar_gen_unisim.vbom +[sim]ram_1swar_1ar_gen.vbom +[xst,vsyn]ram_1swar_1ar_gen_unisim.vbom ../genlib/gray_cnt_gen.vbom ../genlib/gray2bin_gen.vbom # design diff --git a/rtl/vlib/memlib/fifo_2c_dram.vhd b/rtl/vlib/memlib/fifo_2c_dram.vhd index 6307c3dc..6aaf487e 100644 --- a/rtl/vlib/memlib/fifo_2c_dram.vhd +++ b/rtl/vlib/memlib/fifo_2c_dram.vhd @@ -1,4 +1,4 @@ --- $Id: fifo_2c_dram.vhd 424 2011-11-13 16:38:23Z mueller $ +-- $Id: fifo_2c_dram.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2007-2011 by Walter F.J. Mueller -- @@ -22,7 +22,7 @@ -- -- Test bench: tb/tb_fifo_2c_dram -- Target Devices: generic Spartan, Virtex --- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-11-13 424 1.1 use capture+sync flops; reset now glitch free diff --git a/rtl/vlib/memlib/memlib.vhd b/rtl/vlib/memlib/memlib.vhd index c05c0428..6344c69b 100644 --- a/rtl/vlib/memlib/memlib.vhd +++ b/rtl/vlib/memlib/memlib.vhd @@ -1,4 +1,4 @@ --- $Id: memlib.vhd 424 2011-11-13 16:38:23Z mueller $ +-- $Id: memlib.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2006-2007 by Walter F.J. Mueller -- @@ -17,7 +17,7 @@ -- asynchronus rams; Fifo's. -- -- Dependencies: - --- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2008-03-08 123 1.0.3 add ram_2swsr_xfirst_gen_unisim diff --git a/rtl/vlib/memlib/ram_1swar_1ar_gen.vhd b/rtl/vlib/memlib/ram_1swar_1ar_gen.vhd index 110cf1cc..0afc422f 100644 --- a/rtl/vlib/memlib/ram_1swar_1ar_gen.vhd +++ b/rtl/vlib/memlib/ram_1swar_1ar_gen.vhd @@ -1,4 +1,4 @@ --- $Id: ram_1swar_1ar_gen.vhd 422 2011-11-10 18:44:06Z mueller $ +-- $Id: ram_1swar_1ar_gen.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2006-2011 by Walter F.J. Mueller -- @@ -22,7 +22,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic Spartan, Virtex --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-11-08 422 1.0.2 now numeric_std clean diff --git a/rtl/vlib/memlib/ram_1swar_1ar_gen_unisim.vhd b/rtl/vlib/memlib/ram_1swar_1ar_gen_unisim.vhd index 1f29f14b..d46694b6 100644 --- a/rtl/vlib/memlib/ram_1swar_1ar_gen_unisim.vhd +++ b/rtl/vlib/memlib/ram_1swar_1ar_gen_unisim.vhd @@ -1,4 +1,4 @@ --- $Id: ram_1swar_1ar_gen_unisim.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: ram_1swar_1ar_gen_unisim.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2008-2010 by Walter F.J. Mueller -- @@ -20,7 +20,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic Spartan, Virtex --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2010-06-03 300 1.1 add hack for AW=5 for Spartan's diff --git a/rtl/vlib/memlib/ram_1swar_gen.vhd b/rtl/vlib/memlib/ram_1swar_gen.vhd index ac1459f4..e73d2df4 100644 --- a/rtl/vlib/memlib/ram_1swar_gen.vhd +++ b/rtl/vlib/memlib/ram_1swar_gen.vhd @@ -1,4 +1,4 @@ --- $Id: ram_1swar_gen.vhd 422 2011-11-10 18:44:06Z mueller $ +-- $Id: ram_1swar_gen.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2006-2011 by Walter F.J. Mueller -- @@ -22,7 +22,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic Spartan, Virtex --- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-11-08 422 1.0.2 now numeric_std clean diff --git a/rtl/vlib/memlib/ram_1swar_gen_unisim.vhd b/rtl/vlib/memlib/ram_1swar_gen_unisim.vhd index 4e46c80c..a264f489 100644 --- a/rtl/vlib/memlib/ram_1swar_gen_unisim.vhd +++ b/rtl/vlib/memlib/ram_1swar_gen_unisim.vhd @@ -1,4 +1,4 @@ --- $Id: ram_1swar_gen_unisim.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: ram_1swar_gen_unisim.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2008- by Walter F.J. Mueller -- @@ -20,7 +20,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic Spartan, Virtex --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2008-03-08 123 1.0.1 use shorter label names diff --git a/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd b/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd index 7bae823d..ee9f3044 100644 --- a/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd +++ b/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd @@ -1,4 +1,4 @@ --- $Id: ram_1swsr_wfirst_gen.vhd 422 2011-11-10 18:44:06Z mueller $ +-- $Id: ram_1swsr_wfirst_gen.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2006-2011 by Walter F.J. Mueller -- @@ -27,7 +27,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic Spartan, Virtex --- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-11-08 422 1.0.4 now numeric_std clean diff --git a/rtl/vlib/memlib/ram_1swsr_wfirst_gen_unisim.vhd b/rtl/vlib/memlib/ram_1swsr_wfirst_gen_unisim.vhd index 68c16d38..7eafdfd1 100644 --- a/rtl/vlib/memlib/ram_1swsr_wfirst_gen_unisim.vhd +++ b/rtl/vlib/memlib/ram_1swsr_wfirst_gen_unisim.vhd @@ -1,4 +1,4 @@ --- $Id: ram_1swsr_wfirst_gen_unisim.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: ram_1swsr_wfirst_gen_unisim.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2008- by Walter F.J. Mueller -- @@ -20,7 +20,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: Spartan-3, Virtex-2,-4 --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2008-03-08 123 1.0 Initial version diff --git a/rtl/vlib/memlib/ram_1swsr_xfirst_gen_unisim.vhd b/rtl/vlib/memlib/ram_1swsr_xfirst_gen_unisim.vhd index d43a6549..541c2f79 100644 --- a/rtl/vlib/memlib/ram_1swsr_xfirst_gen_unisim.vhd +++ b/rtl/vlib/memlib/ram_1swsr_xfirst_gen_unisim.vhd @@ -1,4 +1,4 @@ --- $Id: ram_1swsr_xfirst_gen_unisim.vhd 406 2011-08-14 21:06:44Z mueller $ +-- $Id: ram_1swsr_xfirst_gen_unisim.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2008-2011 by Walter F.J. Mueller -- @@ -19,7 +19,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: Spartan-3, Virtex-2,-4 --- Tool versions: xst 8.1, 8.2, 9.1, 9.2,.., 13.1; ghdl 0.18-0.25 +-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-08-14 406 1.0.2 cleaner code for L_DI initialization diff --git a/rtl/vlib/memlib/ram_2swsr_rfirst_gen.vhd b/rtl/vlib/memlib/ram_2swsr_rfirst_gen.vhd index 59e43e1a..f8702916 100644 --- a/rtl/vlib/memlib/ram_2swsr_rfirst_gen.vhd +++ b/rtl/vlib/memlib/ram_2swsr_rfirst_gen.vhd @@ -1,4 +1,4 @@ --- $Id: ram_2swsr_rfirst_gen.vhd 422 2011-11-10 18:44:06Z mueller $ +-- $Id: ram_2swsr_rfirst_gen.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2006-2011 by Walter F.J. Mueller -- @@ -22,7 +22,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic Spartan, Virtex --- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-11-08 422 1.0.4 now numeric_std clean diff --git a/rtl/vlib/memlib/ram_2swsr_rfirst_gen_unisim.vhd b/rtl/vlib/memlib/ram_2swsr_rfirst_gen_unisim.vhd index 7cfbff1b..a7d2e135 100644 --- a/rtl/vlib/memlib/ram_2swsr_rfirst_gen_unisim.vhd +++ b/rtl/vlib/memlib/ram_2swsr_rfirst_gen_unisim.vhd @@ -1,4 +1,4 @@ --- $Id: ram_2swsr_rfirst_gen_unisim.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: ram_2swsr_rfirst_gen_unisim.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2008- by Walter F.J. Mueller -- @@ -20,7 +20,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: Spartan-3, Virtex-2,-4 --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2008-03-08 123 1.1 use now ram_2swsr_xfirst_gen_unisim diff --git a/rtl/vlib/memlib/ram_2swsr_wfirst_gen.vhd b/rtl/vlib/memlib/ram_2swsr_wfirst_gen.vhd index c4e0e035..b5b7f1af 100644 --- a/rtl/vlib/memlib/ram_2swsr_wfirst_gen.vhd +++ b/rtl/vlib/memlib/ram_2swsr_wfirst_gen.vhd @@ -1,4 +1,4 @@ --- $Id: ram_2swsr_wfirst_gen.vhd 422 2011-11-10 18:44:06Z mueller $ +-- $Id: ram_2swsr_wfirst_gen.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2006-2011 by Walter F.J. Mueller -- @@ -22,7 +22,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic Spartan, Virtex --- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-11-08 422 1.0.4 now numeric_std clean diff --git a/rtl/vlib/memlib/ram_2swsr_wfirst_gen_unisim.vhd b/rtl/vlib/memlib/ram_2swsr_wfirst_gen_unisim.vhd index 19008942..3262e377 100644 --- a/rtl/vlib/memlib/ram_2swsr_wfirst_gen_unisim.vhd +++ b/rtl/vlib/memlib/ram_2swsr_wfirst_gen_unisim.vhd @@ -1,4 +1,4 @@ --- $Id: ram_2swsr_wfirst_gen_unisim.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: ram_2swsr_wfirst_gen_unisim.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2008- by Walter F.J. Mueller -- @@ -20,7 +20,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: Spartan-3, Virtex-2,-4 --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2008-03-08 123 1.1 use now ram_2swsr_xfirst_gen_unisim diff --git a/rtl/vlib/memlib/ram_2swsr_xfirst_gen_unisim.vhd b/rtl/vlib/memlib/ram_2swsr_xfirst_gen_unisim.vhd index a522b635..8a316b73 100644 --- a/rtl/vlib/memlib/ram_2swsr_xfirst_gen_unisim.vhd +++ b/rtl/vlib/memlib/ram_2swsr_xfirst_gen_unisim.vhd @@ -1,4 +1,4 @@ --- $Id: ram_2swsr_xfirst_gen_unisim.vhd 406 2011-08-14 21:06:44Z mueller $ +-- $Id: ram_2swsr_xfirst_gen_unisim.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2008-2011 by Walter F.J. Mueller -- @@ -19,7 +19,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: Spartan-3, Virtex-2,-4 --- Tool versions: xst 8.1, 8.2, 9.1, 9.2,.., 13.1; ghdl 0.18-0.25 +-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-08-14 406 1.0.2 cleaner code for L_DI(A|B) initialization diff --git a/rtl/vlib/rbus/Makefile b/rtl/vlib/rbus/Makefile index 93b27d98..c9425e0e 100644 --- a/rtl/vlib/rbus/Makefile +++ b/rtl/vlib/rbus/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 575 2014-07-27 20:55:41Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -14,7 +14,7 @@ NGC_all = $(VBOM_all:.vbom=.ngc) ifndef XTW_BOARD XTW_BOARD=nexys3 endif -include $(RETROBASE)/rtl/make/xflow_default_$(XTW_BOARD).mk +include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # .PHONY : all clean # @@ -24,7 +24,7 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/vlib/rbus/rb_sel.vhd b/rtl/vlib/rbus/rb_sel.vhd index a0cc6488..9b103d84 100644 --- a/rtl/vlib/rbus/rb_sel.vhd +++ b/rtl/vlib/rbus/rb_sel.vhd @@ -1,4 +1,4 @@ --- $Id: rb_sel.vhd 583 2014-08-16 07:40:12Z mueller $ +-- $Id: rb_sel.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2010-2014 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 12.1-14.7; ghdl 0.29-0.31 +-- Tool versions: ise 12.1-14.7; viv 2014.4; ghdl 0.29-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/vlib/rbus/rb_sres_or_2.vbom b/rtl/vlib/rbus/rb_sres_or_2.vbom index 31f92bd1..5851caf8 100644 --- a/rtl/vlib/rbus/rb_sres_or_2.vbom +++ b/rtl/vlib/rbus/rb_sres_or_2.vbom @@ -2,6 +2,6 @@ ../slvtypes.vhd rblib.vhd # components -[ghdl,isim]rb_sres_or_mon.vbom +[sim]rb_sres_or_mon.vbom # design rb_sres_or_2.vhd diff --git a/rtl/vlib/rbus/rb_sres_or_2.vhd b/rtl/vlib/rbus/rb_sres_or_2.vhd index 3bd7e651..ee2c4ed8 100644 --- a/rtl/vlib/rbus/rb_sres_or_2.vhd +++ b/rtl/vlib/rbus/rb_sres_or_2.vhd @@ -1,4 +1,4 @@ --- $Id: rb_sres_or_2.vhd 343 2010-12-05 21:24:38Z mueller $ +-- $Id: rb_sres_or_2.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2008-2010 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: rb_sres_or_mon [sim only] -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29 +-- Tool versions: ise 8.114.7; viv 2014.4; ghdl 0.18-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/vlib/rbus/rb_sres_or_3.vbom b/rtl/vlib/rbus/rb_sres_or_3.vbom index 51df0b70..e008a480 100644 --- a/rtl/vlib/rbus/rb_sres_or_3.vbom +++ b/rtl/vlib/rbus/rb_sres_or_3.vbom @@ -2,6 +2,6 @@ ../slvtypes.vhd rblib.vhd # components -[ghdl,isim]rb_sres_or_mon.vbom +[sim]rb_sres_or_mon.vbom # design rb_sres_or_3.vhd diff --git a/rtl/vlib/rbus/rb_sres_or_3.vhd b/rtl/vlib/rbus/rb_sres_or_3.vhd index 0824bfa1..f45ba645 100644 --- a/rtl/vlib/rbus/rb_sres_or_3.vhd +++ b/rtl/vlib/rbus/rb_sres_or_3.vhd @@ -1,4 +1,4 @@ --- $Id: rb_sres_or_3.vhd 343 2010-12-05 21:24:38Z mueller $ +-- $Id: rb_sres_or_3.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2008-2010 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: rb_sres_or_mon [sim only] -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29 +-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/vlib/rbus/rb_sres_or_4.vbom b/rtl/vlib/rbus/rb_sres_or_4.vbom index 0c30996d..6b75ad03 100644 --- a/rtl/vlib/rbus/rb_sres_or_4.vbom +++ b/rtl/vlib/rbus/rb_sres_or_4.vbom @@ -2,6 +2,6 @@ ../slvtypes.vhd rblib.vhd # components -[ghdl,isim]rb_sres_or_mon.vbom +[sim]rb_sres_or_mon.vbom # design rb_sres_or_4.vhd diff --git a/rtl/vlib/rbus/rb_sres_or_4.vhd b/rtl/vlib/rbus/rb_sres_or_4.vhd index 6eb4ca5a..4e8a79ae 100644 --- a/rtl/vlib/rbus/rb_sres_or_4.vhd +++ b/rtl/vlib/rbus/rb_sres_or_4.vhd @@ -1,4 +1,4 @@ --- $Id: rb_sres_or_4.vhd 343 2010-12-05 21:24:38Z mueller $ +-- $Id: rb_sres_or_4.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2008-2010 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: rb_sres_or_mon [sim only] -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.114.7; ghdl 0.18-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/vlib/rbus/rb_sres_or_mon.vhd b/rtl/vlib/rbus/rb_sres_or_mon.vhd index ca394454..0159de83 100644 --- a/rtl/vlib/rbus/rb_sres_or_mon.vhd +++ b/rtl/vlib/rbus/rb_sres_or_mon.vhd @@ -1,4 +1,4 @@ --- $Id: rb_sres_or_mon.vhd 347 2010-12-24 12:10:42Z mueller $ +-- $Id: rb_sres_or_mon.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2010- by Walter F.J. Mueller -- @@ -17,7 +17,7 @@ -- -- Dependencies: - -- Test bench: - --- Tool versions: ghdl 0.29 +-- Tool versions: ghdl 0.29-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/vlib/rbus/rbd_bram.vbom b/rtl/vlib/rbus/rbd_bram.vbom index deb1eff0..18c13613 100644 --- a/rtl/vlib/rbus/rbd_bram.vbom +++ b/rtl/vlib/rbus/rbd_bram.vbom @@ -3,7 +3,7 @@ ../memlib/memlib.vhd rblib.vhd # components -[ghdl,isim]../memlib/ram_1swsr_wfirst_gen.vbom -[xst]../memlib/ram_1swsr_wfirst_gen_unisim.vbom +[sim]../memlib/ram_1swsr_wfirst_gen.vbom +[xst,vsyn]../memlib/ram_1swsr_wfirst_gen_unisim.vbom # design rbd_bram.vhd diff --git a/rtl/vlib/rbus/rbd_eyemon.vbom b/rtl/vlib/rbus/rbd_eyemon.vbom index 7234d91f..ccbe7584 100644 --- a/rtl/vlib/rbus/rbd_eyemon.vbom +++ b/rtl/vlib/rbus/rbd_eyemon.vbom @@ -3,7 +3,7 @@ ../memlib/memlib.vhd rblib.vhd # components -[ghdl,isim]../memlib/ram_2swsr_wfirst_gen.vbom -[xst]../memlib/ram_2swsr_wfirst_gen_unisim.vbom +[sim]../memlib/ram_2swsr_wfirst_gen.vbom +[xst,vsyn]../memlib/ram_2swsr_wfirst_gen_unisim.vbom # design rbd_eyemon.vhd diff --git a/rtl/vlib/rbus/rbd_rbmon.vbom b/rtl/vlib/rbus/rbd_rbmon.vbom index 822bb17e..7acdae02 100644 --- a/rtl/vlib/rbus/rbd_rbmon.vbom +++ b/rtl/vlib/rbus/rbd_rbmon.vbom @@ -3,7 +3,7 @@ ../memlib/memlib.vhd rblib.vhd # components -[ghdl,isim]../memlib/ram_1swsr_wfirst_gen.vbom -[xst]../memlib/ram_1swsr_wfirst_gen_unisim.vbom +[sim]../memlib/ram_1swsr_wfirst_gen.vbom +[xst,vsyn]../memlib/ram_1swsr_wfirst_gen_unisim.vbom # design rbd_rbmon.vhd diff --git a/rtl/vlib/rbus/rblib.vhd b/rtl/vlib/rbus/rblib.vhd index 5552cfab..dda567fb 100644 --- a/rtl/vlib/rbus/rblib.vhd +++ b/rtl/vlib/rbus/rblib.vhd @@ -1,4 +1,4 @@ --- $Id: rblib.vhd 593 2014-09-14 22:21:33Z mueller $ +-- $Id: rblib.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2007-2014 by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Definitions for rbus interface and bus entities -- -- Dependencies: - --- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/vlib/rlink/Makefile b/rtl/vlib/rlink/Makefile index 93cacabd..c9425e0e 100644 --- a/rtl/vlib/rlink/Makefile +++ b/rtl/vlib/rlink/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 582 2014-08-14 21:37:51Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -14,7 +14,7 @@ NGC_all = $(VBOM_all:.vbom=.ngc) ifndef XTW_BOARD XTW_BOARD=nexys3 endif -include $(RETROBASE)/rtl/make/xflow_default_$(XTW_BOARD).mk +include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # .PHONY : all clean # @@ -24,7 +24,7 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/vlib/rlink/ioleds_sp1c.vbom b/rtl/vlib/rlink/ioleds_sp1c.vbom new file mode 100644 index 00000000..b751048d --- /dev/null +++ b/rtl/vlib/rlink/ioleds_sp1c.vbom @@ -0,0 +1,7 @@ +# libs +../slvtypes.vhd +../rlink/rlinklib.vbom +../serport/serportlib.vbom +# components +# design +ioleds_sp1c.vhd diff --git a/rtl/vlib/rlink/ioleds_sp1c.vhd b/rtl/vlib/rlink/ioleds_sp1c.vhd new file mode 100644 index 00000000..b4e755fa --- /dev/null +++ b/rtl/vlib/rlink/ioleds_sp1c.vhd @@ -0,0 +1,55 @@ +-- $Id: ioleds_sp1c.vhd 649 2015-02-21 21:10:16Z mueller $ +-- +-- Copyright 2015- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: ioleds_sp1c - syn +-- Description: io activity leds for rlink+serport_1clk combo +-- +-- Dependencies: - +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: xst 17.7; viv 2014.4; ghdl 0.31 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2015-02-21 649 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.rlinklib.all; +use work.serportlib.all; + +entity ioleds_sp1c is -- io activity leds for rlink_sp1c + port ( + SER_MONI : in serport_moni_type; -- ser: monitor port + IOLEDS : out slv4 -- 4 bit IO monitor (e.g. for DSP_DP) + ); +end entity ioleds_sp1c; + + +architecture syn of ioleds_sp1c is + +begin + + -- currently very minimal implementation + IOLEDS(3) <= not SER_MONI.txok; + IOLEDS(2) <= SER_MONI.txact; + IOLEDS(1) <= not SER_MONI.rxok; + IOLEDS(0) <= SER_MONI.rxact; + +end syn; diff --git a/rtl/vlib/rlink/rlink_core.vbom b/rtl/vlib/rlink/rlink_core.vbom index b238d108..2c147f36 100644 --- a/rtl/vlib/rlink/rlink_core.vbom +++ b/rtl/vlib/rlink/rlink_core.vbom @@ -5,13 +5,13 @@ ../rbus/rblib.vhd rlinklib.vbom # components -[ghdl,isim]../memlib/ram_2swsr_rfirst_gen.vbom -[xst]../memlib/ram_2swsr_rfirst_gen_unisim.vbom +[sim]../memlib/ram_2swsr_rfirst_gen.vbom +[xst,vsyn]../memlib/ram_2swsr_rfirst_gen_unisim.vbom ../memlib/fifo_1c_dram.vbom ../comlib/crc16.vbom ../rbus/rb_sel.vbom ../rbus/rb_sres_or_2.vbom -[ghdl,isim]rlink_mon_sb.vbom -[ghdl,isim]../rbus/rb_mon_sb.vbom +[sim]rlink_mon_sb.vbom +[sim]../rbus/rb_mon_sb.vbom # design rlink_core.vhd diff --git a/rtl/vlib/rlink/rlink_core.vhd b/rtl/vlib/rlink/rlink_core.vhd index bd533448..e65f4d72 100644 --- a/rtl/vlib/rlink/rlink_core.vhd +++ b/rtl/vlib/rlink/rlink_core.vhd @@ -1,4 +1,4 @@ --- $Id: rlink_core.vhd 620 2014-12-25 10:48:35Z mueller $ +-- $Id: rlink_core.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2007-2014 by Walter F.J. Mueller -- @@ -28,7 +28,7 @@ -- tb/tb_rlink_tba_ttcombo -- -- Target Devices: generic --- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri diff --git a/rtl/vlib/rlink/rlink_core8.vbom b/rtl/vlib/rlink/rlink_core8.vbom index dd26930c..288526a0 100644 --- a/rtl/vlib/rlink/rlink_core8.vbom +++ b/rtl/vlib/rlink/rlink_core8.vbom @@ -7,6 +7,6 @@ rlinklib.vbom rlink_core.vbom ../comlib/byte2cdata.vbom ../comlib/cdata2byte.vbom -[ghdl,isim]rlink_mon_sb.vbom +[sim]rlink_mon_sb.vbom # design rlink_core8.vhd diff --git a/rtl/vlib/rlink/rlink_core8.vhd b/rtl/vlib/rlink/rlink_core8.vhd index 4d1aa57b..9f1a4a80 100644 --- a/rtl/vlib/rlink/rlink_core8.vhd +++ b/rtl/vlib/rlink/rlink_core8.vhd @@ -1,4 +1,4 @@ --- $Id: rlink_core8.vhd 612 2014-12-20 08:12:06Z mueller $ +-- $Id: rlink_core8.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2011-2014 by Walter F.J. Mueller -- @@ -23,7 +23,7 @@ -- Test bench: - -- -- Target Devices: generic --- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 +-- Tool versions: ise 13.1-14.7; viv 2014.4; ghdl 0.29-0.31 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri diff --git a/rtl/vlib/rlink/rlink_mon_sb.vhd b/rtl/vlib/rlink/rlink_mon_sb.vhd index f37b0cd0..08f7e248 100644 --- a/rtl/vlib/rlink/rlink_mon_sb.vhd +++ b/rtl/vlib/rlink/rlink_mon_sb.vhd @@ -1,4 +1,4 @@ --- $Id: rlink_mon_sb.vhd 444 2011-12-25 10:04:58Z mueller $ +-- $Id: rlink_mon_sb.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2007-2011 by Walter F.J. Mueller -- @@ -19,7 +19,7 @@ -- simlib/simclkcnt -- rlink_mon -- Test bench: - --- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/vlib/rlink/rlink_rlbmux.vhd b/rtl/vlib/rlink/rlink_rlbmux.vhd index 6d16b771..74a145e9 100644 --- a/rtl/vlib/rlink/rlink_rlbmux.vhd +++ b/rtl/vlib/rlink/rlink_rlbmux.vhd @@ -1,4 +1,4 @@ --- $Id: rlink_rlbmux.vhd 466 2012-12-30 13:26:55Z mueller $ +-- $Id: rlink_rlbmux.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2012- by Walter F.J. Mueller -- @@ -17,7 +17,7 @@ -- -- Dependencies: - -- Test bench: - --- Tool versions: xst 13.3; ghdl 0.29 +-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/vlib/rlink/rlink_sp1c.vhd b/rtl/vlib/rlink/rlink_sp1c.vhd index 3973fb71..1c98e496 100644 --- a/rtl/vlib/rlink/rlink_sp1c.vhd +++ b/rtl/vlib/rlink/rlink_sp1c.vhd @@ -1,4 +1,4 @@ --- $Id: rlink_sp1c.vhd 610 2014-12-09 22:44:43Z mueller $ +-- $Id: rlink_sp1c.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2011-2014 by Walter F.J. Mueller -- @@ -21,7 +21,7 @@ -- Test bench: - -- -- Target Devices: generic --- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 +-- Tool versions: ise 13.1-14.7; viv 2014.4; ghdl 0.29-0.31 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri ifa ofa diff --git a/rtl/vlib/rlink/rlinklib.vhd b/rtl/vlib/rlink/rlinklib.vhd index eaeb6567..ae435648 100644 --- a/rtl/vlib/rlink/rlinklib.vhd +++ b/rtl/vlib/rlink/rlinklib.vhd @@ -1,6 +1,6 @@ --- $Id: rlinklib.vhd 617 2014-12-21 14:18:53Z mueller $ +-- $Id: rlinklib.vhd 649 2015-02-21 21:10:16Z mueller $ -- --- Copyright 2007-2014 by Walter F.J. Mueller +-- Copyright 2007-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,10 +16,11 @@ -- Description: Definitions for rlink interface and bus entities -- -- Dependencies: - --- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- -- Revision History: -- Date Rev Version Comment +-- 2014-02-21 649 4.1.1 add ioleds_sp1c -- 2014-12-21 617 4.1 use stat(2) to signal rbus timeout -- 2014-10-12 596 4.0 now rlink v4.0 iface, 4 bit STAT -- 2014-08-15 583 3.5 rb_mreq addr now 16 bit @@ -245,6 +246,16 @@ component rlink_sp1c is -- rlink_core8+serport_1clock combo ); end component; +-- +-- io activity leds +-- +component ioleds_sp1c -- io activity leds for rlink_sp1c + port ( + SER_MONI : in serport_moni_type; -- ser: monitor port + IOLEDS : out slv4 -- 4 bit IO monitor (e.g. for DSP_DP) + ); +end component; + -- -- components for use in test benches (not synthesizable) -- diff --git a/rtl/vlib/rlink/tb/Makefile b/rtl/vlib/rlink/tb/Makefile index 96283ca4..a42dfe3a 100644 --- a/rtl/vlib/rlink/tb/Makefile +++ b/rtl/vlib/rlink/tb/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 575 2014-07-27 20:55:41Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -18,7 +18,7 @@ EXE_all += tb_rlink_sp1c ifndef XTW_BOARD XTW_BOARD=nexys3 endif -include $(RETROBASE)/rtl/make/xflow_default_$(XTW_BOARD).mk +include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # .PHONY : all all_ssim all_tsim clean # @@ -30,9 +30,9 @@ clean : ise_clean ghdl_clean isim_clean # #----- # -include $(RETROBASE)/rtl/make/generic_ghdl.mk -include $(RETROBASE)/rtl/make/generic_isim.mk -include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_isim.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/vlib/rlink/tb/rlink_cext_vhpi.vhd b/rtl/vlib/rlink/tb/rlink_cext_vhpi.vhd index d54ea6fe..f8a6a787 100644 --- a/rtl/vlib/rlink/tb/rlink_cext_vhpi.vhd +++ b/rtl/vlib/rlink/tb/rlink_cext_vhpi.vhd @@ -1,4 +1,4 @@ --- $Id: rlink_cext_vhpi.vhd 389 2011-07-07 21:59:00Z mueller $ +-- $Id: rlink_cext_vhpi.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2007-2010 by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: VHDL procedural interface: VHDL declaration side -- -- Dependencies: - --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2010-12-29 351 1.1 rename vhpi_rriext->rlink_cext_vhpi; new rbv3 names diff --git a/rtl/vlib/rlink/tb/tbcore_rlink.vhd b/rtl/vlib/rlink/tb/tbcore_rlink.vhd index f3145831..c7325836 100644 --- a/rtl/vlib/rlink/tb/tbcore_rlink.vhd +++ b/rtl/vlib/rlink/tb/tbcore_rlink.vhd @@ -1,4 +1,4 @@ --- $Id: tbcore_rlink.vhd 469 2013-01-05 12:29:44Z mueller $ +-- $Id: tbcore_rlink.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2010-2013 by Walter F.J. Mueller -- @@ -20,7 +20,7 @@ -- To test: generic, any rlink_cext based target -- -- Target Devices: generic --- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29 +-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31 -- Revision History: -- Date Rev Version Comment -- 2013-01-04 469 3.1.2 use 1ns wait for .sinit to allow simbus debugging diff --git a/rtl/vlib/serport/Makefile b/rtl/vlib/serport/Makefile index b6518b05..bd2bb47c 100644 --- a/rtl/vlib/serport/Makefile +++ b/rtl/vlib/serport/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 575 2014-07-27 20:55:41Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -14,7 +14,7 @@ NGC_all = $(VBOM_all:.vbom=.ngc) ifndef XTW_BOARD XTW_BOARD=nexys3 endif -include $(RETROBASE)/rtl/make/xflow_default_$(XTW_BOARD).mk +include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # .PHONY : all clean # @@ -24,7 +24,7 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/vlib/serport/serport_1clock.vhd b/rtl/vlib/serport/serport_1clock.vhd index 8794a63d..d1a920e4 100644 --- a/rtl/vlib/serport/serport_1clock.vhd +++ b/rtl/vlib/serport/serport_1clock.vhd @@ -1,6 +1,6 @@ --- $Id: serport_1clock.vhd 476 2013-01-26 22:23:53Z mueller $ +-- $Id: serport_1clock.vhd 641 2015-02-01 22:12:15Z mueller $ -- --- Copyright 2011- by Walter F.J. Mueller +-- Copyright 2011-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -21,7 +21,7 @@ -- memlib/fifo_1c_dram -- Test bench: - -- Target Devices: generic --- Tool versions: xst 13.1; ghdl 0.29 +-- Tool versions: ise 13.1-14.7; viv 2014.4; ghdl 0.29-0.31 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri @@ -29,6 +29,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2015-02-01 641 1.1 add CLKDIV_F for autobaud; -- 2011-12-10 438 1.0.2 internal reset on abact -- 2011-12-09 437 1.0.1 rename stat->moni port -- 2011-11-13 424 1.0 Initial version @@ -99,6 +100,7 @@ architecture syn of serport_1clock is signal ABACT : slbit := '0'; signal ABDONE : slbit := '0'; signal ABCLKDIV : slv(CDWIDTH-1 downto 0) := (others=>'0'); + signal ABCLKDIV_F : slv3 := (others=>'0'); signal TXOK : slbit := '0'; signal RXOK : slbit := '0'; @@ -114,21 +116,22 @@ begin CDWIDTH => CDWIDTH, CDINIT => CDINIT) port map ( - CLK => CLK, - CE_MSEC => CE_MSEC, - RESET => RESET, - RXSD => RXSD, - RXDATA => UART_RXDATA, - RXVAL => UART_RXVAL, - RXERR => RXERR, - RXACT => RXACT, - TXSD => TXSD, - TXDATA => UART_TXDATA, - TXENA => UART_TXENA, - TXBUSY => UART_TXBUSY, - ABACT => ABACT, - ABDONE => ABDONE, - ABCLKDIV => ABCLKDIV + CLK => CLK, + CE_MSEC => CE_MSEC, + RESET => RESET, + RXSD => RXSD, + RXDATA => UART_RXDATA, + RXVAL => UART_RXVAL, + RXERR => RXERR, + RXACT => RXACT, + TXSD => TXSD, + TXDATA => UART_TXDATA, + TXENA => UART_TXENA, + TXBUSY => UART_TXBUSY, + ABACT => ABACT, + ABDONE => ABDONE, + ABCLKDIV => ABCLKDIV, + ABCLKDIV_F => ABCLKDIV_F ); RESET_INT <= RESET or ABACT; @@ -241,10 +244,11 @@ begin MONI.rxok <= RXOK; MONI.txok <= TXOK; - proc_abclkdiv: process (ABCLKDIV) + proc_abclkdiv: process (ABCLKDIV, ABCLKDIV_F) begin MONI.abclkdiv <= (others=>'0'); MONI.abclkdiv(ABCLKDIV'range) <= ABCLKDIV; + MONI.abclkdiv_f <= ABCLKDIV_F; end process proc_abclkdiv; end syn; diff --git a/rtl/vlib/serport/serport_2clock.vhd b/rtl/vlib/serport/serport_2clock.vhd index 1944ca62..7f12b95a 100644 --- a/rtl/vlib/serport/serport_2clock.vhd +++ b/rtl/vlib/serport/serport_2clock.vhd @@ -1,6 +1,6 @@ --- $Id: serport_2clock.vhd 476 2013-01-26 22:23:53Z mueller $ +-- $Id: serport_2clock.vhd 641 2015-02-01 22:12:15Z mueller $ -- --- Copyright 2011- by Walter F.J. Mueller +-- Copyright 2011-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -22,7 +22,7 @@ -- memlib/fifo_2c_dram -- Test bench: - -- Target Devices: generic --- Tool versions: xst 13.1; ghdl 0.29 +-- Tool versions: ise 13.1-14.7; ghdl 0.29-0.31 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri @@ -30,6 +30,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2015-02-01 641 1.1 add CLKDIV_F for autobaud; -- 2011-12-10 438 1.0.2 internal reset on abact -- 2011-12-09 437 1.0.1 rename stat->moni port -- 2011-11-13 424 1.0 Initial version @@ -175,21 +176,22 @@ begin CDWIDTH => CDWIDTH, CDINIT => CDINIT) port map ( - CLK => CLKS, - CE_MSEC => CES_MSEC, - RESET => RESET_CLKS, - RXSD => RXSD, - RXDATA => UART_RXDATA, - RXVAL => UART_RXVAL, - RXERR => RXERR, - RXACT => RXACT, - TXSD => TXSD, - TXDATA => UART_TXDATA, - TXENA => UART_TXENA, - TXBUSY => UART_TXBUSY, - ABACT => ABACT, - ABDONE => ABDONE, - ABCLKDIV => ABCLKDIV + CLK => CLKS, + CE_MSEC => CES_MSEC, + RESET => RESET_CLKS, + RXSD => RXSD, + RXDATA => UART_RXDATA, + RXVAL => UART_RXVAL, + RXERR => RXERR, + RXACT => RXACT, + TXSD => TXSD, + TXDATA => UART_TXDATA, + TXENA => UART_TXENA, + TXBUSY => UART_TXBUSY, + ABACT => ABACT, + ABDONE => ABDONE, + ABCLKDIV => ABCLKDIV, + ABCLKDIV_F => open ); RESET_INT <= RESET_CLKS or ABACT; diff --git a/rtl/vlib/serport/serport_uart_autobaud.vhd b/rtl/vlib/serport/serport_uart_autobaud.vhd index 6098a65f..f07895b7 100644 --- a/rtl/vlib/serport/serport_uart_autobaud.vhd +++ b/rtl/vlib/serport/serport_uart_autobaud.vhd @@ -1,6 +1,6 @@ --- $Id: serport_uart_autobaud.vhd 417 2011-10-22 10:30:29Z mueller $ +-- $Id: serport_uart_autobaud.vhd 641 2015-02-01 22:12:15Z mueller $ -- --- Copyright 2007-2011 by Walter F.J. Mueller +-- Copyright 2007-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,9 +18,10 @@ -- Dependencies: - -- Test bench: tb/tb_serport_autobaud -- Target Devices: generic --- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 13.1; ghdl 0.18-0.29 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment +-- 2015-02-01 641 1.1 add CLKDIV_F -- 2011-10-22 417 1.0.4 now numeric_std clean -- 2010-04-18 279 1.0.3 change ccnt start value to -3, better rounding -- 2007-10-14 89 1.0.2 all instantiation with CDINIT=0 @@ -44,6 +45,7 @@ entity serport_uart_autobaud is -- serial port uart: autobauder RESET : in slbit; -- reset RXSD : in slbit; -- receive serial data (uart view) CLKDIV : out slv(CDWIDTH-1 downto 0); -- clock divider setting + CLKDIV_F: out slv3; -- clock divider fractional part ACT : out slbit; -- active; if 1 clkdiv is invalid DONE : out slbit -- resync done ); @@ -163,11 +165,12 @@ begin when others => null; -- ----------------------------------- end case; - N_REGS <= n; + N_REGS <= n; - CLKDIV <= r.ccnt(CDWIDTH-1+3 downto 3); - ACT <= iact or RESET; - DONE <= idone; + CLKDIV <= r.ccnt(CDWIDTH-1+3 downto 3); + CLKDIV_F <= r.ccnt(2 downto 0); + ACT <= iact or RESET; + DONE <= idone; end process proc_next; diff --git a/rtl/vlib/serport/serport_uart_rx.vhd b/rtl/vlib/serport/serport_uart_rx.vhd index 71e4a2da..8adb456c 100644 --- a/rtl/vlib/serport/serport_uart_rx.vhd +++ b/rtl/vlib/serport/serport_uart_rx.vhd @@ -1,4 +1,4 @@ --- $Id: serport_uart_rx.vhd 421 2011-11-07 21:23:50Z mueller $ +-- $Id: serport_uart_rx.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2007-2011 by Walter F.J. Mueller -- @@ -24,7 +24,7 @@ -- Dependencies: - -- Test bench: tb/tb_serport_uart_rxtx -- Target Devices: generic --- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-10-22 417 2.0.3 now numeric_std clean diff --git a/rtl/vlib/serport/serport_uart_rxtx.vhd b/rtl/vlib/serport/serport_uart_rxtx.vhd index fb6d006b..8facfbff 100644 --- a/rtl/vlib/serport/serport_uart_rxtx.vhd +++ b/rtl/vlib/serport/serport_uart_rxtx.vhd @@ -1,4 +1,4 @@ --- $Id: serport_uart_rxtx.vhd 476 2013-01-26 22:23:53Z mueller $ +-- $Id: serport_uart_rxtx.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2007-2011 by Walter F.J. Mueller -- @@ -19,7 +19,7 @@ -- serport_uart_tx -- Test bench: tb/tb_serport_uart_rxtx -- Target Devices: generic --- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 13.1; ghdl 0.18-0.29 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2007-06-24 60 1.0 Initial version diff --git a/rtl/vlib/serport/serport_uart_rxtx_ab.vhd b/rtl/vlib/serport/serport_uart_rxtx_ab.vhd index 67fd43f2..1b60bff2 100644 --- a/rtl/vlib/serport/serport_uart_rxtx_ab.vhd +++ b/rtl/vlib/serport/serport_uart_rxtx_ab.vhd @@ -1,6 +1,6 @@ --- $Id: serport_uart_rxtx_ab.vhd 476 2013-01-26 22:23:53Z mueller $ +-- $Id: serport_uart_rxtx_ab.vhd 641 2015-02-01 22:12:15Z mueller $ -- --- Copyright 2007-2011 by Walter F.J. Mueller +-- Copyright 2007-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -19,7 +19,7 @@ -- serport_uart_rxtx -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri @@ -27,6 +27,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2015-02-01 641 1.2 add CLKDIV_F for autobaud; -- 2011-10-22 417 1.1.1 now numeric_std clean -- 2010-12-26 348 1.1 add ABCLKDIV port for clock divider setting -- 2007-06-24 60 1.0 Initial version @@ -58,13 +59,15 @@ entity serport_uart_rxtx_ab is -- serial port uart: rx+tx+autobaud TXBUSY : out slbit; -- transmit busy ABACT : out slbit; -- autobaud active; if 1 clkdiv invalid ABDONE : out slbit; -- autobaud resync done - ABCLKDIV : out slv(CDWIDTH-1 downto 0) -- autobaud clock divider setting + ABCLKDIV : out slv(CDWIDTH-1 downto 0); -- autobaud clock divider setting + ABCLKDIV_F : out slv3 -- autobaud clock divider fraction ); end serport_uart_rxtx_ab; architecture syn of serport_uart_rxtx_ab is signal CLKDIV : slv(CDWIDTH-1 downto 0) := slv(to_unsigned(0, CDWIDTH)); + signal CLKDIV_F : slv3 := (others=>'0'); signal ABACT_L : slbit := '0'; -- local readable copy of ABACT signal UART_RESET : slbit := '0'; @@ -75,19 +78,21 @@ begin CDWIDTH => CDWIDTH, CDINIT => CDINIT) port map ( - CLK => CLK, - CE_MSEC => CE_MSEC, - RESET => RESET, - RXSD => RXSD, - CLKDIV => CLKDIV, - ACT => ABACT_L, - DONE => ABDONE + CLK => CLK, + CE_MSEC => CE_MSEC, + RESET => RESET, + RXSD => RXSD, + CLKDIV => CLKDIV, + CLKDIV_F => CLKDIV_F, + ACT => ABACT_L, + DONE => ABDONE ); UART_RESET <= ABACT_L or RESET; ABACT <= ABACT_L; ABCLKDIV <= CLKDIV; - + ABCLKDIV_F <= CLKDIV_F; + RXTX : serport_uart_rxtx generic map ( CDWIDTH => CDWIDTH) diff --git a/rtl/vlib/serport/serport_uart_tx.vhd b/rtl/vlib/serport/serport_uart_tx.vhd index ae43906e..5daeafac 100644 --- a/rtl/vlib/serport/serport_uart_tx.vhd +++ b/rtl/vlib/serport/serport_uart_tx.vhd @@ -1,4 +1,4 @@ --- $Id: serport_uart_tx.vhd 417 2011-10-22 10:30:29Z mueller $ +-- $Id: serport_uart_tx.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2007-2011 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: tb/tb_serport_uart_rxtx -- Target Devices: generic --- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-10-22 417 1.0.4 now numeric_std clean diff --git a/rtl/vlib/serport/serport_xonrx.vhd b/rtl/vlib/serport/serport_xonrx.vhd index 4447e5d9..f2412b25 100644 --- a/rtl/vlib/serport/serport_xonrx.vhd +++ b/rtl/vlib/serport/serport_xonrx.vhd @@ -1,4 +1,4 @@ --- $Id: serport_xonrx.vhd 476 2013-01-26 22:23:53Z mueller $ +-- $Id: serport_xonrx.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 13.1; ghdl 0.29 +-- Tool versions: ise 13.1-14.7; viv 2014.4; ghdl 0.29-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-10-22 417 1.0 Initial version diff --git a/rtl/vlib/serport/serport_xontx.vhd b/rtl/vlib/serport/serport_xontx.vhd index 145ea1a0..980e1c17 100644 --- a/rtl/vlib/serport/serport_xontx.vhd +++ b/rtl/vlib/serport/serport_xontx.vhd @@ -1,4 +1,4 @@ --- $Id: serport_xontx.vhd 476 2013-01-26 22:23:53Z mueller $ +-- $Id: serport_xontx.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 13.1; ghdl 0.29 +-- Tool versions: ise 13.1-14.7; viv 2014.4; ghdl 0.29-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-11-13 425 1.0 Initial version diff --git a/rtl/vlib/serport/serportlib.vhd b/rtl/vlib/serport/serportlib.vhd index ec47be22..b5ac8f22 100644 --- a/rtl/vlib/serport/serportlib.vhd +++ b/rtl/vlib/serport/serportlib.vhd @@ -1,6 +1,6 @@ --- $Id: serportlib.vhd 476 2013-01-26 22:23:53Z mueller $ +-- $Id: serportlib.vhd 641 2015-02-01 22:12:15Z mueller $ -- --- Copyright 2007-2013 by Walter F.J. Mueller +-- Copyright 2007-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,10 +16,11 @@ -- Description: serial port interface components -- -- Dependencies: - --- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- -- Revision History: -- Date Rev Version Comment +-- 2015-02-01 641 1.3 add CLKDIV_F for autobaud; -- 2013-01-26 476 1.2.6 renamed package to serportlib -- 2011-12-09 437 1.2.5 rename stat->moni port -- 2011-10-23 419 1.2.4 remove serport_clkdiv_ consts; @@ -109,7 +110,8 @@ component serport_uart_rxtx_ab is -- serial port uart: rx+tx+autobaud TXBUSY : out slbit; -- transmit busy ABACT : out slbit; -- autobaud active; if 1 clkdiv invalid ABDONE : out slbit; -- autobaud resync done - ABCLKDIV : out slv(CDWIDTH-1 downto 0) -- autobaud clock divider setting + ABCLKDIV : out slv(CDWIDTH-1 downto 0); -- autobaud clock divider setting + ABCLKDIV_F : out slv3 -- autobaud clock divider fraction ); end component; @@ -123,6 +125,7 @@ component serport_uart_autobaud is -- serial port uart: autobauder RESET : in slbit; -- reset RXSD : in slbit; -- receive serial data (uart view) CLKDIV : out slv(CDWIDTH-1 downto 0); -- clock divider setting + CLKDIV_F: out slv3; -- clock divider fractional part ACT : out slbit; -- active; if 1 clkdiv is invalid DONE : out slbit -- resync done ); @@ -169,6 +172,7 @@ type serport_moni_type is record -- serport monitor port abact : slbit; -- autobauder active;if 1 clkdiv invalid abdone : slbit; -- autobauder resync done abclkdiv : slv16; -- autobauder clock divider + abclkdiv_f : slv3; -- autobauder clock divider fraction rxok : slbit; -- rx channel ok txok : slbit; -- tx channel ok end record serport_moni_type; @@ -178,6 +182,7 @@ constant serport_moni_init : serport_moni_type := ( '0','0', -- rxact,txact '0','0', -- abact,abdone (others=>'0'), -- abclkdiv + (others=>'0'), -- abclkdiv_f '0','0' -- rxok,txok ); diff --git a/rtl/vlib/serport/tb/Makefile b/rtl/vlib/serport/tb/Makefile index ee2c35f9..f403fdd7 100644 --- a/rtl/vlib/serport/tb/Makefile +++ b/rtl/vlib/serport/tb/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 575 2014-07-27 20:55:41Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -16,7 +16,7 @@ EXE_all += tb_serport_autobaud ifndef XTW_BOARD XTW_BOARD=nexys3 endif -include $(RETROBASE)/rtl/make/xflow_default_$(XTW_BOARD).mk +include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # .PHONY : all all_ssim all_tsim clean # @@ -28,9 +28,9 @@ clean : ise_clean ghdl_clean isim_clean # #----- # -include $(RETROBASE)/rtl/make/generic_ghdl.mk -include $(RETROBASE)/rtl/make/generic_isim.mk -include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_isim.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/vlib/serport/tb/tbd_serport_autobaud.vhd b/rtl/vlib/serport/tb/tbd_serport_autobaud.vhd index 19f7d799..71641f37 100644 --- a/rtl/vlib/serport/tb/tbd_serport_autobaud.vhd +++ b/rtl/vlib/serport/tb/tbd_serport_autobaud.vhd @@ -1,4 +1,4 @@ --- $Id: tbd_serport_autobaud.vhd 476 2013-01-26 22:23:53Z mueller $ +-- $Id: tbd_serport_autobaud.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2007-2011 by Walter F.J. Mueller -- @@ -34,7 +34,7 @@ -- 2007-10-27 92 8.2.03 I34 xc3s1000-4 153 338 0 178 s 9.45 -- 2007-10-27 92 8.1.03 I27 xc3s1000-4 152 293 0 - s 9.40 -- --- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2008-01-20 112 1.0.1 rename clkgen->clkdivce diff --git a/rtl/vlib/serport/tb/tbd_serport_uart_rx.vhd b/rtl/vlib/serport/tb/tbd_serport_uart_rx.vhd index 56585a48..401a81db 100644 --- a/rtl/vlib/serport/tb/tbd_serport_uart_rx.vhd +++ b/rtl/vlib/serport/tb/tbd_serport_uart_rx.vhd @@ -1,4 +1,4 @@ --- $Id: tbd_serport_uart_rx.vhd 476 2013-01-26 22:23:53Z mueller $ +-- $Id: tbd_serport_uart_rx.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2007-2011 by Walter F.J. Mueller -- @@ -30,7 +30,7 @@ -- 2007-10-27 92 8.2.03 I34 xc3s1000-4 29 90 0 47 s 8.45 -- 2007-10-27 92 8.1.03 I27 xc3s1000-4 31 92 0 - s 8.25 -- --- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2007-10-21 91 1.0 Initial version diff --git a/rtl/vlib/serport/tb/tbd_serport_uart_rxtx.vhd b/rtl/vlib/serport/tb/tbd_serport_uart_rxtx.vhd index 0570e75f..a8b00c2d 100644 --- a/rtl/vlib/serport/tb/tbd_serport_uart_rxtx.vhd +++ b/rtl/vlib/serport/tb/tbd_serport_uart_rxtx.vhd @@ -1,4 +1,4 @@ --- $Id: tbd_serport_uart_rxtx.vhd 476 2013-01-26 22:23:53Z mueller $ +-- $Id: tbd_serport_uart_rxtx.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2007-2011 by Walter F.J. Mueller -- @@ -30,7 +30,7 @@ -- 2007-10-27 92 8.2.03 I34 xc3s1000-4 73 152 0 81 s 9.30 -- 2007-10-27 92 8.1.03 I27 xc3s1000-4 73 125 0 - s 9.30 -- --- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2007-10-21 91 1.0 Initial version diff --git a/rtl/vlib/simlib/simbus.vhd b/rtl/vlib/simlib/simbus.vhd index 66c48f0f..003927a5 100644 --- a/rtl/vlib/simlib/simbus.vhd +++ b/rtl/vlib/simlib/simbus.vhd @@ -1,4 +1,4 @@ --- $Id: simbus.vhd 444 2011-12-25 10:04:58Z mueller $ +-- $Id: simbus.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2007-2011 by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Global signals for support control in test benches -- -- Dependencies: - --- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 13.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-12-23 444 2.0 remove global clock cycle signal diff --git a/rtl/vlib/simlib/simclk.vhd b/rtl/vlib/simlib/simclk.vhd index c6ecdb91..488f206c 100644 --- a/rtl/vlib/simlib/simclk.vhd +++ b/rtl/vlib/simlib/simclk.vhd @@ -1,4 +1,4 @@ --- $Id: simclk.vhd 444 2011-12-25 10:04:58Z mueller $ +-- $Id: simclk.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2007-2011 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/vlib/simlib/simclkcnt.vhd b/rtl/vlib/simlib/simclkcnt.vhd index 6eba7906..4e3a4182 100644 --- a/rtl/vlib/simlib/simclkcnt.vhd +++ b/rtl/vlib/simlib/simclkcnt.vhd @@ -1,4 +1,4 @@ --- $Id: simclkcnt.vhd 444 2011-12-25 10:04:58Z mueller $ +-- $Id: simclkcnt.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 12.1, 13.1; ghdl 0.29 +-- Tool versions: xst 12.1-14.7; ghdl 0.29-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/vlib/slvtypes.vhd b/rtl/vlib/slvtypes.vhd index 15d9c2cf..5021954f 100644 --- a/rtl/vlib/slvtypes.vhd +++ b/rtl/vlib/slvtypes.vhd @@ -1,4 +1,4 @@ --- $Id: slvtypes.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: slvtypes.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2007-2008 by Walter F.J. Mueller -- @@ -20,7 +20,7 @@ -- commonly used (n downto 0) vectors -- -- Dependencies: - --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2008-08-24 162 1.0.4 add slv60 and 64 diff --git a/rtl/vlib/xlib/Makefile b/rtl/vlib/xlib/Makefile index 963471bd..0e34fb72 100644 --- a/rtl/vlib/xlib/Makefile +++ b/rtl/vlib/xlib/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 575 2014-07-27 20:55:41Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version omment @@ -13,7 +13,7 @@ NGC_all = $(VBOM_all:.vbom=.ngc) ifndef XTW_BOARD XTW_BOARD=nexys3 endif -include $(RETROBASE)/rtl/make/xflow_default_$(XTW_BOARD).mk +include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # .PHONY : all clean # @@ -23,7 +23,7 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/vlib/xlib/dcm_sfs_gsim.vhd b/rtl/vlib/xlib/dcm_sfs_gsim.vhd index 75f341fb..089b6f0c 100644 --- a/rtl/vlib/xlib/dcm_sfs_gsim.vhd +++ b/rtl/vlib/xlib/dcm_sfs_gsim.vhd @@ -1,4 +1,4 @@ --- $Id: dcm_sfs_gsim.vhd 426 2011-11-18 18:14:08Z mueller $ +-- $Id: dcm_sfs_gsim.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2010-2011 by Walter F.J. Mueller -- @@ -19,7 +19,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic Spartan-3A,-3E --- Tool versions: xst 12.1, 13.1; ghdl 0.29 +-- Tool versions: xst 12.1-14.7; ghdl 0.29-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/vlib/xlib/dcm_sfs_unisim_s3.vhd b/rtl/vlib/xlib/dcm_sfs_unisim_s3.vhd index d4187e33..db24bc44 100644 --- a/rtl/vlib/xlib/dcm_sfs_unisim_s3.vhd +++ b/rtl/vlib/xlib/dcm_sfs_unisim_s3.vhd @@ -1,4 +1,4 @@ --- $Id: dcm_sfs_unisim_s3.vhd 426 2011-11-18 18:14:08Z mueller $ +-- $Id: dcm_sfs_unisim_s3.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2010-2011 by Walter F.J. Mueller -- @@ -19,7 +19,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic Spartan-3A,-3E --- Tool versions: xst 12.1; ghdl 0.29 +-- Tool versions: xst 12.1-14.7; ghdl 0.29-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/vlib/xlib/dcm_sfs_unisim_s3e.vhd b/rtl/vlib/xlib/dcm_sfs_unisim_s3e.vhd index 9a324fb3..20a4cbb9 100644 --- a/rtl/vlib/xlib/dcm_sfs_unisim_s3e.vhd +++ b/rtl/vlib/xlib/dcm_sfs_unisim_s3e.vhd @@ -1,4 +1,4 @@ --- $Id: dcm_sfs_unisim_s3e.vhd 534 2013-09-22 21:37:24Z mueller $ +-- $Id: dcm_sfs_unisim_s3e.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2010-2011 by Walter F.J. Mueller -- @@ -19,7 +19,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic Spartan-3A,-3E; Spartan-6 --- Tool versions: xst 12.1; ghdl 0.29 +-- Tool versions: xst 12.1-14.7; ghdl 0.29-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/vlib/xlib/iob_keeper_gen.vhd b/rtl/vlib/xlib/iob_keeper_gen.vhd index fabca080..e8a3bf31 100644 --- a/rtl/vlib/xlib/iob_keeper_gen.vhd +++ b/rtl/vlib/xlib/iob_keeper_gen.vhd @@ -1,4 +1,4 @@ --- $Id: iob_keeper_gen.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: iob_keeper_gen.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2010- by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic Spartan, Virtex --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2010-06-03 299 1.1 add explicit R_KEEP and driver diff --git a/rtl/vlib/xlib/iob_reg_i.vhd b/rtl/vlib/xlib/iob_reg_i.vhd index 091cf2a1..774d87a3 100644 --- a/rtl/vlib/xlib/iob_reg_i.vhd +++ b/rtl/vlib/xlib/iob_reg_i.vhd @@ -1,4 +1,4 @@ --- $Id: iob_reg_i.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: iob_reg_i.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2007- by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic Spartan, Virtex --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2007-12-16 101 1.0.1 add INIT generic port diff --git a/rtl/vlib/xlib/iob_reg_i_gen.vhd b/rtl/vlib/xlib/iob_reg_i_gen.vhd index 8024d39a..bec5099a 100644 --- a/rtl/vlib/xlib/iob_reg_i_gen.vhd +++ b/rtl/vlib/xlib/iob_reg_i_gen.vhd @@ -1,4 +1,4 @@ --- $Id: iob_reg_i_gen.vhd 426 2011-11-18 18:14:08Z mueller $ +-- $Id: iob_reg_i_gen.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2007- by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic Spartan, Virtex --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2007-12-16 101 1.0.1 add INIT generic port diff --git a/rtl/vlib/xlib/iob_reg_io_gen.vbom b/rtl/vlib/xlib/iob_reg_io_gen.vbom index 4883f327..4b127b59 100644 --- a/rtl/vlib/xlib/iob_reg_io_gen.vbom +++ b/rtl/vlib/xlib/iob_reg_io_gen.vbom @@ -1,6 +1,6 @@ # libs ../slvtypes.vhd # components -[ghdl,isim]iob_keeper_gen.vbom +[sim]iob_keeper_gen.vbom # design iob_reg_io_gen.vhd diff --git a/rtl/vlib/xlib/iob_reg_io_gen.vhd b/rtl/vlib/xlib/iob_reg_io_gen.vhd index 43166565..b3397553 100644 --- a/rtl/vlib/xlib/iob_reg_io_gen.vhd +++ b/rtl/vlib/xlib/iob_reg_io_gen.vhd @@ -1,4 +1,4 @@ --- $Id: iob_reg_io_gen.vhd 427 2011-11-19 21:04:11Z mueller $ +-- $Id: iob_reg_io_gen.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2007-2008 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: iob_keeper_gen [sim only] -- Test bench: - -- Target Devices: generic Spartan, Virtex --- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2008-05-22 149 1.0.4 use internally TE to match OBUFT T polarity diff --git a/rtl/vlib/xlib/iob_reg_o.vhd b/rtl/vlib/xlib/iob_reg_o.vhd index 94f4cfed..3ddcda1b 100644 --- a/rtl/vlib/xlib/iob_reg_o.vhd +++ b/rtl/vlib/xlib/iob_reg_o.vhd @@ -1,4 +1,4 @@ --- $Id: iob_reg_o.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: iob_reg_o.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2007- by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic Spartan, Virtex --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2007-12-16 101 1.0.1 add INIT generic port diff --git a/rtl/vlib/xlib/iob_reg_o_gen.vhd b/rtl/vlib/xlib/iob_reg_o_gen.vhd index 941d17ad..2e8b7ff0 100644 --- a/rtl/vlib/xlib/iob_reg_o_gen.vhd +++ b/rtl/vlib/xlib/iob_reg_o_gen.vhd @@ -1,4 +1,4 @@ --- $Id: iob_reg_o_gen.vhd 426 2011-11-18 18:14:08Z mueller $ +-- $Id: iob_reg_o_gen.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2007- by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic Spartan, Virtex --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2007-12-16 101 1.0.1 add INIT generic port diff --git a/rtl/vlib/xlib/s6_cmt_sfs_gsim.vhd b/rtl/vlib/xlib/s6_cmt_sfs_gsim.vhd index 8d04bb00..973c24c0 100644 --- a/rtl/vlib/xlib/s6_cmt_sfs_gsim.vhd +++ b/rtl/vlib/xlib/s6_cmt_sfs_gsim.vhd @@ -1,4 +1,4 @@ --- $Id: s6_cmt_sfs_gsim.vhd 556 2014-05-29 19:01:39Z mueller $ +-- $Id: s6_cmt_sfs_gsim.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2013- by Walter F.J. Mueller -- @@ -19,7 +19,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic Spartan-6 --- Tool versions: xst 14.5, 14.6; ghdl 0.29 +-- Tool versions: xst 14.5-14.7; ghdl 0.29-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/vlib/xlib/s6_cmt_sfs_unisim.vhd b/rtl/vlib/xlib/s6_cmt_sfs_unisim.vhd index 90f662a3..d09bfec8 100644 --- a/rtl/vlib/xlib/s6_cmt_sfs_unisim.vhd +++ b/rtl/vlib/xlib/s6_cmt_sfs_unisim.vhd @@ -1,4 +1,4 @@ --- $Id: s6_cmt_sfs_unisim.vhd 601 2014-11-07 22:44:43Z mueller $ +-- $Id: s6_cmt_sfs_unisim.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2013- by Walter F.J. Mueller -- @@ -19,7 +19,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic Spartan-6 --- Tool versions: xst 14.5; ghdl 0.29 +-- Tool versions: xst 14.5-14.7; ghdl 0.29-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/vlib/xlib/s7_cmt_sfs_gsim.vbom b/rtl/vlib/xlib/s7_cmt_sfs_gsim.vbom new file mode 100644 index 00000000..d8590e00 --- /dev/null +++ b/rtl/vlib/xlib/s7_cmt_sfs_gsim.vbom @@ -0,0 +1,4 @@ +# libs +../slvtypes.vhd +# design +s7_cmt_sfs_gsim.vhd diff --git a/rtl/vlib/xlib/s7_cmt_sfs_gsim.vhd b/rtl/vlib/xlib/s7_cmt_sfs_gsim.vhd new file mode 100644 index 00000000..6ab0e228 --- /dev/null +++ b/rtl/vlib/xlib/s7_cmt_sfs_gsim.vhd @@ -0,0 +1,213 @@ +-- $Id: s7_cmt_sfs_gsim.vhd 554 2014-04-21 14:01:51Z mueller $ +-- +-- Copyright 2013- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: s7_cmt_sfs - sim +-- Description: Series-7 CMT for simple frequency synthesis +-- simple vhdl model, without Xilinx UNISIM primitives +-- +-- Dependencies: - +-- Test bench: - +-- Target Devices: generic Series-7 +-- Tool versions: xst 14.5; viv 2014.1; ghdl 0.29 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2013-09-28 535 1.0 Initial version (derived from dcm_sfs_gsim) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +entity s7_cmt_sfs is -- 7-Series CMT for simple freq. synth. + generic ( + VCO_DIVIDE : positive := 1; -- vco clock divide + VCO_MULTIPLY : positive := 1; -- vco clock multiply + OUT_DIVIDE : positive := 1; -- output divide + CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns) + CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps) + STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED + GEN_TYPE : string := "PLL"); -- PLL or MMCM + port ( + CLKIN : in slbit; -- clock input + CLKFX : out slbit; -- clock output (synthesized freq.) + LOCKED : out slbit -- pll/mmcm locked + ); +end s7_cmt_sfs; + + +architecture sim of s7_cmt_sfs is + + signal CLK_DIVPULSE : slbit := '0'; + signal CLKOUT_PERIOD : time := 0 ns; + signal R_CLKOUT : slbit := '0'; + signal R_LOCKED : slbit := '0'; + +begin + + proc_init : process + + -- currently frequency limits taken from Artix-7 speed grade -1 + constant f_vcomin_pll : integer := 800; + constant f_vcomax_pll : integer := 1600; + constant f_pdmin_pll : integer := 19; + constant f_pdmax_pll : integer := 450; + + constant f_vcomin_mmcm : integer := 600; + constant f_vcomax_mmcm : integer := 1200; + constant f_pdmin_mmcm : integer := 10; + constant f_pdmax_mmcm : integer := 450; + + variable t_vco : time := 0 ns; + variable t_vcomin : time := 0 ns; + variable t_vcomax : time := 0 ns; + variable t_pd : time := 0 ns; + variable t_pdmin : time := 0 ns; + variable t_pdmax : time := 0 ns; + + begin + -- validate generics + + + if not (GEN_TYPE = "PLL" or GEN_TYPE = "MMCM") then + assert false + report "assert(GEN_TYPE='PLL' or GEN_TYPE='MMCM')" + severity failure; + end if; + + if VCO_DIVIDE/=1 or VCO_MULTIPLY/=1 or OUT_DIVIDE/=1 then + + if GEN_TYPE = "PLL" then + -- check DIV/MULT parameter range + if VCO_DIVIDE<1 or VCO_DIVIDE>56 or + VCO_MULTIPLY<2 or VCO_MULTIPLY>64 or + OUT_DIVIDE<1 or OUT_DIVIDE>128 + then + assert false + report + "assert(VCO_DIVIDE in 1:56 VCO_MULTIPLY in 2:64 OUT_DIVIDE in 1:128)" + severity failure; + end if; + -- setup VCO and PD range check boundaries + t_vcomin := (1000 ns / f_vcomax_pll) - 1 ps; + t_vcomax := (1000 ns / f_vcomin_pll) + 1 ps; + t_pdmin := (1000 ns / f_pdmax_pll) - 1 ps; + t_pdmax := (1000 ns / f_pdmin_pll) + 1 ps; + + end if; -- GEN_TYPE = "PLL" + + if GEN_TYPE = "MMCM" then + -- check DIV/MULT parameter range + if VCO_DIVIDE<1 or VCO_DIVIDE>106 or + VCO_MULTIPLY<2 or VCO_MULTIPLY>64 or + OUT_DIVIDE<1 or OUT_DIVIDE>128 + then + assert false + report + "assert(VCO_DIVIDE in 1:106 VCO_MULTIPLY in 2:64 OUT_DIVIDE in 1:128)" + severity failure; + end if; + -- setup VCO and PD range check boundaries + t_vcomin := (1000 ns / f_vcomax_pll) - 1 ps; + t_vcomax := (1000 ns / f_vcomin_pll) + 1 ps; + t_pdmin := (1000 ns / f_pdmax_pll) - 1 ps; + t_pdmax := (1000 ns / f_pdmin_pll) + 1 ps; + + end if; -- GEN_TYPE = "MMCM" + + -- now common check whether VCO and PD frequency is in range + t_pd := (1 ps * (1000.0*CLKIN_PERIOD)) * VCO_DIVIDE; + t_vco := t_pd / VCO_MULTIPLY; + + if t_vcot_vcomax then + assert false + report "assert(VCO frequency out of range)" + severity failure; + end if; + + if t_pdt_pdmax then + assert FALSE + report "assert(PD frequency out of range)" + severity failure; + end if; + + end if; -- one factor /= 1 + + wait; + end process proc_init; + + proc_clkin : process (CLKIN) + variable t_lastclkin : time := 0 ns; + variable t_lastperiod : time := 0 ns; + variable t_period : time := 0 ns; + variable nclkin : integer := 1; + begin + + if CLKIN'event then + if CLKIN = '1' then -- if CLKIN rising edge + + if t_lastclkin > 0 ns then + t_lastperiod := t_period; + t_period := now - t_lastclkin; + CLKOUT_PERIOD <= (t_period * VCO_DIVIDE * OUT_DIVIDE) / VCO_MULTIPLY; + if t_lastperiod > 0 ns and abs(t_period-t_lastperiod) > 1 ps then + report "s7_cmt_sp_sfs: CLKIN unstable" severity warning; + end if; + end if; + t_lastclkin := now; + + if t_period > 0 ns then + nclkin := nclkin - 1; + if nclkin <= 0 then + nclkin := VCO_DIVIDE * OUT_DIVIDE; + CLK_DIVPULSE <= '1'; + R_LOCKED <= '1'; + end if; + end if; + + else -- if CLKIN falling edge + CLK_DIVPULSE <= '0'; + end if; + end if; + + end process proc_clkin; + + proc_clkout : process + variable t_lastclkin : time := 0 ns; + variable t_lastperiod : time := 0 ns; + variable t_period : time := 0 ns; + variable nclkin : integer := 1; + begin + + loop + wait until CLK_DIVPULSE = '1'; + + for i in 1 to VCO_MULTIPLY loop + R_CLKOUT <= '1'; + wait for CLKOUT_PERIOD/2; + R_CLKOUT <= '0'; + if i /= VCO_MULTIPLY then + wait for CLKOUT_PERIOD/2; + end if; + end loop; -- i + + end loop; + + end process proc_clkout; + + CLKFX <= R_CLKOUT; + LOCKED <= R_LOCKED; + +end sim; diff --git a/rtl/vlib/xlib/s7_cmt_sfs_unisim.vbom b/rtl/vlib/xlib/s7_cmt_sfs_unisim.vbom new file mode 100644 index 00000000..908b28ba --- /dev/null +++ b/rtl/vlib/xlib/s7_cmt_sfs_unisim.vbom @@ -0,0 +1,5 @@ +# libs +../slvtypes.vhd +@lib:unisim +# design +s7_cmt_sfs_unisim.vhd diff --git a/rtl/vlib/xlib/s7_cmt_sfs_unisim.vhd b/rtl/vlib/xlib/s7_cmt_sfs_unisim.vhd new file mode 100644 index 00000000..cb467a93 --- /dev/null +++ b/rtl/vlib/xlib/s7_cmt_sfs_unisim.vhd @@ -0,0 +1,198 @@ +-- $Id: s7_cmt_sfs_unisim.vhd 641 2015-02-01 22:12:15Z mueller $ +-- +-- Copyright 2013- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: s7_cmt_sfs - syn +-- Description: Series-7 CMT for simple frequency synthesis +-- Direct instantiation of Xilinx UNISIM primitives +-- +-- Dependencies: - +-- Test bench: - +-- Target Devices: generic Series-7 +-- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2013-09-28 535 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +library unisim; +use unisim.vcomponents.ALL; + +use work.slvtypes.all; + +entity s7_cmt_sfs is -- 7-Series CMT for simple freq. synth. + generic ( + VCO_DIVIDE : positive := 1; -- vco clock divide + VCO_MULTIPLY : positive := 1; -- vco clock multiply + OUT_DIVIDE : positive := 1; -- output divide + CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns) + CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps) + STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED + GEN_TYPE : string := "PLL"); -- PLL or MMCM + port ( + CLKIN : in slbit; -- clock input + CLKFX : out slbit; -- clock output (synthesized freq.) + LOCKED : out slbit -- pll/mmcm locked + ); +end s7_cmt_sfs; + + +architecture syn of s7_cmt_sfs is + +begin + + assert GEN_TYPE = "PLL" or GEN_TYPE = "MMCM" + report "assert(GEN_TYPE='PLL' or GEN_TYPE='MMCM')" + severity failure; + + NOGEN: if VCO_DIVIDE=1 and VCO_MULTIPLY=1 and OUT_DIVIDE=1 generate + CLKFX <= CLKIN; + LOCKED <= '1'; + end generate NOGEN; + + USEPLL: if GEN_TYPE = "PLL" and + not(VCO_DIVIDE=1 and VCO_MULTIPLY=1 and OUT_DIVIDE=1) generate + + signal CLKFBOUT : slbit; + signal CLKFBOUT_BUF : slbit; + signal CLKOUT0 : slbit; + signal CLKOUT1_UNUSED : slbit; + signal CLKOUT2_UNUSED : slbit; + signal CLKOUT3_UNUSED : slbit; + signal CLKOUT4_UNUSED : slbit; + signal CLKOUT5_UNUSED : slbit; + signal CLKOUT6_UNUSED : slbit; + + pure function bool2string (val : boolean) return string is + begin + if val then + return "TRUE"; + else + return "FALSE"; + end if; + end function bool2string; + + begin + + PLL : PLLE2_BASE + generic map ( + BANDWIDTH => "OPTIMIZED", + DIVCLK_DIVIDE => VCO_DIVIDE, + CLKFBOUT_MULT => VCO_MULTIPLY, + CLKFBOUT_PHASE => 0.000, + CLKOUT0_DIVIDE => OUT_DIVIDE, + CLKOUT0_PHASE => 0.000, + CLKOUT0_DUTY_CYCLE => 0.500, + CLKIN1_PERIOD => CLKIN_PERIOD, + REF_JITTER1 => CLKIN_JITTER, + STARTUP_WAIT => bool2string(STARTUP_WAIT)) + port map ( + CLKFBOUT => CLKFBOUT, + CLKOUT0 => CLKOUT0, + CLKOUT1 => CLKOUT1_UNUSED, + CLKOUT2 => CLKOUT2_UNUSED, + CLKOUT3 => CLKOUT3_UNUSED, + CLKOUT4 => CLKOUT4_UNUSED, + CLKOUT5 => CLKOUT5_UNUSED, + CLKFBIN => CLKFBOUT_BUF, + CLKIN1 => CLKIN, + LOCKED => LOCKED, + PWRDWN => '0', + RST => '0' + ); + + BUFG_CLKFB : BUFG + port map ( + I => CLKFBOUT, + O => CLKFBOUT_BUF + ); + + BUFG_CLKOUT : BUFG + port map ( + I => CLKOUT0, + O => CLKFX + ); + + end generate USEPLL; + + USEMMCM: if GEN_TYPE = "MMCM" and + not(VCO_DIVIDE=1 and VCO_MULTIPLY=1 and OUT_DIVIDE=1) generate + + signal CLKFBOUT : slbit; + signal CLKFBOUT_BUF : slbit; + signal CLKFBOUTB_UNUSED : slbit; + signal CLKOUT0 : slbit; + signal CLKOUT0B_UNUSED : slbit; + signal CLKOUT1_UNUSED : slbit; + signal CLKOUT1B_UNUSED : slbit; + signal CLKOUT2_UNUSED : slbit; + signal CLKOUT2B_UNUSED : slbit; + signal CLKOUT3_UNUSED : slbit; + signal CLKOUT3B_UNUSED : slbit; + signal CLKOUT4_UNUSED : slbit; + signal CLKOUT5_UNUSED : slbit; + signal CLKOUT6_UNUSED : slbit; + + begin + + MMCM : MMCME2_BASE + generic map ( + BANDWIDTH => "OPTIMIZED", + DIVCLK_DIVIDE => VCO_DIVIDE, + CLKFBOUT_MULT_F => real(VCO_MULTIPLY), + CLKFBOUT_PHASE => 0.000, + CLKOUT0_DIVIDE_F => real(OUT_DIVIDE), + CLKOUT0_PHASE => 0.000, + CLKOUT0_DUTY_CYCLE => 0.500, + CLKIN1_PERIOD => CLKIN_PERIOD, + REF_JITTER1 => CLKIN_JITTER, + STARTUP_WAIT => STARTUP_WAIT) + port map ( + CLKFBOUT => CLKFBOUT, + CLKFBOUTB => CLKFBOUTB_UNUSED, + CLKOUT0 => CLKOUT0, + CLKOUT0B => CLKOUT0B_UNUSED, + CLKOUT1 => CLKOUT1_UNUSED, + CLKOUT1B => CLKOUT1B_UNUSED, + CLKOUT2 => CLKOUT2_UNUSED, + CLKOUT2B => CLKOUT2B_UNUSED, + CLKOUT3 => CLKOUT3_UNUSED, + CLKOUT3B => CLKOUT3B_UNUSED, + CLKOUT4 => CLKOUT4_UNUSED, + CLKOUT5 => CLKOUT5_UNUSED, + CLKFBIN => CLKFBOUT_BUF, + CLKIN1 => CLKIN, + LOCKED => LOCKED, + PWRDWN => '0', + RST => '0' + ); + + BUFG_CLKFB : BUFG + port map ( + I => CLKFBOUT, + O => CLKFBOUT_BUF + ); + + BUFG_CLKOUT : BUFG + port map ( + I => CLKOUT0, + O => CLKFX + ); + + end generate USEMMCM; + +end syn; diff --git a/rtl/vlib/xlib/xlib.vhd b/rtl/vlib/xlib/xlib.vhd index 8c51b39f..7f376dd5 100644 --- a/rtl/vlib/xlib/xlib.vhd +++ b/rtl/vlib/xlib/xlib.vhd @@ -1,4 +1,4 @@ --- $Id: xlib.vhd 538 2013-10-06 17:21:25Z mueller $ +-- $Id: xlib.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2007-2013 by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Xilinx specific components -- -- Dependencies: - --- Tool versions: xst 8.2, 9.1, 9.2, 13.1, 14.5, 14.6; ghdl 0.18-0.29 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2013-10-06 538 1.0.10 add s6_cmt_sfs diff --git a/rtl/w11a/Makefile b/rtl/w11a/Makefile index 04fd8d06..dd701ff8 100644 --- a/rtl/w11a/Makefile +++ b/rtl/w11a/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 575 2014-07-27 20:55:41Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -14,7 +14,7 @@ NGC_all = $(VBOM_all:.vbom=.ngc) ifndef XTW_BOARD XTW_BOARD=nexys3 endif -include $(RETROBASE)/rtl/make/xflow_default_$(XTW_BOARD).mk +include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # .PHONY : all clean # @@ -24,7 +24,7 @@ clean : ise_clean # #---- # -include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_xst) diff --git a/rtl/w11a/pdp11.vhd b/rtl/w11a/pdp11.vhd index 64da78b7..877ffe85 100644 --- a/rtl/w11a/pdp11.vhd +++ b/rtl/w11a/pdp11.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11.vhd 621 2014-12-26 21:20:05Z mueller $ +-- $Id: pdp11.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2006-2014 by Walter F.J. Mueller -- @@ -16,10 +16,12 @@ -- Description: Definitions for pdp11 components -- -- Dependencies: - --- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- -- Revision History: -- Date Rev Version Comment +-- 2015-02-20 649 1.5.3 add pdp11_statleds +-- 2015-02-08 644 1.5.2 add pdp11_bram_memctl -- 2014-08-28 588 1.5.1 use new rlink v4 iface and 4 bit STAT -- 2014-08-15 583 1.5 rb_mreq addr now 16 bit -- 2014-08-10: 581 1.4.10 add c_cc_f_* field defs for condition code array @@ -1080,6 +1082,60 @@ component pdp11_bram is -- BRAM based ext. memory dummy ); end component; +component pdp11_bram_memctl is -- BRAM based memctl + generic ( + MAWIDTH : positive := 4; -- mux address width + NBLOCK : positive := 11); -- write delay in clock cycles + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + REQ : in slbit; -- request + WE : in slbit; -- write enable + BUSY : out slbit; -- controller busy + ACK_R : out slbit; -- acknowledge read + ACK_W : out slbit; -- acknowledge write + ACT_R : out slbit; -- signal active read + ACT_W : out slbit; -- signal active write + ADDR : in slv20; -- address + BE : in slv4; -- byte enable + DI : in slv32; -- data in (memory view) + DO : out slv32 -- data out (memory view) + ); +end component; + +component pdp11_statleds is -- status leds + port ( + MEM_ACT_R : in slbit; -- memory active read + MEM_ACT_W : in slbit; -- memory active write + CP_STAT : in cp_stat_type; -- console port status + DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status + STATLEDS : out slv8 -- 8 bit CPU status + ); +end component; + +component pdp11_ledmux is -- hio led mux + generic ( + LWIDTH : positive := 8); -- led width + port ( + SEL : in slbit; -- select (0=stat;1=dr) + STATLEDS : in slv8; -- 8 bit CPU status + DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status + LED : out slv(LWIDTH-1 downto 0) -- hio leds + ); +end component; + +component pdp11_dspmux is -- hio dsp mux + generic ( + DCWIDTH : positive := 2); -- digit counter width (2 or 3) + port ( + SEL : in slv2; -- select + ABCLKDIV : in slv16; -- serport clock divider + DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status + DISPREG : in slv16; -- display register + DSP_DAT : out slv(4*(2**DCWIDTH)-1 downto 0) -- display data + ); +end component; + component pdp11_core_rbus is -- core to rbus interface generic ( RB_ADDR_CORE : slv16 := slv(to_unsigned(16#0000#,16)); diff --git a/rtl/w11a/pdp11_aunit.vhd b/rtl/w11a/pdp11_aunit.vhd index 03c17878..39aa04ab 100644 --- a/rtl/w11a/pdp11_aunit.vhd +++ b/rtl/w11a/pdp11_aunit.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11_aunit.vhd 581 2014-08-10 21:48:46Z mueller $ +-- $Id: pdp11_aunit.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2006-2014 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2014-08-10 581 1.1.1 use c_cc_f_* diff --git a/rtl/w11a/pdp11_bram.vbom b/rtl/w11a/pdp11_bram.vbom index ec468167..cf52651e 100644 --- a/rtl/w11a/pdp11_bram.vbom +++ b/rtl/w11a/pdp11_bram.vbom @@ -3,7 +3,7 @@ ../vlib/memlib/memlib.vhd pdp11.vbom # components -[ghdl,isim]../vlib/memlib/ram_2swsr_rfirst_gen.vbom -[xst]../vlib/memlib/ram_2swsr_rfirst_gen_unisim.vbom +[sim]../vlib/memlib/ram_2swsr_rfirst_gen.vbom +[xst,vsyn]../vlib/memlib/ram_2swsr_rfirst_gen_unisim.vbom # design pdp11_bram.vhd diff --git a/rtl/w11a/pdp11_bram.vhd b/rtl/w11a/pdp11_bram.vhd index a8144a53..2e7ee518 100644 --- a/rtl/w11a/pdp11_bram.vhd +++ b/rtl/w11a/pdp11_bram.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11_bram.vhd 427 2011-11-19 21:04:11Z mueller $ +-- $Id: pdp11_bram.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2008-2011 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: memlib/ram_2swsr_rfirst_gen -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-11-18 427 1.0.3 now numeric_std clean diff --git a/rtl/w11a/pdp11_bram_memctl.vbom b/rtl/w11a/pdp11_bram_memctl.vbom new file mode 100644 index 00000000..875d8e83 --- /dev/null +++ b/rtl/w11a/pdp11_bram_memctl.vbom @@ -0,0 +1,8 @@ +# libs +../vlib/slvtypes.vhd +pdp11.vbom +@lib:unisim +@lib:unimacro +# components +# design +pdp11_bram_memctl.vhd diff --git a/rtl/w11a/pdp11_bram_memctl.vhd b/rtl/w11a/pdp11_bram_memctl.vhd new file mode 100644 index 00000000..14ec0b7b --- /dev/null +++ b/rtl/w11a/pdp11_bram_memctl.vhd @@ -0,0 +1,219 @@ +-- $Id: pdp11_bram_memctl.vhd 644 2015-02-08 22:56:54Z mueller $ +-- +-- Copyright 2015- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: pdp11_bram_memctl - syn +-- Description: pdp11: BRAM based memctl +-- +-- Dependencies: - +-- Test bench: - +-- Target Devices: 7-Series +-- Tool versions: ise 14.7; viv 2014.4; ghdl 0.31 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2015-02-08 644 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library unisim; +use unisim.vcomponents.all; +library unimacro; +use unimacro.vcomponents.all; + +use work.slvtypes.all; +use work.pdp11.all; + +-- ---------------------------------------------------------------------------- + +entity pdp11_bram_memctl is -- BRAM based memctl + generic ( + MAWIDTH : positive := 4; -- mux address width + NBLOCK : positive := 11); -- write delay in clock cycles + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + REQ : in slbit; -- request + WE : in slbit; -- write enable + BUSY : out slbit; -- controller busy + ACK_R : out slbit; -- acknowledge read + ACK_W : out slbit; -- acknowledge write + ACT_R : out slbit; -- signal active read + ACT_W : out slbit; -- signal active write + ADDR : in slv20; -- address + BE : in slv4; -- byte enable + DI : in slv32; -- data in (memory view) + DO : out slv32 -- data out (memory view) + ); +end pdp11_bram_memctl; + +architecture syn of pdp11_bram_memctl is + + type state_type is ( + s_idle, -- s_idle: wait for req + s_read0, -- s_read0 + s_read1, -- s_read1 + s_write -- s_write + ); + + type regs_type is record + state : state_type; -- state + muxaddr : slv(MAWIDTH-1 downto 0); -- mux addr buffer + celladdr : slv12; -- cell addr buffer + cellen : slv(2**MAWIDTH-1 downto 0);-- cell enables + cellwe : slv4; -- write enables + dibuf : slv32; -- data in buffer + dobuf : slv32; -- data out buffer + ackr : slbit; -- signal ack_r + end record regs_type; + + constant muxaddrzero : slv(MAWIDTH-1 downto 0) := (others=>'0'); + constant cellenzero : slv(2**MAWIDTH-1 downto 0) := (others=>'0'); + constant regs_init : regs_type := ( + s_idle, -- state + muxaddrzero, -- muxaddr + (others=>'0'), -- celladdr + cellenzero, -- cellen + (others=>'0'), -- cellwe + (others=>'0'), -- dibuf + (others=>'0'), -- dobuf + '0' -- ackr + ); + + signal R_REGS : regs_type := regs_init; -- state registers + signal N_REGS : regs_type := regs_init; -- next value state regs + + type mem_do_type is array (NBLOCK-1 downto 0) of slv32; + signal MEM_DO : mem_do_type := (others=> (others => '0')); + +begin + + assert MAWIDTH <= 8 + report "assert(MAWIDTH <= 8)" severity failure; + assert NBLOCK <= 2**MAWIDTH + report "assert(NBLOCK <= 2**MAWIDTH)" severity failure; + + -- generate memory array + -- 4 colums, one for each byte of the 32 bit word + -- NBLOCK rows, as many as one can afford ... + + MARRAY: for row in NBLOCK-1 downto 0 generate + MROW: for col in 3 downto 0 generate + signal WE : slv(0 downto 0) := "0"; + begin + WE(0) <= R_REGS.cellwe(col); + MCELL : BRAM_SINGLE_MACRO + generic map ( + BRAM_SIZE => "36Kb", + DEVICE => "7SERIES", + WRITE_WIDTH => 8, + READ_WIDTH => 8, + WRITE_MODE => "WRITE_FIRST") + port map ( + CLK => CLK, + RST => '0', + REGCE => '1', + ADDR => R_REGS.celladdr, + EN => R_REGS.cellen(row), + WE => WE, + DI => R_REGS.dibuf(8*col+7 downto 8*col), + DO => MEM_DO(row)(8*col+7 downto 8*col) + ); + end generate MROW; + end generate MARRAY; + + proc_regs: process (CLK) + begin + + if rising_edge(CLK) then + if RESET = '1' then + R_REGS <= regs_init; + else + R_REGS <= N_REGS; + end if; + end if; + + end process proc_regs; + + proc_next: process (R_REGS, ADDR, DI, REQ, WE, BE, MEM_DO) + + variable r : regs_type := regs_init; + variable n : regs_type := regs_init; + variable ibusy : slbit := '0'; + variable iackw : slbit := '0'; + variable iactr : slbit := '0'; + variable iactw : slbit := '0'; + begin + + r := R_REGS; + n := R_REGS; + n.ackr := '0'; + + ibusy := '0'; + iackw := '0'; + iactr := '0'; + iactw := '0'; + + case r.state is + when s_idle => -- s_idle: wait for req + n.cellen := (others=>'0'); + n.cellwe := (others=>'0'); + if REQ = '1' then + n.muxaddr := ADDR(MAWIDTH-1+12 downto 12); + n.celladdr := ADDR(11 downto 0); + n.dibuf := DI; + n.cellen(to_integer(unsigned(ADDR(MAWIDTH-1+12 downto 12)))) := '1'; + if WE = '1' then + n.cellwe := BE; + n.state := s_write; + else + n.state := s_read0; + end if; + end if; + + when s_read0 => -- s_read0 + ibusy := '1'; + iactr := '1'; + n.state := s_read1; + + when s_read1 => -- s_read1 + ibusy := '1'; + iactr := '1'; + n.dobuf := MEM_DO(to_integer(unsigned(r.muxaddr))); + n.ackr := '1'; + n.state := s_idle; + + when s_write => -- s_write + ibusy := '1'; + iactw := '1'; + iackw := '1'; + n.cellwe := (others=>'0'); + n.state := s_idle; + + when others => null; + end case; + + N_REGS <= n; + + BUSY <= ibusy; + ACK_R <= r.ackr; + ACK_W <= iackw; + ACT_R <= iactr; + ACT_W <= iactw; + DO <= r.dobuf; + end process proc_next; + +end syn; diff --git a/rtl/w11a/pdp11_cache.vbom b/rtl/w11a/pdp11_cache.vbom index 886867bf..afb45e2c 100644 --- a/rtl/w11a/pdp11_cache.vbom +++ b/rtl/w11a/pdp11_cache.vbom @@ -3,7 +3,7 @@ ../vlib/memlib/memlib.vhd pdp11.vbom # components -[ghdl,isim]../vlib/memlib/ram_2swsr_rfirst_gen.vbom -[xst]../vlib/memlib/ram_2swsr_rfirst_gen_unisim.vbom +[sim]../vlib/memlib/ram_2swsr_rfirst_gen.vbom +[xst,vsyn]../vlib/memlib/ram_2swsr_rfirst_gen_unisim.vbom # design pdp11_cache.vhd diff --git a/rtl/w11a/pdp11_cache.vhd b/rtl/w11a/pdp11_cache.vhd index 7e62d1a5..268a0875 100644 --- a/rtl/w11a/pdp11_cache.vhd +++ b/rtl/w11a/pdp11_cache.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11_cache.vhd 427 2011-11-19 21:04:11Z mueller $ +-- $Id: pdp11_cache.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2008-2011 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: memlib/ram_2swsr_rfirst_gen -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-11-18 427 1.0.3 now numeric_std clean diff --git a/rtl/w11a/pdp11_core.vhd b/rtl/w11a/pdp11_core.vhd index 5e9ffa45..8aa56bd1 100644 --- a/rtl/w11a/pdp11_core.vhd +++ b/rtl/w11a/pdp11_core.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11_core.vhd 427 2011-11-19 21:04:11Z mueller $ +-- $Id: pdp11_core.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2006-2011 by Walter F.J. Mueller -- @@ -27,7 +27,7 @@ -- tb/tb_rlink_tba_pdp11core -- -- Target Devices: generic --- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-11-18 427 1.3.1 now numeric_std clean diff --git a/rtl/w11a/pdp11_core_rbus.vhd b/rtl/w11a/pdp11_core_rbus.vhd index 994e9a8e..7f89cf95 100644 --- a/rtl/w11a/pdp11_core_rbus.vhd +++ b/rtl/w11a/pdp11_core_rbus.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11_core_rbus.vhd 621 2014-12-26 21:20:05Z mueller $ +-- $Id: pdp11_core_rbus.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2007-2014 by Walter F.J. Mueller -- @@ -19,7 +19,7 @@ -- Test bench: tb/tb_rlink_tba_pdp11core -- -- Target Devices: generic --- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri diff --git a/rtl/w11a/pdp11_decode.vhd b/rtl/w11a/pdp11_decode.vhd index 02d8f039..86d6c0a3 100644 --- a/rtl/w11a/pdp11_decode.vhd +++ b/rtl/w11a/pdp11_decode.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11_decode.vhd 427 2011-11-19 21:04:11Z mueller $ +-- $Id: pdp11_decode.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2006-2011 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-11-18 427 1.0.6 now numeric_std clean diff --git a/rtl/w11a/pdp11_dpath.vhd b/rtl/w11a/pdp11_dpath.vhd index b2c06207..4a631c2a 100644 --- a/rtl/w11a/pdp11_dpath.vhd +++ b/rtl/w11a/pdp11_dpath.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11_dpath.vhd 581 2014-08-10 21:48:46Z mueller $ +-- $Id: pdp11_dpath.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2006-2014 by Walter F.J. Mueller -- @@ -24,7 +24,7 @@ -- -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/w11a/pdp11_dspmux.vbom b/rtl/w11a/pdp11_dspmux.vbom new file mode 100644 index 00000000..16f33b31 --- /dev/null +++ b/rtl/w11a/pdp11_dspmux.vbom @@ -0,0 +1,6 @@ +# libs +../vlib/slvtypes.vhd +pdp11.vbom +# components +# design +pdp11_dspmux.vhd diff --git a/rtl/w11a/pdp11_dspmux.vhd b/rtl/w11a/pdp11_dspmux.vhd new file mode 100644 index 00000000..280555f1 --- /dev/null +++ b/rtl/w11a/pdp11_dspmux.vhd @@ -0,0 +1,115 @@ +-- $Id: pdp11_dspmux.vhd 652 2015-02-28 12:18:08Z mueller $ +-- +-- Copyright 2015- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: pdp11_dspmux - syn +-- Description: pdp11: hio dsp mux +-- +-- Dependencies: - +-- Test bench: - +-- Target Devices: generic +-- Tool versions: ise 14.7; viv 2014.4; ghdl 0.31 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2015-02-22 650 1.0 Initial version +-- 2015-02-21 649 0.1 First draft +------------------------------------------------------------------------------ +-- selects display data +-- 4 Digit Displays +-- SEL(1:0) 00 ABCLKDIV +-- 01 DM_STAT_DP.pc +-- 10 DISPREG +-- 11 DM_STAT_DP.dsrc +-- +-- 8 Digit Displays +-- SEL(1) select DSP(7:4) +-- 0 ABCLKDIV +-- 1 DM_STAT_DP.pc +-- SEL(0) select DSP(7:4) +-- 0 DISPREG +-- 1 DM_STAT_DP.dsrc +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.pdp11.all; + +-- ---------------------------------------------------------------------------- + +entity pdp11_dspmux is -- hio dsp mux + generic ( + DCWIDTH : positive := 2); -- digit counter width (2 or 3) + port ( + SEL : in slv2; -- select + ABCLKDIV : in slv16; -- serport clock divider + DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status + DISPREG : in slv16; -- display register + DSP_DAT : out slv(4*(2**DCWIDTH)-1 downto 0) -- display data + ); +end pdp11_dspmux; + +architecture syn of pdp11_dspmux is + + subtype dspdat_msb is integer range 4*(2**DCWIDTH)-1 downto 4*(2**DCWIDTH)-16; + subtype dspdat_lsb is integer range 15 downto 0; + +begin + + assert DCWIDTH=2 or DCWIDTH=3 + report "assert(DCWIDTH=2 or DCWIDTH=3): unsupported DCWIDTH" + severity failure; + + proc_mux: process (SEL, ABCLKDIV, DM_STAT_DP, DISPREG) + variable idat : slv(4*(2**DCWIDTH)-1 downto 0) := (others=>'0'); + begin + idat := (others=>'0'); + + if DCWIDTH = 2 then + + case SEL is + when "00" => + idat(dspdat_lsb) := ABCLKDIV; + when "01" => + idat(dspdat_lsb) := DM_STAT_DP.pc; + when "10" => + idat(dspdat_lsb) := DISPREG; + when "11" => + idat(dspdat_lsb) := DM_STAT_DP.dsrc; + when others => null; + end case; + + else + + if SEL(1) = '0' then + idat(dspdat_msb) := ABCLKDIV; + else + idat(dspdat_msb) := DM_STAT_DP.pc; + end if; + + if SEL(0) = '0' then + idat(dspdat_lsb) := DISPREG; + else + idat(dspdat_lsb) := DM_STAT_DP.dsrc; + end if; + + end if; + + DSP_DAT <= idat; + + end process proc_mux; + +end syn; diff --git a/rtl/w11a/pdp11_gpr.vbom b/rtl/w11a/pdp11_gpr.vbom index 9bc38e6d..a40dd120 100644 --- a/rtl/w11a/pdp11_gpr.vbom +++ b/rtl/w11a/pdp11_gpr.vbom @@ -4,7 +4,7 @@ ../ibus/iblib.vhd pdp11.vbom # components -[ghdl,isim]../vlib/memlib/ram_1swar_1ar_gen.vbom -[xst]../vlib/memlib/ram_1swar_1ar_gen_unisim.vbom +[sim]../vlib/memlib/ram_1swar_1ar_gen.vbom +[xst,vsyn]../vlib/memlib/ram_1swar_1ar_gen_unisim.vbom # design pdp11_gpr.vhd diff --git a/rtl/w11a/pdp11_gpr.vhd b/rtl/w11a/pdp11_gpr.vhd index e3d089bb..3ec04404 100644 --- a/rtl/w11a/pdp11_gpr.vhd +++ b/rtl/w11a/pdp11_gpr.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11_gpr.vhd 427 2011-11-19 21:04:11Z mueller $ +-- $Id: pdp11_gpr.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2006-2011 by Walter F.J. Mueller -- @@ -19,7 +19,7 @@ -- -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-11-18 427 1.0.4 now numeric_std clean diff --git a/rtl/w11a/pdp11_irq.vhd b/rtl/w11a/pdp11_irq.vhd index a743566c..1de0342d 100644 --- a/rtl/w11a/pdp11_irq.vhd +++ b/rtl/w11a/pdp11_irq.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11_irq.vhd 427 2011-11-19 21:04:11Z mueller $ +-- $Id: pdp11_irq.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2007-2011 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: ib_sel -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/w11a/pdp11_ledmux.vbom b/rtl/w11a/pdp11_ledmux.vbom new file mode 100644 index 00000000..f01cce26 --- /dev/null +++ b/rtl/w11a/pdp11_ledmux.vbom @@ -0,0 +1,6 @@ +# libs +../vlib/slvtypes.vhd +pdp11.vbom +# components +# design +pdp11_ledmux.vhd diff --git a/rtl/w11a/pdp11_ledmux.vhd b/rtl/w11a/pdp11_ledmux.vhd new file mode 100644 index 00000000..fec08db3 --- /dev/null +++ b/rtl/w11a/pdp11_ledmux.vhd @@ -0,0 +1,76 @@ +-- $Id: pdp11_ledmux.vhd 652 2015-02-28 12:18:08Z mueller $ +-- +-- Copyright 2015- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: pdp11_ledmux - syn +-- Description: pdp11: hio led mux +-- +-- Dependencies: - +-- Test bench: - +-- Target Devices: generic +-- Tool versions: ise 14.7; viv 2014.4; ghdl 0.31 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2015-02-27 652 1.0 Initial version +-- 2015-02-20 649 0.1 First draft +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.pdp11.all; + +-- ---------------------------------------------------------------------------- + +entity pdp11_ledmux is -- hio led mux + generic ( + LWIDTH : positive := 8); -- led width + port ( + SEL : in slbit; -- select (0=stat;1=dr) + STATLEDS : in slv8; -- 8 bit CPU status + DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status + LED : out slv(LWIDTH-1 downto 0) -- hio leds + ); +end pdp11_ledmux; + +architecture syn of pdp11_ledmux is + +begin + + assert LWIDTH=8 or LWIDTH=16 + report "assert(LWIDTH=8 or LWIDTH=16): unsupported LWIDTH" + severity failure; + + proc_mux: process (SEL, STATLEDS, DM_STAT_DP.dsrc) + variable iled : slv(LWIDTH-1 downto 0) := (others=>'0'); + begin + iled := (others=>'0'); + + if SEL = '0' then + iled(STATLEDS'range) := STATLEDS; + else + if LWIDTH=8 then + iled := DM_STAT_DP.dsrc(11 downto 4); --take middle part + else + iled := DM_STAT_DP.dsrc(iled'range); + end if; + end if; + + LED <= iled; + + end process proc_mux; + +end syn; diff --git a/rtl/w11a/pdp11_lunit.vhd b/rtl/w11a/pdp11_lunit.vhd index cef2acfc..b5c6e9db 100644 --- a/rtl/w11a/pdp11_lunit.vhd +++ b/rtl/w11a/pdp11_lunit.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11_lunit.vhd 581 2014-08-10 21:48:46Z mueller $ +-- $Id: pdp11_lunit.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2006-2014 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2014-08-10 581 1.1.2 use c_cc_f_* diff --git a/rtl/w11a/pdp11_mem70.vhd b/rtl/w11a/pdp11_mem70.vhd index 5d3aa02c..e606e113 100644 --- a/rtl/w11a/pdp11_mem70.vhd +++ b/rtl/w11a/pdp11_mem70.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11_mem70.vhd 427 2011-11-19 21:04:11Z mueller $ +-- $Id: pdp11_mem70.vhd 644 2015-02-08 22:56:54Z mueller $ -- -- Copyright 2008-2011 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- -- Revision History: -- Date Rev Version Comment @@ -83,7 +83,7 @@ architecture syn of pdp11_mem70 is constant regs_init : regs_type := ( '0','0','0','0', -- ibsel_* (others=>'0'), -- hm_data - "00","00", -- cr_freq,_fmiss + "00","00", -- cr_frep,_fmiss '0','0' -- dis(u)trap ); diff --git a/rtl/w11a/pdp11_mmu.vhd b/rtl/w11a/pdp11_mmu.vhd index 941d8320..cafa4f2f 100644 --- a/rtl/w11a/pdp11_mmu.vhd +++ b/rtl/w11a/pdp11_mmu.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11_mmu.vhd 427 2011-11-19 21:04:11Z mueller $ +-- $Id: pdp11_mmu.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2006-2011 by Walter F.J. Mueller -- @@ -22,7 +22,7 @@ -- -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/w11a/pdp11_mmu_sadr.vbom b/rtl/w11a/pdp11_mmu_sadr.vbom index 696da376..f598c1dc 100644 --- a/rtl/w11a/pdp11_mmu_sadr.vbom +++ b/rtl/w11a/pdp11_mmu_sadr.vbom @@ -4,7 +4,7 @@ ../ibus/iblib.vhd pdp11.vbom # components -[ghdl,isim]../vlib/memlib/ram_1swar_gen.vbom -[xst]../vlib/memlib/ram_1swar_gen_unisim.vbom +[sim]../vlib/memlib/ram_1swar_gen.vbom +[xst,vsyn]../vlib/memlib/ram_1swar_gen_unisim.vbom # design pdp11_mmu_sadr.vhd diff --git a/rtl/w11a/pdp11_mmu_sadr.vhd b/rtl/w11a/pdp11_mmu_sadr.vhd index d7b18e12..985bd343 100644 --- a/rtl/w11a/pdp11_mmu_sadr.vhd +++ b/rtl/w11a/pdp11_mmu_sadr.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11_mmu_sadr.vhd 427 2011-11-19 21:04:11Z mueller $ +-- $Id: pdp11_mmu_sadr.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2006-2011 by Walter F.J. Mueller -- @@ -19,7 +19,7 @@ -- -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/w11a/pdp11_mmu_ssr12.vhd b/rtl/w11a/pdp11_mmu_ssr12.vhd index ca93abd8..78c9b0b0 100644 --- a/rtl/w11a/pdp11_mmu_ssr12.vhd +++ b/rtl/w11a/pdp11_mmu_ssr12.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11_mmu_ssr12.vhd 427 2011-11-19 21:04:11Z mueller $ +-- $Id: pdp11_mmu_ssr12.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2006-2011 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: ib_sel -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/w11a/pdp11_munit.vhd b/rtl/w11a/pdp11_munit.vhd index 6d3ff08b..db60aeb9 100644 --- a/rtl/w11a/pdp11_munit.vhd +++ b/rtl/w11a/pdp11_munit.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11_munit.vhd 581 2014-08-10 21:48:46Z mueller $ +-- $Id: pdp11_munit.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2006-2014 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri diff --git a/rtl/w11a/pdp11_ounit.vhd b/rtl/w11a/pdp11_ounit.vhd index 45fece37..643b7c98 100644 --- a/rtl/w11a/pdp11_ounit.vhd +++ b/rtl/w11a/pdp11_ounit.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11_ounit.vhd 427 2011-11-19 21:04:11Z mueller $ +-- $Id: pdp11_ounit.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2006-2011 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2011-11-18 427 1.1.1 now numeric_std clean diff --git a/rtl/w11a/pdp11_psr.vhd b/rtl/w11a/pdp11_psr.vhd index 28bb5825..d5685d01 100644 --- a/rtl/w11a/pdp11_psr.vhd +++ b/rtl/w11a/pdp11_psr.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11_psr.vhd 427 2011-11-19 21:04:11Z mueller $ +-- $Id: pdp11_psr.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2006-2011 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: ib_sel -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/w11a/pdp11_sequencer.vhd b/rtl/w11a/pdp11_sequencer.vhd index a1b137f4..291391d2 100644 --- a/rtl/w11a/pdp11_sequencer.vhd +++ b/rtl/w11a/pdp11_sequencer.vhd @@ -1,6 +1,6 @@ --- $Id: pdp11_sequencer.vhd 569 2014-07-13 14:36:32Z mueller $ +-- $Id: pdp11_sequencer.vhd 643 2015-02-07 17:41:53Z mueller $ -- --- Copyright 2006-2014 by Walter F.J. Mueller +-- Copyright 2006-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,10 +18,11 @@ -- Dependencies: ib_sel -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: xst 8.2-14.7; viv 2014.1; ghdl 0.18-0.31 +-- Tool versions: ise 8.2-14.7; viv 2014.1; ghdl 0.18-0.31 -- -- Revision History: -- Date Rev Version Comment +-- 2015-02-07 643 1.5.2 s_op_wait: load R0 in DSRC for DR emulation -- 2014-07-12 569 1.5.1 rename s_opg_div_zero -> s_opg_div_quit; -- use DP_STAT.div_quit; set munit_s_div_sr; -- BUGFIX: s_opg_div_sr: check for late div_quit @@ -1481,6 +1482,10 @@ begin end if; when s_op_wait => -- WAIT + ndpcntl.gpr_asrc := "000"; -- load R0 in DSRC for DR emulation + ndpcntl.dsrc_sel := c_dpath_dsrc_src; + ndpcntl.dsrc_we := '1'; + nstate := s_op_wait; -- spin here if is_kmode = '0' then -- but act as nop if not in kernel nstate := s_idle; diff --git a/rtl/w11a/pdp11_sim.vhd b/rtl/w11a/pdp11_sim.vhd index b5a45cba..6b4bb5b0 100644 --- a/rtl/w11a/pdp11_sim.vhd +++ b/rtl/w11a/pdp11_sim.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11_sim.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: pdp11_sim.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2006-2007 by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Definitions for simulations -- -- Dependencies: - --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2007-10-12 88 1.0.2 avoid ieee.std_logic_unsigned, use cast to unsigned diff --git a/rtl/w11a/pdp11_statleds.vbom b/rtl/w11a/pdp11_statleds.vbom new file mode 100644 index 00000000..4e6b7825 --- /dev/null +++ b/rtl/w11a/pdp11_statleds.vbom @@ -0,0 +1,6 @@ +# libs +../vlib/slvtypes.vhd +pdp11.vbom +# components +# design +pdp11_statleds.vhd diff --git a/rtl/w11a/pdp11_statleds.vhd b/rtl/w11a/pdp11_statleds.vhd new file mode 100644 index 00000000..22f440a9 --- /dev/null +++ b/rtl/w11a/pdp11_statleds.vhd @@ -0,0 +1,96 @@ +-- $Id: pdp11_statleds.vhd 649 2015-02-21 21:10:16Z mueller $ +-- +-- Copyright 2015- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: pdp11_statleds - syn +-- Description: pdp11: status leds +-- +-- Dependencies: - +-- Test bench: - +-- Target Devices: generic +-- Tool versions: ise 14.7; viv 2014.4; ghdl 0.31 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2015-02-20 649 1.0 Initial version +------------------------------------------------------------------------------ +-- LED (7) MEM_ACT_W +-- (6) MEM_ACT_R +-- (5) cmdbusy (all rlink access, mostly rdma) +-- (4:0) if cpugo=1 show cpu mode activity +-- (4) kernel mode, pri>0 +-- (3) kernel mode, pri=0 +-- (2) kernel mode, wait +-- (1) supervisor mode +-- (0) user mode +-- if cpugo=0 shows cpurust +-- (4) '1' +-- (3:0) cpurust code + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.pdp11.all; + +-- ---------------------------------------------------------------------------- + +entity pdp11_statleds is -- status leds + port ( + MEM_ACT_R : in slbit; -- memory active read + MEM_ACT_W : in slbit; -- memory active write + CP_STAT : in cp_stat_type; -- console port status + DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status + STATLEDS : out slv8 -- 8 bit CPU status + ); +end pdp11_statleds; + +architecture syn of pdp11_statleds is + +begin + + proc_led: process (MEM_ACT_W, MEM_ACT_R, CP_STAT, DM_STAT_DP.psw) + variable iled : slv8 := (others=>'0'); + begin + iled := (others=>'0'); + + iled(7) := MEM_ACT_W; + iled(6) := MEM_ACT_R; + iled(5) := CP_STAT.cmdbusy; + if CP_STAT.cpugo = '1' then + case DM_STAT_DP.psw.cmode is + when c_psw_kmode => + if CP_STAT.cpuwait = '1' then + iled(2) := '1'; + elsif unsigned(DM_STAT_DP.psw.pri) = 0 then + iled(3) := '1'; + else + iled(4) := '1'; + end if; + when c_psw_smode => + iled(1) := '1'; + when c_psw_umode => + iled(0) := '1'; + when others => null; + end case; + else + iled(4) := '1'; + iled(3 downto 0) := CP_STAT.cpurust; + end if; + + STATLEDS <= iled; + + end process proc_led; + +end syn; diff --git a/rtl/w11a/pdp11_sys70.vhd b/rtl/w11a/pdp11_sys70.vhd index 75e2f723..6b41cf36 100644 --- a/rtl/w11a/pdp11_sys70.vhd +++ b/rtl/w11a/pdp11_sys70.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11_sys70.vhd 427 2011-11-19 21:04:11Z mueller $ +-- $Id: pdp11_sys70.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2008-2011 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/w11a/pdp11_tmu.vhd b/rtl/w11a/pdp11_tmu.vhd index c152ced4..126b706b 100644 --- a/rtl/w11a/pdp11_tmu.vhd +++ b/rtl/w11a/pdp11_tmu.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11_tmu.vhd 444 2011-12-25 10:04:58Z mueller $ +-- $Id: pdp11_tmu.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2008-2011 by Walter F.J. Mueller -- @@ -19,7 +19,7 @@ -- -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: ghdl 0.18-0.29 +-- Tool versions: ghdl 0.18-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/w11a/pdp11_tmu_sb.vhd b/rtl/w11a/pdp11_tmu_sb.vhd index cd26fb65..170e79d2 100644 --- a/rtl/w11a/pdp11_tmu_sb.vhd +++ b/rtl/w11a/pdp11_tmu_sb.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11_tmu_sb.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: pdp11_tmu_sb.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2009- by Walter F.J. Mueller -- @@ -17,7 +17,7 @@ -- -- Dependencies: simbus -- Test bench: - --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2009-05-10 214 1.0 Initial version diff --git a/rtl/w11a/pdp11_ubmap.vbom b/rtl/w11a/pdp11_ubmap.vbom index 188318aa..ad80e09a 100644 --- a/rtl/w11a/pdp11_ubmap.vbom +++ b/rtl/w11a/pdp11_ubmap.vbom @@ -4,8 +4,8 @@ ../ibus/iblib.vhd pdp11.vbom # components -[ghdl,isim]../vlib/memlib/ram_1swar_gen.vbom -[xst]../vlib/memlib/ram_1swar_gen_unisim.vbom +[sim]../vlib/memlib/ram_1swar_gen.vbom +[xst,vsyn]../vlib/memlib/ram_1swar_gen_unisim.vbom ../ibus/ib_sel.vbom # design pdp11_ubmap.vhd diff --git a/rtl/w11a/pdp11_ubmap.vhd b/rtl/w11a/pdp11_ubmap.vhd index d1e64565..01d74558 100644 --- a/rtl/w11a/pdp11_ubmap.vhd +++ b/rtl/w11a/pdp11_ubmap.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11_ubmap.vhd 427 2011-11-19 21:04:11Z mueller $ +-- $Id: pdp11_ubmap.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2008-2011 by Walter F.J. Mueller -- @@ -19,7 +19,7 @@ -- ib_sel -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/w11a/pdp11_vmbox.vhd b/rtl/w11a/pdp11_vmbox.vhd index 20b860df..bcfcd299 100644 --- a/rtl/w11a/pdp11_vmbox.vhd +++ b/rtl/w11a/pdp11_vmbox.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11_vmbox.vhd 427 2011-11-19 21:04:11Z mueller $ +-- $Id: pdp11_vmbox.vhd 641 2015-02-01 22:12:15Z mueller $ -- -- Copyright 2006-2011 by Walter F.J. Mueller -- @@ -23,7 +23,7 @@ -- -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/w11a/sys_conf.vhd b/rtl/w11a/sys_conf.vhd index cb0ceba8..da06d8aa 100644 --- a/rtl/w11a/sys_conf.vhd +++ b/rtl/w11a/sys_conf.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: sys_conf.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2007-2008 by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Default definitions for pdp11core (for simple test benches) -- -- Dependencies: - --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment -- 2008-02-23 118 1.0 Initial version diff --git a/rtl/w11a/tb/Makefile b/rtl/w11a/tb/Makefile index 3a1f96a9..30048866 100644 --- a/rtl/w11a/tb/Makefile +++ b/rtl/w11a/tb/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 621 2014-12-26 21:20:05Z mueller $ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ # # Revision History: # Date Rev Version Comment @@ -17,7 +17,7 @@ EXE_all = tb_pdp11core ifndef XTW_BOARD XTW_BOARD=nexys3 endif -include $(RETROBASE)/rtl/make/xflow_default_$(XTW_BOARD).mk +include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk # .PHONY : all all_ssim all_tsim clean @@ -30,9 +30,9 @@ clean : ise_clean ghdl_clean isim_clean # #----- # -include $(RETROBASE)/rtl/make/generic_ghdl.mk -include $(RETROBASE)/rtl/make/generic_isim.mk -include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_isim.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk # VBOM_all = $(wildcard *.vbom) # diff --git a/rtl/w11a/tb/tbd_pdp11core.vbom b/rtl/w11a/tb/tbd_pdp11core.vbom index 313fe9a0..00107217 100644 --- a/rtl/w11a/tb/tbd_pdp11core.vbom +++ b/rtl/w11a/tb/tbd_pdp11core.vbom @@ -10,6 +10,6 @@ ${sys_conf := ../sys_conf.vhd} ../pdp11_core.vbom ../pdp11_bram.vbom ../../ibus/ibdr_minisys.vbom -[ghdl,isim]../pdp11_tmu_sb.vbom +[sim]../pdp11_tmu_sb.vbom # design tbd_pdp11core.vhd diff --git a/rtl/w11a/tb/tbd_pdp11core.vhd b/rtl/w11a/tb/tbd_pdp11core.vhd index e9ea74dd..aee601d0 100644 --- a/rtl/w11a/tb/tbd_pdp11core.vhd +++ b/rtl/w11a/tb/tbd_pdp11core.vhd @@ -1,4 +1,4 @@ --- $Id: tbd_pdp11core.vhd 427 2011-11-19 21:04:11Z mueller $ +-- $Id: tbd_pdp11core.vhd 649 2015-02-21 21:10:16Z mueller $ -- -- Copyright 2007-2011 by Walter F.J. Mueller -- @@ -26,7 +26,7 @@ -- To test: pdp11_core -- -- Target Devices: generic --- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri diff --git a/tools/bin/rm_dep b/tools/bin/rm_dep index bd1a43ba..3f8f5072 100755 --- a/tools/bin/rm_dep +++ b/tools/bin/rm_dep @@ -1,13 +1,17 @@ #!/bin/sh -# $Id: rm_dep 354 2011-01-09 22:38:53Z mueller $ +# $Id: rm_dep 646 2015-02-15 12:04:55Z mueller $ +# +# Copyright 2010-2015 by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory # # Revision History: # Date Rev Version Comment +# 2015-02-14 646 1.2 add dep_vsyn # 2011-01-09 354 1.1.1 add *.dep for cpp depends # 2010-04-26 284 1.1 add xargs -r to prevent rm errors on empty lists # 2010-04-24 282 1.0 Initial version # -for ftype in dep dep_ghdl dep_isim dep_xst dep_ucf_cpp +for ftype in dep dep_ghdl dep_xst dep_isim dep_ucf_cpp dep_vsyn do echo "---------- remove *.$ftype ----------------------------------------" find -name "*.$ftype" | xargs --no-run-if-empty rm -v diff --git a/tools/bin/set_ftdi_lat b/tools/bin/set_ftdi_lat deleted file mode 100755 index d174f4bc..00000000 --- a/tools/bin/set_ftdi_lat +++ /dev/null @@ -1,34 +0,0 @@ -#!/bin/sh -# $Id: set_ftdi_lat 282 2010-04-24 12:08:32Z mueller $ -# -# Usage: sudo $HOME/other/retro/trunk/bin/set_ftdi_lat USB0 1 -# -# Revision History: -# Date Rev Version Comment -# 2010-04-24 282 1.0 fix filename for retrieving old latency -# 2010-04-24 281 0.9 Initial version -# - -dev=${1:-USB0} -lat=${2:-1} - -file="/sys/bus/usb-serial/devices/tty$dev/latency_timer" - -if [ ! -r $file ] -then - echo "set_ftdi_lat-E: device $dev not available" - echo " $file not found" - exit 1 -fi - -if [ ! -w $file ] -then - echo "set_ftdi_lat-E: parameters for $dev not writable" - exit 1 -fi - -old=`cat $file` - -echo "Set latency for tty$dev: old=$old new=$lat" - -echo "$lat" > $file diff --git a/tools/bin/tbrun_tbw b/tools/bin/tbrun_tbw index e3768f01..ad0dee57 100755 --- a/tools/bin/tbrun_tbw +++ b/tools/bin/tbrun_tbw @@ -1,5 +1,8 @@ #!/bin/bash -# $Id: tbrun_tbw 622 2014-12-28 20:45:26Z mueller $ +# $Id: tbrun_tbw 641 2015-02-01 22:12:15Z mueller $ +# +# Copyright 2014- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory # # Revision History: # Date Rev Version Comment diff --git a/tools/bin/tbrun_tbwrri b/tools/bin/tbrun_tbwrri index eb40eaa0..f41c0c91 100755 --- a/tools/bin/tbrun_tbwrri +++ b/tools/bin/tbrun_tbwrri @@ -1,5 +1,8 @@ #!/bin/bash -# $Id: tbrun_tbwrri 622 2014-12-28 20:45:26Z mueller $ +# $Id: tbrun_tbwrri 641 2015-02-01 22:12:15Z mueller $ +# +# Copyright 2014- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory # # Revision History: # Date Rev Version Comment diff --git a/tools/bin/tbw b/tools/bin/tbw index 47cfd621..f5913617 100755 --- a/tools/bin/tbw +++ b/tools/bin/tbw @@ -1,5 +1,5 @@ #!/usr/bin/perl -w -# $Id: tbw 619 2014-12-23 13:17:41Z mueller $ +# $Id: tbw 642 2015-02-06 18:53:12Z mueller $ # # Copyright 2007-2015 by Walter F.J. Mueller # @@ -55,7 +55,7 @@ my @file_dsc; # file descriptors from tbw.dat sub print_usage; -autoflush STDOUT 1; # autoflush, so noting lost on exec later +autoflush STDOUT 1; # autoflush, so nothing lost on exec later if (scalar(@ARGV) && $ARGV[0] =~ /^-*help$/) { # -help or --help given print_usage; diff --git a/tools/bin/ti_rri b/tools/bin/ti_rri index a42788af..bf4bd9a7 100755 --- a/tools/bin/ti_rri +++ b/tools/bin/ti_rri @@ -1,8 +1,8 @@ #! /usr/bin/env tclshcpp # -*- tcl -*- -# $Id: ti_rri 601 2014-11-07 22:44:43Z mueller $ +# $Id: ti_rri 631 2015-01-09 21:36:51Z mueller $ # -# Copyright 2011-2014 by Walter F.J. Mueller +# Copyright 2011-2015 by Walter F.J. Mueller # # This program is free software; you may redistribute and/or modify it under # the terms of the GNU General Public License as published by the Free @@ -15,6 +15,7 @@ # # Revision History: # Date Rev Version Comment +# 2015-01-09 631 1.2.1 use rlc get/set rather config # 2014-11-07 601 1.2 use tclshcpp (C++ based) rather tclsh # 2013-05-19 521 1.1.6 setup proper interactive handling; add --run reap # 2013-04-26 510 1.1.5 reorganize readline startup @@ -210,11 +211,11 @@ if { $opts(pack_) ne "" } { # setup logging if { $opts(log_) ne "-" } { - rlc config -logfile $opts(log_) + rlc set logfile $opts(log_) } -rlc config -logprintlevel $opts(logl_) -rlc config -logdumplevel $opts(dmpl_) -rlc config -logtracelevel $opts(tiol_) +rlc set printlevel $opts(logl_) +rlc set dumplevel $opts(dmpl_) +rlc set tracelevel $opts(tiol_) # first start, if specified with --run, the test bench # exec sh -c $cmd is used to execute a shell command including [], '',"" diff --git a/tools/bin/ti_w11 b/tools/bin/ti_w11 index f1f74802..c3599e41 100755 --- a/tools/bin/ti_w11 +++ b/tools/bin/ti_w11 @@ -1,8 +1,12 @@ #!/usr/bin/perl -w -# $Id: ti_w11 619 2014-12-23 13:17:41Z mueller $ +# $Id: ti_w11 654 2015-03-01 18:45:38Z mueller $ +# +# Copyright 2013-2015 by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory # # Revision History: # Date Rev Version Comment +# 2015-01-02 640 1.2.2 BUGFIX: allow 'M' unit in baud rates # 2014-12-23 619 1.2.1 use -fifo tbw option for test bench starts # 2014-07-13 570 1.2 BUGFIX: split options args into ti_rri opts and cmds # 2013-05-05 516 1.1 renamed to ti_w11 @@ -15,7 +19,7 @@ use FileHandle; sub print_usage; -autoflush STDOUT 1; # autoflush, so noting lost on exec later +autoflush STDOUT 1; # autoflush, so nothing lost on exec later my $sysbase = "$ENV{RETROBASE}/rtl/sys_gen/w11a"; @@ -25,9 +29,12 @@ my $opt_f = ''; my $opt_tmu; my $tirri; my $val_term; -my $val_tb_s3 = "tbw $sysbase/s3board/tb/tb_w11a_s3 -fifo"; -my $val_tb_n2 = "tbw $sysbase/nexys2/tb/tb_w11a_n2 -fifo"; -my $val_tb_n3 = "tbw $sysbase/nexys3/tb/tb_w11a_n3 -fifo"; +my $val_tb_s3 = "tbw $sysbase/s3board/tb/tb_w11a_s3 -fifo"; +my $val_tb_n2 = "tbw $sysbase/nexys2/tb/tb_w11a_n2 -fifo"; +my $val_tb_n3 = "tbw $sysbase/nexys3/tb/tb_w11a_n3 -fifo"; +my $val_tb_b3 = "tbw $sysbase/basys3/tb/tb_w11a_b3 -fifo"; +my $val_tb_n4 = "tbw $sysbase/nexys4/tb/tb_w11a_n4 -fifo"; +my $val_tb_bn4 = "tbw $sysbase/nexys4_bram/tb/tb_w11a_br_n4 -fifo"; my $val_tb; my $val_e; @@ -62,6 +69,21 @@ while (scalar(@ARGV)) { $val_tb = $val_tb_n3; shift @ARGV; + } elsif ($curarg =~ m{^-b4$} ) { # -b3 + $opt_io = 'f'; + $val_tb = $val_tb_b3; + shift @ARGV; + + } elsif ($curarg =~ m{^-n4$} ) { # -n4 + $opt_io = 'f'; + $val_tb = $val_tb_n4; + shift @ARGV; + + } elsif ($curarg =~ m{^-bn4$} ) { # -bn4 + $opt_io = 'f'; + $val_tb = $val_tb_bn4; + shift @ARGV; + } elsif ($curarg =~ m{^-f(s\d?|u)$} ) { # -f[su] $opt_f = $1; shift @ARGV; @@ -72,7 +94,7 @@ while (scalar(@ARGV)) { my ($dev,$baud,$opt1,$opt2) = split /,/,$curarg; $baud = '115k' unless defined $baud; - if ($baud !~ m{^\d*k?$}) { + if ($baud !~ m{^\d*[kM]?$}) { print STDERR "ti_w11-E: invalid format of -ts or -tu option\n"; exit 1; } @@ -129,7 +151,7 @@ while (scalar(@ARGV)) { } # -# check that either -s3/n2/n3 or -t or -u given +# check that either -(s3|n2|n3|n4|bn4) or -t or -u given # setup pi_rri options for either case # @@ -141,7 +163,7 @@ if ($opt_io eq 'f') { } elsif ($opt_io eq 'u') { push @arglist, '--cuff'; } else { - print STDERR "ti_w11-E: neither -s3/-n2/-n3 nor -t or -u specified\n"; + print STDERR "ti_w11-E: neither -(s3|n2|n3|b3|n4|bn4) nor -t or -u specified\n"; print_usage(); exit 1; } @@ -223,9 +245,12 @@ exit 1; sub print_usage { print "usage: ti_w11 ...\n"; print " setup options for ghdl simulation runs:\n"; - print " -s3 start tb_w11a_s3 simulation\n"; - print " -n2 start tb_w11a_n2 simulation\n"; + print " -b3 start tb_w11a_b3 simulation\n"; + print " -n4 start tb_w11a_n4 simulation\n"; + print " -bn4 start tb_w11a_br_n4 simulation\n"; print " -n3 start tb_w11a_n3 simulation\n"; + print " -n2 start tb_w11a_n2 simulation\n"; + print " -s3 start tb_w11a_s3 simulation\n"; print " -f.. simulation communication options\n"; print " -fu use cuff data path\n"; print " -tmu activate trace and monitoring unit\n"; @@ -240,6 +265,6 @@ sub print_usage { print " file type '.mac': on the fly compile with asm-11\n"; print " any other file type: assume lda format\n"; print "\n"; - print " either one of -s3,-n2, or -n3 must be given -> sim run\n"; + print " either one of -s3,-n2,-n3,-b3,-n4,-bn4 must be given -> sim run\n"; print " or one of -t or -u must be given -> fpga run\n"; } diff --git a/tools/bin/ticonv_pdpcp b/tools/bin/ticonv_pdpcp index d6126610..173a7df9 100755 --- a/tools/bin/ticonv_pdpcp +++ b/tools/bin/ticonv_pdpcp @@ -1,5 +1,5 @@ #!/usr/bin/perl -w -# $Id: ticonv_pdpcp 622 2014-12-28 20:45:26Z mueller $ +# $Id: ticonv_pdpcp 646 2015-02-15 12:04:55Z mueller $ # # Copyright 2013-2014 by Walter F.J. Mueller # @@ -42,7 +42,7 @@ sub add_edata; my @cmdlist; if (scalar(@ARGV) != 2) { - print STDERR "%ticonv_pdpcp-E: usage: ticonv_pdpcp \n"; + print STDERR "ticonv_pdpcp-E: usage: ticonv_pdpcp \n"; exit 1; } diff --git a/tools/bin/vbomconv b/tools/bin/vbomconv index 5bbb3efc..105e0f65 100755 --- a/tools/bin/vbomconv +++ b/tools/bin/vbomconv @@ -1,7 +1,7 @@ #!/usr/bin/perl -w -# $Id: vbomconv 575 2014-07-27 20:55:41Z mueller $ +# $Id: vbomconv 646 2015-02-15 12:04:55Z mueller $ # -# Copyright 2007-2014 by Walter F.J. Mueller +# Copyright 2007-2015 by Walter F.J. Mueller # # This program is free software; you may redistribute and/or modify it under # the terms of the GNU General Public License as published by the Free @@ -14,6 +14,10 @@ # # Revision History: # Date Rev Version Comment +# 2015-02-15 646 1.11 add vivado support: add -xlpath, use instead +# of XTWI_PATH; drop --ise_path; add @lib:unimacro; +# drop --viv_vhdl; add --vsyn_prj, --dep_vsyn; +# drop cygwin support; # 2014-07-26 575 1.10.1 use XTWI_PATH now (ise/vivado switch done later) # 2013-10-20 543 1.10 add --viv_vhdl # 2012-02-05 456 1.9.4 redo filename substitution (= and :); add --get_top @@ -40,7 +44,7 @@ # 2007-11-25 98 1.6.1 drop trailing blanks on input lines # 2007-11-02 94 1.6 added (xst|ghdl)_export # 2007-10-26 92 1.5.1 emit '--no-vital-checks' for --ghdl_m for _[sft]sim -# 2007-10-14 98 1.5 handle .exe files under cycwin properly +# 2007-10-14 98 1.5 handle .exe files under cygwin properly # 2007-09-15 82 1.4 handle C source objects properly # 2007-08-10 72 1.3 add [xst], [ghdl] prefix support # 2007-07-22 68 1.2 add "tag = val"; list files in 'ready to analyse' @@ -56,15 +60,15 @@ use Getopt::Long; my %opts = (); -GetOptions(\%opts, "help", "trace", "ise_path=s", - "dep_xst", "dep_ghdl", "dep_isim", +GetOptions(\%opts, "help", "trace", "xlpath=s", + "dep_ghdl", "dep_xst", "dep_isim", "dep_vsyn", "xst_prj", "isim_prj", - "viv_vhdl", + "vsyn_prj", "ghdl_a", "ghdl_a_cmd", "ghdl_i", "ghdl_i_cmd", "ghdl_m", "ghdl_m_cmd", - "xst_export=s", "ghdl_export=s", + "xst_export=s", "isim_export=s", "get_top", "flist") || exit 1; @@ -76,40 +80,41 @@ sub copy_edir; sub write_vbomdep; sub canon_fname; -my @vbom_list; -my @file_list; -my %vbom_tbl; -my %file_tbl; -my %read_tbl; -my %para_tbl; +my @vbom_queue; # list of pending vbom's +my @srcfile_list; # list of sources in compile order +my @xdcfile_list; # list of xdc files +my %vbom_files; # key=vbom; val=full file list +my %vbom_xdc; # key=vbom; val=xdc spec list +my %vbom_done; # key=vbom; val=done flags +my %vbom_rank; # key=vbom; val=vbom ranks +my %srcfile_rank; # key=source file; val=file rank +my %para_tbl; # substitution table my @ucf_cpp_list; -my $is_xst = 0; # XST synthesis target my $is_ghdl = 0; # ghdl simulation target +my $is_xst = 0; # XST synthesis target my $is_isim = 0; # ISim simulation target +my $is_vsyn = 0; # vivado synthesis target +my $is_vsim = 0; # vivado simulation target my $is_sim = 0; # simulation target (generic) -my $is_any = 0; -my $nactions = 0; -my $top_vbom; -my $stem; -my $top; -my $top_done = 0; -my $has_unisim; -my $has_simprim; +my $is_any = 0; # ignore tags (for --flist) +my $nactions = 0; # number of action commands +my $top_vbom; # top level vbom (from argv) +my $stem; # stem of $top_vbom +my $top; # top level entity name +my $top_done = 0; # @top seen +my $has_unisim; # @lib:unisim seen or implied +my $has_unimacro; # @lib:unimacro seen +my $has_simprim; # @lib:simprim seen or implied my $is_ssim; my $is_fsim; my $is_tsim; my $do_trace = exists $opts{trace}; -my $level; +my $level = 0; # vbom nesting level my $xst_writevhdl = 1; +my $xlpath=$opts{xlpath}; +my $no_xlpath = ! defined $xlpath || $xlpath eq ""; -# now using '-ifmt mixed', so language always needed (2011-08-13) -#if (defined $opts{ise_path}) { -# if ($opts{ise_path} =~ /^xc6s/) { -# $xst_writevhdl = 0; -# } -#} - -autoflush STDOUT 1; # autoflush, so noting lost on exec later +autoflush STDOUT 1; # autoflush, so nothing lost on exec later if (exists $opts{help}) { print_help; @@ -119,7 +124,7 @@ if (exists $opts{help}) { # ensure that one and only one vbom is specified if (scalar(@ARGV) != 1) { - print STDERR "%vbomconv-E: only one vbom file name allowed\n\n"; + print STDERR "vbomconv-E: only one vbom file name allowed\n\n"; print_help; exit 1; } @@ -127,25 +132,33 @@ if (scalar(@ARGV) != 1) { # check that only one action is defined, mark xst, gdhl, or isim class foreach (keys %opts) { - $nactions += 1 unless ($_ eq "trace" || $_ eq "ise_path"); - $is_xst = 1 if ($_ eq "dep_xst"); + $nactions += 1 unless ($_ eq "trace" || $_ eq "xlpath"); $is_ghdl = 1 if ($_ eq "dep_ghdl"); - $is_isim = 1 if ($_ eq "dep_isim"); - $is_xst = 1 if ($_ =~ /^xst_/); $is_ghdl = 1 if ($_ =~ /^ghdl_/); + + $is_xst = 1 if ($_ eq "dep_xst"); + $is_xst = 1 if ($_ =~ /^xst_/); + + $is_isim = 1 if ($_ eq "dep_isim"); $is_isim = 1 if ($_ =~ /^isim_/); + + $is_vsyn = 1 if ($_ eq "dep_vsyn"); + $is_vsyn = 1 if ($_ =~ /^vsyn_/); + $is_any = 1 if ($_ eq "flist"); } -$is_sim = $is_ghdl | $is_isim; +$is_sim = $is_ghdl | $is_isim | $is_vsim; -print STDERR "-- [xst] active\n" if $do_trace && $is_xst; print STDERR "-- [ghdl] active\n" if $do_trace && $is_ghdl; +print STDERR "-- [xst] active\n" if $do_trace && $is_xst; print STDERR "-- [isim] active\n" if $do_trace && $is_isim; +print STDERR "-- [vsyn] active\n" if $do_trace && $is_vsyn; +print STDERR "-- [vsim] active\n" if $do_trace && $is_vsim; print STDERR "-- [sim] active\n" if $do_trace && $is_sim; if ($nactions > 1) { - print STDERR "%vbomconv-E: only one action qualifier allowed\n\n"; + print STDERR "vbomconv-E: only one action qualifier allowed\n\n"; print_help; exit 1; } @@ -177,25 +190,44 @@ if ($top_vbom =~ m{_tsim\.vbom$}) { # map _tsim -> _ssim # traverse all vbom's start with command line argument -push @vbom_list, $top_vbom; +push @vbom_queue, $top_vbom; -while (@vbom_list) { - my $cur_vbom = shift @vbom_list; +while (@vbom_queue) { + my $cur_vbom = shift @vbom_queue; read_vbom($cur_vbom); } # traverse internal vbom representation to build file table +$vbom_rank{$top_vbom} = {min=>1, max=>1}; scan_vbom($top_vbom); # sort file table, build file list (decreasing rank) +# sort first by decreasing rank and second by filename +# second sort only to get stable sequence, independent of hash keys -my @pair_list; -foreach (keys %file_tbl) { - push @pair_list, [$file_tbl{$_}, $_]; +my @srcpair_list; +foreach (keys %srcfile_rank) { + push @srcpair_list, [$srcfile_rank{$_}, $_]; } -@file_list = map {$_->[1]} sort {$b->[0] <=> $a->[0]} @pair_list; +@srcfile_list = map {$_->[1]} + sort {$b->[0] <=> $a->[0] || $a->[1] cmp $b->[1]} + @srcpair_list; + +# setup vbom list by rank +my @vbom_rank_list; +foreach (sort keys %vbom_rank) { + push @vbom_rank_list, [$vbom_rank{$_}{min}, $vbom_rank{$_}{max}, $_]; +} +my @vbomfile_list_min = map {$_->[2]} + sort {$a->[0] <=> $b->[0] || $a->[1] cmp $b->[1]} + @vbom_rank_list; + +# setup xdc files list (if one @xdc: seen) +foreach (@vbomfile_list_min) { + push @xdcfile_list, @{$vbom_xdc{$_}} if exists $vbom_xdc{$_}; +} # now generate output and actions, depending on options given @@ -207,10 +239,22 @@ if ($do_trace) { foreach (sort keys %para_tbl) { print STDERR " $_ = $para_tbl{$_}\n"; } - print STDERR "final file_list:\n"; - foreach (@file_list) { - print STDERR " $_\n"; + + print STDERR "\n"; + print STDERR "final vbom_rank table (sort by min rank):\n"; + print STDERR " min max var vbom-name:\n"; + foreach (sort {$a->[0] <=> $b->[0] || $a->[2] cmp $b->[2]} @vbom_rank_list) { + printf STDERR " %3d %3d %3d %s\n", + $_->[0], $_->[1], $_->[1]-$_->[0], $_->[2]; } + + print STDERR "\n"; + print STDERR "final srcfile_rank table (sort by rank):\n"; + foreach (sort {$b->[0] <=> $a->[0] || $a->[1] cmp $b->[1]} @srcpair_list) { + printf STDERR " %5d %s\n", $_->[0], $_->[1]; + } + + print STDERR "\n"; print STDERR "properties:\n"; print STDERR " \@top: $top\n"; } @@ -218,11 +262,17 @@ if ($do_trace) { # --ghdh_a -- ghdl analysis command ---------------------------------- if (exists $opts{ghdl_a} || exists $opts{ghdl_a_cmd}) { - foreach (@file_list) { + if ($no_xlpath && ($has_unisim || $has_unimacro || $has_simprim) ) { + print STDERR "vbomconv-E: --xlpath required with ghdl_a or ghdl_a_cmd"; + exit 1; + } + + foreach (@srcfile_list) { my $file = $_; my $cmd = "ghdl -a"; - $cmd .= ' -P$XTWI_PATH/ISE_DS/ISE/ghdl/unisim' if $has_unisim; - $cmd .= ' -P$XTWI_PATH/ISE_DS/ISE/ghdl/simprim' if $has_simprim; + $cmd .= " -P$xlpath/unisim" if $has_unisim; + $cmd .= " -P$xlpath/unimacro" if $has_unimacro; + $cmd .= " -P$xlpath/simprim" if $has_simprim; $cmd .= " --ieee=synopsys"; $cmd .= " $file"; print "$cmd\n"; @@ -232,10 +282,10 @@ if (exists $opts{ghdl_a} || exists $opts{ghdl_a_cmd}) { my $rc = int($wrc/256); if ($rc == 0) { my $sig = $wrc % 256; - print STDERR "%vbomconv-I: compilation aborted by signal $sig\n"; + print STDERR "vbomconv-I: compilation aborted by signal $sig\n"; exit(1); } else { - print STDERR "%vbomconv-I: compilation failed (rc=$rc) $?\n"; + print STDERR "vbomconv-I: compilation failed (rc=$rc) $?\n"; exit($rc); } } @@ -267,7 +317,7 @@ if (exists $opts{ghdl_i} || exists $opts{ghdl_i_cmd}) { my $cmd = "ghdl -i"; my $nfile = 0; - foreach (@file_list) { + foreach (@srcfile_list) { next if /\.c$/; # skip C sources, only vhd handled if (not exists $ghdl_work{$_}) { $cmd .= " \\\n $_"; @@ -296,22 +346,26 @@ if (exists $opts{ghdl_i} || exists $opts{ghdl_i_cmd}) { if (exists $opts{ghdl_m} || exists $opts{ghdl_m_cmd} ) { my $cmd = ""; - if (-r "$stem.exe") { # check for .exe, in case we are in cygwin - $cmd .= "rm $stem.exe\n"; # rm old executable to force elaboration - } elsif (-r $stem) { # otherwise - $cmd .= "rm $stem\n" ; # rm old executable to force elaboration + if ($no_xlpath && ($has_unisim || $has_unimacro || $has_simprim) ) { + print STDERR "vbomconv-E: --xlpath required with ghdl_m or ghdl_m_cmd"; + exit 1; + } + + if (-r $stem) { # check for old executable + $cmd .= "rm $stem\n" ; # rm to force elaboration } $cmd .= "ghdl -m"; $cmd .= " -o $stem"; - # -fexplicit needed for ISE 13.1,13.3 - $cmd .= ' -fexplicit' if $has_unisim or $has_simprim; - $cmd .= ' -P$XTWI_PATH/ISE_DS/ISE/ghdl/unisim' if $has_unisim; - $cmd .= ' -P$XTWI_PATH/ISE_DS/ISE/ghdl/simprim' if $has_simprim; + # -fexplicit needed for ISE 13.1,13.3 + $cmd .= ' -fexplicit' if $has_unisim or $has_unimacro or $has_simprim; + $cmd .= " -P$xlpath/unisim" if $has_unisim; + $cmd .= " -P$xlpath/unimacro" if $has_unimacro; + $cmd .= " -P$xlpath/simprim" if $has_simprim; $cmd .= " --ieee=synopsys"; $cmd .= " --no-vital-checks" if $is_ssim or $is_fsim or $is_tsim; - foreach (@file_list) { + foreach (@srcfile_list) { next unless /\.c$/; # C source ? my $ofile = $_; # copy to break alias for following s/// $ofile =~ s{^.*/}{}; # remove directory path @@ -329,7 +383,7 @@ if (exists $opts{ghdl_m} || exists $opts{ghdl_m_cmd} ) { # --xst_prj ---------------------------------------------------------- if (exists $opts{xst_prj}) { - foreach (@file_list) { + foreach (@srcfile_list) { if ($xst_writevhdl) { print "vhdl work $_\n"; } else { @@ -341,44 +395,45 @@ if (exists $opts{xst_prj}) { # --isim_prj --------------------------------------------------------- if (exists $opts{isim_prj}) { - foreach (@file_list) { + foreach (@srcfile_list) { print "vhdl work $_\n"; } } -# --viv_vhdl --------------------------------------------------------- +# --vsyn_prj --------------------------------------------------------- -if (exists $opts{viv_vhdl}) { - print "read_vhdl {\n"; - foreach (@file_list) { +if (exists $opts{vsyn_prj}) { + # setup sources + print "#\n"; + print "# setup sources\n"; + print "#\n"; + print "set src_files {\n"; + foreach (@srcfile_list) { print " $_\n"; } print "}\n"; -} + print "\n"; -# --dep_xst ---------------------------------------------------------- + print "set obj [get_filesets sources_1]\n"; + print "add_files -norecurse -fileset \$obj \$src_files\n"; + print "set_property \"top\" \"$top\" \$obj\n"; -if (exists $opts{dep_xst}) { + # setup constraints print "#\n"; - print "$stem.ngc : $stem.dep_xst\n"; + print "# setup constraints\n"; print "#\n"; - foreach (@file_list) { - print "$stem.ngc : $_\n"; + + print "set xdc_files {\n"; + foreach (@xdcfile_list) { + print " $_\n"; } - # handle cpp preprocessed ucf's - foreach (@ucf_cpp_list) { - my $file = $_; - $file =~ s/\.ucf$//; - print "#\n"; - print "$file.ncd : $file.ucf\n"; - print "include $file.dep_ucf_cpp\n"; - } - # handle plain ucf's - if (scalar(@ucf_cpp_list)==0 && -r "$stem.ucf") { - print "#\n"; - print "$stem.ncd : $stem.ucf\n"; - } - write_vbomdep("$stem.dep_xst"); + print "}\n"; + print "\n"; + + print "set obj [get_filesets constrs_1]\n"; + print "add_files -norecurse -fileset \$obj \$xdc_files\n"; + + print "\n"; } # --dep_ghdl --------------------------------------------------------- @@ -398,7 +453,7 @@ if (exists $opts{dep_ghdl}) { } print "#\n"; - foreach (@file_list) { + foreach (@srcfile_list) { if (/\.c$/) { my $ofile = $_; # copy to break alias for following s/// $ofile =~ s{^.*/}{}; # remove directory path @@ -417,7 +472,7 @@ if (exists $opts{dep_ghdl}) { if ($is_ssim) { - foreach (@file_list) { + foreach (@srcfile_list) { my $file = $_; # copy to break alias for following s/// if (/\.c$/) { $file =~ s{^.*/}{}; # remove directory path @@ -428,7 +483,7 @@ if (exists $opts{dep_ghdl}) { print "$stem_fsim : $file\n"; } - foreach (@file_list) { + foreach (@srcfile_list) { my $file = $_; # copy to break alias for following s/// if (/\.c$/) { $file =~ s{^.*/}{}; # remove directory path @@ -445,6 +500,31 @@ if (exists $opts{dep_ghdl}) { } +# --dep_xst ---------------------------------------------------------- + +if (exists $opts{dep_xst}) { + print "#\n"; + print "$stem.ngc : $stem.dep_xst\n"; + print "#\n"; + foreach (@srcfile_list) { + print "$stem.ngc : $_\n"; + } + # handle cpp preprocessed ucf's + foreach (@ucf_cpp_list) { + my $file = $_; + $file =~ s/\.ucf$//; + print "#\n"; + print "$file.ncd : $file.ucf\n"; + print "include $file.dep_ucf_cpp\n"; + } + # handle plain ucf's + if (scalar(@ucf_cpp_list)==0 && -r "$stem.ucf") { + print "#\n"; + print "$stem.ncd : $stem.ucf\n"; + } + write_vbomdep("$stem.dep_xst"); +} + # --dep_isim --------------------------------------------------------- if (exists $opts{dep_isim}) { @@ -465,19 +545,19 @@ if (exists $opts{dep_isim}) { } print "#\n"; - foreach (@file_list) { + foreach (@srcfile_list) { print "$stem_isim : $_\n"; } if ($is_ssim) { - foreach (@file_list) { + foreach (@srcfile_list) { my $file = $_; # copy to break alias for following s/// $file =~ s/_ssim\.vhd$/_fsim.vhd/; print "$stem_fsim_isim : $file\n"; } - foreach (@file_list) { + foreach (@srcfile_list) { my $file = $_; # copy to break alias for following s/// $file =~ s/_ssim\.vhd$/_tsim.vhd/; print "$stem_tsim_isim : $file\n"; @@ -488,26 +568,49 @@ if (exists $opts{dep_isim}) { write_vbomdep("$stem.dep_isim"); } -# --xst_export or ghdl_export or isim_export ------------------------- +# --dep_vsyn --------------------------------------------------------- -if (exists $opts{xst_export} or - exists $opts{ghdl_export} or +if (exists $opts{dep_vsyn}) { + print "#\n"; + print "$stem.bit : $stem.dep_vsyn\n"; + print "#\n"; + my @files; + push @files, @srcfile_list; + push @files, @xdcfile_list; + foreach (@files) { + print "$stem.bit : $_\n"; + } + print "#\n"; + foreach (@files) { + print "${stem}_syn.dcp : $_\n"; + } + print "#\n"; + foreach (@files) { + print "${stem}_rou.dcp : $_\n"; + } + write_vbomdep("$stem.dep_vsyn"); +} + +# --ghdl_export or xst_export or isim_export ------------------------- + +if (exists $opts{ghdl_export} or + exists $opts{xst_export} or exists $opts{isim_export}) { my $edir; - $edir = $opts{xst_export} if exists $opts{xst_export}; $edir = $opts{ghdl_export} if exists $opts{ghdl_export}; + $edir = $opts{xst_export} if exists $opts{xst_export}; $edir = $opts{isim_export} if exists $opts{isim_export}; if (not -d $edir) { - print STDERR "%vbomconv-I: create target directory $edir\n"; + print STDERR "vbomconv-I: create target directory $edir\n"; system("mkdir -p $edir") == 0 or die "mkdir failed: $?"; } else { - print STDERR "%vbomconv-I: target directory $edir already exists\n"; + print STDERR "vbomconv-I: target directory $edir already exists\n"; } open(PFILE, ">$edir/$stem.prj") or die "can't write open $edir/$stem.prj: $!"; - foreach (@file_list) { + foreach (@srcfile_list) { my $fname = $_; my $fdpath = "."; if (m{(.*)/(.*)}) { @@ -549,8 +652,8 @@ if (exists $opts{flist}) { my @flist; - push @flist, @file_list; - push @flist, sort keys %read_tbl; + push @flist, @srcfile_list; + push @flist, sort keys %vbom_done; if (scalar(@ucf_cpp_list)) { foreach (@ucf_cpp_list) { @@ -562,6 +665,8 @@ if (exists $opts{flist}) { } } + push @flist, @xdcfile_list; + foreach (sort @flist) { my $fname = $_; my $fdpath = "."; @@ -590,7 +695,7 @@ sub read_vbom { $vbom_file = $2; } - $read_tbl{$vbom} += 1; # mark this vbom already read + $vbom_done{$vbom} += 1; # mark this vbom already read while () { chomp; @@ -604,7 +709,7 @@ sub read_vbom { my $para = $1; my $val = $2; if ($val eq "") { - print STDERR "%vbomconv-E: invalid \'$_\' in $vbom_file\n"; + print STDERR "vbomconv-E: invalid \'$_\' in $vbom_file\n"; exit 1; } if (not exists $para_tbl{$para}) { @@ -635,11 +740,11 @@ sub read_vbom { if ($do_trace) { print STDERR "--- use \${$para} -> $para_tbl{$para}\n"; } else { - ## print STDERR "%vbomconv-I: \${$para} -> $para_tbl{$para}\n"; + ## print STDERR "vbomconv-I: \${$para} -> $para_tbl{$para}\n"; } $_ = $pre . "!" . $para_tbl{$para} . $post; } else { - print STDERR "%vbomconv-E: undefined \${$para} in $vbom_file\n"; + print STDERR "vbomconv-E: undefined \${$para} in $vbom_file\n"; exit 1; } } @@ -650,13 +755,15 @@ sub read_vbom { my $keep = $is_any; ## print STDERR "+++1 |$qual|$name|$vbom|\n"; foreach my $pref (split /,/,$qual) { - if ($pref =~ /^(xst|ghdl|isim|sim)$/) { - $keep = 1 if ($pref eq "xst" && $is_xst); + if ($pref =~ /^(ghdl|xst|isim|vsyn|vsim|sim)$/) { $keep = 1 if ($pref eq "ghdl" && $is_ghdl); + $keep = 1 if ($pref eq "xst" && $is_xst); $keep = 1 if ($pref eq "isim" && $is_isim); + $keep = 1 if ($pref eq "vsyn" && $is_vsyn); + $keep = 1 if ($pref eq "vsim" && $is_vsim); $keep = 1 if ($pref eq "sim" && $is_sim); } else { - print STDERR "%vbomconv-W: unknown tag [$pref] in $vbom_file\n"; + print STDERR "vbomconv-W: unknown tag [$pref] in $vbom_file\n"; } } if (not $keep) { @@ -682,18 +789,26 @@ sub read_vbom { } elsif ($tag eq '@ucf_cpp') { push @ucf_cpp_list, $val; + # process @xdc: lines + } elsif ($tag eq '@xdc') { + push @{$vbom_xdc{$vbom}}, canon_fname($vbom_path, $val); + # process @lib: lines } elsif ($tag eq '@lib') { if ($val eq 'unisim') { $has_unisim = 1; + } elsif ($val eq 'unimacro') { + $has_unimacro = 1; } elsif ($val eq 'simprim') { $has_simprim = 1; } else { - print STDERR "%vbomconv-E: invalid lib type \'$tag\' in $vbom_file\n"; + print STDERR "vbomconv-E: invalid lib type \'$tag\' in $vbom_file\n"; exit 1; } + + # catch invalid @ tags } else { - print STDERR "%vbomconv-E: invalid \'$tag:\' line in $vbom_file\n"; + print STDERR "vbomconv-E: invalid \'$tag:\' line in $vbom_file\n"; exit 1; } next; @@ -720,15 +835,14 @@ sub read_vbom { $has_simprim = 1; } - # build vbom table - push @{$vbom_tbl{$vbom}}, $fullname; - print STDERR "--- add $fullname\n" if $do_trace; + push @{$vbom_files{$vbom}}, $fullname; + print STDERR "--- add $fullname\n" if $do_trace; # if a vbom, queue if not not already read - if ($fullname =~ m{\.vbom$} && not exists $read_tbl{$fullname} ) { - push @vbom_list, $fullname; - print STDERR "--- queue $fullname\n" if $do_trace; + if ($fullname =~ m{\.vbom$} && not exists $vbom_done{$fullname} ) { + push @vbom_queue, $fullname; + print STDERR "--- queue $fullname\n" if $do_trace; } } @@ -744,27 +858,34 @@ sub scan_vbom { my ($vbom) = @_; $level += 1; - my $rank = 1000*$level + scalar(@{$vbom_tbl{$vbom}}); + my $rank = 1000*$level + scalar(@{$vbom_files{$vbom}}); print STDERR "--> $level: $vbom\n" if $do_trace; - die "%vbomcov-E excessive vbom stack depth \n" if $level>=1000; + die "vbomcov-E excessive vbom stack depth \n" if $level>=1000; - foreach (@{$vbom_tbl{$vbom}}) { + if (exists $vbom_rank{$vbom}) { + $vbom_rank{$vbom}{min} = $level if $level < $vbom_rank{$vbom}{min}; + $vbom_rank{$vbom}{max} = $level if $level > $vbom_rank{$vbom}{max}; + } else { + $vbom_rank{$vbom} = {min=>$level, max=>$level}; + } + + foreach (@{$vbom_files{$vbom}}) { my $file = $_; $rank -= 1; if (m{\.vbom$}) { scan_vbom($file); } else { - if (exists $file_tbl{$file}) { - if ($rank > $file_tbl{$file}) { - print STDERR " $file $file_tbl{$file} -> $rank\n" if $do_trace; - $file_tbl{$file} = $rank; + if (exists $srcfile_rank{$file}) { + if ($rank > $srcfile_rank{$file}) { + print STDERR " $file $srcfile_rank{$file} -> $rank\n" if $do_trace; + $srcfile_rank{$file} = $rank; } else { - print STDERR " $file $file_tbl{$file} (keep)\n" if $do_trace; + print STDERR " $file $srcfile_rank{$file} (keep)\n" if $do_trace; } } else { - $file_tbl{$file} = $rank; - print STDERR " $file $file_tbl{$file} (new)\n" if $do_trace; + $srcfile_rank{$file} = $rank; + print STDERR " $file $srcfile_rank{$file} (new)\n" if $do_trace; } } } @@ -787,9 +908,9 @@ sub copy_edir { sub write_vbomdep { my ($target) = @_; print "#\n"; - print "# .dep_ on .vbom dependencies\n"; + print "# .dep_* on .vbom dependencies\n"; print "#\n"; - foreach (sort keys %read_tbl) { + foreach (sort keys %vbom_done) { print "$target : $_\n"; } } @@ -821,20 +942,21 @@ sub print_help { print "usage: vbomconf file.vbom\n"; print " --help this message\n"; print " --trace trace recursive processing of vbom's\n"; - print " --dep_xst generate xst dependencies for make (on stdout)\n"; - print " --dep_ghdl generate ghdl dependencies for make (on stdout)\n"; - print " --dep_isim generate isim dependencies for make (on stdout)\n"; - print " --xst_prj generate xst project file (on stdout)\n"; - print " --isim_prj generate isim project file (on stdout)\n"; - print " --viv_vhdl generate vivado read_vhdl command (on stdout)\n"; + print " --dep_ghdl generate ghdl dependencies for make\n"; + print " --dep_xst generate xst dependencies for make\n"; + print " --dep_isim generate isim dependencies for make\n"; + print " --dep_vsyn generate vsyn dependencies for make\n"; print " --ghdl_a generate and execute ghdl -a (analyse)\n"; print " --ghdl_a_cmd like ghdl_a, but only print command, no exec\n"; print " --ghdl_i generate and execute ghdl -i (inspect)\n"; print " --ghdl_i_cmd like ghdl_i, but only print command, no exec\n"; print " --ghdl_m generate and execute ghdl -m (make)\n"; print " --ghdl_m_cmd like ghdl_m, but only print command, no exec\n"; - print " --xst_export=s export all xst source files into directory s\n"; + print " --xst_prj generate xst project file\n"; + print " --isim_prj generate isim project file\n"; + print " --vsyn_prj generate vivado synthesis project definition\n"; print " --ghdl_export=s export all ghdl source files into directory s\n"; + print " --xst_export=s export all xst source files into directory s\n"; print " --isim_export=s export all isim source files into directory s\n"; print " --get_top return top level entity name\n"; print " --flist list all files touched by vbom for all tags\n"; diff --git a/tools/bin/xilinx_ghdl_unisim b/tools/bin/xilinx_ghdl_unisim deleted file mode 100755 index 99d66302..00000000 --- a/tools/bin/xilinx_ghdl_unisim +++ /dev/null @@ -1,74 +0,0 @@ -#!/bin/sh -# $Id: xilinx_ghdl_unisim 547 2013-12-29 13:10:07Z mueller $ -# -# Revision History: -# Date Rev Vers Comment -# 2009-11-08 248 1.1 adopt to ISE 11.1, use VITAL models from ./primitive -# 2007-10-26 92 1.0 Initial version -# - -if [ -z "$XILINX" ] -then - echo "XILINX not defined" - exit 1 -fi -# -cd $XILINX -echo "============================================================" -echo "* Build ghdl UNISIM libs for $XILINX" -echo "============================================================" -# -if [ ! -d ghdl ] -then - mkdir ghdl -fi -# -cd $XILINX/ghdl -if [ ! -d unisim ] -then - mkdir unisim -fi -# -cd $XILINX/ghdl/unisim -cp $XILINX/vhdl/src/unisims/unisim_VCOMP.vhd . -cp $XILINX/vhdl/src/unisims/unisim_VPKG.vhd . -# -# for ISE 11.1 the VITAL models are individually in sub-dir primitives -# and vhdl_analyze_order is a file with best compilation order -# for ISE 10 and before all VITAL models are in one concatenetaed file -# in this case xilinx_vhdl_chop will chop this into individual model files -# -if [ ! -d primitive ] -then - mkdir primitive -fi -cd primitive -# -if [ -d $XILINX/vhdl/src/unisims/primitive ] -then - cp -p $XILINX/vhdl/src/unisims/primitive/*.vhd . - cp -p $XILINX/vhdl/src/unisims/primitive/vhdl_analyze_order . -else - xilinx_vhdl_chop $XILINX/vhdl/src/unisims/unisim_VITAL.vhd - find . -maxdepth 1 -name "*.vhd" | perl -p -e 's|\./||' > vhdl_analyze_order -fi -# -xilinx_vhdl_memcolltype_fix -# -cd .. -echo "# ghdl ... unisim_VCOMP.vhd" -ghdl -a --ieee=synopsys --work=unisim unisim_VCOMP.vhd -echo "# ghdl ... unisim_VPKG.vhd" -ghdl -a --ieee=synopsys --work=unisim unisim_VPKG.vhd - -for file in `cat primitive/vhdl_analyze_order` -do - echo "# ghdl ... primitive/$file" - ghdl -a -fexplicit --ieee=synopsys --work=unisim \ - --no-vital-checks primitive/$file 2>&1 |\ - tee primitive/$file.ghdl.log -done -# -echo "--- scan for compilation errors:" -find primitive -name "*.ghdl.log" | xargs grep error -# diff --git a/tools/bin/xilinx_vhdl_chop b/tools/bin/xilinx_vhdl_chop deleted file mode 100755 index 78b04455..00000000 --- a/tools/bin/xilinx_vhdl_chop +++ /dev/null @@ -1,40 +0,0 @@ -#!/usr/bin/perl -w -# $Id: xilinx_vhdl_chop 314 2010-07-09 17:38:41Z mueller $ -# -# Copyright 2007- by Walter F.J. Mueller -# -# This program is free software; you may redistribute and/or modify it under -# the terms of the GNU General Public License as published by the Free -# Software Foundation, either version 2, or at your option any later version. -# -# This program is distributed in the hope that it will be useful, but -# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY -# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -# for complete details. -# -# Revision History: -# Date Rev Vers Comment -# 2007-06-06 50 1.0 Initial version -# -# splits a xilinx unisim_VITAL.vhd file along separators looking like: -# -# -- $Header: /and5b1.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ -# - -use 5.003; # require Perl 5.003 or higher -use strict; # require strict checking - -while (<>) { - chomp; - my @line = split; - if (/^-- \$Header/) { - my @file = split(/\//,$line[2]); - my $name = $file[$#file]; - $name =~ s/,v//; - print "writing $name \n"; - close(OFILE); - open(OFILE, "> $name") or die "Couldn't open output file: $!\n"; - } - print OFILE $_,"\n"; -} -close(OFILE); diff --git a/tools/bin/xilinx_ghdl_simprim b/tools/bin/xise_ghdl_simprim similarity index 53% rename from tools/bin/xilinx_ghdl_simprim rename to tools/bin/xise_ghdl_simprim index 60f09f8e..68725efd 100755 --- a/tools/bin/xilinx_ghdl_simprim +++ b/tools/bin/xise_ghdl_simprim @@ -1,21 +1,33 @@ -#!/bin/sh -# $Id: xilinx_ghdl_simprim 547 2013-12-29 13:10:07Z mueller $ +#!/bin/bash +# $Id: xise_ghdl_simprim 642 2015-02-06 18:53:12Z mueller $ +# +# Copyright 2007-2015 by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory # # Revision History: # Date Rev Vers Comment +# 2015-02-03 642 1.3 remove ISE 10 legacy support +# 2015-01-29 639 1.2 rename from xilinx_*; use XTWI_PATH rather XILINX # 2009-11-08 248 1.1 adopt to ISE 11.1, use VITAL models from ./primitive # 2007-10-26 92 1.0 Initial version # -if [ -z "$XILINX" ] +if [ -z "$XTWI_PATH" ] then - echo "XILINX not defined" + echo "XTWI_PATH not defined" + exit 1 +fi +if [ ! -d "$XTWI_PATH/ISE_DS/ISE" ] +then + echo "$XTWI_PATHISE_DS/ISE not existing" exit 1 fi # -cd $XILINX +ise_path=$XTWI_PATH/ISE_DS/ISE +# +cd $ise_path echo "============================================================" -echo "* Build ghdl SIMPRIM libs for $XILINX" +echo "* Build ghdl SIMPRIM lib for $ise_path" echo "============================================================" # if [ ! -d ghdl ] @@ -23,39 +35,27 @@ then mkdir ghdl fi # -cd $XILINX/ghdl +cd $ise_path/ghdl if [ ! -d simprim ] then mkdir simprim fi +cd simprim # -cd $XILINX/ghdl/simprim -cp $XILINX/vhdl/src/simprims/simprim_Vcomponents.vhd . -cp $XILINX/vhdl/src/simprims/simprim_Vpackage.vhd . -# -# for ISE 11.1 the VITAL models are individually in sub-dir primitives -# and vhdl_analyze_order is a file with best compilation order -# for ISE 10 and before all VITAL models are in one concatenetaed file -# in this case xilinx_vhdl_chop will chop this into individual model files +cp $ise_path/vhdl/src/simprims/simprim_Vcomponents.vhd . +cp $ise_path/vhdl/src/simprims/simprim_Vpackage.vhd . # if [ ! -d primitive ] then mkdir primitive fi -cd primitive -# -if [ -d $XILINX/vhdl/src/simprims/primitive ] -then - cp -p $XILINX/vhdl/src/simprims/primitive/other/*.vhd . - cp -p $XILINX/vhdl/src/simprims/primitive/other/vhdl_analyze_order . -else - xilinx_vhdl_chop $XILINX/vhdl/src/simprims/simprim_VITAL.vhd - find . -maxdepth 1 -name "*.vhd" | perl -p -e 's|\./||' > vhdl_analyze_order -fi # +pushd primitive +cp -p $ise_path/vhdl/src/simprims/primitive/other/*.vhd . +cp -p $ise_path/vhdl/src/simprims/primitive/other/vhdl_analyze_order . xilinx_vhdl_memcolltype_fix +popd # -cd .. echo "# ghdl ... simprim_Vcomponents.vhd" ghdl -a --ieee=synopsys --work=simprim --no-vital-checks simprim_Vcomponents.vhd echo "# ghdl ... simprim_Vpackage.vhd" diff --git a/tools/bin/xise_ghdl_unisim b/tools/bin/xise_ghdl_unisim new file mode 100755 index 00000000..af135833 --- /dev/null +++ b/tools/bin/xise_ghdl_unisim @@ -0,0 +1,98 @@ +#!/bin/bash +# $Id: xise_ghdl_unisim 642 2015-02-06 18:53:12Z mueller $ +# +# Copyright 2007-2015 by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# Revision History: +# Date Rev Vers Comment +# 2015-02-03 642 1.3 remove ISE 10 legacy support; add unimacro support +# 2015-01-29 639 1.2 rename from xilinx_*; use XTWI_PATH rather XILINX +# 2009-11-08 248 1.1 adopt to ISE 11.1, use VITAL models from ./primitive +# 2007-10-26 92 1.0 Initial version +# + +if [ -z "$XTWI_PATH" ] +then + echo "XTWI_PATH not defined" + exit 1 +fi +if [ ! -d "$XTWI_PATH/ISE_DS/ISE" ] +then + echo "$XTWI_PATH/ISE_DS/ISE not existing" + exit 1 +fi +# +ise_path=$XTWI_PATH/ISE_DS/ISE +# +cd $ise_path +echo "============================================================" +echo "* Build ghdl UNISIM lib for $ise_path" +echo "============================================================" +# +if [ ! -d ghdl ] +then + mkdir ghdl +fi +cd ghdl +# +if [ ! -d unisim ] +then + mkdir unisim +fi +cd unisim +# +cp $ise_path/vhdl/src/unisims/unisim_VCOMP.vhd . +cp $ise_path/vhdl/src/unisims/unisim_VPKG.vhd . +# +if [ ! -d primitive ] +then + mkdir primitive +fi +pushd primitive +# +cp -p $ise_path/vhdl/src/unisims/primitive/*.vhd . +cp -p $ise_path/vhdl/src/unisims/primitive/vhdl_analyze_order . +# +xilinx_vhdl_memcolltype_fix +popd + +echo "# ghdl ... unisim_VCOMP.vhd" +ghdl -a --ieee=synopsys --work=unisim unisim_VCOMP.vhd +echo "# ghdl ... unisim_VPKG.vhd" +ghdl -a --ieee=synopsys --work=unisim unisim_VPKG.vhd + +for file in `cat primitive/vhdl_analyze_order` +do + echo "# ghdl ... primitive/$file" + ghdl -a -fexplicit --ieee=synopsys --work=unisim \ + --no-vital-checks primitive/$file 2>&1 |\ + tee primitive/$file.ghdl.log +done +# +echo "--- scan for compilation errors:" +find primitive -name "*.ghdl.log" | xargs grep error +# +echo "============================================================" +echo "* Build ghdl UNIMACRO lib for $XTWI_PATH/ISE_DS/ISE" +echo "============================================================" +# +cd $ise_path/ghdl +if [ ! -d unimacro ] +then + mkdir unimacro +fi +# +cd unimacro +cp $ise_path/vhdl/src/unimacro/*.vhd . +# +for file in *.vhd +do + echo "# ghdl ... $file" + ghdl -a -P../unisim -fexplicit --ieee=synopsys --work=unimacro \ + --no-vital-checks $file 2>&1 | tee $file.ghdl.log +done +# +echo "--- scan for compilation errors:" +find . -name "*.ghdl.log" | xargs grep error +# diff --git a/tools/bin/isemsg_filter b/tools/bin/xise_msg_filter similarity index 88% rename from tools/bin/isemsg_filter rename to tools/bin/xise_msg_filter index d479eca0..9d2dad8c 100755 --- a/tools/bin/isemsg_filter +++ b/tools/bin/xise_msg_filter @@ -1,7 +1,7 @@ #!/usr/bin/perl -w -# $Id: isemsg_filter 550 2014-02-03 08:16:57Z mueller $ +# $Id: xise_msg_filter 646 2015-02-15 12:04:55Z mueller $ # -# Copyright 2011-2014 by Walter F.J. Mueller +# Copyright 2011-2015 by Walter F.J. Mueller # # This program is free software; you may redistribute and/or modify it under # the terms of the GNU General Public License as published by the Free @@ -14,6 +14,7 @@ # # Revision History: # Date Rev Version Comment +# 2015-01-30 640 1.1.2 renamed from isemsg_filter # 2014-02-01 550 1.1.1 rename --pack to --pacc (accepted is meant here) # 2012-01-04 450 1.1 preliminary check for par 'all constraints met' # 2011-08-14 406 1.0 Initial version @@ -43,7 +44,7 @@ my $ackcnt = 0; my $misscnt = 0; -autoflush STDOUT 1; # autoflush, so noting lost on exec later +autoflush STDOUT 1; # autoflush, so nothing lost on exec later if (exists $opts{help}) { print_help; @@ -51,13 +52,13 @@ if (exists $opts{help}) { } if (!defined $type || !defined $mfsnam || !defined $lognam) { - print STDERR "%isemsg_filter-E: one of 'type mfset log' missing \n\n"; + print STDERR "xise_msg_filter-E: one of 'type mfset log' missing \n\n"; print_help; exit 1; } if ($type !~ m{^(xst|tra|map|par|twr|bgn)$}) { - print STDERR "%isemsg_filter-E: type must be xst,tra,map,par,twr, or bgn\n"; + print STDERR "xise_msg_filter-E: type must be xst,tra,map,par,twr, or bgn\n"; exit 1; } @@ -121,7 +122,7 @@ if ($misscnt) { #------------------------------------------------------------------------------- sub read_mfs { if (not -r $mfsnam) { - print STDERR "%isemsg_filter-E: \'$mfsnam\' not existing or readable\n"; + print STDERR "xise_msg_filter-E: \'$mfsnam\' not existing or readable\n"; return 1; } @@ -155,7 +156,7 @@ sub read_mfs { #------------------------------------------------------------------------------- sub read_log { if (not -r $lognam) { - print STDERR "%isemsg_filter-E: \'$lognam\' not existing or readable\n"; + print STDERR "xise_msg_filter-E: \'$lognam\' not existing or readable\n"; return 1; } @@ -203,7 +204,7 @@ sub read_log { #------------------------------------------------------------------------------- sub print_help { - print "usage: isemsg_filter [options] type mfset log\n"; + print "usage: xise_msg_filter [options] type mfset log\n"; print " type log file type: xst,tra,map,par,twr, or bgn\n"; print " mfset message filter set file\n"; print " log log file\n"; diff --git a/tools/bin/xtwi b/tools/bin/xtwi index 8fc6a973..e5eace9e 100755 --- a/tools/bin/xtwi +++ b/tools/bin/xtwi @@ -1,5 +1,8 @@ #!/bin/bash -# $Id: xtwi 544 2013-11-10 22:42:16Z mueller $ +# $Id: xtwi 641 2015-02-01 22:12:15Z mueller $ +# +# Copyright 2013- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory # # Xilinx Tool Wrapper script for ISE: # define XTWI_PATH diff --git a/tools/bin/xtwv b/tools/bin/xtwv index e063a7f7..219e82d3 100755 --- a/tools/bin/xtwv +++ b/tools/bin/xtwv @@ -1,5 +1,8 @@ #!/bin/bash -# $Id: xtwv 554 2014-04-21 14:01:51Z mueller $ +# $Id: xtwv 641 2015-02-01 22:12:15Z mueller $ +# +# Copyright 2013- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory # # Xilinx Tool Wrapper script for Vivado # define XTWV_PATH diff --git a/tools/bin/xviv_ghdl_unisim b/tools/bin/xviv_ghdl_unisim new file mode 100755 index 00000000..a74da50f --- /dev/null +++ b/tools/bin/xviv_ghdl_unisim @@ -0,0 +1,127 @@ +#!/bin/bash +# $Id: xviv_ghdl_unisim 642 2015-02-06 18:53:12Z mueller $ +# +# Copyright 2015- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# Revision History: +# Date Rev Vers Comment +# 2015-02-02 642 1.0 Initial version +# + +if [ -z "$XTWV_PATH" ] +then + echo "XTWV_PATH not defined" + exit 1 +fi +if [ ! -d "$XTWV_PATH" ] +then + echo "$XTWV_PATH not existing" + exit 1 +fi +# +cd $XTWV_PATH +echo "============================================================" +echo "* Build ghdl UNISIM lib for $XTWV_PATH" +echo "============================================================" +# +if [ ! -d ghdl ] +then + mkdir ghdl +fi +cd ghdl +# +if [ ! -d unisim ] +then + mkdir unisim +fi +cd unisim +# +# copy VCOMP and VPKG ---------------------------- +# +cp $XTWV_PATH/data/vhdl/src/unisims/unisim_retarget_VCOMP.vhd . +cp $XTWV_PATH/data/vhdl/src/unisims/unisim_VPKG.vhd . +# +# copy 'primitive' models ------------------------ +# +if [ ! -d primitive ] +then + mkdir primitive +fi +pushd primitive +# +cp -p $XTWV_PATH/data/vhdl/src/unisims/primitive/*.vhd . +cp -p $XTWV_PATH/data/vhdl/src/unisims/primitive/vhdl_analyze_order . +# in Vivado 2014.4 the vhdl_analyze_order and contains two extraneous entries +# simply drop them to avoid errors later on +sed -i.bak -e '\|OBUFTDSE3| d' \ + -e '\|OBUFTE3| d' \ + vhdl_analyze_order +# +xilinx_vhdl_memcolltype_fix +popd +# +# copy 'retarget' models ------------------------- +# +if [ ! -d retarget ] +then + mkdir retarget +fi +pushd retarget +# +cp -p $XTWV_PATH/data/vhdl/src/unisims/retarget/*.vhd . +ls -1 *.vhd > vhdl_analyze_order +# +xilinx_vhdl_memcolltype_fix +popd +# +# now compile all -------------------------------- +# +echo "# ghdl ... unisim_retarget_VCOMP.vhd" +ghdl -a --ieee=synopsys --work=unisim unisim_retarget_VCOMP.vhd +echo "# ghdl ... unisim_VPKG.vhd" +ghdl -a --ieee=synopsys --work=unisim unisim_VPKG.vhd + +for file in `cat primitive/vhdl_analyze_order` +do + echo "# ghdl ... primitive/$file" + ghdl -a -fexplicit --ieee=synopsys --work=unisim \ + --no-vital-checks primitive/$file 2>&1 |\ + tee primitive/$file.ghdl.log +done +# +for file in `cat retarget/vhdl_analyze_order` +do + echo "# ghdl ... retarget/$file" + ghdl -a -fexplicit --ieee=synopsys --work=unisim \ + --no-vital-checks retarget/$file 2>&1 |\ + tee retarget/$file.ghdl.log +done +# +echo "--- scan for compilation errors:" +find primitive retarget -name "*.ghdl.log" | xargs grep error +# +# +echo "============================================================" +echo "* Build ghdl UNIMACRO lib for $XTWV_PATH" +echo "============================================================" +# +cd $XTWV_PATH/ghdl +if [ ! -d unimacro ] +then + mkdir unimacro +fi +cd unimacro +# +cp $XTWV_PATH/data/vhdl/src/unimacro/*.vhd . +# +for file in *.vhd +do + echo "# ghdl ... $file" + ghdl -a -P../unisim -fexplicit --ieee=synopsys --work=unimacro \ + --no-vital-checks $file 2>&1 | tee $file.ghdl.log +done +# +echo "--- scan for compilation errors:" +find . -name "*.ghdl.log" | xargs grep error +# diff --git a/tools/dox/w11_cpp.Doxyfile b/tools/dox/w11_cpp.Doxyfile index 865d65a2..d9e62b9e 100644 --- a/tools/dox/w11_cpp.Doxyfile +++ b/tools/dox/w11_cpp.Doxyfile @@ -5,7 +5,7 @@ #--------------------------------------------------------------------------- DOXYFILE_ENCODING = UTF-8 PROJECT_NAME = "w11 - cpp" -PROJECT_NUMBER = 0.63 +PROJECT_NUMBER = 0.64 PROJECT_BRIEF = "Backend server for Rlink and w11" PROJECT_LOGO = OUTPUT_DIRECTORY = $(RETRODOXY)/w11/cpp diff --git a/tools/dox/w11_tcl.Doxyfile b/tools/dox/w11_tcl.Doxyfile index 3c5ead96..268523af 100644 --- a/tools/dox/w11_tcl.Doxyfile +++ b/tools/dox/w11_tcl.Doxyfile @@ -5,7 +5,7 @@ #--------------------------------------------------------------------------- DOXYFILE_ENCODING = UTF-8 PROJECT_NAME = "w11 - tcl" -PROJECT_NUMBER = 0.63 +PROJECT_NUMBER = 0.64 PROJECT_BRIEF = "Backend server for Rlink and w11" PROJECT_LOGO = OUTPUT_DIRECTORY = $(RETRODOXY)/w11/tcl diff --git a/tools/dox/w11_vhd_all.Doxyfile b/tools/dox/w11_vhd_all.Doxyfile index 1ab62bf2..ffda9d04 100644 --- a/tools/dox/w11_vhd_all.Doxyfile +++ b/tools/dox/w11_vhd_all.Doxyfile @@ -5,7 +5,7 @@ #--------------------------------------------------------------------------- DOXYFILE_ENCODING = UTF-8 PROJECT_NAME = "w11 - vhd" -PROJECT_NUMBER = 0.63 +PROJECT_NUMBER = 0.64 PROJECT_BRIEF = "W11 CPU core and support modules" PROJECT_LOGO = OUTPUT_DIRECTORY = $(RETRODOXY)/w11/vhd diff --git a/tools/fx2/bin/nexys2_jtag_2fifo_as.ihx b/tools/fx2/bin/nexys2_jtag_2fifo_as.ihx deleted file mode 100644 index efea57a4..00000000 --- a/tools/fx2/bin/nexys2_jtag_2fifo_as.ihx +++ /dev/null @@ -1,144 +0,0 @@ -:06000000020E7402006B09 -:03000B0002006B85 -:0300130002006B7D -:03001B0002006B75 -:0300230002006B6D -:03002B0002006B65 -:0300330002006B5D -:03003B0002006B55 -:0300430002006B4D -:03004B0002006B45 -:0300530002006B3D -:03005B0002006B35 -:0300630002006B2D -:01006B003262 -:2000800002006B0002006B0002006B0002006B0002006B0002006B0002006B0002006B00F8 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-:200DFB00F000000090E65774FFF000000090E658E4F090E65974FFF090E65AE4F090E65B6F -:200E1B0074FFF090E65CE4F090E65D74FFF090E65EE4F090E65F74FFF000000090E660E4DE -:200E3B00F000000090E66174FFF090E662E4F090E66374FFF090E665E4F090E668740BF089 -:130E5B00AF9174EF5FF591AF9174BF5FF591D2E8D2EA220C -:200E6E0022AF82120E6EDFFB2290FB50A3E582458370F922AE82AF83120E771EBEFF011F5B -:050E8E00EE4F70F4229C -:0D0E9F007581211205D6E5826003020E9CCC -:00000001FF diff --git a/tools/fx2/src/Makefile b/tools/fx2/src/Makefile index ceee3b19..a0ee9147 100644 --- a/tools/fx2/src/Makefile +++ b/tools/fx2/src/Makefile @@ -1,6 +1,6 @@ -# $Id: Makefile 604 2014-11-16 22:33:09Z mueller $ +# $Id: Makefile 638 2015-01-25 22:01:38Z mueller $ # -# Copyright 2011-2014 by Walter F.J. Mueller +# Copyright 2011-2015 by Walter F.J. Mueller # Code was forked from ixo-jtag.svn.sourceforge.net on 2011-07-17 # # - original copyright and licence disclaimer -------------------------------- @@ -22,6 +22,7 @@ # # Revision History: # Date Rev Version Comment +# 2015-01-25 638 2.1 retire _as versions (old async interface) # 2014-11-16 604 2.0 add sdcc 3.x migration # 2012-04-09 461 1.5.1 fixed nexys3_jtag_3fifo_ic.ihx rule,used _2fifo code # 2012-02-11 457 1.5 re-organize VID/PID and descriptor handling @@ -95,13 +96,9 @@ LDFLAGS+=-L ${LIBDIR} # primary target rules # ALLIHX =nexys2_jtag.ihx -ALLIHX +=nexys2_jtag_2fifo_as.ihx -ALLIHX +=nexys2_jtag_3fifo_as.ihx ALLIHX +=nexys2_jtag_2fifo_ic.ihx ALLIHX +=nexys2_jtag_3fifo_ic.ihx ALLIHX +=nexys3_jtag.ihx -ALLIHX +=nexys3_jtag_2fifo_as.ihx -ALLIHX +=nexys3_jtag_3fifo_as.ihx ALLIHX +=nexys3_jtag_2fifo_ic.ihx ALLIHX +=nexys3_jtag_3fifo_ic.ihx @@ -118,10 +115,6 @@ CPPA51=cpp -P -x assembler-with-cpp dscr_nexys2_jtag.a51 : dscr_gen.A51 $(CPPA51) $(DEFVIDPID) -DUSE_NEXYS2 $< > $@ -dscr_nexys2_jtag_2fifo_as.a51 : dscr_gen.A51 - $(CPPA51) $(DEFVIDPID) -DUSE_NEXYS2 -DUSE_2FIFO -DUSE_AS $< > $@ -dscr_nexys2_jtag_3fifo_as.a51 : dscr_gen.A51 - $(CPPA51) $(DEFVIDPID) -DUSE_NEXYS2 -DUSE_3FIFO -DUSE_AS $< > $@ dscr_nexys2_jtag_2fifo_ic.a51 : dscr_gen.A51 $(CPPA51) $(DEFVIDPID) -DUSE_NEXYS2 -DUSE_2FIFO -DUSE_IC $< > $@ dscr_nexys2_jtag_3fifo_ic.a51 : dscr_gen.A51 @@ -129,10 +122,6 @@ dscr_nexys2_jtag_3fifo_ic.a51 : dscr_gen.A51 dscr_nexys3_jtag.a51 : dscr_gen.A51 $(CPPA51) $(DEFVIDPID) -DUSE_NEXYS3 $< > $@ -dscr_nexys3_jtag_2fifo_as.a51 : dscr_gen.A51 - $(CPPA51) $(DEFVIDPID) -DUSE_NEXYS3 -DUSE_2FIFO -DUSE_AS $< > $@ -dscr_nexys3_jtag_3fifo_as.a51 : dscr_gen.A51 - $(CPPA51) $(DEFVIDPID) -DUSE_NEXYS3 -DUSE_3FIFO -DUSE_AS $< > $@ dscr_nexys3_jtag_2fifo_ic.a51 : dscr_gen.A51 $(CPPA51) $(DEFVIDPID) -DUSE_NEXYS3 -DUSE_2FIFO -DUSE_IC $< > $@ dscr_nexys3_jtag_3fifo_ic.a51 : dscr_gen.A51 @@ -143,11 +132,6 @@ dscr_nexys3_jtag_3fifo_ic.a51 : dscr_gen.A51 usb_fifo_init_jtag.rel : usb_fifo_init.c $(CC) -c $(CFLAGS) $< -o $@ # -usb_fifo_init_jtag_2fifo_as.rel : usb_fifo_init.c - $(CC) -c $(CFLAGS) -DUSE_2FIFO $< -o $@ -usb_fifo_init_jtag_3fifo_as.rel : usb_fifo_init.c - $(CC) -c $(CFLAGS) -DUSE_3FIFO $< -o $@ -# usb_fifo_init_jtag_2fifo_ic.rel : usb_fifo_init.c $(CC) -c $(CFLAGS) -DUSE_2FIFO -DUSE_IC30 $< -o $@ usb_fifo_init_jtag_3fifo_ic.rel : usb_fifo_init.c @@ -157,9 +141,6 @@ COM_REL=vectors.rel main.rel eeprom.rel startup.rel # I0_REL=usb_fifo_init_jtag.rel # -IAS2_REL=usb_fifo_init_jtag_2fifo_as.rel -IAS3_REL=usb_fifo_init_jtag_3fifo_as.rel -# IIC2_REL=usb_fifo_init_jtag_2fifo_ic.rel IIC3_REL=usb_fifo_init_jtag_3fifo_ic.rel # @@ -185,11 +166,6 @@ $(N3_REL) : hw_nexys3.c hardware.h nexys2_jtag.ihx : $(COM_REL) dscr_nexys2_jtag.rel \ $(N2_REL) $(I0_REL) $(LIB_REL) # -nexys2_jtag_2fifo_as.ihx : $(COM_REL) dscr_nexys2_jtag_2fifo_as.rel \ - $(N2_REL) $(IAS2_REL) $(LIB_REL) -nexys2_jtag_3fifo_as.ihx : $(COM_REL) dscr_nexys2_jtag_3fifo_as.rel \ - $(N2_REL) $(IAS3_REL) $(LIB_REL) -# nexys2_jtag_2fifo_ic.ihx : $(COM_REL) dscr_nexys2_jtag_2fifo_ic.rel \ $(N2_REL) $(IIC2_REL) $(LIB_REL) nexys2_jtag_3fifo_ic.ihx : $(COM_REL) dscr_nexys2_jtag_3fifo_ic.rel \ @@ -200,11 +176,6 @@ nexys2_jtag_3fifo_ic.ihx : $(COM_REL) dscr_nexys2_jtag_3fifo_ic.rel \ nexys3_jtag.ihx : $(COM_REL) dscr_nexys3_jtag.rel \ $(N3_REL) $(I0_REL) $(LIB_REL) # -nexys3_jtag_2fifo_as.ihx : $(COM_REL) dscr_nexys3_jtag_2fifo_as.rel \ - $(N3_REL) $(IAS2_REL) $(LIB_REL) -nexys3_jtag_3fifo_as.ihx : $(COM_REL) dscr_nexys3_jtag_3fifo_as.rel \ - $(N3_REL) $(IAS3_REL) $(LIB_REL) -# nexys3_jtag_2fifo_ic.ihx : $(COM_REL) dscr_nexys3_jtag_2fifo_ic.rel \ $(N3_REL) $(IIC2_REL) $(LIB_REL) nexys3_jtag_3fifo_ic.ihx : $(COM_REL) dscr_nexys3_jtag_3fifo_ic.rel \ diff --git a/tools/make/generic_cpp.mk b/tools/make/generic_cpp.mk index 67ab35f4..1d92e87a 100644 --- a/tools/make/generic_cpp.mk +++ b/tools/make/generic_cpp.mk @@ -1,8 +1,9 @@ -# $Id: generic_cpp.mk 576 2014-08-02 12:24:28Z mueller $ +# $Id: generic_cpp.mk 630 2015-01-04 22:43:32Z mueller $ # # Revision History: # Date Rev Version Comment -# 2011-11-28 434 1.0.2 use -fno-strict-aliasing to avoid warings from boost bind +# 2015-01-04 630 1.0.3 use -Wextra +# 2011-11-28 434 1.0.2 use -fno-strict-aliasing, avoid warn from boost bind # 2011-11-21 432 1.0.1 gcc 4.4.5 wants explict -fPIC for .so code # 2011-01-09 354 1.0 Initial version (from wrepo/make/generic_cxx.mk) #--- @@ -10,35 +11,39 @@ # Compile options # # -- handle C -# -O optimize -# -fPIC position independent code -# -Wall all warnings +# -O optimize +# -fPIC position independent code +# -Wall all warnings +# -Wextra extra warnings # ifdef CCCOMMAND CC = $(CCCOMMAND) endif ifndef CCOPTFLAGS -CCOPTFLAGS = -O +CCOPTFLAGS = -O3 endif # CC = gcc -CFLAGS = -Wall -fPIC $(CCOPTFLAGS) $(INCLFLAGS) +CFLAGS = -Wall -Wextra -fPIC +CFLAGS += $(CCOPTFLAGS) $(INCLFLAGS) # # -- handle C++ # -# -O optimize -# -fPIC position independent code -# -Wall all warnings +# -O3 optimize +# -fPIC position independent code +# -Wall all warnings +# -Wextra extra warnings # ifdef CXXCOMMAND CXX = $(CXXCOMMAND) endif # ifndef CXXOPTFLAGS -CXXOPTFLAGS = -O2 +CXXOPTFLAGS = -O3 endif # -CXXFLAGS = -Wall -fPIC -fno-strict-aliasing -std=c++0x $(CXXOPTFLAGS) $(INCLFLAGS) +CXXFLAGS = -Wall -Wextra -fPIC -fno-strict-aliasing -std=c++0x +CXXFLAGS += $(CXXOPTFLAGS) $(INCLFLAGS) COMPILE.cc = $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c # LINK.o = $(CXX) $(CXXOPTFLAGS) $(LDOPTFLAGS) $(LDFLAGS) $(TARGET_ARCH) diff --git a/tools/oskit/211bsd_rl/.cvsignore b/tools/oskit/211bsd_rl/.cvsignore new file mode 100644 index 00000000..d9d13510 --- /dev/null +++ b/tools/oskit/211bsd_rl/.cvsignore @@ -0,0 +1,5 @@ +*.dat +*.dsk +*.log +*license.txt +*license.pdf diff --git a/tools/oskit/211bsd_rl/211bsd_rl_boot.scmd b/tools/oskit/211bsd_rl/211bsd_rl_boot.scmd new file mode 100644 index 00000000..f232f4ec --- /dev/null +++ b/tools/oskit/211bsd_rl/211bsd_rl_boot.scmd @@ -0,0 +1,16 @@ +; $Id: 211bsd_rl_boot.scmd 633 2015-01-11 22:58:48Z mueller $ +; +; Setup file for 211bsd RL02 based system +; +; Usage: +; +; pdp11 211bsd_rl_boot.scmd +; +do ../../simh/setup_w11a_max.scmd +set tto 7b +set dlo0 7b +; +att rl0 211bsd_rl_root.dsk +att rl1 211bsd_rl_usr.dsk +; +boo rl0 diff --git a/tools/oskit/211bsd_rl/211bsd_rl_boot.tcl b/tools/oskit/211bsd_rl/211bsd_rl_boot.tcl new file mode 100644 index 00000000..54549c4a --- /dev/null +++ b/tools/oskit/211bsd_rl/211bsd_rl_boot.tcl @@ -0,0 +1,26 @@ +# $Id: 211bsd_rl_boot.tcl 633 2015-01-11 22:58:48Z mueller $ +# +# Setup file for 211bsd RL02 based system +# +# Usage: +# +# console_starter -d DL0 & +# console_starter -d DL1 & +# ti_w11 -xxx @211bsd_rl_boot.tcl ( -xxx depends on sim or fpga connect) +# + +# setup w11 cpu +puts [rlw] + +# setup tt,lp (211bsd uses parity -> use 7 bit mode) +rw11::setup_tt "cpu0" {to7bit 1} +rw11::setup_lp + +# mount disks +cpu0rla0 att 211bsd_rl_root.dsk +cpu0rla1 att 211bsd_rl_usr.dsk + +# and boot +rw11::cpumon +rw11::cpucons +cpu0 boot rla0 diff --git a/tools/oskit/211bsd_rl/README_211bsd_rlset.txt b/tools/oskit/211bsd_rl/README_211bsd_rlset.txt new file mode 100644 index 00000000..81f87fe2 --- /dev/null +++ b/tools/oskit/211bsd_rl/README_211bsd_rlset.txt @@ -0,0 +1,125 @@ +# $Id: README_211bsd_rlset.txt 633 2015-01-11 22:58:48Z mueller $ + +Notes on oskit: 2.11BSD system on RL02 volumes + + Table of content: + + 1. General remarks + 2. Installation + 3. Usage + +1. General remarks --------------------------------------------------- + + See notes on + + 1. I/O emulation setup + 2. FPGA Board setup + 3. Rlink and Backend Server setup + 4. Legal terms + + in $RETROBASE/doc/w11a_os_guide.txt + +2. Installation ------------------------------------------------------ + + - A disk set is available from + http://www.retro11.de/data/oc_w11/oskits/211bsd_rlset.tgz + Download, unpack and copy the disk images (*.dsk), e.g. + + cd $RETROBASE/tools/oskit/211bsd_rl/ + wget http://www.retro11.de/data/oc_w11/oskits/211bsd_rlset.tgz + tar -xzf 211bsd_rlset.tgz + +3. Usage ------------------------------------------------------------- + + - Start backend server and boot system (see section 3 in w11a_os_guide.txt) + boot script: 211bsd_rl_boot.tcl + example: ti_w11 -u @211bsd_rl_boot.tcl + + - Hit in the xterm window to connnect to backend server. + The boot dialog in the console xterm window will look like + (required input is in {..}, with {} denoting a carriage return: + + 70Boot from rl(0,0,0) at 0174400 + : {} + : rl(0,0,0)unix + Boot: bootdev=03400 bootcsr=0174400 + + 2.11 BSD UNIX #1: Thu Jan 1 22:05:02 PST 2009 + root@curly.2bsd.com:/usr/src/sys/RETRONFPRL + + phys mem = 3932160 + avail mem = 3577344 + user mem = 307200 + + January 1 22:44:48 init: configure system + + dz ? csr 160100 vector 310 skipped: No CSR. + lp 0 csr 177514 vector 200 attached + rk ? csr 177400 vector 220 didn't interrupt. + rl 0 csr 174400 vector 160 attached + tm ? csr 172520 vector 224 skipped: No CSR. + xp ? csr 176700 vector 254 skipped: No CSR. + cn 1 csr 176500 vector 300 attached + erase, kill ^U, intr ^C + + In first '#' prompt the system is in single-user mode. Just enter a ^D + to continue the system startup to multi-user mode: + + #^D + + Fast boot ... skipping disk checks + checking quotas: done. + Assuming non-networking system ... + preserving editor files + clearing /tmp + standard daemons: update cron accounting. + January 1 22:46:13 acctd[51]: open(/usr/adm/acct,O_WRONLY|O_APPEND): 2 + starting lpd + starting local daemons:Thu Jan 1 22:46:13 PST 2009 + January 1 22:46:13 init: kernel security level changed from 0 to 1 + January 1 22:46:15 getty: /dev/tty01: Device not configured + January 1 22:46:15 getty: /dev/tty00: Device not configured + January 1 22:46:15 getty: /dev/tty02: Device not configured + January 1 22:46:15 getty: /dev/tty03: Device not configured + + 2.11 BSD UNIX (curly.2bsd.com) (console) + + login: + + The login prompt is sometimes mangled with the 'Device not configured' + system messages, if its not visible just hit to get a fresh one. + + login: {root} + erase, kill ^U, intr ^C + + Now the system is in multi-user mode, daemons runnng. You can explore + the system, e.g. with a 'pstat -T' or a 'mount' command. The second + xterm can be activated too, it will connect to a second emulated DL11. + At the end is important to shutdown properly with a 'halt': + + # {pstat -T} + 7/186 files + 40/208 inodes + 11/150 processes + 6/ 46 texts active, 31 used + 2/135 swapmap entries, 420 kB used, 2139 kB free, 2133 kB max + 34/150 coremap entries, 2906 kB free, 2818 kB max + 1/ 10 ub_map entries, 10 free, 10 max + # {mount} + /dev/rl0a on / + /dev/rl1h on /usr + # {halt} + syncing disks... done + halting + + While the system was running the server process display the + cpumon> + prompt. When the w11 has halted after 211bsd shutdown a message like + + CPU down attention + Processor registers and status: + PS: 030350 cm,pm=k,u s,p,t=0,7,0 NZVC=1000 rust: 01 HALTed + R0: 177560 R1: 161322 R2: 053770 R3: 000010 + R4: 003400 R5: 147510 SP: 147466 PC: 000014 + + will be visible. Now the server process can be stopped with ^D. diff --git a/tools/oskit/rt11-53_rl/.cvsignore b/tools/oskit/rt11-53_rl/.cvsignore new file mode 100644 index 00000000..19315df3 --- /dev/null +++ b/tools/oskit/rt11-53_rl/.cvsignore @@ -0,0 +1,4 @@ +*.dat +*.dsk +*.log +*license.txt diff --git a/tools/oskit/rt11-53_rl/README_rt11-53_rlset.txt b/tools/oskit/rt11-53_rl/README_rt11-53_rlset.txt new file mode 100644 index 00000000..686c8c1d --- /dev/null +++ b/tools/oskit/rt11-53_rl/README_rt11-53_rlset.txt @@ -0,0 +1,70 @@ +# $Id: $ + +Notes on oskit: RT-11 V5.3 system on a RL02 volume + + Table of content: + + 1. General remarks + 2. Installation + 3. Usage + +1. General remarks --------------------------------------------------- + + See notes, especially on legal terms, in $RETROBASE/doc/w11a_os_guide.txt + + Also read README_license.txt which is included in the oskit !! + +2. Installation ------------------------------------------------------ + + - A disk set is available from + http://www.retro11.de/data/oc_w11/oskits/rt11-53_rlset.tgz + Download, unpack and copy the disk images (*.dsk), e.g. + + cd $RETROBASE/tools/oskit/rt11-53_rl + wget http://www.retro11.de/data/oc_w11/oskits/rt11-53_rlset.tgz + tar -xzf rt11-53_rlset.tgz + +3. Usage ------------------------------------------------------------- + + - Start them in simulator + pdp11 rt11-53_rl_boot.scmd + or ONLY IF YOU HAVE A VALID LICENSE on w11a + ti_w11 -u @rt11-53_rl_boot.tcl + + - Hit in the xterm window to connect to simh or backend server. + The boot dialog in the console xterm window will look like + (required input is in {..}, with {} denoting a carriage return: + + RT-11FB V05.03 + + .TYPE V5USER.TXT + + RT-11 V5.3 + + Installation of RT-11 Version 5.3 is complete and you are now + executing from the working volume (provided you have used the + automatic installation procedure). DIGITAL recommends you verify + the correct operation of your system's software using the + verification procedure. To do this, enter the command: + + IND VERIFY + + Note that VERIFY should be performed only after the distri- + bution media have been backed up. This was accomplished as part + of automatic installation on all RL02, RX02, TK50, and RX50 + based systems, including the MicroPDP-11 and the Professional + 300. If you have not completed automatic installation, you must + perform a manual backup before using VERIFY. Note also, VERIFY + is NOT supported on RX01 diskettes, DECtape I or II, or the + Professional 325. + + DIGITAL also recommends you read the file V5NOTE.TXT, which + contains information formalized too late to be included in the + Release Notes. V5NOTE.TXT can be TYPED or PRINTED. + + . + + Now you are at the RT-11 prompt and can exercise the system. + + There is no 'halt' or 'shutdown' command, just terminate the + simulator or backend server session. diff --git a/tools/oskit/rt11-53_rl/rt11-53_rl_boot.scmd b/tools/oskit/rt11-53_rl/rt11-53_rl_boot.scmd new file mode 100644 index 00000000..51f0b83f --- /dev/null +++ b/tools/oskit/rt11-53_rl/rt11-53_rl_boot.scmd @@ -0,0 +1,16 @@ +; $ Id: $ +; +; Setup file for RT-11 V5.3 RL02 based system +; +; Usage: +; +; pdp11 rt11-53_rl_boot.scmd +; +do ../../simh/setup_w11a_max.scmd +; +att rl0 RT11_V5.3_SYSTEM.dsk +; +set rl debug +set cons debug=rlboot_simh.log +; +boo rl0 diff --git a/tools/oskit/rt11-53_rl/rt11-53_rl_boot.tcl b/tools/oskit/rt11-53_rl/rt11-53_rl_boot.tcl new file mode 100644 index 00000000..51918e35 --- /dev/null +++ b/tools/oskit/rt11-53_rl/rt11-53_rl_boot.tcl @@ -0,0 +1,25 @@ +# $ Id: $ +# +# Setup file for RT-11 V5.3 RL02 based system +# +# Usage: +# +# console_starter -d DL0 & +# ti_w11 -xxx @rt11-53_rl_boot.tcl ( -xxx depends on sim or fpga connect) +# + +# setup w11 cpu +puts [rlw] + +# setup tt,lp,pp (single console; enable rx rate limiter on old DEC OS) +rw11::setup_tt "cpu0" {ndl 1 dlrlim 5} +rw11::setup_lp +rw11::setup_pp + +# mount disks +cpu0rla0 att RT11_V5.3_SYSTEM.dsk + +# and boot +rw11::cpumon +rw11::cpucons +cpu0 boot rla0 diff --git a/tools/oskit/xxdp_rl/.cvsignore b/tools/oskit/xxdp_rl/.cvsignore new file mode 100644 index 00000000..acaaccce --- /dev/null +++ b/tools/oskit/xxdp_rl/.cvsignore @@ -0,0 +1,4 @@ +*.gz +*.dat +*.dsk +*.log diff --git a/tools/oskit/xxdp_rl/README_license.txt b/tools/oskit/xxdp_rl/README_license.txt new file mode 100644 index 00000000..503e8fd1 --- /dev/null +++ b/tools/oskit/xxdp_rl/README_license.txt @@ -0,0 +1,9 @@ +Unlike most other PDP-11 software xxdp was not sold to Mentec. +By now, ownership of xxdp software is in the hands of HP. + +PDP-11 customers were not required to sign a license agreement for xxdp, +the software was provided with the system or brought to the customer site +by a Field Service representative. + +Bottom line is that there is certainly a copyright on the xxdp software, +but as it seems not a license. diff --git a/tools/oskit/xxdp_rl/README_xxdp_rlset.txt b/tools/oskit/xxdp_rl/README_xxdp_rlset.txt new file mode 100644 index 00000000..553252ea --- /dev/null +++ b/tools/oskit/xxdp_rl/README_xxdp_rlset.txt @@ -0,0 +1,85 @@ +# $Id: README_xxdp_rlset.txt 652 2015-02-28 12:18:08Z mueller $ + +Notes on oskit: XXDP V2.2 and V2.5 system on RL02 volumes + + Table of content: + + 1. General remarks + 2. Installation + 3. Usage + +1. General remarks --------------------------------------------------- + + See notes, especially on legal terms, in README_license.txt !! + +2. Installation ------------------------------------------------------ + + - A disk images for XXDP V2.2 and V2.5 are available from bitsavers + http://bitsavers.trailing-edge.com/bits/DEC/pdp11/discimages/rl02 + xxdp22.rl02.gz + xxdp25.rl02.gz + Download, unpack and copy the disk images (*.dsk), e.g. + + cd $RETROBASE/tools/oskit/xxdp_rl + + disk_path=http://bitsavers.trailing-edge.com/bits/DEC/pdp11/discimages + wget $disk_path/rl02/xxdp22.rl02.gz + wget $disk_path/rl02/xxdp25.rl02.gz + + gunzip -c xxdp22.rl02.gz > xxdp22.dsk + gunzip -c xxdp25.rl02.gz > xxdp25.dsk + +3. Usage ------------------------------------------------------------- + + - Start them in simulator + pdp11 xxdp22_rl_boot.scmd + pdp11 xxdp25_rl_boot.scmd + + or on w11a + ti_w11 @xxdp22_rl_boot.tcl + ti_w11 @xxdp25_rl_boot.tcl + where opt is the proper option set for the board. + + - Hit in the xterm window to connect to simh or backend server. + The boot dialog in the console xterm window will look like + (required input is in {..}, with {} denoting a carriage return. + + XXDP V2.2 boot dialog: + + CHMDLD0 XXDP+ DL MONITOR + BOOTED VIA UNIT 0 + 28K UNIBUS SYSTEM + + ENTER DATE (DD-MMM-YY): {10-jan-85} + + RESTART ADDR: 152010 + THIS IS XXDP+. TYPE "H" OR "H/L" FOR HELP. + + . + + XXDP V2.5 boot dialog: + + BOOTING UP XXDP-XM EXTENDED MONITOR + + XXDP-XM EXTENDED MONITOR - XXDP V2.5 + REVISION: F0 + BOOTED FROM DL0 + 124KW OF MEMORY + UNIBUS SYSTEM + + RESTART ADDRESS: 152000 + TYPE "H" FOR HELP ! + + . + + Now you are at the XXDP prompt '.' and can exercise the system: + + . {H} + --> will print help + . {D} + --> will list the files + . {R EKBAD0} + --> will run the 'PDP 11/70 cpu diagnostic part 1' + + There is no 'halt' or 'shutdown' command, just terminate the + simulator or backend server session. diff --git a/tools/oskit/xxdp_rl/xxdp22_rl_boot.scmd b/tools/oskit/xxdp_rl/xxdp22_rl_boot.scmd new file mode 100644 index 00000000..e33ba51a --- /dev/null +++ b/tools/oskit/xxdp_rl/xxdp22_rl_boot.scmd @@ -0,0 +1,13 @@ +; $Id: xxdp22_rl_boot.scmd 633 2015-01-11 22:58:48Z mueller $ +; +; Setup file for XXDP V2.2 RL02 based system +; +; Usage: +; +; pdp11 xxdp22_rl_boot.scmd +; +do ../../simh/setup_w11a_max.scmd +; +att rl0 xxdp22.dsk +; +boo rl0 diff --git a/tools/oskit/xxdp_rl/xxdp22_rl_boot.tcl b/tools/oskit/xxdp_rl/xxdp22_rl_boot.tcl new file mode 100644 index 00000000..4e1d3045 --- /dev/null +++ b/tools/oskit/xxdp_rl/xxdp22_rl_boot.tcl @@ -0,0 +1,25 @@ +# $Id: xxdp22_rl_boot.tcl 654 2015-03-01 18:45:38Z mueller $ +# +# Setup file for XXDP V2.2 RL02 based system +# +# Usage: +# +# console_starter -d DL0 & +# ti_w11 -xxx @xxdp22_rl_boot.tcl ( -xxx depends on sim or fpga connect) +# + +# setup w11 cpu +puts [rlw] + +# setup tt,lp,pp (single console; enable rx rate limiter on old DEC OS) +rw11::setup_tt "cpu0" {ndl 1 dlrlim 5 to7bit 1} +rw11::setup_lp +rw11::setup_pp + +# mount disks +cpu0rla0 att xxdp22.dsk + +# and boot +rw11::cpumon +rw11::cpucons +cpu0 boot rla0 diff --git a/tools/oskit/xxdp_rl/xxdp25_rl_boot.scmd b/tools/oskit/xxdp_rl/xxdp25_rl_boot.scmd new file mode 100644 index 00000000..db05b8fc --- /dev/null +++ b/tools/oskit/xxdp_rl/xxdp25_rl_boot.scmd @@ -0,0 +1,13 @@ +; $Id: xxdp25_rl_boot.scmd 633 2015-01-11 22:58:48Z mueller $ +; +; Setup file for XXDP V2.5 RL02 based system +; +; Usage: +; +; pdp11 xxdp25_rl_boot.scmd +; +do ../../simh/setup_w11a_max.scmd +; +att rl0 xxdp25.dsk +; +boo rl0 diff --git a/tools/oskit/xxdp_rl/xxdp25_rl_boot.tcl b/tools/oskit/xxdp_rl/xxdp25_rl_boot.tcl new file mode 100644 index 00000000..6fc58811 --- /dev/null +++ b/tools/oskit/xxdp_rl/xxdp25_rl_boot.tcl @@ -0,0 +1,25 @@ +# $Id: xxdp25_rl_boot.tcl 654 2015-03-01 18:45:38Z mueller $ +# +# Setup file for XXDP V2.5 RL02 based system +# +# Usage: +# +# console_starter -d DL0 & +# ti_w11 -xxx @xxdp25_rl_boot.tcl ( -xxx depends on sim or fpga connect) +# + +# setup w11 cpu +puts [rlw] + +# setup tt,lp,pp (single console; enable rx rate limiter on old DEC OS) +rw11::setup_tt "cpu0" {ndl 1 dlrlim 5 to7bit 1} +rw11::setup_lp +rw11::setup_pp + +# mount disks +cpu0rla0 att xxdp25.dsk + +# and boot +rw11::cpumon +rw11::cpucons +cpu0 boot rla0 diff --git a/tools/src/librlink/RlinkCommand.cpp b/tools/src/librlink/RlinkCommand.cpp index 1ee19a6e..57d09183 100644 --- a/tools/src/librlink/RlinkCommand.cpp +++ b/tools/src/librlink/RlinkCommand.cpp @@ -1,4 +1,4 @@ -// $Id: RlinkCommand.cpp 628 2015-01-04 16:22:09Z mueller $ +// $Id: RlinkCommand.cpp 643 2015-02-07 17:41:53Z mueller $ // // Copyright 2011-2015 by Walter F.J. Mueller // @@ -13,7 +13,7 @@ // // Revision History: // Date Rev Version Comment -// 2015-01-04 628 1.2.3 Print(): adopt large nblk; +// 2015-02-07 642 1.2.3 Print()+Dump(): adopt for large nblk; // 2014-12-21 617 1.2.2 use kStat_M_RbTout for rbus timeout // 2014-12-20 616 1.2.1 Print(): display BlockDone; add kFlagChkDone // 2014-12-06 609 1.2 new rlink v4 iface @@ -26,7 +26,7 @@ /*! \file - \version $Id: RlinkCommand.cpp 628 2015-01-04 16:22:09Z mueller $ + \version $Id: RlinkCommand.cpp 643 2015-02-07 17:41:53Z mueller $ \brief Implemenation of class RlinkCommand. */ @@ -91,13 +91,13 @@ RlinkCommand::RlinkCommand() fAddress(0), fData(0), fBlock(), - fpBlockExt(0), + fpBlockExt(nullptr), fBlockExtSize(0), fBlockDone(0), fStatus(0), fFlags(0), fRcvSize(0), - fpExpect(0) + fpExpect(nullptr) {} //------------------------------------------+----------------------------------- @@ -114,7 +114,7 @@ RlinkCommand::RlinkCommand(const RlinkCommand& rhs) fStatus(rhs.fStatus), fFlags(rhs.fFlags), fRcvSize(rhs.fRcvSize), - fpExpect(rhs.fpExpect ? new RlinkCommandExpect(*rhs.fpExpect) : 0) + fpExpect(rhs.fpExpect ? new RlinkCommandExpect(*rhs.fpExpect) : nullptr) {} //------------------------------------------+----------------------------------- @@ -175,14 +175,14 @@ void RlinkCommand::SetCommand(uint8_t cmd, uint16_t addr, uint16_t data) fRequest = cmd; fAddress = addr; fData = data; - fpBlockExt = 0; + fpBlockExt = nullptr; fBlockExtSize = 0; fBlockDone = 0; fStatus = 0; fFlags = kFlagInit; fRcvSize = 0; delete fpExpect; - fpExpect = 0; + fpExpect = nullptr; return; } @@ -204,7 +204,7 @@ void RlinkCommand::SetBlockWrite(const std::vector& block) throw Rexception("RlinkCommand::SetBlockWrite()", "Bad args: invalid block size"); fBlock = block; - fpBlockExt = 0; + fpBlockExt = nullptr; fBlockExtSize = 0; fBlockDone = 0; return; @@ -220,7 +220,7 @@ void RlinkCommand::SetBlockRead(size_t size) "Bad args: invalid block size"); fBlock.clear(); fBlock.resize(size); - fpBlockExt = 0; + fpBlockExt = nullptr; fBlockExtSize = 0; fBlockDone = 0; return; @@ -445,7 +445,7 @@ void RlinkCommand::Dump(std::ostream& os, int ind, const char* text) const size_t ncol = max(1, (80-ind-4-5)/(4+1)); os << bl << " block data:"; for (size_t i=0; i // @@ -13,7 +13,7 @@ // // Revision History: // Date Rev Version Comment -// 2015-01-01 626 2.1 full rlink v4 implementation +// 2015-01-06 631 2.1 full rlink v4 implementation // 2014-12-10 611 2.0 re-organize for rlink v4 // 2014-08-26 587 1.5 start accept rlink v4 protocol (partially...) // 2014-08-15 583 1.4 rb_mreq addr now 16 bit @@ -33,7 +33,7 @@ /*! \file - \version $Id: RlinkConnect.cpp 626 2015-01-03 14:41:37Z mueller $ + \version $Id: RlinkConnect.cpp 632 2015-01-11 12:30:03Z mueller $ \brief Implemenation of RlinkConnect. */ @@ -91,19 +91,24 @@ const uint16_t RlinkConnect::kRbufPrudentDelta; RlinkConnect::RlinkConnect() : fpPort(), - fpServ(0), + fpServ(nullptr), fSndPkt(), fRcvPkt(), fContext(), fAddrMap(), fStats(), - fLogOpts(), - fspLog(new RlogFile(&cout, "")), + fLogBaseAddr(16), + fLogBaseData(16), + fLogBaseStat(16), + fPrintLevel(0), + fDumpLevel(0), + fTraceLevel(0), + fspLog(new RlogFile(&cout)), fConnectMutex(), fAttnNotiPatt(0), fTsLastAttnNoti(-1), fSysId(0xffffffff), - fRbufSize(0) + fRbufSize(2048) { for (size_t i=0; i<8; i++) fSeqNumber[i] = 0; @@ -152,7 +157,7 @@ bool RlinkConnect::Open(const std::string& name, RerrMsg& emsg) if (!fpPort) return false; fpPort->SetLogFile(fspLog); - fpPort->SetTraceLevel(fLogOpts.tracelevel); + fpPort->SetTraceLevel(fTraceLevel); RlinkCommandList clist; clist.AddRreg(kRbaddr_RLSTAT); @@ -335,12 +340,12 @@ bool RlinkConnect::Exec(RlinkCommandList& clist, RlinkContext& cntx, size_t loglevel = 3; if (checkseen) loglevel = 2; if (errorseen) loglevel = 1; - if (loglevel <= fLogOpts.printlevel) { + if (loglevel <= fPrintLevel) { RlogMsg lmsg(*fspLog); - clist.Print(lmsg(), cntx, &AddrMap(), fLogOpts.baseaddr, fLogOpts.basedata, - fLogOpts.basestat); + clist.Print(lmsg(), cntx, &AddrMap(), fLogBaseAddr, fLogBaseData, + fLogBaseStat); } - if (loglevel <= fLogOpts.dumplevel) { + if (loglevel <= fDumpLevel) { RlogMsg lmsg(*fspLog); clist.Dump(lmsg(), 0); } @@ -351,17 +356,19 @@ bool RlinkConnect::Exec(RlinkCommandList& clist, RlinkContext& cntx, //------------------------------------------+----------------------------------- //! FIXME_docs -bool RlinkConnect::Exec(RlinkCommandList& clist, RlinkContext& cntx) +void RlinkConnect::Exec(RlinkCommandList& clist, RlinkContext& cntx) { RerrMsg emsg; bool rc = Exec(clist, cntx, emsg); if (!rc) { - RlogMsg lmsg(*fspLog, 'E'); + RlogMsg lmsg(*fspLog, 'F'); lmsg << emsg << endl; lmsg << "Dump of failed clist:" << endl; clist.Dump(lmsg(), 0); } - return rc; + if (!rc) + throw Rexception("RlinkConnect::Exec", "Exec() failed: ", emsg); + return; } //------------------------------------------+----------------------------------- @@ -466,30 +473,74 @@ bool RlinkConnect::SndAttn(RerrMsg& emsg) //------------------------------------------+----------------------------------- //! FIXME_docs -void RlinkConnect::SetLogOpts(const LogOpts& opts) +void RlinkConnect::SetLogBaseAddr(uint32_t base) { - if (opts.baseaddr!=2 && opts.baseaddr!=8 && opts.baseaddr!=16) - throw Rexception("RlinkConnect::SetLogOpts()", - "Bad args: baseaddr != 2,8,16"); - if (opts.basedata!=2 && opts.basedata!=8 && opts.basedata!=16) - throw Rexception("RlinkConnect::SetLogOpts()", - "Bad args: basedata != 2,8,16"); - if (opts.basestat!=2 && opts.basestat!=8 && opts.basestat!=16) - throw Rexception("RlinkConnect::SetLogOpts()", - "Bad args: basestat != 2,8,16"); - - fLogOpts = opts; - if (fpPort) fpPort->SetTraceLevel(opts.tracelevel); + if (base!=2 && base!=8 && base!=16) + throw Rexception("RlinkConnect::SetLogBaseAddr()", + "Bad args: base != 2,8,16"); + fLogBaseAddr = base; return; } + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +void RlinkConnect::SetLogBaseData(uint32_t base) +{ + if (base!=2 && base!=8 && base!=16) + throw Rexception("RlinkConnect::SetLogBaseData()", + "Bad args: base != 2,8,16"); + fLogBaseData = base; + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +void RlinkConnect::SetLogBaseStat(uint32_t base) +{ + if (base!=2 && base!=8 && base!=16) + throw Rexception("RlinkConnect::SetLogBaseStat()", + "Bad args: base != 2,8,16"); + fLogBaseStat = base; + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +void RlinkConnect::SetPrintLevel(uint32_t lvl) +{ + fPrintLevel = lvl; + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +void RlinkConnect::SetDumpLevel(uint32_t lvl) +{ + fDumpLevel = lvl; + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +void RlinkConnect::SetTraceLevel(uint32_t lvl) +{ + fTraceLevel = lvl; + if (fpPort) fpPort->SetTraceLevel(lvl); + return; +} //------------------------------------------+----------------------------------- //! FIXME_docs -bool RlinkConnect::LogOpen(const std::string& name) +bool RlinkConnect::LogOpen(const std::string& name, RerrMsg& emsg) { - if (!fspLog->Open(name)) { - fspLog->UseStream(&cout, ""); + if (!fspLog->Open(name, emsg)) { + fspLog->UseStream(&cout); return false; } return true; @@ -507,6 +558,19 @@ void RlinkConnect::LogUseStream(std::ostream* pstr, const std::string& name) //------------------------------------------+----------------------------------- //! FIXME_docs +void RlinkConnect::SetLogFileName(const std::string& name) +{ + RerrMsg emsg; + if (!LogOpen(name, emsg)) { + throw Rexception("RlinkConnect::SetLogFile", + emsg.Text() + "', using stdout"); + } + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + void RlinkConnect::Print(std::ostream& os) const { os << "RlinkConnect::Print(std::ostream& os)" << endl; @@ -537,12 +601,12 @@ void RlinkConnect::Dump(std::ostream& os, int ind, const char* text) const fContext.Dump(os, ind+2, "fContext: "); fAddrMap.Dump(os, ind+2, "fAddrMap: "); fStats.Dump(os, ind+2, "fStats: "); - os << bl << " fLogOpts.baseaddr " << fLogOpts.baseaddr << endl; - os << bl << " .basedata " << fLogOpts.basedata << endl; - os << bl << " .basestat " << fLogOpts.basestat << endl; - os << bl << " .printlevel " << fLogOpts.printlevel << endl; - os << bl << " .dumplevel " << fLogOpts.dumplevel << endl; - os << bl << " .tracelevel " << fLogOpts.tracelevel << endl; + os << bl << " fLogBaseAddr: " << fLogBaseAddr << endl; + os << bl << " fLogBaseData: " << fLogBaseData << endl; + os << bl << " fLogBaseStat: " << fLogBaseStat << endl; + os << bl << " fPrintLevel: " << fPrintLevel << endl; + os << bl << " fDumpLevel " << fDumpLevel << endl; + os << bl << " fTraceLevel " << fTraceLevel << endl; fspLog->Dump(os, ind+2, "fspLog: "); os << bl << " fAttnNotiPatt: " << RosPrintBvi(fAttnNotiPatt,16) << endl; //FIXME_code: fTsLastAttnNoti not yet in Dump (get formatter...) @@ -1016,7 +1080,7 @@ void RlinkConnect::ProcessAttnNotify() } } - if (ok && fLogOpts.printlevel == 3) { + if (ok && fPrintLevel == 3) { RlogMsg lmsg(*fspLog, 'I'); lmsg << "ATTN notify apat = " << RosPrintf(apat,"x0",4) << " lams ="; diff --git a/tools/src/librlink/RlinkConnect.hpp b/tools/src/librlink/RlinkConnect.hpp index 54782cbe..5e993f4e 100644 --- a/tools/src/librlink/RlinkConnect.hpp +++ b/tools/src/librlink/RlinkConnect.hpp @@ -1,4 +1,4 @@ -// $Id: RlinkConnect.hpp 626 2015-01-03 14:41:37Z mueller $ +// $Id: RlinkConnect.hpp 632 2015-01-11 12:30:03Z mueller $ // // Copyright 2011-2015 by Walter F.J. Mueller // @@ -13,7 +13,7 @@ // // Revision History: // Date Rev Version Comment -// 2015-01-01 626 2.1 full rlink v4 implementation +// 2015-01-06 631 2.1 full rlink v4 implementation // 2014-12-25 621 2.0.2 Reorganize packet send/revd stats // 2014-12-20 616 2.0.1 add BlockDone expect checks // 2014-12-10 611 2.0 re-organize for rlink v4 @@ -35,7 +35,7 @@ /*! \file - \version $Id: RlinkConnect.hpp 626 2015-01-03 14:41:37Z mueller $ + \version $Id: RlinkConnect.hpp 632 2015-01-11 12:30:03Z mueller $ \brief Declaration of class \c RlinkConnect. */ @@ -71,19 +71,6 @@ namespace Retro { class RlinkConnect : public Rbits, private boost::noncopyable { public: - struct LogOpts { - uint32_t baseaddr; - uint32_t basedata; - uint32_t basestat; - uint32_t printlevel; // 0=off,1=err,2=chk,3=all - uint32_t dumplevel; // 0=off,1=err,2=chk,3=all - uint32_t tracelevel; // 0=off,1=buf,2=char - - LogOpts() - : baseaddr(16), basedata(16), basestat(16), - printlevel(0), dumplevel(0), tracelevel(0) - {} - }; RlinkConnect(); ~RlinkConnect(); @@ -109,8 +96,8 @@ namespace Retro { bool Exec(RlinkCommandList& clist, RerrMsg& emsg); bool Exec(RlinkCommandList& clist, RlinkContext& cntx, RerrMsg& emsg); - bool Exec(RlinkCommandList& clist); - bool Exec(RlinkCommandList& clist, RlinkContext& cntx); + void Exec(RlinkCommandList& clist); + void Exec(RlinkCommandList& clist, RlinkContext& cntx); double WaitAttn(double timeout, uint16_t& apat, RerrMsg& emsg); bool SndOob(uint16_t addr, uint16_t data, RerrMsg& emsg); @@ -131,15 +118,29 @@ namespace Retro { const Rstats& SndStats() const; const Rstats& RcvStats() const; - void SetLogOpts(const LogOpts& opts); - const LogOpts& GetLogOpts() const; + void SetLogBaseAddr(uint32_t base); + void SetLogBaseData(uint32_t base); + void SetLogBaseStat(uint32_t base); + void SetPrintLevel(uint32_t lvl); + void SetDumpLevel(uint32_t lvl); + void SetTraceLevel(uint32_t lvl); - bool LogOpen(const std::string& name); + uint32_t LogBaseAddr() const; + uint32_t LogBaseData() const; + uint32_t LogBaseStat() const; + uint32_t PrintLevel() const; + uint32_t DumpLevel() const; + uint32_t TraceLevel() const; + + bool LogOpen(const std::string& name, RerrMsg& emsg); void LogUseStream(std::ostream* pstr, const std::string& name = ""); RlogFile& LogFile() const; const boost::shared_ptr& LogFileSPtr() const; + void SetLogFileName(const std::string& name); + std::string LogFileName() const; + void Print(std::ostream& os) const; void Dump(std::ostream& os, int ind=0, const char* text=0) const; @@ -221,7 +222,12 @@ namespace Retro { RlinkContext fContext; //!< default context RlinkAddrMap fAddrMap; //!< name<->address mapping Rstats fStats; //!< statistics - LogOpts fLogOpts; //!< log options + uint32_t fLogBaseAddr; //!< log: base for addr + uint32_t fLogBaseData; //!< log: base for data + uint32_t fLogBaseStat; //!< log: base for stat + uint32_t fPrintLevel; //!< print 0=off,1=err,2=chk,3=all + uint32_t fDumpLevel; //!< dump 0=off,1=err,2=chk,3=all + uint32_t fTraceLevel; //!< trace 0=off,1=buf,2=char boost::shared_ptr fspLog; //!< log file ptr boost::recursive_mutex fConnectMutex; //!< mutex to lock whole connect uint16_t fAttnNotiPatt; //!< attn notifier pattern diff --git a/tools/src/librlink/RlinkConnect.ipp b/tools/src/librlink/RlinkConnect.ipp index c44be331..28f324df 100644 --- a/tools/src/librlink/RlinkConnect.ipp +++ b/tools/src/librlink/RlinkConnect.ipp @@ -1,4 +1,4 @@ -// $Id: RlinkConnect.ipp 626 2015-01-03 14:41:37Z mueller $ +// $Id: RlinkConnect.ipp 632 2015-01-11 12:30:03Z mueller $ // // Copyright 2011-2015 by Walter F.J. Mueller // @@ -13,7 +13,7 @@ // // Revision History: // Date Rev Version Comment -// 2015-01-01 626 2.1 full rlink v4 implementation +// 2015-01-06 631 2.1 full rlink v4 implementation // 2013-03-05 495 1.2.1 add Exec() without emsg (will send emsg to LogFile) // 2013-02-23 492 1.2 use scoped_ptr for Port; Close allways allowed // use RlinkContext, add Context(), Exec(..., cntx) @@ -25,7 +25,7 @@ /*! \file - \version $Id: RlinkConnect.ipp 626 2015-01-03 14:41:37Z mueller $ + \version $Id: RlinkConnect.ipp 632 2015-01-11 12:30:03Z mueller $ \brief Implemenation (inline) of RlinkConnect. */ @@ -82,9 +82,10 @@ inline bool RlinkConnect::Exec(RlinkCommandList& clist, RerrMsg& emsg) //------------------------------------------+----------------------------------- //! FIXME_docs -inline bool RlinkConnect::Exec(RlinkCommandList& clist) +inline void RlinkConnect::Exec(RlinkCommandList& clist) { - return Exec(clist, fContext); + Exec(clist, fContext); + return; } //------------------------------------------+----------------------------------- @@ -182,9 +183,49 @@ inline const Rstats& RlinkConnect::RcvStats() const //------------------------------------------+----------------------------------- //! FIXME_docs -inline const RlinkConnect::LogOpts& RlinkConnect::GetLogOpts() const +inline uint32_t RlinkConnect::LogBaseAddr() const { - return fLogOpts; + return fLogBaseAddr; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline uint32_t RlinkConnect::LogBaseData() const +{ + return fLogBaseData; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline uint32_t RlinkConnect::LogBaseStat() const +{ + return fLogBaseStat; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline uint32_t RlinkConnect::PrintLevel() const +{ + return fPrintLevel; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline uint32_t RlinkConnect::DumpLevel() const +{ + return fDumpLevel; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline uint32_t RlinkConnect::TraceLevel() const +{ + return fTraceLevel; } //------------------------------------------+----------------------------------- @@ -203,5 +244,13 @@ inline const boost::shared_ptr& RlinkConnect::LogFileSPtr() const return fspLog; } +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline std::string RlinkConnect::LogFileName() const +{ + return LogFile().Name(); +} + } // end namespace Retro diff --git a/tools/src/librlink/RlinkPacketBufRcv.cpp b/tools/src/librlink/RlinkPacketBufRcv.cpp index 33ac09c2..3c768ac2 100644 --- a/tools/src/librlink/RlinkPacketBufRcv.cpp +++ b/tools/src/librlink/RlinkPacketBufRcv.cpp @@ -1,4 +1,4 @@ -// $Id: RlinkPacketBufRcv.cpp 621 2014-12-26 21:20:05Z mueller $ +// $Id: RlinkPacketBufRcv.cpp 632 2015-01-11 12:30:03Z mueller $ // // Copyright 2014- by Walter F.J. Mueller // @@ -20,7 +20,7 @@ /*! \file - \version $Id: RlinkPacketBufRcv.cpp 621 2014-12-26 21:20:05Z mueller $ + \version $Id: RlinkPacketBufRcv.cpp 632 2015-01-11 12:30:03Z mueller $ \brief Implemenation of class RlinkPacketBuf. */ @@ -77,7 +77,7 @@ RlinkPacketBufRcv::~RlinkPacketBufRcv() int RlinkPacketBufRcv::ReadData(RlinkPort* port, double timeout, RerrMsg& emsg) { - if (port == 0) + if (port == nullptr) throw Rexception("RlinkPacketBufRcv::ReadData()", "Bad state: port not open"); if (fRawBufDone != fRawBufSize) diff --git a/tools/src/librlink/RlinkPort.cpp b/tools/src/librlink/RlinkPort.cpp index d4f4d502..91beb767 100644 --- a/tools/src/librlink/RlinkPort.cpp +++ b/tools/src/librlink/RlinkPort.cpp @@ -1,4 +1,4 @@ -// $Id: RlinkPort.cpp 611 2014-12-10 23:23:58Z mueller $ +// $Id: RlinkPort.cpp 632 2015-01-11 12:30:03Z mueller $ // // Copyright 2011-2014 by Walter F.J. Mueller // @@ -30,7 +30,7 @@ /*! \file - \version $Id: RlinkPort.cpp 611 2014-12-10 23:23:58Z mueller $ + \version $Id: RlinkPort.cpp 632 2015-01-11 12:30:03Z mueller $ \brief Implemenation of RlinkPort. */ @@ -120,7 +120,7 @@ int RlinkPort::Read(uint8_t* buf, size_t size, double timeout, RerrMsg& emsg) { if (!IsOpen()) throw Rexception("RlinkPort::Read()","Bad state: port not open"); - if (buf == 0) + if (buf == nullptr) throw Rexception("RlinkPort::Read()","Bad args: buf==nullptr"); if (size == 0) throw Rexception("RlinkPort::Read()","Bad args: size==0"); @@ -170,7 +170,7 @@ int RlinkPort::Write(const uint8_t* buf, size_t size, RerrMsg& emsg) { if (!IsOpen()) throw Rexception("RlinkPort::Write()","Bad state: port not open"); - if (buf == 0) + if (buf == nullptr) throw Rexception("RlinkPort::Write()","Bad args: buf==nullptr"); if (size == 0) throw Rexception("RlinkPort::Write()","Bad args: size==0"); diff --git a/tools/src/librlink/RlinkPort.hpp b/tools/src/librlink/RlinkPort.hpp index 308c66fe..1b0bcc93 100644 --- a/tools/src/librlink/RlinkPort.hpp +++ b/tools/src/librlink/RlinkPort.hpp @@ -1,4 +1,4 @@ -// $Id: RlinkPort.hpp 611 2014-12-10 23:23:58Z mueller $ +// $Id: RlinkPort.hpp 632 2015-01-11 12:30:03Z mueller $ // // Copyright 2011-2014 by Walter F.J. Mueller // @@ -27,7 +27,7 @@ /*! \file - \version $Id: RlinkPort.hpp 611 2014-12-10 23:23:58Z mueller $ + \version $Id: RlinkPort.hpp 632 2015-01-11 12:30:03Z mueller $ \brief Declaration of class RlinkPort. */ @@ -72,6 +72,7 @@ namespace Retro { void SetLogFile(const boost::shared_ptr& splog); void SetTraceLevel(uint32_t level); + uint32_t TraceLevel() const; const Rstats& Stats() const; diff --git a/tools/src/librlink/RlinkPortCuff.cpp b/tools/src/librlink/RlinkPortCuff.cpp index ed8d6262..c5e91ff2 100644 --- a/tools/src/librlink/RlinkPortCuff.cpp +++ b/tools/src/librlink/RlinkPortCuff.cpp @@ -1,4 +1,4 @@ -// $Id: RlinkPortCuff.cpp 584 2014-08-22 19:38:12Z mueller $ +// $Id: RlinkPortCuff.cpp 632 2015-01-11 12:30:03Z mueller $ // // Copyright 2012-2014 by Walter F.J. Mueller // @@ -24,7 +24,7 @@ /*! \file - \version $Id: RlinkPortCuff.cpp 584 2014-08-22 19:38:12Z mueller $ + \version $Id: RlinkPortCuff.cpp 632 2015-01-11 12:30:03Z mueller $ \brief Implemenation of RlinkPortCuff. */ @@ -68,10 +68,10 @@ RlinkPortCuff::RlinkPortCuff() : RlinkPort(), fFdReadDriver(-1), fFdWriteDriver(-1), - fpUsbContext(0), - fpUsbDevList(0), + fpUsbContext(nullptr), + fpUsbDevList(nullptr), fUsbDevCount(0), - fpUsbDevHdl(0), + fpUsbDevHdl(nullptr), fLoopState(kLoopStateStopped) { fStats.Define(kStatNPollAddCB, "kStatNPollAddCB", "USB poll add cb"); @@ -139,7 +139,7 @@ bool RlinkPortCuff::Open(const std::string& url, RerrMsg& emsg) } // connect to USB device - libusb_device* mydev = 0; + libusb_device* mydev = nullptr; // path syntax: /bus/dev if (fUrl.Path().length()==8 && fUrl.Path()[0]=='/' && fUrl.Path()[4]=='/') { string busnam = fUrl.Path().substr(1,3); @@ -185,7 +185,7 @@ bool RlinkPortCuff::Open(const std::string& url, RerrMsg& emsg) return false; } - if (mydev == 0) { + if (mydev == nullptr) { emsg.Init("RlinkPortCuff::Open()", string("no usb device '") + fUrl.Path() + "', found'"); Cleanup(); @@ -194,7 +194,7 @@ bool RlinkPortCuff::Open(const std::string& url, RerrMsg& emsg) irc = libusb_open(mydev, &fpUsbDevHdl); if (irc) { - fpUsbDevHdl = 0; + fpUsbDevHdl = nullptr; emsg.Init("RlinkPortCuff::Open()", string("opening usb device '") + fUrl.Path() + "', failed: " + string(USBErrorName(irc))); @@ -288,15 +288,15 @@ void RlinkPortCuff::Cleanup() if (fpUsbDevHdl) { libusb_release_interface(fpUsbDevHdl, 0); libusb_close(fpUsbDevHdl); - fpUsbDevHdl = 0; + fpUsbDevHdl = nullptr; } if (fpUsbDevList) { libusb_free_device_list(fpUsbDevList, 1); - fpUsbDevList = 0; + fpUsbDevList = nullptr; } libusb_set_pollfd_notifiers(fpUsbContext, nullptr, nullptr, nullptr); libusb_exit(fpUsbContext); - fpUsbContext = 0; + fpUsbContext = nullptr; } fPollFds.clear(); @@ -462,7 +462,7 @@ void RlinkPortCuff::DriverEventUSB() libusb_transfer* RlinkPortCuff::NewWriteTransfer() { - libusb_transfer* t = 0; + libusb_transfer* t = nullptr; if (!fWriteQueueFree.empty()) { t = fWriteQueueFree.front(); fWriteQueueFree.pop_front(); @@ -531,7 +531,7 @@ void RlinkPortCuff::BadUSBCall(const char* meth, const char* text, int rc) void RlinkPortCuff::CheckUSBTransfer(const char* meth, libusb_transfer *t) { - const char* etext = 0; + const char* etext = nullptr; if (t->status == LIBUSB_TRANSFER_ERROR) etext = "ERROR"; if (t->status == LIBUSB_TRANSFER_STALL) etext = "STALL"; diff --git a/tools/src/librlink/RlinkPortFactory.cpp b/tools/src/librlink/RlinkPortFactory.cpp index b94abc3a..7af51ccd 100644 --- a/tools/src/librlink/RlinkPortFactory.cpp +++ b/tools/src/librlink/RlinkPortFactory.cpp @@ -1,4 +1,4 @@ -// $Id: RlinkPortFactory.cpp 516 2013-05-05 21:24:52Z mueller $ +// $Id: RlinkPortFactory.cpp 632 2015-01-11 12:30:03Z mueller $ // // Copyright 2011-2013 by Walter F.J. Mueller // @@ -21,7 +21,7 @@ /*! \file - \version $Id: RlinkPortFactory.cpp 516 2013-05-05 21:24:52Z mueller $ + \version $Id: RlinkPortFactory.cpp 632 2015-01-11 12:30:03Z mueller $ \brief Implemenation of RlinkPortFactory. */ @@ -74,7 +74,7 @@ RlinkPort* Retro::RlinkPortFactory::New(const std::string& url, RerrMsg& emsg) RlinkPort* RlinkPortFactory::Open(const std::string& url, RerrMsg& emsg) { RlinkPort* pport = New(url, emsg); - if (pport == 0) return 0; + if (pport == nullptr) return 0; if (pport->Open(url, emsg)) return pport; delete pport; diff --git a/tools/src/librlink/RlinkPortTerm.cpp b/tools/src/librlink/RlinkPortTerm.cpp index 9c3cb64e..33efe1a9 100644 --- a/tools/src/librlink/RlinkPortTerm.cpp +++ b/tools/src/librlink/RlinkPortTerm.cpp @@ -1,6 +1,6 @@ -// $Id: RlinkPortTerm.cpp 607 2014-11-30 20:02:48Z mueller $ +// $Id: RlinkPortTerm.cpp 641 2015-02-01 22:12:15Z mueller $ // -// Copyright 2011-2013 by Walter F.J. Mueller +// Copyright 2011-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-02-01 641 1.2 support custom baud rates (5M,6M,10M,12M) // 2013-02-23 492 1.1 use RparseUrl // 2011-12-18 440 1.0.4 add kStatNPort stats; Open(): autoadd /dev/tty, // BUGFIX: Open(): set VSTART, VSTOP @@ -25,7 +26,7 @@ /*! \file - \version $Id: RlinkPortTerm.cpp 607 2014-11-30 20:02:48Z mueller $ + \version $Id: RlinkPortTerm.cpp 641 2015-02-01 22:12:15Z mueller $ \brief Implemenation of RlinkPortTerm. */ @@ -35,6 +36,8 @@ #include #include #include +#include +#include #include "RlinkPortTerm.hpp" @@ -90,6 +93,7 @@ bool RlinkPortTerm::Open(const std::string& url, RerrMsg& emsg) } speed_t speed = B115200; + unsigned long nsbaud = 0; string baud; if (fUrl.FindOpt("baud", baud)) { speed = B0; @@ -112,10 +116,19 @@ bool RlinkPortTerm::Open(const std::string& url, RerrMsg& emsg) if (baud=="3000000" || baud=="3000k" || baud=="3M") speed = B3000000; if (baud=="3500000" || baud=="3500k") speed = B3500000; if (baud=="4000000" || baud=="4000k" || baud=="4M") speed = B4000000; + + // now handle non-standart baud rates if (speed == B0) { - emsg.Init("RlinkPortTerm::Open()", - string("invalid baud rate '") + baud + "' specified"); - return false; + if (baud== "5000000" || baud== "5000k" || baud== "5M") nsbaud = 5000000; + if (baud== "6000000" || baud== "6000k" || baud== "6M") nsbaud = 6000000; + if (baud== "6666666" || baud== "6666k") nsbaud = 6666666; + if (baud=="10000000" || baud=="10000k" || baud=="10M") nsbaud = 10000000; + if (baud=="12000000" || baud=="12000k" || baud=="12M") nsbaud = 12000000; + if (nsbaud == 0) { + emsg.Init("RlinkPortTerm::Open()", + string("invalid baud rate '") + baud + "' specified"); + return false; + } } } @@ -145,6 +158,22 @@ bool RlinkPortTerm::Open(const std::string& url, RerrMsg& emsg) return false; } + struct serial_struct sioctl; + int cdivisor = 0; + + if (nsbaud != 0) { + if (::ioctl(fd, TIOCGSERIAL, &sioctl) < 0) { + emsg.InitErrno("RlinkPortTerm::Open()", + string("ioctl(TIOCGSERIAL) for '")+fUrl.Path()+"' failed: ", + errno); + ::close(fd); + return false; + } + double fcdivisor = double(sioctl.baud_base) / double(nsbaud); + cdivisor = fcdivisor + 0.5; + speed = B38400; + } + bool use_cts = fUrl.FindOpt("cts"); bool use_xon = fUrl.FindOpt("xon"); fUseXon = use_xon; @@ -179,6 +208,18 @@ bool RlinkPortTerm::Open(const std::string& url, RerrMsg& emsg) return false; } + if (cdivisor != 0) { + sioctl.flags |= ASYNC_SPD_CUST; + sioctl.custom_divisor = cdivisor; + if (::ioctl(fd, TIOCSSERIAL, &sioctl) < 0) { + emsg.InitErrno("RlinkPortTerm::Open()", + string("ioctl(TIOCSSERIAL) for '")+fUrl.Path()+"' failed: ", + errno); + ::close(fd); + return false; + } + } + fTiosNew.c_cc[VEOF] = 0; // undef fTiosNew.c_cc[VEOL] = 0; // undef fTiosNew.c_cc[VERASE] = 0; // undef @@ -227,7 +268,8 @@ bool RlinkPortTerm::Open(const std::string& url, RerrMsg& emsg) if (tios.c_cc[i] != fTiosNew.c_cc[i]) pmsg = "c_cc char"; } - if (pmsg) { + // FIXME_code: why does readback fail for 38400 ? + if (speed != B38400 && pmsg) { emsg.Init("RlinkPortTerm::Open()", string("tcsetattr() failed to set") + string(pmsg)); ::close(fd); diff --git a/tools/src/librlink/RlinkServer.cpp b/tools/src/librlink/RlinkServer.cpp index 98e990e9..1f6f98ed 100644 --- a/tools/src/librlink/RlinkServer.cpp +++ b/tools/src/librlink/RlinkServer.cpp @@ -1,6 +1,6 @@ -// $Id: RlinkServer.cpp 628 2015-01-04 16:22:09Z mueller $ +// $Id: RlinkServer.cpp 632 2015-01-11 12:30:03Z mueller $ // -// Copyright 2013-2014 by Walter F.J. Mueller +// Copyright 2013-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-01-10 632 2.2 Exec() without emsg now void, will throw // 2014-12-30 625 2.1 adopt to Rlink V4 attn logic // 2014-12-21 617 2.0.1 use kStat_M_RbTout for rbus timeout // 2014-12-11 611 2.0 re-organize for rlink v4 @@ -24,7 +25,7 @@ /*! \file - \version $Id: RlinkServer.cpp 628 2015-01-04 16:22:09Z mueller $ + \version $Id: RlinkServer.cpp 632 2015-01-11 12:30:03Z mueller $ \brief Implemenation of RlinkServer. */ @@ -159,9 +160,7 @@ void RlinkServer::GetAttnInfo(AttnArgs& args, RlinkCommandList& clist) if (cmd0.Command() != RlinkCommand::kCmdAttn) throw Rexception("RlinkServer::GetAttnInfo", "clist did't start with attn"); - RerrMsg emsg; - if (!Exec(clist, emsg)) - throw Rexception("RlinkServer::GetAttnInfo", "Exec() failed: ", emsg); + Exec(clist); args.fAttnHarvest = cmd0.Data(); args.fHarvestDone = true; diff --git a/tools/src/librlink/RlinkServer.hpp b/tools/src/librlink/RlinkServer.hpp index 2815b352..cda9cc44 100644 --- a/tools/src/librlink/RlinkServer.hpp +++ b/tools/src/librlink/RlinkServer.hpp @@ -1,6 +1,6 @@ -// $Id: RlinkServer.hpp 625 2014-12-30 16:17:45Z mueller $ +// $Id: RlinkServer.hpp 632 2015-01-11 12:30:03Z mueller $ // -// Copyright 2013-2014 by Walter F.J. Mueller +// Copyright 2013-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-01-10 632 2.2 Exec() without emsg now void, will throw // 2014-12-30 625 2.1 adopt to Rlink V4 attn logic // 2014-11-30 607 2.0 re-organize for rlink v4 // 2013-05-01 513 1.0.2 fTraceLevel now uint32_t @@ -23,7 +24,7 @@ /*! \file - \version $Id: RlinkServer.hpp 625 2014-12-30 16:17:45Z mueller $ + \version $Id: RlinkServer.hpp 632 2015-01-11 12:30:03Z mueller $ \brief Declaration of class \c RlinkServer. */ @@ -75,11 +76,11 @@ namespace Retro { RlinkContext& Context(); bool Exec(RlinkCommandList& clist, RerrMsg& emsg); - bool Exec(RlinkCommandList& clist); + void Exec(RlinkCommandList& clist); void AddAttnHandler(const attnhdl_t& attnhdl, uint16_t mask, - void* cdata = 0); - void RemoveAttnHandler(uint16_t mask, void* cdata = 0); + void* cdata = nullptr); + void RemoveAttnHandler(uint16_t mask, void* cdata = nullptr); void GetAttnInfo(AttnArgs& args, RlinkCommandList& clist); void GetAttnInfo(AttnArgs& args); diff --git a/tools/src/librlink/RlinkServer.ipp b/tools/src/librlink/RlinkServer.ipp index 5ed3b329..5d941c9c 100644 --- a/tools/src/librlink/RlinkServer.ipp +++ b/tools/src/librlink/RlinkServer.ipp @@ -1,6 +1,6 @@ -// $Id: RlinkServer.ipp 625 2014-12-30 16:17:45Z mueller $ +// $Id: RlinkServer.ipp 632 2015-01-11 12:30:03Z mueller $ // -// Copyright 2013-2014 by Walter F.J. Mueller +// Copyright 2013-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-01-10 632 2.2 Exec() without emsg now void, will throw // 2014-12-30 625 2.1 adopt to Rlink V4 attn logic // 2014-11-30 607 2.0 re-organize for rlink v4 // 2013-05-01 513 1.0.1 fTraceLevel now uint32_t @@ -22,7 +23,7 @@ /*! \file - \version $Id: RlinkServer.ipp 625 2014-12-30 16:17:45Z mueller $ + \version $Id: RlinkServer.ipp 632 2015-01-11 12:30:03Z mueller $ \brief Implemenation (inline) of RlinkServer. */ @@ -72,9 +73,10 @@ inline bool RlinkServer::Exec(RlinkCommandList& clist, RerrMsg& emsg) //------------------------------------------+----------------------------------- //! FIXME_docs -inline bool RlinkServer::Exec(RlinkCommandList& clist) +inline void RlinkServer::Exec(RlinkCommandList& clist) { - return Connect().Exec(clist, fContext); + Connect().Exec(clist, fContext); + return; } //------------------------------------------+----------------------------------- diff --git a/tools/src/librlinktpp/RtclAttnShuttle.cpp b/tools/src/librlinktpp/RtclAttnShuttle.cpp index 679db534..66f317b0 100644 --- a/tools/src/librlinktpp/RtclAttnShuttle.cpp +++ b/tools/src/librlinktpp/RtclAttnShuttle.cpp @@ -1,4 +1,4 @@ -// $Id: RtclAttnShuttle.cpp 625 2014-12-30 16:17:45Z mueller $ +// $Id: RtclAttnShuttle.cpp 631 2015-01-09 21:36:51Z mueller $ // // Copyright 2013-2014 by Walter F.J. Mueller // @@ -23,7 +23,7 @@ /*! \file - \version $Id: RtclAttnShuttle.cpp 625 2014-12-30 16:17:45Z mueller $ + \version $Id: RtclAttnShuttle.cpp 631 2015-01-09 21:36:51Z mueller $ \brief Implemenation of class RtclAttnShuttle. */ @@ -49,8 +49,8 @@ namespace Retro { //! constructor RtclAttnShuttle::RtclAttnShuttle(uint16_t mask, Tcl_Obj* pobj) - : fpServ(0), - fpInterp(0), + : fpServ(nullptr), + fpInterp(nullptr), fFdPipeRead(-1), fFdPipeWrite(-1), fShuttleChn(0), @@ -110,7 +110,7 @@ void RtclAttnShuttle::Remove() // disconnect from RlinkServer if (fpServ) { fpServ->RemoveAttnHandler(fMask, (void*)this); - fpServ = 0; + fpServ = nullptr; } // disconnect from Tcl if (fpInterp) { @@ -118,7 +118,7 @@ void RtclAttnShuttle::Remove() (Tcl_FileProc*) ThunkTclChannelHandler, (ClientData) this); Tcl_Close(fpInterp, fShuttleChn); - fpInterp = 0; + fpInterp = nullptr; } return; diff --git a/tools/src/librlinktpp/RtclRlinkConnect.cpp b/tools/src/librlinktpp/RtclRlinkConnect.cpp index c4aae9ec..5e707926 100644 --- a/tools/src/librlinktpp/RtclRlinkConnect.cpp +++ b/tools/src/librlinktpp/RtclRlinkConnect.cpp @@ -1,4 +1,4 @@ -// $Id: RtclRlinkConnect.cpp 628 2015-01-04 16:22:09Z mueller $ +// $Id: RtclRlinkConnect.cpp 631 2015-01-09 21:36:51Z mueller $ // // Copyright 2011-2015 by Walter F.J. Mueller // @@ -13,7 +13,7 @@ // // Revision History: // Date Rev Version Comment -// 2015-01-04 628 1.3.2 add M_get +// 2015-01-06 631 1.3.2 add M_get, M_set, remove M_config // 2014-12-20 616 1.3.1 M_exec: add -edone for BlockDone checking // 2014-12-06 609 1.3 new rlink v4 iface // 2014-08-22 584 1.2.1 use nullptr @@ -33,7 +33,7 @@ /*! \file - \version $Id: RtclRlinkConnect.cpp 628 2015-01-04 16:22:09Z mueller $ + \version $Id: RtclRlinkConnect.cpp 631 2015-01-09 21:36:51Z mueller $ \brief Implemenation of class RtclRlinkConnect. */ @@ -71,7 +71,8 @@ namespace Retro { RtclRlinkConnect::RtclRlinkConnect(Tcl_Interp* interp, const char* name) : RtclProxyOwned("RlinkConnect", interp, name, new RlinkConnect()), - fGets() + fGets(), + fSets() { AddMeth("open", boost::bind(&RtclRlinkConnect::M_open, this, _1)); AddMeth("close", boost::bind(&RtclRlinkConnect::M_close, this, _1)); @@ -85,8 +86,8 @@ RtclRlinkConnect::RtclRlinkConnect(Tcl_Interp* interp, const char* name) AddMeth("log", boost::bind(&RtclRlinkConnect::M_log, this, _1)); AddMeth("print", boost::bind(&RtclRlinkConnect::M_print, this, _1)); AddMeth("dump", boost::bind(&RtclRlinkConnect::M_dump, this, _1)); - AddMeth("config", boost::bind(&RtclRlinkConnect::M_config, this, _1)); AddMeth("get", boost::bind(&RtclRlinkConnect::M_get, this, _1)); + AddMeth("set", boost::bind(&RtclRlinkConnect::M_set, this, _1)); AddMeth("$default", boost::bind(&RtclRlinkConnect::M_default, this, _1)); for (size_t i=0; i<8; i++) { @@ -94,6 +95,20 @@ RtclRlinkConnect::RtclRlinkConnect(Tcl_Interp* interp, const char* name) } RlinkConnect* pobj = &Obj(); + fGets.Add ("baseaddr", + boost::bind(&RlinkConnect::LogBaseAddr, pobj)); + fGets.Add ("basedata", + boost::bind(&RlinkConnect::LogBaseData, pobj)); + fGets.Add ("basestat", + boost::bind(&RlinkConnect::LogBaseStat, pobj)); + fGets.Add ("printlevel", + boost::bind(&RlinkConnect::PrintLevel, pobj)); + fGets.Add ("dumplevel", + boost::bind(&RlinkConnect::DumpLevel, pobj)); + fGets.Add ("tracelevel", + boost::bind(&RlinkConnect::TraceLevel, pobj)); + fGets.Add ("logfile", + boost::bind(&RlinkConnect::LogFileName, pobj)); fGets.Add ("sysid", boost::bind(&RlinkConnect::SysId, pobj)); fGets.Add ("rbufsize", @@ -102,6 +117,21 @@ RtclRlinkConnect::RtclRlinkConnect(Tcl_Interp* interp, const char* name) boost::bind(&RlinkConnect::BlockSizeMax, pobj)); fGets.Add ("bsizeprudent", boost::bind(&RlinkConnect::BlockSizePrudent, pobj)); + + fSets.Add ("baseaddr", + boost::bind(&RlinkConnect::SetLogBaseAddr, pobj, _1)); + fSets.Add ("basedata", + boost::bind(&RlinkConnect::SetLogBaseData, pobj, _1)); + fSets.Add ("basestat", + boost::bind(&RlinkConnect::SetLogBaseStat, pobj, _1)); + fSets.Add ("printlevel", + boost::bind(&RlinkConnect::SetPrintLevel, pobj, _1)); + fSets.Add ("dumplevel", + boost::bind(&RlinkConnect::SetDumpLevel, pobj, _1)); + fSets.Add ("tracelevel", + boost::bind(&RlinkConnect::SetTraceLevel, pobj, _1)); + fSets.Add ("logfile", + boost::bind(&RlinkConnect::SetLogFileName, pobj, _1)); } //------------------------------------------+----------------------------------- @@ -337,9 +367,8 @@ int RtclRlinkConnect::M_exec(RtclArgs& args) if (!varprint.empty()) { ostringstream sos; - const RlinkConnect::LogOpts& logopts = Obj().GetLogOpts(); - clist.Print(sos, Obj().Context(), &Obj().AddrMap(), logopts.baseaddr, - logopts.basedata, logopts.basestat); + clist.Print(sos, Obj().Context(), &Obj().AddrMap(), Obj().LogBaseAddr(), + Obj().LogBaseData(), Obj().LogBaseStat()); RtclOPtr pobj(Rtcl::NewLinesObj(sos)); if (!Rtcl::SetVarOrResult(args.Interp(), varprint, pobj)) return kERR; } @@ -528,7 +557,7 @@ int RtclRlinkConnect::M_wtlam(RtclArgs& args) if (twait == -2.) { // IO error return args.Quit(emsg); } else if (twait == -1.) { // timeout - if (Obj().GetLogOpts().printlevel >= 1) { + if (Obj().PrintLevel() >= 1) { RlogMsg lmsg(Obj().LogFile()); lmsg << "-- wtlam to=" << RosPrintf(tout, "f", 0,3) << " FAIL timeout" << endl; @@ -538,7 +567,7 @@ int RtclRlinkConnect::M_wtlam(RtclArgs& args) } } - if (Obj().GetLogOpts().printlevel >= 3) { + if (Obj().PrintLevel() >= 3) { RlogMsg lmsg(Obj().LogFile()); lmsg << "-- wtlam to=" << RosPrintf(tout, "f", 0,3) << " T=" << RosPrintf(twait, "f", 0,3) @@ -635,9 +664,9 @@ int RtclRlinkConnect::M_log(RtclArgs& args) string msg; if (!args.GetArg("msg", msg)) return kERR; if (!args.AllDone()) return kERR; - if (Obj().GetLogOpts().printlevel != 0 || - Obj().GetLogOpts().dumplevel != 0 || - Obj().GetLogOpts().tracelevel != 0) { + if (Obj().PrintLevel() != 0 || + Obj().DumpLevel() != 0 || + Obj().TraceLevel() != 0) { Obj().LogFile().Write(string("# ") + msg); } return kOK; @@ -672,77 +701,6 @@ int RtclRlinkConnect::M_dump(RtclArgs& args) //------------------------------------------+----------------------------------- //! FIXME_docs -int RtclRlinkConnect::M_config(RtclArgs& args) -{ - static RtclNameSet optset("-baseaddr|-basedata|-basestat|" - "-logfile|-logprintlevel|-logdumplevel|" - "-logtracelevel"); - - RlinkConnect::LogOpts logopts = Obj().GetLogOpts(); - - if (args.NDone() == (size_t)args.Objc()) { - ostringstream sos; - sos << "-baseaddr " << RosPrintf(logopts.baseaddr, "d") - << " -basedata " << RosPrintf(logopts.basedata, "d") - << " -basestat " << RosPrintf(logopts.basestat, "d") - << " -logfile {" << Obj().LogFile().Name() << "}" - << " -logprintlevel " << RosPrintf(logopts.printlevel, "d") - << " -logdumplevel " << RosPrintf(logopts.dumplevel, "d") - << " -logtracelevel " << RosPrintf(logopts.tracelevel, "d"); - args.AppendResult(sos); - return kOK; - } - - string opt; - while (args.NextOpt(opt, optset)) { - if (opt == "-baseaddr") { // -baseaddr ?base ----------------- - if (!ConfigBase(args, logopts.baseaddr)) return kERR; - if (args.NOptMiss() == 0) Obj().SetLogOpts(logopts); - - } else if (opt == "-basedata") { // -basedata ?base ----------------- - if (!ConfigBase(args, logopts.basedata)) return kERR; - if (args.NOptMiss() == 0) Obj().SetLogOpts(logopts); - - } else if (opt == "-basestat") { // -basestat ?base ----------------- - if (!ConfigBase(args, logopts.basestat)) return kERR; - if (args.NOptMiss() == 0) Obj().SetLogOpts(logopts); - - } else if (opt == "-logfile") { // -logfile ?name ------------------ - string name; - if (!args.Config("??name", name)) return false; - if (args.NOptMiss() == 0) { // new filename ? - if (name == "-" || name == "") { - Obj().LogUseStream(&cout, ""); - } else { - if (!Obj().LogOpen(name)) { - Obj().LogUseStream(&cout, ""); - return args.Quit(string("-E: open failed for '") + name + - "', using stdout"); - } - } - } - - } else if (opt == "-logprintlevel") { // -logprintlevel ?loglevel -------- - if (!args.Config("??loglevel", logopts.printlevel, 3)) return false; - if (args.NOptMiss() == 0) Obj().SetLogOpts(logopts); - - } else if (opt == "-logdumplevel") { // -logdumplevel ?loglevel --------- - if (!args.Config("??loglevel", logopts.dumplevel, 3)) return false; - if (args.NOptMiss() == 0) Obj().SetLogOpts(logopts); - - } else if (opt == "-logtracelevel") { // -logtracelevel ?loglevel -------- - if (!args.Config("??loglevel", logopts.tracelevel, 3)) return false; - if (args.NOptMiss() == 0) Obj().SetLogOpts(logopts); - } - } - - if (!args.AllDone()) return kERR; - return kOK; -} - -//------------------------------------------+----------------------------------- -//! FIXME_docs - int RtclRlinkConnect::M_get(RtclArgs& args) { // synchronize with server thread (really needed ??) @@ -753,18 +711,27 @@ int RtclRlinkConnect::M_get(RtclArgs& args) //------------------------------------------+----------------------------------- //! FIXME_docs +int RtclRlinkConnect::M_set(RtclArgs& args) +{ + // synchronize with server thread (really needed ??) + boost::lock_guard lock(Obj()); + return fSets.M_set(args); +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + int RtclRlinkConnect::M_default(RtclArgs& args) { if (!args.AllDone()) return kERR; ostringstream sos; - const RlinkConnect::LogOpts& logopts = Obj().GetLogOpts(); - sos << "print base: " << "addr " << RosPrintf(logopts.baseaddr, "d", 2) - << " data " << RosPrintf(logopts.basedata, "d", 2) - << " stat " << RosPrintf(logopts.basestat, "d", 2) << endl; + sos << "print base: " << "addr " << RosPrintf(Obj().LogBaseAddr(), "d", 2) + << " data " << RosPrintf(Obj().LogBaseData(), "d", 2) + << " stat " << RosPrintf(Obj().LogBaseStat(), "d", 2) << endl; sos << "logfile: " << Obj().LogFile().Name() - << " printlevel " << logopts.printlevel - << " dumplevel " << logopts.dumplevel; + << " printlevel " << Obj().PrintLevel() + << " dumplevel " << Obj().DumpLevel(); args.AppendResultLines(sos); return kOK; diff --git a/tools/src/librlinktpp/RtclRlinkConnect.hpp b/tools/src/librlinktpp/RtclRlinkConnect.hpp index 21eede42..2f617dc3 100644 --- a/tools/src/librlinktpp/RtclRlinkConnect.hpp +++ b/tools/src/librlinktpp/RtclRlinkConnect.hpp @@ -1,4 +1,4 @@ -// $Id: RtclRlinkConnect.hpp 628 2015-01-04 16:22:09Z mueller $ +// $Id: RtclRlinkConnect.hpp 631 2015-01-09 21:36:51Z mueller $ // // Copyright 2011-2015 by Walter F.J. Mueller // @@ -13,7 +13,7 @@ // // Revision History: // Date Rev Version Comment -// 2015-01-04 628 1.0.4 add M_get +// 2015-01-06 631 1.0.4 add M_get, M_set, remove M_config // 2013-02-23 492 1.0.3 use RlogFile.Name(); use Context().ErrorCount() // 2013-01-06 473 1.0.2 add M_rawio // 2011-11-28 434 1.0.1 ConfigBase(): use uint32_t for lp64 compatibility @@ -23,7 +23,7 @@ /*! \file - \version $Id: RtclRlinkConnect.hpp 628 2015-01-04 16:22:09Z mueller $ + \version $Id: RtclRlinkConnect.hpp 631 2015-01-09 21:36:51Z mueller $ \brief Declaration of class RtclRlinkConnect. */ @@ -36,6 +36,7 @@ #include "librtcltools/RtclOPtr.hpp" #include "librtcltools/RtclProxyOwned.hpp" #include "librtcltools/RtclGetList.hpp" +#include "librtcltools/RtclSetList.hpp" #include "librlink/RlinkConnect.hpp" @@ -59,8 +60,8 @@ namespace Retro { int M_log(RtclArgs& args); int M_print(RtclArgs& args); int M_dump(RtclArgs& args); - int M_config(RtclArgs& args); int M_get(RtclArgs& args); + int M_set(RtclArgs& args); int M_default(RtclArgs& args); bool GetAddr(RtclArgs& args, uint16_t& addr); @@ -73,6 +74,7 @@ namespace Retro { protected: RtclOPtr fCmdnameObj[8]; RtclGetList fGets; + RtclSetList fSets; }; } // end namespace Retro diff --git a/tools/src/librlinktpp/RtclRlinkPort.cpp b/tools/src/librlinktpp/RtclRlinkPort.cpp index 764c4aa9..d1084e3b 100644 --- a/tools/src/librlinktpp/RtclRlinkPort.cpp +++ b/tools/src/librlinktpp/RtclRlinkPort.cpp @@ -1,6 +1,6 @@ -// $Id: RtclRlinkPort.cpp 584 2014-08-22 19:38:12Z mueller $ +// $Id: RtclRlinkPort.cpp 632 2015-01-11 12:30:03Z mueller $ // -// Copyright 2013-2014 by Walter F.J. Mueller +// Copyright 2013-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-01-09 632 1.0.4 add M_get, M_set, remove M_config // 2014-08-22 584 1.0.3 use nullptr // 2013-02-23 492 1.0.2 use RlogFile.Name(); // 2013-02-22 491 1.0.1 use new RlogFile/RlogMsg interfaces @@ -21,7 +22,7 @@ /*! \file - \version $Id: RtclRlinkPort.cpp 584 2014-08-22 19:38:12Z mueller $ + \version $Id: RtclRlinkPort.cpp 632 2015-01-11 12:30:03Z mueller $ \brief Implemenation of class RtclRlinkPort. */ @@ -56,8 +57,8 @@ namespace Retro { RtclRlinkPort::RtclRlinkPort(Tcl_Interp* interp, const char* name) : RtclProxyBase("RlinkPort"), - fpObj(0), - fspLog(new RlogFile(&cout, "")), + fpObj(nullptr), + fspLog(new RlogFile(&cout)), fTraceLevel(0), fErrCnt(0) { @@ -69,8 +70,11 @@ RtclRlinkPort::RtclRlinkPort(Tcl_Interp* interp, const char* name) AddMeth("stats", boost::bind(&RtclRlinkPort::M_stats, this, _1)); AddMeth("log", boost::bind(&RtclRlinkPort::M_log, this, _1)); AddMeth("dump", boost::bind(&RtclRlinkPort::M_dump, this, _1)); - AddMeth("config", boost::bind(&RtclRlinkPort::M_config, this, _1)); + AddMeth("get", boost::bind(&RtclRlinkPort::M_get, this, _1)); + AddMeth("set", boost::bind(&RtclRlinkPort::M_set, this, _1)); AddMeth("$default", boost::bind(&RtclRlinkPort::M_default, this, _1)); + + SetupGetSet(); } //------------------------------------------+----------------------------------- @@ -95,6 +99,7 @@ int RtclRlinkPort::M_open(RtclArgs& args) if (args.NOptMiss() == 0) { // open path delete fpObj; fpObj = RlinkPortFactory::Open(path, emsg); + SetupGetSet(); if (!fpObj) return args.Quit(emsg); fpObj->SetLogFile(fspLog); fpObj->SetTraceLevel(fTraceLevel); @@ -113,6 +118,8 @@ int RtclRlinkPort::M_close(RtclArgs& args) if (!args.AllDone()) return kERR; if (!TestOpen(args)) return kERR; delete fpObj; + fpObj = nullptr; + SetupGetSet(); return kOK; } @@ -186,42 +193,17 @@ int RtclRlinkPort::M_dump(RtclArgs& args) //------------------------------------------+----------------------------------- //! FIXME_docs -int RtclRlinkPort::M_config(RtclArgs& args) +int RtclRlinkPort::M_get(RtclArgs& args) { - static RtclNameSet optset("-logfile|-logtracelevel"); + return fGets.M_get(args); +} - if (args.NDone() == (size_t)args.Objc()) { - ostringstream sos; - sos << " -logfile {" << fspLog->Name() << "}" - << " -logtracelevel " << RosPrintf(fTraceLevel, "d"); - args.AppendResult(sos); - return kOK; - } +//------------------------------------------+----------------------------------- +//! FIXME_docs - string opt; - while (args.NextOpt(opt, optset)) { - if (opt == "-logfile") { // -logfile ?name ------------------ - string name; - if (!args.Config("??name", name)) return false; - if (args.NOptMiss() == 0) { // new filename ? - if (name == "-" || name == "") { - fspLog->UseStream(&cout, ""); - } else { - if (!fspLog->Open(name)) { - fspLog->UseStream(&cout, ""); - return args.Quit(string("-E: open failed for '") + name + - "', using stdout"); - } - } - } - } else if (opt == "-logtracelevel") { // -logtracelevel ?loglevel -------- - if (!args.Config("??loglevel", fTraceLevel, 3)) return false; - if (fpObj) fpObj->SetTraceLevel(fTraceLevel); - } - } - - if (!args.AllDone()) return kERR; - return kOK; +int RtclRlinkPort::M_set(RtclArgs& args) +{ + return fSets.M_set(args); } //------------------------------------------+----------------------------------- @@ -242,6 +224,27 @@ int RtclRlinkPort::M_default(RtclArgs& args) //------------------------------------------+----------------------------------- //! FIXME_docs +void RtclRlinkPort::SetupGetSet() +{ + fGets.Clear(); + fSets.Clear(); + + fGets.Add ("logfile", + boost::bind(&RtclRlinkPort::LogFileName, this)); + fSets.Add ("logfile", + boost::bind(&RtclRlinkPort::SetLogFileName, this, _1)); + + if (fpObj == nullptr) return; + + fGets.Add ("tracelevel", + boost::bind(&RlinkPort::TraceLevel, fpObj)); + fSets.Add ("tracelevel", + boost::bind(&RlinkPort::SetTraceLevel, fpObj, _1)); +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + bool RtclRlinkPort::TestOpen(RtclArgs& args) { if (fpObj) return true; @@ -252,6 +255,28 @@ bool RtclRlinkPort::TestOpen(RtclArgs& args) //------------------------------------------+----------------------------------- //! FIXME_docs +void RtclRlinkPort::SetLogFileName(const std::string& name) +{ + RerrMsg emsg; + if (!fspLog->Open(name, emsg)) { + fspLog->UseStream(&cout); + throw Rexception("RtclRlinkPort::SetLogFile", + emsg.Text() + "', using stdout"); + } + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline std::string RtclRlinkPort::LogFileName() const +{ + return fspLog->Name(); +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + int RtclRlinkPort::DoRawio(RtclArgs& args, RlinkPort* pport, size_t& errcnt) { static RtclNameSet optset("-rblk|-wblk|-edata|-timeout"); diff --git a/tools/src/librlinktpp/RtclRlinkPort.hpp b/tools/src/librlinktpp/RtclRlinkPort.hpp index 081870ac..be92dee3 100644 --- a/tools/src/librlinktpp/RtclRlinkPort.hpp +++ b/tools/src/librlinktpp/RtclRlinkPort.hpp @@ -1,6 +1,6 @@ -// $Id: RtclRlinkPort.hpp 492 2013-02-24 22:14:47Z mueller $ +// $Id: RtclRlinkPort.hpp 632 2015-01-11 12:30:03Z mueller $ // -// Copyright 2013- by Walter F.J. Mueller +// Copyright 2013-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,13 +13,14 @@ // // Revision History: // Date Rev Version Comment +// 2015-01-09 632 1.0.2 add M_get, M_set, remove M_config // 2013-02-23 492 1.0.1 use RlogFile.Name(); // 2013-01-27 478 1.0 Initial version // --------------------------------------------------------------------------- /*! \file - \version $Id: RtclRlinkPort.hpp 492 2013-02-24 22:14:47Z mueller $ + \version $Id: RtclRlinkPort.hpp 632 2015-01-11 12:30:03Z mueller $ \brief Declaration of class RtclRlinkPort. */ @@ -31,9 +32,11 @@ #include "boost/shared_ptr.hpp" -#include "librtcltools/RtclProxyBase.hpp" - #include "librtools/RlogFile.hpp" +#include "librtcltools/RtclProxyBase.hpp" +#include "librtcltools/RtclGetList.hpp" +#include "librtcltools/RtclSetList.hpp" + #include "librlink/RlinkPort.hpp" namespace Retro { @@ -53,10 +56,14 @@ namespace Retro { int M_stats(RtclArgs& args); int M_log(RtclArgs& args); int M_dump(RtclArgs& args); - int M_config(RtclArgs& args); + int M_get(RtclArgs& args); + int M_set(RtclArgs& args); int M_default(RtclArgs& args); + void SetupGetSet(); bool TestOpen(RtclArgs& args); + void SetLogFileName(const std::string& name); + std::string LogFileName() const; static int DoRawio(RtclArgs& args, RlinkPort* pport, size_t& errcnt); @@ -65,6 +72,8 @@ namespace Retro { boost::shared_ptr fspLog; //!< port log file uint32_t fTraceLevel; //!< 0=off,1=buf,2=char size_t fErrCnt; //!< error count + RtclGetList fGets; + RtclSetList fSets; }; } // end namespace Retro diff --git a/tools/src/librlinktpp/RtclRlinkServer.cpp b/tools/src/librlinktpp/RtclRlinkServer.cpp index 155ccc35..fdcdb3fe 100644 --- a/tools/src/librlinktpp/RtclRlinkServer.cpp +++ b/tools/src/librlinktpp/RtclRlinkServer.cpp @@ -1,4 +1,4 @@ -// $Id: RtclRlinkServer.cpp 584 2014-08-22 19:38:12Z mueller $ +// $Id: RtclRlinkServer.cpp 632 2015-01-11 12:30:03Z mueller $ // // Copyright 2013-2014 by Walter F.J. Mueller // @@ -24,7 +24,7 @@ /*! \file - \version $Id: RtclRlinkServer.cpp 584 2014-08-22 19:38:12Z mueller $ + \version $Id: RtclRlinkServer.cpp 632 2015-01-11 12:30:03Z mueller $ \brief Implemenation of class RtclRlinkServer. */ @@ -94,7 +94,7 @@ int RtclRlinkServer::ClassCmdConfig(RtclArgs& args) // locate RlinkConnect proxy and object -> setup Server->Connect linkage RtclProxyBase* pprox = RtclContext::Find(args.Interp()).FindProxy( "RlinkConnect", parent); - if (pprox == 0) + if (pprox == nullptr) return args.Quit(string("-E: object '") + parent + "' not found or not type RlinkConnect"); @@ -192,10 +192,10 @@ int RtclRlinkServer::M_attn(RtclArgs& args) uint16_t mask=0; if (!args.GetArg("mask", mask)) return kERR; if (!args.AllDone()) return kERR; - RtclOPtr pres(Tcl_NewListObj(0,0)); + RtclOPtr pres(Tcl_NewListObj(0,nullptr)); for (alist_it_t it = fAttnHdl.begin(); it != fAttnHdl.end(); it++) { if ((*it)->Mask() & mask) { - RtclOPtr pele(Tcl_NewListObj(0,0)); + RtclOPtr pele(Tcl_NewListObj(0,nullptr)); Tcl_ListObjAppendElement(nullptr, pele, Tcl_NewIntObj((*it)->Mask()) ); Tcl_ListObjAppendElement(nullptr, pele, (*it)->Script() ); diff --git a/tools/src/librtcltools/Rtcl.cpp b/tools/src/librtcltools/Rtcl.cpp index 28c6d8b3..2c6581e4 100644 --- a/tools/src/librtcltools/Rtcl.cpp +++ b/tools/src/librtcltools/Rtcl.cpp @@ -1,4 +1,4 @@ -// $Id: Rtcl.cpp 584 2014-08-22 19:38:12Z mueller $ +// $Id: Rtcl.cpp 632 2015-01-11 12:30:03Z mueller $ // // Copyright 2011-2014 by Walter F.J. Mueller // @@ -23,7 +23,7 @@ /*! \file - \version $Id: Rtcl.cpp 584 2014-08-22 19:38:12Z mueller $ + \version $Id: Rtcl.cpp 632 2015-01-11 12:30:03Z mueller $ \brief Implemenation of Rtcl. */ @@ -103,7 +103,7 @@ Tcl_Obj* Rtcl::NewListIntObj(const std::vector& vec) bool Rtcl::SetVar(Tcl_Interp* interp, const std::string& varname, Tcl_Obj* pobj) { - Tcl_Obj* pret = 0; + Tcl_Obj* pret = nullptr; size_t pos_pbeg = varname.find_first_of('('); size_t pos_pend = varname.find_first_of(')'); diff --git a/tools/src/librtcltools/RtclArgs.cpp b/tools/src/librtcltools/RtclArgs.cpp index 95dd4e42..e29f4200 100644 --- a/tools/src/librtcltools/RtclArgs.cpp +++ b/tools/src/librtcltools/RtclArgs.cpp @@ -1,4 +1,4 @@ -// $Id: RtclArgs.cpp 584 2014-08-22 19:38:12Z mueller $ +// $Id: RtclArgs.cpp 632 2015-01-11 12:30:03Z mueller $ // // Copyright 2011-2014 by Walter F.J. Mueller // @@ -28,7 +28,7 @@ /*! \file - \version $Id: RtclArgs.cpp 584 2014-08-22 19:38:12Z mueller $ + \version $Id: RtclArgs.cpp 632 2015-01-11 12:30:03Z mueller $ \brief Implemenation of RtclArgs. */ @@ -57,7 +57,7 @@ namespace Retro { //! Default constructor RtclArgs::RtclArgs() - : fpInterp(0), + : fpInterp(nullptr), fObjc(0), fObjv(0), fNDone(0), @@ -278,7 +278,7 @@ bool RtclArgs::GetArg(const char* name, std::vector& val, size_t lmin, size_t lmax) { int objc = 0; - Tcl_Obj** objv = 0; + Tcl_Obj** objv = nullptr; if (!NextArgList(name, objc, objv, lmin, lmax)) return false; if (objv==0) return true; @@ -309,7 +309,7 @@ bool RtclArgs::GetArg(const char* name, std::vector& val, size_t lmin, size_t lmax) { int objc = 0; - Tcl_Obj** objv = 0; + Tcl_Obj** objv = nullptr; if (!NextArgList(name, objc, objv, lmin, lmax)) return false; if (objv==0) return true; @@ -504,7 +504,7 @@ void RtclArgs::AppendResultLines(const std::string& str) bool RtclArgs::NextArg(const char* name, Tcl_Obj*& pobj) { - pobj = 0; + pobj = nullptr; bool isopt = name[0] == '?'; bool isoptopt = isopt && (name[1] == '?'); @@ -542,8 +542,8 @@ bool RtclArgs::NextArgList(const char* name, int& objc, Tcl_Obj**& objv, size_t lmin, size_t lmax) { objc = 0; - objv = 0; - Tcl_Obj* pobj = 0; + objv = nullptr; + Tcl_Obj* pobj = nullptr; if (!NextArg(name, pobj)) return false; if (pobj==0) return true; diff --git a/tools/src/librtcltools/RtclGetList.cpp b/tools/src/librtcltools/RtclGetList.cpp index 1155af3b..f5d80314 100644 --- a/tools/src/librtcltools/RtclGetList.cpp +++ b/tools/src/librtcltools/RtclGetList.cpp @@ -1,6 +1,6 @@ -// $Id: RtclGetList.cpp 584 2014-08-22 19:38:12Z mueller $ +// $Id: RtclGetList.cpp 631 2015-01-09 21:36:51Z mueller $ // -// Copyright 2013-2014 by Walter F.J. Mueller +// Copyright 2013-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,13 +13,14 @@ // // Revision History: // Date Rev Version Comment +// 2015-01-08 631 1.1 add Clear(), add '?' (key list) and '*' (kv list) // 2014-08-22 584 1.0.1 use nullptr // 2013-02-12 487 1.0 Initial version // --------------------------------------------------------------------------- /*! \file - \version $Id: RtclGetList.cpp 584 2014-08-22 19:38:12Z mueller $ + \version $Id: RtclGetList.cpp 631 2015-01-09 21:36:51Z mueller $ \brief Implemenation of class RtclGetList. */ @@ -29,6 +30,7 @@ #include "RtclGet.hpp" #include "RtclGetList.hpp" +#include "RtclOPtr.hpp" using namespace std; @@ -73,12 +75,42 @@ void RtclGetList::Add(const std::string& name, RtclGetBase* pget) //------------------------------------------+----------------------------------- //! FIXME_docs +void RtclGetList::Clear() +{ + fMap.clear(); + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + int RtclGetList::M_get(RtclArgs& args) { - string pname; - if (!args.GetArg("pname", pname)) return TCL_ERROR; - Tcl_Interp* interp = args.Interp(); + string pname("*"); + if (!args.GetArg("??pname", pname)) return TCL_ERROR; + if (!args.AllDone()) return TCL_ERROR; + + if (pname == "?") { + RtclOPtr rlist(Tcl_NewListObj(0,nullptr)); + for (const auto& kv : fMap) { + RtclOPtr pele(Tcl_NewStringObj(kv.first.c_str(), -1)); + Tcl_ListObjAppendElement(nullptr, rlist, pele); + } + Tcl_SetObjResult(interp, rlist); + return TCL_OK; + + } else if (pname == "*") { + RtclOPtr rlist(Tcl_NewListObj(0,nullptr)); + for (const auto& kv : fMap) { + RtclOPtr pele(Tcl_NewStringObj(kv.first.c_str(), -1)); + Tcl_ListObjAppendElement(nullptr, rlist, pele); + Tcl_ListObjAppendElement(nullptr, rlist, kv.second->operator()()); + } + Tcl_SetObjResult(interp, rlist); + return TCL_OK; + } + map_cit_t it = fMap.lower_bound(pname); // complain if not found @@ -109,8 +141,6 @@ int RtclGetList::M_get(RtclArgs& args) return TCL_ERROR; } - if (!args.AllDone()) return TCL_ERROR; - args.SetResult((it->second)->operator()()); return TCL_OK; } diff --git a/tools/src/librtcltools/RtclGetList.hpp b/tools/src/librtcltools/RtclGetList.hpp index 9962334a..9991a893 100644 --- a/tools/src/librtcltools/RtclGetList.hpp +++ b/tools/src/librtcltools/RtclGetList.hpp @@ -1,6 +1,6 @@ -// $Id: RtclGetList.hpp 488 2013-02-16 18:49:47Z mueller $ +// $Id: RtclGetList.hpp 631 2015-01-09 21:36:51Z mueller $ // -// Copyright 2013- by Walter F.J. Mueller +// Copyright 2013-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,12 +13,13 @@ // // Revision History: // Date Rev Version Comment +// 2015-01-08 631 1.1 add Clear() // 2013-02-12 487 1.0 Initial version // --------------------------------------------------------------------------- /*! \file - \version $Id: RtclGetList.hpp 488 2013-02-16 18:49:47Z mueller $ + \version $Id: RtclGetList.hpp 631 2015-01-09 21:36:51Z mueller $ \brief Declaration of class \c RtclGetList. */ @@ -50,11 +51,9 @@ namespace Retro { void Add(const std::string& name, const boost::function& get); + void Clear(); int M_get(RtclArgs& args); - protected: - - protected: typedef std::map map_t; typedef map_t::iterator map_it_t; diff --git a/tools/src/librtcltools/RtclSetList.cpp b/tools/src/librtcltools/RtclSetList.cpp index f6d19b28..b1326c66 100644 --- a/tools/src/librtcltools/RtclSetList.cpp +++ b/tools/src/librtcltools/RtclSetList.cpp @@ -1,6 +1,6 @@ -// $Id: RtclSetList.cpp 584 2014-08-22 19:38:12Z mueller $ +// $Id: RtclSetList.cpp 631 2015-01-09 21:36:51Z mueller $ // -// Copyright 2013-2014 by Walter F.J. Mueller +// Copyright 2013-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,13 +13,14 @@ // // Revision History: // Date Rev Version Comment +// 2015-01-08 631 1.1 add Clear(), add '?' (key list) // 2014-08-22 584 1.0.1 use nullptr // 2013-02-12 487 1.0 Initial version // --------------------------------------------------------------------------- /*! \file - \version $Id: RtclSetList.cpp 584 2014-08-22 19:38:12Z mueller $ + \version $Id: RtclSetList.cpp 631 2015-01-09 21:36:51Z mueller $ \brief Implemenation of class RtclSetList. */ @@ -29,6 +30,7 @@ #include "RtclSet.hpp" #include "RtclSetList.hpp" +#include "RtclOPtr.hpp" using namespace std; @@ -73,12 +75,32 @@ void RtclSetList::Add(const std::string& name, RtclSetBase* pset) //------------------------------------------+----------------------------------- //! FIXME_docs +void RtclSetList::Clear() +{ + fMap.clear(); + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + int RtclSetList::M_set(RtclArgs& args) { + Tcl_Interp* interp = args.Interp(); string pname; if (!args.GetArg("pname", pname)) return TCL_ERROR; - Tcl_Interp* interp = args.Interp(); + if (pname == "?") { + if (!args.AllDone()) return TCL_ERROR; + RtclOPtr rlist(Tcl_NewListObj(0,nullptr)); + for (const auto& kv : fMap) { + RtclOPtr pele(Tcl_NewStringObj(kv.first.c_str(), -1)); + Tcl_ListObjAppendElement(nullptr, rlist, pele); + } + Tcl_SetObjResult(interp, rlist); + return TCL_OK; + } + map_cit_t it = fMap.lower_bound(pname); // complain if not found @@ -116,9 +138,11 @@ int RtclSetList::M_set(RtclArgs& args) try { (it->second)->operator()(args); } catch (Rexception& e) { - Tcl_AppendResult(args.Interp(), ", ", e.ErrMsg().Text().c_str(), nullptr); + Tcl_AppendResult(args.Interp(), "-E: ", e.ErrMsg().Text().c_str(), nullptr); + return TCL_ERROR; } catch (exception& e) { - Tcl_AppendResult(args.Interp(), " -E: ", e.what(), nullptr); + Tcl_AppendResult(args.Interp(), "-E: ", e.what(), nullptr); + return TCL_ERROR; } return TCL_OK; diff --git a/tools/src/librtcltools/RtclSetList.hpp b/tools/src/librtcltools/RtclSetList.hpp index 676f5c86..e4a32087 100644 --- a/tools/src/librtcltools/RtclSetList.hpp +++ b/tools/src/librtcltools/RtclSetList.hpp @@ -1,6 +1,6 @@ -// $Id: RtclSetList.hpp 488 2013-02-16 18:49:47Z mueller $ +// $Id: RtclSetList.hpp 631 2015-01-09 21:36:51Z mueller $ // -// Copyright 2013- by Walter F.J. Mueller +// Copyright 2013-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,12 +13,13 @@ // // Revision History: // Date Rev Version Comment +// 2015-01-08 631 1.1 add Clear() // 2013-02-12 487 1.0 Initial version // --------------------------------------------------------------------------- /*! \file - \version $Id: RtclSetList.hpp 488 2013-02-16 18:49:47Z mueller $ + \version $Id: RtclSetList.hpp 631 2015-01-09 21:36:51Z mueller $ \brief Declaration of class \c RtclSetList. */ @@ -50,11 +51,9 @@ namespace Retro { void Add(const std::string& name, const boost::function& set); + void Clear(); int M_set(RtclArgs& args); - protected: - - protected: typedef std::map map_t; typedef map_t::iterator map_it_t; diff --git a/tools/src/librtcltools/RtclStats.cpp b/tools/src/librtcltools/RtclStats.cpp index 131d23ab..9c3ccca5 100644 --- a/tools/src/librtcltools/RtclStats.cpp +++ b/tools/src/librtcltools/RtclStats.cpp @@ -1,4 +1,4 @@ -// $Id: RtclStats.cpp 584 2014-08-22 19:38:12Z mueller $ +// $Id: RtclStats.cpp 631 2015-01-09 21:36:51Z mueller $ // // Copyright 2011-2014 by Walter F.J. Mueller // @@ -21,7 +21,7 @@ /*! \file - \version $Id: RtclStats.cpp 584 2014-08-22 19:38:12Z mueller $ + \version $Id: RtclStats.cpp 631 2015-01-09 21:36:51Z mueller $ \brief Implemenation of RtclStats. */ @@ -111,7 +111,7 @@ bool RtclStats::Collect(RtclArgs& args, const Context& cntx, } else if (cntx.opt == "-lpair" || cntx.opt == "-lall") { // -lpair -lall --- for (size_t i=0; i +// Copyright 2011-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-01-08 631 2.2 Open(): now with RerrMsg and cout/cerr support // 2014-12-10 611 2.1.2 timestamp now usec precision (was msec) // 2013-10-11 539 2.1.1 fix date print (month was off by one) // 2013-02-23 492 2.1 add Name(), keep log file name; add Dump() @@ -22,11 +23,12 @@ /*! \file - \version $Id: RlogFile.cpp 611 2014-12-10 23:23:58Z mueller $ + \version $Id: RlogFile.cpp 631 2015-01-09 21:36:51Z mueller $ \brief Implemenation of RlogFile. */ #include +#include #include "boost/thread/locks.hpp" @@ -50,7 +52,7 @@ namespace Retro { //! Default constructor RlogFile::RlogFile() - : fpExtStream(0), + : fpExtStream(nullptr), fIntStream(), fNew(true), fName(), @@ -66,7 +68,7 @@ RlogFile::RlogFile(std::ostream* os, const std::string& name) : fpExtStream(os), fIntStream(), fNew(false), - fName(name), + fName(BuildinStreamName(os, name)), fMutex() { ClearTime(); @@ -81,12 +83,25 @@ RlogFile::~RlogFile() //------------------------------------------+----------------------------------- //! FIXME_docs -bool RlogFile::Open(std::string name) +bool RlogFile::Open(std::string name, RerrMsg& emsg) { + std::ostream* os = nullptr; + if (name == "" || name == "-") os = &cout; + else if (name == "") os = &cerr; + else if (name == "") os = &clog; + if (os) { + UseStream(os); + return true; + } + fNew = false; - fpExtStream = 0; + fpExtStream = nullptr; fName = name; fIntStream.open(name.c_str()); + if (!fIntStream.is_open()) + emsg.InitErrno("RlogFile::Open", + string("open for '") + name + "' failed: ", + errno); return fIntStream.is_open(); } @@ -107,7 +122,7 @@ void RlogFile::UseStream(std::ostream* os, const std::string& name) fNew = false; if (fIntStream.is_open()) Close(); fpExtStream = os; - fName = name; + fName = BuildinStreamName(os, name); return; } @@ -209,4 +224,17 @@ void RlogFile::ClearTime() return; } +//------------------------------------------+----------------------------------- +//! FIXME_docs + + std::string RlogFile::BuildinStreamName(std::ostream* os, + const std::string& str) +{ + if (str.size()) return str; + if (os == &cout) return string(""); + if (os == &cerr) return string(""); + if (os == &clog) return string(""); + return string(""); +} + } // end namespace Retro diff --git a/tools/src/librtools/RlogFile.hpp b/tools/src/librtools/RlogFile.hpp index 24d7b664..bcc37899 100644 --- a/tools/src/librtools/RlogFile.hpp +++ b/tools/src/librtools/RlogFile.hpp @@ -1,6 +1,6 @@ -// $Id: RlogFile.hpp 492 2013-02-24 22:14:47Z mueller $ +// $Id: RlogFile.hpp 631 2015-01-09 21:36:51Z mueller $ // -// Copyright 2011-2013 by Walter F.J. Mueller +// Copyright 2011-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-01-08 631 2.2 Open(): now with RerrMsg and cout/cerr support // 2013-02-23 492 2.1 add Name(), keep log file name; add Dump() // 2013-02-22 491 2.0 add Write(),IsNew(), RlogMsg iface; use lockable // 2011-04-24 380 1.0.1 use boost::noncopyable (instead of private dcl's) @@ -21,7 +22,7 @@ /*! \file - \version $Id: RlogFile.hpp 492 2013-02-24 22:14:47Z mueller $ + \version $Id: RlogFile.hpp 631 2015-01-09 21:36:51Z mueller $ \brief Declaration of class RlogFile. */ @@ -35,6 +36,8 @@ #include "boost/utility.hpp" #include "boost/thread/mutex.hpp" +#include "RerrMsg.hpp" + namespace Retro { class RlogMsg; // forw decl to avoid circular incl @@ -46,7 +49,7 @@ namespace Retro { ~RlogFile(); bool IsNew() const; - bool Open(std::string name); + bool Open(std::string name, RerrMsg& emsg); void Close(); void UseStream(std::ostream* os, const std::string& name = ""); const std::string& Name() const; @@ -64,6 +67,7 @@ namespace Retro { protected: std::ostream& Stream(); void ClearTime(); + std::string BuildinStreamName(std::ostream* os, const std::string& str); protected: std::ostream* fpExtStream; //!< pointer to external stream diff --git a/tools/src/librtools/RlogFileCatalog.cpp b/tools/src/librtools/RlogFileCatalog.cpp index bfa50348..7a55409e 100644 --- a/tools/src/librtools/RlogFileCatalog.cpp +++ b/tools/src/librtools/RlogFileCatalog.cpp @@ -1,4 +1,4 @@ -// $Id: RlogFileCatalog.cpp 521 2013-05-20 22:16:45Z mueller $ +// $Id: RlogFileCatalog.cpp 631 2015-01-09 21:36:51Z mueller $ // // Copyright 2013- by Walter F.J. Mueller // @@ -18,7 +18,7 @@ /*! \file - \version $Id: RlogFileCatalog.cpp 521 2013-05-20 22:16:45Z mueller $ + \version $Id: RlogFileCatalog.cpp 631 2015-01-09 21:36:51Z mueller $ \brief Implemenation of RlogFileCatalog. */ @@ -74,8 +74,8 @@ void RlogFileCatalog::Delete(const std::string& name) RlogFileCatalog::RlogFileCatalog() { - FindOrCreate("cout")->UseStream(&cout, ""); - FindOrCreate("cerr")->UseStream(&cerr, ""); + FindOrCreate("cout")->UseStream(&cout); + FindOrCreate("cerr")->UseStream(&cerr); } //------------------------------------------+----------------------------------- diff --git a/tools/src/librutiltpp/RtclBvi.cpp b/tools/src/librutiltpp/RtclBvi.cpp index 708b6b30..870a3547 100644 --- a/tools/src/librutiltpp/RtclBvi.cpp +++ b/tools/src/librutiltpp/RtclBvi.cpp @@ -1,4 +1,4 @@ -// $Id: RtclBvi.cpp 584 2014-08-22 19:38:12Z mueller $ +// $Id: RtclBvi.cpp 632 2015-01-11 12:30:03Z mueller $ // // Copyright 2011-2014 by Walter F.J. Mueller // @@ -21,7 +21,7 @@ /*! \file - \version $Id: RtclBvi.cpp 584 2014-08-22 19:38:12Z mueller $ + \version $Id: RtclBvi.cpp 632 2015-01-11 12:30:03Z mueller $ \brief Implemenation of RtclBvi. */ @@ -73,7 +73,7 @@ int RtclBvi::DoCmd(ClientData cdata, Tcl_Interp* interp, int objc, if (list) { int lobjc = 0; - Tcl_Obj** lobjv = 0; + Tcl_Obj** lobjv = nullptr; if (Tcl_ListObjGetElements(interp, objv[2], &lobjc, &lobjv) != kOK) { return kERR; } diff --git a/tools/src/librutiltpp/RtclSignalAction.cpp b/tools/src/librutiltpp/RtclSignalAction.cpp index b292b7ee..35b07e38 100644 --- a/tools/src/librutiltpp/RtclSignalAction.cpp +++ b/tools/src/librutiltpp/RtclSignalAction.cpp @@ -1,4 +1,4 @@ -// $Id: RtclSignalAction.cpp 602 2014-11-08 21:42:47Z mueller $ +// $Id: RtclSignalAction.cpp 631 2015-01-09 21:36:51Z mueller $ // // Copyright 2013-2014 by Walter F.J. Mueller // @@ -21,7 +21,7 @@ /*! \file - \version $Id: RtclSignalAction.cpp 602 2014-11-08 21:42:47Z mueller $ + \version $Id: RtclSignalAction.cpp 631 2015-01-09 21:36:51Z mueller $ \brief Implemenation of class RtclSignalAction. */ @@ -46,7 +46,7 @@ using namespace std; // all method definitions in namespace Retro namespace Retro { -RtclSignalAction* RtclSignalAction::fpObj = 0; +RtclSignalAction* RtclSignalAction::fpObj = nullptr; //------------------------------------------+----------------------------------- //! FIXME_docs @@ -132,7 +132,7 @@ bool RtclSignalAction::ClearAction(int signum, RerrMsg& emsg) "sigaction() failed: ", errno); return false; } - fpScript[signum] = 0; + fpScript[signum] = nullptr; fActionSet[signum] = false; return true; } @@ -211,7 +211,7 @@ void RtclSignalAction::ThunkTclChannelHandler(ClientData cdata, int mask) void RtclSignalAction::ThunkTclExitProc(ClientData cdata) { delete fpObj; - fpObj = 0; + fpObj = nullptr; return; } diff --git a/tools/src/librutiltpp/RtclSystem.cpp b/tools/src/librutiltpp/RtclSystem.cpp index e53aec1e..846dbe91 100644 --- a/tools/src/librutiltpp/RtclSystem.cpp +++ b/tools/src/librutiltpp/RtclSystem.cpp @@ -1,4 +1,4 @@ -// $Id: RtclSystem.cpp 584 2014-08-22 19:38:12Z mueller $ +// $Id: RtclSystem.cpp 632 2015-01-11 12:30:03Z mueller $ // // Copyright 2013-2014 by Walter F.J. Mueller // @@ -19,7 +19,7 @@ /*! \file - \version $Id: RtclSystem.cpp 584 2014-08-22 19:38:12Z mueller $ + \version $Id: RtclSystem.cpp 632 2015-01-11 12:30:03Z mueller $ \brief Implemenation of RtclSystem. */ @@ -145,7 +145,7 @@ int RtclSystem::SignalAction(ClientData cdata, Tcl_Interp* interp, return kOK; } else if (opt == "-info") { // -info - RtclOPtr pres(Tcl_NewListObj(0,0)); + RtclOPtr pres(Tcl_NewListObj(0,nullptr)); int siglist[] = {SIGHUP,SIGINT,SIGTERM,SIGUSR1,SIGUSR2}; for (size_t i=0; iGetAction(signum, pobj, emsg)) return args.Quit("no handler defined"); - if (pobj == 0) pobj = Tcl_NewStringObj("{}",-1); + if (pobj == nullptr) pobj = Tcl_NewStringObj("{}",-1); args.SetResult(pobj); } diff --git a/tools/src/librw11/Makefile b/tools/src/librw11/Makefile index 5b30a6b3..f778ba9b 100644 --- a/tools/src/librw11/Makefile +++ b/tools/src/librw11/Makefile @@ -30,6 +30,7 @@ OBJ_all += Rw11UnitStream.o OBJ_all += Rw11CntlDL11.o Rw11UnitDL11.o OBJ_all += Rw11CntlLP11.o Rw11UnitLP11.o OBJ_all += Rw11CntlPC11.o Rw11UnitPC11.o +OBJ_all += Rw11CntlRL11.o Rw11UnitRL11.o OBJ_all += Rw11CntlRK11.o Rw11UnitRK11.o OBJ_all += Rw11Virt.o OBJ_all += Rw11VirtTerm.o Rw11VirtTermPty.o Rw11VirtTermTcp.o diff --git a/tools/src/librw11/Rw11Cntl.cpp b/tools/src/librw11/Rw11Cntl.cpp index 60856d48..f3ab2175 100644 --- a/tools/src/librw11/Rw11Cntl.cpp +++ b/tools/src/librw11/Rw11Cntl.cpp @@ -1,4 +1,4 @@ -// $Id: Rw11Cntl.cpp 625 2014-12-30 16:17:45Z mueller $ +// $Id: Rw11Cntl.cpp 631 2015-01-09 21:36:51Z mueller $ // // Copyright 2013-2014 by Walter F.J. Mueller // @@ -20,7 +20,7 @@ /*! \file - \version $Id: Rw11Cntl.cpp 625 2014-12-30 16:17:45Z mueller $ + \version $Id: Rw11Cntl.cpp 631 2015-01-09 21:36:51Z mueller $ \brief Implemenation of Rw11Cntl. */ @@ -44,7 +44,7 @@ namespace Retro { //! Constructor Rw11Cntl::Rw11Cntl(const std::string& type) - : fpCpu(0), + : fpCpu(nullptr), fType(type), fName(), fBase(0), diff --git a/tools/src/librw11/Rw11CntlDL11.cpp b/tools/src/librw11/Rw11CntlDL11.cpp index 0ee232b2..53a388d9 100644 --- a/tools/src/librw11/Rw11CntlDL11.cpp +++ b/tools/src/librw11/Rw11CntlDL11.cpp @@ -1,4 +1,4 @@ -// $Id: Rw11CntlDL11.cpp 625 2014-12-30 16:17:45Z mueller $ +// $Id: Rw11CntlDL11.cpp 632 2015-01-11 12:30:03Z mueller $ // // Copyright 2013-2014 by Walter F.J. Mueller // @@ -23,7 +23,7 @@ /*! \file - \version $Id: Rw11CntlDL11.cpp 625 2014-12-30 16:17:45Z mueller $ + \version $Id: Rw11CntlDL11.cpp 632 2015-01-11 12:30:03Z mueller $ \brief Implemenation of Rw11CntlDL11. */ @@ -150,14 +150,12 @@ void Rw11CntlDL11::Wakeup() RlinkCommandList clist; size_t ircsr = Cpu().AddRibr(clist, fBase+kRCSR); Server().Exec(clist); - // FIXME_code: handle errors uint16_t rcsr = clist[ircsr].Data(); if ((rcsr & kRCSR_M_RDONE) == 0) { // RBUF not full uint8_t ichr = fspUnit[0]->RcvNext(); clist.Clear(); Cpu().AddWibr(clist, fBase+kRBUF, ichr); Server().Exec(clist); - // FIXME_code: handle errors } } @@ -258,7 +256,6 @@ int Rw11CntlDL11::AttnHandler(RlinkServer::AttnArgs& args) RlinkCommandList clist; Cpu().AddWibr(clist, fBase+kRBUF, ichr); Server().Exec(clist); - // FIXME_code: handle errors } return 0; diff --git a/tools/src/librw11/Rw11CntlRK11.cpp b/tools/src/librw11/Rw11CntlRK11.cpp index 74b88bb7..336c1f5c 100644 --- a/tools/src/librw11/Rw11CntlRK11.cpp +++ b/tools/src/librw11/Rw11CntlRK11.cpp @@ -1,4 +1,4 @@ -// $Id: Rw11CntlRK11.cpp 628 2015-01-04 16:22:09Z mueller $ +// $Id: Rw11CntlRK11.cpp 647 2015-02-17 22:35:36Z mueller $ // // Copyright 2013-2015 by Walter F.J. Mueller // Other credits: @@ -15,6 +15,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-02-17 647 2.0.1 use Nwrd2Nblk(); BUGFIX: revise RdmaPostExecCB() // 2015-01-04 628 2.0 use Rw11RdmaDisk // 2014-12-30 625 1.2 adopt to Rlink V4 attn logic // 2014-12-25 621 1.1 adopt to 4k word ibus window @@ -25,7 +26,7 @@ /*! \file - \version $Id: Rw11CntlRK11.cpp 628 2015-01-04 16:22:09Z mueller $ + \version $Id: Rw11CntlRK11.cpp 647 2015-02-17 22:35:36Z mueller $ \brief Implemenation of Rw11CntlRK11. */ @@ -102,16 +103,17 @@ const uint16_t Rw11CntlRK11::kRKCS_V_MEX; const uint16_t Rw11CntlRK11::kRKCS_B_MEX; const uint16_t Rw11CntlRK11::kRKCS_V_FUNC; const uint16_t Rw11CntlRK11::kRKCS_B_FUNC; -const uint16_t Rw11CntlRK11::kRKCS_CRESET; -const uint16_t Rw11CntlRK11::kRKCS_WRITE; -const uint16_t Rw11CntlRK11::kRKCS_READ; -const uint16_t Rw11CntlRK11::kRKCS_WCHK; -const uint16_t Rw11CntlRK11::kRKCS_SEEK; -const uint16_t Rw11CntlRK11::kRKCS_RCHK; -const uint16_t Rw11CntlRK11::kRKCS_DRESET; -const uint16_t Rw11CntlRK11::kRKCS_WLOCK; const uint16_t Rw11CntlRK11::kRKCS_M_GO; +const uint16_t Rw11CntlRK11::kFUNC_CRESET; +const uint16_t Rw11CntlRK11::kFUNC_WRITE; +const uint16_t Rw11CntlRK11::kFUNC_READ; +const uint16_t Rw11CntlRK11::kFUNC_WCHK; +const uint16_t Rw11CntlRK11::kFUNC_SEEK; +const uint16_t Rw11CntlRK11::kFUNC_RCHK; +const uint16_t Rw11CntlRK11::kFUNC_DRESET; +const uint16_t Rw11CntlRK11::kFUNC_WLOCK; + const uint16_t Rw11CntlRK11::kRKDA_M_DRSEL; const uint16_t Rw11CntlRK11::kRKDA_V_DRSEL; const uint16_t Rw11CntlRK11::kRKDA_B_DRSEL; @@ -148,7 +150,7 @@ Rw11CntlRK11::Rw11CntlRK11() fRd_fu(0), fRd_ovr(false), fRdma(this, - boost::bind(&Rw11CntlRK11::RdmaPreExecCB, this, _1, _2, _3), + boost::bind(&Rw11CntlRK11::RdmaPreExecCB, this, _1, _2, _3, _4), boost::bind(&Rw11CntlRK11::RdmaPostExecCB, this, _1, _2, _3, _4)) { // must be here because Units have a back-ptr (not available at Rw11CntlBase) @@ -349,7 +351,7 @@ int Rw11CntlRK11::AttnHandler(RlinkServer::AttnArgs& args) RlinkCommandList clist; uint32_t lba = unit.Chs2Lba(cy,hd,se); - uint32_t nblk = (2*nwrd+unit.BlockSize()-1)/unit.BlockSize(); + uint32_t nblk = unit.Nwrd2Nblk(nwrd); uint16_t rker = 0; uint16_t rkds = unit.Rkds(); @@ -371,12 +373,12 @@ int Rw11CntlRK11::AttnHandler(RlinkServer::AttnArgs& args) } // check for general abort conditions - if (fu != kRKCS_CRESET && // function not control reset + if (fu != kFUNC_CRESET && // function not control reset (!unit.Virt())) { // and drive not attached rker = kRKER_M_NXD; // --> abort with NXD error - } else if (fu != kRKCS_WRITE && // function neither write - fu != kRKCS_READ && // nor read + } else if (fu != kFUNC_WRITE && // function neither write + fu != kFUNC_READ && // nor read (rkcs & (kRKCS_M_FMT|kRKCS_M_RWA))) { // and FMT or RWA set rker = kRKER_M_PGE; // --> abort with PGE error } else if (rkcs & kRKCS_M_RWA) { // RWA not supported @@ -385,7 +387,7 @@ int Rw11CntlRK11::AttnHandler(RlinkServer::AttnArgs& args) if (rker) { cpu.AddWibr(clist, fBase+kRKER, rker); - if (fu == kRKCS_SEEK || fu == kRKCS_DRESET) + if (fu == kFUNC_SEEK || fu == kFUNC_DRESET) cpu.AddWibr(clist, fBase+kRKMR, kRKMR_M_SBCLR | (1u< unit.NBlock(); if (ovr) nwrd = (unit.NBlock()-lba) * (unit.BlockSize()/2); @@ -408,11 +410,11 @@ int Rw11CntlRK11::AttnHandler(RlinkServer::AttnArgs& args) fRd_fu = fu; // now handle the functions - if (fu == kRKCS_CRESET) { // Control reset ----------------- + if (fu == kFUNC_CRESET) { // Control reset ----------------- fStats.Inc(kStatNFuncCreset); cpu.AddWibr(clist, fBase+kRKMR, kRKMR_M_CRESET); - } else if (fu == kRKCS_WRITE) { // Write ------------------------- + } else if (fu == kFUNC_WRITE) { // Write ------------------------- // Note: WRITE+FMT is just WRITE fStats.Inc(kStatNFuncWrite); if (se >= unit.NSector()) rker |= kRKER_M_NXS; @@ -427,7 +429,7 @@ int Rw11CntlRK11::AttnHandler(RlinkServer::AttnArgs& args) lba, &unit); } - } else if (fu == kRKCS_READ) { // Read -------------------------- + } else if (fu == kFUNC_READ) { // Read -------------------------- fStats.Inc(kStatNFuncRead); if (se >= unit.NSector()) rker |= kRKER_M_NXS; if (cy >= unit.NCylinder()) rker |= kRKER_M_NXC; @@ -440,7 +442,7 @@ int Rw11CntlRK11::AttnHandler(RlinkServer::AttnArgs& args) lba, &unit); } - } else if (fu == kRKCS_WCHK) { // Write Check ------------------- + } else if (fu == kFUNC_WCHK) { // Write Check ------------------- fStats.Inc(kStatNFuncWchk); if (se >= unit.NSector()) rker |= kRKER_M_NXS; if (cy >= unit.NCylinder()) rker |= kRKER_M_NXC; @@ -453,7 +455,7 @@ int Rw11CntlRK11::AttnHandler(RlinkServer::AttnArgs& args) lba, &unit); } - } else if (fu == kRKCS_SEEK) { // Seek -------------------------- + } else if (fu == kFUNC_SEEK) { // Seek -------------------------- fStats.Inc(kStatNFuncSeek); if (se >= unit.NSector()) rker |= kRKER_M_NXS; if (cy >= unit.NCylinder()) rker |= kRKER_M_NXC; @@ -471,7 +473,7 @@ int Rw11CntlRK11::AttnHandler(RlinkServer::AttnArgs& args) cpu.AddWibr(clist, fBase+kRKMR, 1u<= unit.NSector()) rker |= kRKER_M_NXS; if (cy >= unit.NCylinder()) rker |= kRKER_M_NXC; @@ -482,12 +484,12 @@ int Rw11CntlRK11::AttnHandler(RlinkServer::AttnArgs& args) AddNormalExit(clist, nwrd, 0); // no action, virt disks don't err } - } else if (fu == kRKCS_DRESET) { // Drive Reset ------------------- + } else if (fu == kFUNC_DRESET) { // Drive Reset ------------------- fStats.Inc(kStatNFuncDreset); cpu.AddWibr(clist, fBase+kRKMR, kRKMR_M_FDONE); cpu.AddWibr(clist, fBase+kRKMR, 1u<>kRKDA_V_DRSEL) & kRKDA_B_DRSEL; Rw11UnitRK11& unit = *fspUnit[dr]; - size_t bszwrd = unit.BlockSize()/2; // block size in words - size_t nblk = (ndone+bszwrd-1)/bszwrd; + size_t nblk = unit.Nwrd2Nblk(ndone); uint32_t addr = fRd_addr + 2*ndone; size_t lba = fRd_lba + nblk; diff --git a/tools/src/librw11/Rw11CntlRK11.hpp b/tools/src/librw11/Rw11CntlRK11.hpp index 7c50432a..95d91e25 100644 --- a/tools/src/librw11/Rw11CntlRK11.hpp +++ b/tools/src/librw11/Rw11CntlRK11.hpp @@ -1,4 +1,4 @@ -// $Id: Rw11CntlRK11.hpp 627 2015-01-04 11:36:37Z mueller $ +// $Id: Rw11CntlRK11.hpp 647 2015-02-17 22:35:36Z mueller $ // // Copyright 2013-2015 by Walter F.J. Mueller // @@ -23,7 +23,7 @@ /*! \file - \version $Id: Rw11CntlRK11.hpp 627 2015-01-04 11:36:37Z mueller $ + \version $Id: Rw11CntlRK11.hpp 647 2015-02-17 22:35:36Z mueller $ \brief Declaration of class Rw11CntlRK11. */ @@ -107,16 +107,17 @@ namespace Retro { static const uint16_t kRKCS_B_MEX = 0003; static const uint16_t kRKCS_V_FUNC = 1; static const uint16_t kRKCS_B_FUNC = 0007; - static const uint16_t kRKCS_CRESET = 0; - static const uint16_t kRKCS_WRITE = 1; - static const uint16_t kRKCS_READ = 2; - static const uint16_t kRKCS_WCHK = 3; - static const uint16_t kRKCS_SEEK = 4; - static const uint16_t kRKCS_RCHK = 5; - static const uint16_t kRKCS_DRESET = 6; - static const uint16_t kRKCS_WLOCK = 7; static const uint16_t kRKCS_M_GO = kWBit00; + static const uint16_t kFUNC_CRESET = 0; + static const uint16_t kFUNC_WRITE = 1; + static const uint16_t kFUNC_READ = 2; + static const uint16_t kFUNC_WCHK = 3; + static const uint16_t kFUNC_SEEK = 4; + static const uint16_t kFUNC_RCHK = 5; + static const uint16_t kFUNC_DRESET = 6; + static const uint16_t kFUNC_WLOCK = 7; + static const uint16_t kRKDA_M_DRSEL= 0160000; static const uint16_t kRKDA_V_DRSEL= 13; static const uint16_t kRKDA_B_DRSEL= 0007; @@ -150,7 +151,7 @@ namespace Retro { protected: int AttnHandler(RlinkServer::AttnArgs& args); - void RdmaPreExecCB(int stat, size_t nword, + void RdmaPreExecCB(int stat, size_t nwdone, size_t nwnext, RlinkCommandList& clist); void RdmaPostExecCB(int stat, size_t ndone, RlinkCommandList& clist, size_t ncmd); diff --git a/tools/src/librw11/Rw11CntlRL11.cpp b/tools/src/librw11/Rw11CntlRL11.cpp new file mode 100644 index 00000000..4ea9f3db --- /dev/null +++ b/tools/src/librw11/Rw11CntlRL11.cpp @@ -0,0 +1,756 @@ +// $Id: Rw11CntlRL11.cpp 655 2015-03-04 20:35:21Z mueller $ +// +// Copyright 2014-2015 by Walter F.J. Mueller +// Other credits: +// the boot code is from the simh project and Copyright Robert M Supnik +// CalcCrc() is adopted from the simh project and Copyright Robert M Supnik +// +// This program is free software; you may redistribute and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation, either version 2, or at your option any later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for complete details. +// +// Revision History: +// Date Rev Version Comment +// 2015-03-04 655 1.0.1 use original boot code again +// 2015-03-01 653 1.0 Initial version +// 2014-06-08 561 0.1 First draft +// --------------------------------------------------------------------------- + +/*! + \file + \version $Id: Rw11CntlRL11.cpp 655 2015-03-04 20:35:21Z mueller $ + \brief Implemenation of Rw11CntlRL11. +*/ + +#include "boost/bind.hpp" +#include "boost/foreach.hpp" +#define foreach_ BOOST_FOREACH + +#include "librtools/RosFill.hpp" +#include "librtools/RosPrintBvi.hpp" +#include "librtools/RosPrintf.hpp" +#include "librtools/Rexception.hpp" +#include "librtools/RlogMsg.hpp" + +#include "Rw11CntlRL11.hpp" + +using namespace std; + +/*! + \class Retro::Rw11CntlRL11 + \brief FIXME_docs +*/ + +// all method definitions in namespace Retro +namespace Retro { + +//------------------------------------------+----------------------------------- +// constants definitions + +const uint16_t Rw11CntlRL11::kIbaddr; +const int Rw11CntlRL11::kLam; + +const uint16_t Rw11CntlRL11::kRLCS; +const uint16_t Rw11CntlRL11::kRLBA; +const uint16_t Rw11CntlRL11::kRLDA; +const uint16_t Rw11CntlRL11::kRLMP; + +const uint16_t Rw11CntlRL11::kProbeOff; +const bool Rw11CntlRL11::kProbeInt; +const bool Rw11CntlRL11::kProbeRem; + +const uint16_t Rw11CntlRL11::kRLCS_M_ERR; +const uint16_t Rw11CntlRL11::kRLCS_M_DE; +const uint16_t Rw11CntlRL11::kRLCS_V_E; +const uint16_t Rw11CntlRL11::kRLCS_B_E; +const uint16_t Rw11CntlRL11::kRLCS_V_DS; +const uint16_t Rw11CntlRL11::kRLCS_B_DS; +const uint16_t Rw11CntlRL11::kRLCS_M_CRDY; +const uint16_t Rw11CntlRL11::kRLCS_M_IE; +const uint16_t Rw11CntlRL11::kRLCS_M_BAE; +const uint16_t Rw11CntlRL11::kRLCS_V_BAE; +const uint16_t Rw11CntlRL11::kRLCS_B_BAE; +const uint16_t Rw11CntlRL11::kRLCS_V_FUNC; +const uint16_t Rw11CntlRL11::kRLCS_B_FUNC; +const uint16_t Rw11CntlRL11::kRLCS_M_DRDY; + +const uint16_t Rw11CntlRL11::kFUNC_NOOP; +const uint16_t Rw11CntlRL11::kFUNC_WCHK; +const uint16_t Rw11CntlRL11::kFUNC_GS; +const uint16_t Rw11CntlRL11::kFUNC_SEEK; +const uint16_t Rw11CntlRL11::kFUNC_RHDR; +const uint16_t Rw11CntlRL11::kFUNC_WRITE; +const uint16_t Rw11CntlRL11::kFUNC_READ; +const uint16_t Rw11CntlRL11::kFUNC_RNHC; + +const uint16_t Rw11CntlRL11::kERR_M_DE; +const uint16_t Rw11CntlRL11::kERR_OPI; +const uint16_t Rw11CntlRL11::kERR_WCHK; +const uint16_t Rw11CntlRL11::kERR_HCRC; +const uint16_t Rw11CntlRL11::kERR_DLATE; +const uint16_t Rw11CntlRL11::kERR_HNFND; +const uint16_t Rw11CntlRL11::kERR_NXM; + +const uint16_t Rw11CntlRL11::kRLCS_V_MPREM; +const uint16_t Rw11CntlRL11::kRLCS_B_MPREM; +const uint16_t Rw11CntlRL11::kRLCS_V_MPLOC; +const uint16_t Rw11CntlRL11::kRLCS_B_MPLOC; +const uint16_t Rw11CntlRL11::kRLCS_ENA_MPREM; +const uint16_t Rw11CntlRL11::kRLCS_ENA_MPLOC; + +const uint16_t Rw11CntlRL11::kRFUNC_WCS; +const uint16_t Rw11CntlRL11::kRFUNC_WMP; + +const uint16_t Rw11CntlRL11::kMPREM_M_MAP; +const uint16_t Rw11CntlRL11::kMPREM_M_SEQ; +const uint16_t Rw11CntlRL11::kMPREM_S_MP; +const uint16_t Rw11CntlRL11::kMPREM_S_STA; +const uint16_t Rw11CntlRL11::kMPREM_S_POS; + +const uint16_t Rw11CntlRL11::kMPREM_MP; +const uint16_t Rw11CntlRL11::kMPREM_CRC; +const uint16_t Rw11CntlRL11::kMPREM_STA; +const uint16_t Rw11CntlRL11::kMPREM_POS; + +const uint16_t Rw11CntlRL11::kMPREM_SEQ_MPSTAPOS; + +const uint16_t Rw11CntlRL11::kMPLOC_MP; +const uint16_t Rw11CntlRL11::kMPLOC_STA; +const uint16_t Rw11CntlRL11::kMPLOC_POS; +const uint16_t Rw11CntlRL11::kMPLOC_ZERO; +const uint16_t Rw11CntlRL11::kMPLOC_CRC; + +const uint16_t Rw11CntlRL11::kRLDA_SE_M_DF; +const uint16_t Rw11CntlRL11::kRLDA_SE_V_DF; +const uint16_t Rw11CntlRL11::kRLDA_SE_B_DF; +const uint16_t Rw11CntlRL11::kRLDA_SE_M_HS; +const uint16_t Rw11CntlRL11::kRLDA_SE_M_DIR; +const uint16_t Rw11CntlRL11::kRLDA_SE_X_MSK; +const uint16_t Rw11CntlRL11::kRLDA_SE_X_VAL; + +const uint16_t Rw11CntlRL11::kRLDA_RW_M_CA; +const uint16_t Rw11CntlRL11::kRLDA_RW_V_CA; +const uint16_t Rw11CntlRL11::kRLDA_RW_B_CA; +const uint16_t Rw11CntlRL11::kRLDA_RW_M_HS; +const uint16_t Rw11CntlRL11::kRLDA_RW_V_HS; +const uint16_t Rw11CntlRL11::kRLDA_RW_B_HS; +const uint16_t Rw11CntlRL11::kRLDA_RW_B_SA; + +const uint16_t Rw11CntlRL11::kRLDA_GS_M_RST; +const uint16_t Rw11CntlRL11::kRLDA_GS_X_MSK; +const uint16_t Rw11CntlRL11::kRLDA_GS_X_VAL; + +const uint16_t Rw11CntlRL11::kSTA_M_WDE; +const uint16_t Rw11CntlRL11::kSTA_M_CHE; +const uint16_t Rw11CntlRL11::kSTA_M_WL; +const uint16_t Rw11CntlRL11::kSTA_M_STO; +const uint16_t Rw11CntlRL11::kSTA_M_SPE; +const uint16_t Rw11CntlRL11::kSTA_M_WGE; +const uint16_t Rw11CntlRL11::kSTA_M_VCE; +const uint16_t Rw11CntlRL11::kSTA_M_DSE; +const uint16_t Rw11CntlRL11::kSTA_M_DT; +const uint16_t Rw11CntlRL11::kSTA_M_HS; +const uint16_t Rw11CntlRL11::kSTA_M_CO; +const uint16_t Rw11CntlRL11::kSTA_M_HO; +const uint16_t Rw11CntlRL11::kSTA_M_BH; +const uint16_t Rw11CntlRL11::kSTA_B_ST; + +const uint16_t Rw11CntlRL11::kST_LOAD; +const uint16_t Rw11CntlRL11::kST_SPIN; +const uint16_t Rw11CntlRL11::kST_BRUSH; +const uint16_t Rw11CntlRL11::kST_HLOAD; +const uint16_t Rw11CntlRL11::kST_SEEK; +const uint16_t Rw11CntlRL11::kST_LOCK; +const uint16_t Rw11CntlRL11::kST_UNL; +const uint16_t Rw11CntlRL11::kST_DOWN; + +//------------------------------------------+----------------------------------- +//! Default constructor + +Rw11CntlRL11::Rw11CntlRL11() + : Rw11CntlBase("rl11"), + fPC_rlcs(0), + fPC_rlba(0), + fPC_rlda(0), + fPC_imp(0), + fPC_wc(0), + fPC_sta(0), + fPC_pos(0), + fRd_rlcs(0), + fRd_rlda(0), + fRd_rlmp(0), + fRd_sta(0), + fRd_pos(0), + fRd_addr(0), + fRd_lba(0), + fRd_nwrd(0), + fRd_fu(0), + fRd_ovr(false), + fRdma(this, + boost::bind(&Rw11CntlRL11::RdmaPreExecCB, this, _1, _2, _3, _4), + boost::bind(&Rw11CntlRL11::RdmaPostExecCB, this, _1, _2, _3, _4)) +{ + // must be here because Units have a back-ptr (not available at Rw11CntlBase) + for (size_t i=0; i& code, + uint16_t& aload, uint16_t& astart) +{ + uint16_t kBOOT_START = 02000; + uint16_t bootcode[] = { // rl11 boot loader - from simh pdp11_rl.c (v3.9) + 0042114, // "LD" + 0012706, kBOOT_START, // MOV #boot_start, SP + 0012700, uint16_t(unit), // MOV #unit, R0 + 0010003, // MOV R0, R3 + 0000303, // SWAB R3 + 0012701, 0174400, // MOV #RLCS, R1 ; csr + 0012761, 0000013, 0000004, // MOV #13, 4(R1) ; clr err + 0052703, 0000004, // BIS #4, R3 ; unit+gstat + 0010311, // MOV R3, (R1) ; issue cmd + 0105711, // TSTB (R1) ; wait + 0100376, // BPL .-2 + 0105003, // CLRB R3 + 0052703, 0000010, // BIS #10, R3 ; unit+rdhdr + 0010311, // MOV R3, (R1) ; issue cmd + 0105711, // TSTB (R1) ; wait + 0100376, // BPL .-2 + 0016102, 0000006, // MOV 6(R1), R2 ; get hdr + 0042702, 0000077, // BIC #077, R2 ; clr head+sector + 0005202, // INC R2 ; magic bit + 0010261, 0000004, // MOV R2, 4(R1) ; seek to 0 + 0105003, // CLRB R3 + 0052703, 0000006, // BIS #6, R3 ; unit+seek + 0010311, // MOV R3, (R1) ; issue cmd + 0105711, // TSTB (R1) ; wait + 0100376, // BPL .-2 + 0005061, 0000002, // CLR 2(R1) ; clr ba + 0005061, 0000004, // CLR 4(R1) ; clr da + 0012761, 0177000, 0000006, // MOV #-512., 6(R1) ; set wc + 0105003, // CLRB R3 + 0052703, 0000014, // BIS #14, R3 ; unit+read + 0010311, // MOV R3, (R1) ; issue cmd + 0105711, // TSTB (R1) ; wait + 0100376, // BPL .-2 + 0042711, 0000377, // BIC #377, (R1) + 0005002, // CLR R2 + 0005003, // CLR R3 + 0012704, uint16_t(kBOOT_START+020), // MOV #START+20, R4 ; load #rlcs + 0005005, // CLR R5 + 0005007 // CLR PC + }; + + code.clear(); + foreach_ (uint16_t& w, bootcode) code.push_back(w); + aload = kBOOT_START; + astart = kBOOT_START+2; + return true; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +void Rw11CntlRL11::Dump(std::ostream& os, int ind, const char* text) const +{ + RosFill bl(ind); + os << bl << (text?text:"--") << "Rw11CntlRL11 @ " << this << endl; + os << bl << " fPC_rlcs: " << RosPrintf(fPC_rlcs,"d",6) << endl; + os << bl << " fPC_rlba: " << RosPrintf(fPC_rlba,"d",6) << endl; + os << bl << " fPC_rlda: " << RosPrintf(fPC_rlda,"d",6) << endl; + os << bl << " fPC_imp: " << RosPrintf(fPC_imp,"d",6) << endl; + os << bl << " fPC_wc: " << RosPrintf(fPC_wc,"d",6) << endl; + os << bl << " fPC_sta: " << RosPrintf(fPC_sta,"d",6) << endl; + os << bl << " fPC_pos: " << RosPrintf(fPC_pos,"d",6) << endl; + os << bl << " fRd_rlcs: " << RosPrintBvi(fRd_rlcs,8) << endl; + os << bl << " fRd_rlda: " << RosPrintBvi(fRd_rlda,8) << endl; + os << bl << " fRd_rlmp: " << RosPrintBvi(fRd_rlmp,8) << endl; + os << bl << " fRd_sta: " << RosPrintBvi(fRd_sta,8) << endl; + os << bl << " fRd_pos: " << RosPrintBvi(fRd_pos,8) << endl; + os << bl << " fRd_addr: " << RosPrintBvi(fRd_addr,8,22) << endl; + os << bl << " fRd_lba: " << RosPrintf(fRd_lba,"d",6) << endl; + os << bl << " fRd_nwrd: " << RosPrintf(fRd_nwrd,"d",6) << endl; + os << bl << " fRd_fu: " << RosPrintf(fRd_fu,"d",6) << endl; + os << bl << " fRd_ovr: " << fRd_ovr << endl; + fRdma.Dump(os, ind+2, "fRdma: "); + Rw11CntlBase::Dump(os, ind, " ^"); + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +int Rw11CntlRL11::AttnHandler(RlinkServer::AttnArgs& args) +{ + fStats.Inc(kStatNAttnHdl); + Server().GetAttnInfo(args, fPrimClist); + + uint16_t rlcs = fPrimClist[fPC_rlcs].Data(); + uint16_t rlba = fPrimClist[fPC_rlba].Data(); + uint16_t rlda = fPrimClist[fPC_rlda].Data(); + uint16_t wc = fPrimClist[fPC_wc ].Data(); + uint16_t sta = fPrimClist[fPC_sta ].Data(); + uint16_t pos = fPrimClist[fPC_pos ].Data(); + + uint16_t ds = (rlcs>>kRLCS_V_DS) & kRLCS_B_DS; + uint16_t fu = (rlcs>>kRLCS_V_FUNC) & kRLCS_B_FUNC; + uint16_t bae = (rlcs>>kRLCS_V_BAE) & kRLCS_B_BAE; + + uint32_t addr = uint32_t(bae)<<16 | uint32_t(rlba); + + uint16_t sa = rlda & kRLDA_RW_B_SA; + uint16_t hs = (rlda>>kRLDA_RW_V_HS) & kRLDA_RW_B_HS; + uint16_t ca = (rlda>>kRLDA_RW_V_CA) & kRLDA_RW_B_CA; + + uint32_t nwrd = (~uint32_t(wc)&0xffff) + 1; // transfer size in words + + // all 4 units are always available, but check anyway + if (ds > NUnit()) + throw Rexception("Rw11CntlRL11::AttnHandler","Bad state: ds > NUnit()"); + + Rw11UnitRL11& unit = *fspUnit[ds]; + Rw11Cpu& cpu = Cpu(); + RlinkCommandList clist; + + uint32_t lba = unit.Chs2Lba(ca,hs,sa); + uint32_t nblk = unit.Nwrd2Nblk(nwrd); + + // check for overrun (read/write beyond track) + // if found, truncate request length + bool ovr = false; + if (fu==kFUNC_WRITE || fu==kFUNC_WCHK || fu==kFUNC_READ || fu==kFUNC_RNHC) { + ovr = sa + nblk > unit.NSector(); + if (ovr) nwrd = (unit.NSector()-sa) * (unit.BlockSize()/2); + } + + if (fTraceLevel>0) { + RlogMsg lmsg(LogFile()); + static const char* fumnemo[8] = {"no","wc","gs","se","rh","w ","r ","rn"}; + lmsg << "-I RL11 cs=" << RosPrintBvi(rlcs,8) + << " da=" << RosPrintBvi(rlda,8) + << " ad=" << RosPrintBvi(addr,8,18) + << " fu=" << fumnemo[fu&0x7] + << " ds=" << ds + << "," << RosPrintf(ca,"d",3) + << "," << hs + << "," << RosPrintf(sa,"d",2) + << " lba,nw=" << RosPrintf(lba,"d",5) + << ","; + if (nwrd==65536) lmsg << " (0)"; else lmsg << RosPrintf(nwrd,"d",4); + if (ovr) lmsg << "!"; + } + + // remember request parameters for call back and error exit handling + fRd_rlcs = rlcs; + fRd_rlda = rlda; + fRd_rlmp = wc; + fRd_sta = sta; + fRd_pos = pos; + fRd_addr = addr; + fRd_lba = lba; + fRd_nwrd = nwrd; + fRd_ovr = ovr; + fRd_fu = fu; + + // check for general abort conditions + // note: only 'data transfer' functions handled via backend + // SEEK and GSTA are done in ibdr_rl11 autonomously + + // not attached --> assumed Offline, status = load + if (! unit.Virt()) { // not attached + AddErrorExit(clist, kERR_OPI); // just signal OPI + // drive stat is LOAD anyway + Server().Exec(clist); // doit + return 0; + } + + // handle Read Header + // no data transfer, done here to keep crc calc out of firmware + if (fu == kFUNC_RHDR) { + fStats.Inc(kStatNFuncRhdr); + uint16_t buf[2] = {pos, 0}; + uint16_t crc = CalcCrc(2, buf); + + cpu.AddWibr(clist, fBase+kRLCS, + (kMPREM_CRC << kRLCS_V_MPREM) | + (kMPLOC_POS << kRLCS_V_MPLOC) | + kRLCS_ENA_MPREM | + kRLCS_ENA_MPLOC | + (kRFUNC_WMP << kRLCS_V_FUNC)); + cpu.AddWibr(clist, fBase+kRLMP, crc); + + // simulate rotation, inc sector number, wrap at end of track + uint16_t sa = (pos & kRLDA_RW_B_SA) + 1; + if (sa >= unit.NSector()) sa = 0; // wrap to begin of track + uint16_t posn = (pos & (kRLDA_RW_M_CA|kRLDA_RW_M_HS)) + sa; + AddSetPosition(clist, ds, posn); + + uint16_t cs = kRLCS_M_CRDY | // signal command done + (rlcs & kRLCS_M_BAE) | // keep BAE + (kRFUNC_WCS << kRLCS_V_FUNC); + + cpu.AddWibr(clist, fBase+kRLCS, cs); + + if (fTraceLevel>1) { + RlogMsg lmsg(LogFile()); + lmsg << "-I RL11 ok " + << " cs=" << RosPrintBvi(cs,8) + << " mp=" << RosPrintBvi(crc,8) + << " pos=" << RosPrintBvi(pos,8) + << "->" << RosPrintBvi(posn,8); + } + Server().Exec(clist); // doit + return 0; + } + + // now only data transfer functions to handle + + // check track number and proper head positioning + bool poserr = sa >= unit.NSector(); // track number valid ? + if (fu != kFUNC_RNHC) { // unless RNHC: check proper head pos + uint16_t pos_ch = pos & (kRLDA_RW_M_CA|kRLDA_RW_M_HS); // pos: cyl+hd + uint16_t rlda_ch = rlda & (kRLDA_RW_M_CA|kRLDA_RW_M_HS); // da: cyl+hd + poserr |= pos_ch != rlda_ch; + } + if (true && poserr) { + AddErrorExit(clist, kERR_HNFND); + Server().Exec(clist); // doit + return 0; + } + + // now handle the functions + + if (fu == kFUNC_WRITE) { // Write ------------------------- + fStats.Inc(kStatNFuncWrite); + if (unit.WProt()) { // write on write locked drive ? + AddSetStatus(clist, ds, sta | kSTA_M_WGE); + AddErrorExit(clist, kERR_M_DE); + } else { + fRdma.QueueDiskWrite(addr, nwrd, + Rw11Cpu::kCp_ah_m_22bit|Rw11Cpu::kCp_ah_m_ubmap, + lba, &unit); + } + + } else if (fu == kFUNC_WCHK) { // Write Check ------------------- + fStats.Inc(kStatNFuncWchk ); + fRdma.QueueDiskWriteCheck(addr, nwrd, + Rw11Cpu::kCp_ah_m_22bit|Rw11Cpu::kCp_ah_m_ubmap, + lba, &unit); + + } else if (fu == kFUNC_READ || // Read or + fu == kFUNC_RNHC) { // Read No Header Check ---------- + fStats.Inc(fu==kFUNC_READ ? kStatNFuncRead : kStatNFuncRnhc); + + fRdma.QueueDiskRead(addr, nwrd, + Rw11Cpu::kCp_ah_m_22bit|Rw11Cpu::kCp_ah_m_ubmap, + lba, &unit); + } + + if (clist.Size()) { // if handled directly + Server().Exec(clist); // doit + } + return 0; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +void Rw11CntlRL11::RdmaPreExecCB(int stat, size_t nwdone, size_t nwnext, + RlinkCommandList& clist) +{ + // if last chunk and not doing WCHK add a labo and normal exit csr update + if (stat == Rw11Rdma::kStatusBusyLast && fRd_fu != kFUNC_WCHK) { + clist.AddLabo(); + AddNormalExit(clist, nwdone+nwnext, 0); + } + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +void Rw11CntlRL11::RdmaPostExecCB(int stat, size_t ndone, + RlinkCommandList& clist, size_t ncmd) +{ + if (stat == Rw11Rdma::kStatusBusy) return; + + uint16_t rlerr = 0; + + // handle write check + if (fRd_fu == kFUNC_WCHK) { + size_t nwcok = fRdma.WriteCheck(ndone); + if (nwcok != ndone) { // if mismatch found + rlerr = kERR_WCHK; // set error + ndone = nwcok; // truncate word count + } + } + + // handle Rdma aborts + if (stat == Rw11Rdma::kStatusFailRdma && rlerr == 0) rlerr = kERR_NXM; + + // check for fused csr updates + if (clist.Size() > ncmd) { + uint8_t ccode = clist[ncmd].Command(); + uint16_t cdata = clist[ncmd].Data(); + if (ccode != RlinkCommand::kCmdLabo || (rlerr != 0 && cdata == 0)) + throw Rexception("Rw11CntlRL11::RdmaPostExecCB", + "Bad state: Labo not found or missed abort"); + if (cdata == 0) return; + } + + // finally to RL11 register update + RlinkCommandList clist1; + AddNormalExit(clist1, ndone, rlerr); + Server().Exec(clist1); + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs ???? + +void Rw11CntlRL11::LogRler(uint16_t rlerr) +{ + RlogMsg lmsg(LogFile()); + lmsg << "-E RL11 err=" << RosPrintBvi(rlerr,2,5) << " ERROR ABORT"; + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +void Rw11CntlRL11::AddSetPosition(RlinkCommandList& clist, size_t ind, + uint16_t pos) +{ + Rw11Cpu& cpu = Cpu(); + cpu.AddWibr(clist, fBase+kRLCS, + ((kMPREM_POS+ind)<1) { + RlogMsg lmsg(LogFile()); + lmsg << "-I RL11 err" + << " cs=" << RosPrintBvi(cs,8) + << " err=" << RosPrintBvi(rlerr,2,5) + << " pos=" << RosPrintBvi(fRd_pos,8); + } + + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +void Rw11CntlRL11::AddNormalExit(RlinkCommandList& clist, size_t ndone, + uint16_t rlerr) +{ + Rw11Cpu& cpu = Cpu(); + uint16_t ds = (fRd_rlcs>>kRLCS_V_DS) & kRLCS_B_DS; + Rw11UnitRL11& unit = *fspUnit[ds]; + + size_t nblk = unit.Nwrd2Nblk(ndone); + + uint32_t addr = fRd_addr + 2*ndone; + + uint16_t ba = addr & 0177776; // get lower 16 bits + uint16_t bae = (addr>>16) & 03; // get upper 2 bits + + uint16_t da = fRd_rlda+uint16_t(nblk); + + uint16_t rlmp = fRd_rlmp + uint16_t(ndone); + + if (fRd_ovr && rlerr == 0) rlerr = kERR_HNFND; + + cpu.AddWibr(clist, fBase+kRLBA, ba); + cpu.AddWibr(clist, fBase+kRLDA, da); + cpu.AddWibr(clist, fBase+kRLCS, + (kMPREM_MP << kRLCS_V_MPREM) | + (kMPLOC_MP << kRLCS_V_MPLOC) | + kRLCS_ENA_MPREM | + kRLCS_ENA_MPLOC | + (kRFUNC_WMP << kRLCS_V_FUNC)); + cpu.AddWibr(clist, fBase+kRLMP, rlmp); + + // set drive position to one sector past the last the read sector + // Note: take sa from rlda, and ca+hs from fRd_pos (controller context!) + // in case of errors this probably the best solution + uint16_t sa = (fRd_rlda & kRLDA_RW_B_SA) + uint16_t(nblk); + if (sa >= unit.NSector()) sa = 0; // wrap to begin of track + uint16_t posn = (fRd_pos & (kRLDA_RW_M_CA|kRLDA_RW_M_HS)) + sa; + AddSetPosition(clist, ds, posn); + + uint16_t cs = kRLCS_M_CRDY | + (bae << kRLCS_V_BAE) | + (kRFUNC_WCS << kRLCS_V_FUNC); + if (rlerr) cs |= (rlerr << kRLCS_V_E); + cpu.AddWibr(clist, fBase+kRLCS, cs); + + if (fTraceLevel>1) { + RlogMsg lmsg(LogFile()); + lmsg << "-I RL11 " << (rlerr==0 ? " ok" : "err") + << " cs=" << RosPrintBvi(cs,8) + << " ba=" << RosPrintBvi(ba,8) + << " da=" << RosPrintBvi(da,8) + << " mp=" << RosPrintBvi(rlmp,8); + if (rlerr) lmsg << " err=" << RosPrintBvi(rlerr,2,5); + lmsg << " pos=" << RosPrintBvi(fRd_pos,8) + << "->" << RosPrintBvi(posn,8); + } + + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs +// Note: +// CalcCrc() is adopted from the simh project and Copyright Robert M Supnik + +uint16_t Rw11CntlRL11::CalcCrc(size_t size, const uint16_t* data) +{ + uint32_t crc=0; + + for (size_t i = 0; i < size; i++) { + uint32_t d = *data++; + /* cribbed from KG11-A */ + for (size_t j = 0; j < 16; j++) { + crc = (crc & ~01) | ((crc & 01) ^ (d & 01)); + crc = (crc & 01) ? (crc >> 1) ^ 0120001 : crc >> 1; + d >>= 1; + } + } + return crc; +} + + +} // end namespace Retro diff --git a/tools/src/librw11/Rw11CntlRL11.hpp b/tools/src/librw11/Rw11CntlRL11.hpp new file mode 100644 index 00000000..82c343dd --- /dev/null +++ b/tools/src/librw11/Rw11CntlRL11.hpp @@ -0,0 +1,230 @@ +// $Id: Rw11CntlRL11.hpp 653 2015-03-01 12:53:01Z mueller $ +// +// Copyright 2014-2015 by Walter F.J. Mueller +// +// This program is free software; you may redistribute and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation, either version 2, or at your option any later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for complete details. +// +// Revision History: +// Date Rev Version Comment +// 2015-03-01 653 1.0 Initial version +// 2014-06-08 561 0.1 First draft +// --------------------------------------------------------------------------- + + +/*! + \file + \version $Id: Rw11CntlRL11.hpp 653 2015-03-01 12:53:01Z mueller $ + \brief Declaration of class Rw11CntlRL11. +*/ + +#ifndef included_Retro_Rw11CntlRL11 +#define included_Retro_Rw11CntlRL11 1 + +#include "Rw11CntlBase.hpp" +#include "Rw11UnitRL11.hpp" +#include "Rw11RdmaDisk.hpp" + +namespace Retro { + + class Rw11CntlRL11 : public Rw11CntlBase { + public: + + Rw11CntlRL11(); + ~Rw11CntlRL11(); + + void Config(const std::string& name, uint16_t base, int lam); + + virtual void Start(); + + virtual bool BootCode(size_t unit, std::vector& code, + uint16_t& aload, uint16_t& astart); + + virtual void UnitSetup(size_t ind); + + void SetChunkSize(size_t chunk); + size_t ChunkSize() const; + + const Rstats& RdmaStats() const; + + virtual void Dump(std::ostream& os, int ind=0, const char* text=0) const; + + // some constants (also defined in cpp) + static const uint16_t kIbaddr = 0174400; //!< RL11 default address + static const int kLam = 5; //!< RL11 default lam + + static const uint16_t kRLCS = 000; //!< RLCS register address offset + static const uint16_t kRLBA = 002; //!< RLBA register address offset + static const uint16_t kRLDA = 004; //!< RLDA register address offset + static const uint16_t kRLMP = 006; //!< RLMP register address offset + + static const uint16_t kProbeOff = kRLCS; //!< probe address offset (rlcs) + static const bool kProbeInt = true; //!< probe int active + static const bool kProbeRem = true; //!< probr rem active + + static const uint16_t kRLCS_M_ERR = kWBit15; + static const uint16_t kRLCS_M_DE = kWBit14; + static const uint16_t kRLCS_V_E = 10; + static const uint16_t kRLCS_B_E = 0017; + static const uint16_t kRLCS_V_DS = 8; + static const uint16_t kRLCS_B_DS = 0003; + static const uint16_t kRLCS_M_CRDY = kWBit07; + static const uint16_t kRLCS_M_IE = kWBit06; + static const uint16_t kRLCS_M_BAE = 000060; + static const uint16_t kRLCS_V_BAE = 4; + static const uint16_t kRLCS_B_BAE = 0003; + static const uint16_t kRLCS_V_FUNC = 1; + static const uint16_t kRLCS_B_FUNC = 0007; + static const uint16_t kRLCS_M_DRDY = kWBit00; + + static const uint16_t kFUNC_NOOP = 0; // done in ibdr + static const uint16_t kFUNC_WCHK = 1; + static const uint16_t kFUNC_GS = 2; // done in ibdr + static const uint16_t kFUNC_SEEK = 3; // done in ibdr + static const uint16_t kFUNC_RHDR = 4; + static const uint16_t kFUNC_WRITE = 5; + static const uint16_t kFUNC_READ = 6; + static const uint16_t kFUNC_RNHC = 7; + + static const uint16_t kERR_M_DE = kWBit04; // drive error flag + static const uint16_t kERR_OPI = 1; // OPI Operation Incomplete + static const uint16_t kERR_WCHK = 2; // Read Data CRC or Write Check + static const uint16_t kERR_HCRC = 3; // Header CRC + static const uint16_t kERR_DLATE = 4; // Data Late + static const uint16_t kERR_HNFND = 5; // Header not found + static const uint16_t kERR_NXM = 8; // Non-Existant Memory + + // rem usage of rlcs + static const uint16_t kRLCS_V_MPREM = 11; + static const uint16_t kRLCS_B_MPREM = 0037; + static const uint16_t kRLCS_V_MPLOC = 8; + static const uint16_t kRLCS_B_MPLOC = 0007; + static const uint16_t kRLCS_ENA_MPREM = kWBit05; + static const uint16_t kRLCS_ENA_MPLOC = kWBit04; + + static const uint16_t kRFUNC_WCS = 1; + static const uint16_t kRFUNC_WMP = 2; + + static const uint16_t kMPREM_M_MAP = kWBit04; + static const uint16_t kMPREM_M_SEQ = kWBit03; + static const uint16_t kMPREM_S_MP = 0000; // MP+STA+POS sequence + static const uint16_t kMPREM_S_STA = 0001; + static const uint16_t kMPREM_S_POS = 0002; + + static const uint16_t kMPREM_MP = 0003; // mem: mp + static const uint16_t kMPREM_CRC = 0004; // mem: crc + static const uint16_t kMPREM_STA = 0010; // mem: sta array (4 units) + static const uint16_t kMPREM_POS = 0014; // mem: pos array (4 units) + + static const uint16_t kMPREM_SEQ_MPSTAPOS = kMPREM_M_MAP| + kMPREM_M_SEQ|kMPREM_S_MP; + + static const uint16_t kMPLOC_MP = 0000; // 000: return imem(mp) + static const uint16_t kMPLOC_STA = 0001; // 001: return sta(ds) + static const uint16_t kMPLOC_POS = 0002; // 010: return pos(ds) -> ZERO + static const uint16_t kMPLOC_ZERO = 0003; // 011: return 0 -> CRC + static const uint16_t kMPLOC_CRC = 0004; // 100: return imem(crc) + + static const uint16_t kRLDA_SE_M_DF = 0177600; + static const uint16_t kRLDA_SE_V_DF = 7; + static const uint16_t kRLDA_SE_B_DF = 0777; + static const uint16_t kRLDA_SE_M_HS = kWBit04; + static const uint16_t kRLDA_SE_M_DIR = kWBit02; + static const uint16_t kRLDA_SE_X_MSK = 0000153; + static const uint16_t kRLDA_SE_X_VAL = 0000001; + + static const uint16_t kRLDA_RW_M_CA = 0177600; + static const uint16_t kRLDA_RW_V_CA = 7; + static const uint16_t kRLDA_RW_B_CA = 0777; + static const uint16_t kRLDA_RW_M_HS = kWBit06; + static const uint16_t kRLDA_RW_V_HS = 6; + static const uint16_t kRLDA_RW_B_HS = 001; + static const uint16_t kRLDA_RW_B_SA = 077; + + static const uint16_t kRLDA_GS_M_RST = kWBit03; + static const uint16_t kRLDA_GS_X_MSK = 0000367; + static const uint16_t kRLDA_GS_X_VAL = 0000003; + + static const uint16_t kSTA_M_WDE = kWBit15; // Write data error - 0! + static const uint16_t kSTA_M_CHE = kWBit14; // Current head error - 0! + static const uint16_t kSTA_M_WL = kWBit13; // Write lock + static const uint16_t kSTA_M_STO = kWBit12; // Seek time out + static const uint16_t kSTA_M_SPE = kWBit11; // Spin error + static const uint16_t kSTA_M_WGE = kWBit10; // Write gate error + static const uint16_t kSTA_M_VCE = kWBit09; // Volume check + static const uint16_t kSTA_M_DSE = kWBit08; // Drive select error + static const uint16_t kSTA_M_DT = kWBit07; // Drive type 1=RL02 + static const uint16_t kSTA_M_HS = kWBit06; // Head select + static const uint16_t kSTA_M_CO = kWBit05; // Cover open + static const uint16_t kSTA_M_HO = kWBit04; // Heads out + static const uint16_t kSTA_M_BH = kWBit03; // Brush home - 1! + static const uint16_t kSTA_B_ST = 0007; // Drive state + + static const uint16_t kST_LOAD = 0; // Load(ing) cartidge - used + static const uint16_t kST_SPIN = 1; // Spin(ing) up - !unused! + static const uint16_t kST_BRUSH = 2; // Brush(ing) cycle - !unused! + static const uint16_t kST_HLOAD = 3; // Load(ing) heads - !unused! + static const uint16_t kST_SEEK = 4; // Seek(ing) - ?maybe? + static const uint16_t kST_LOCK = 5; // Lock(ed) on - used + static const uint16_t kST_UNL = 6; // Unload(ing) heads - !unused! + static const uint16_t kST_DOWN = 7; // Spin(ing) down - !unused! + + // statistics counter indices + enum stats { + kStatNFuncWchk = Rw11Cntl::kDimStat, + kStatNFuncRhdr, + kStatNFuncWrite, + kStatNFuncRead, + kStatNFuncRnhc, + kDimStat + }; + + protected: + int AttnHandler(RlinkServer::AttnArgs& args); + void RdmaPreExecCB(int stat, size_t nwdone, size_t nwnext, + RlinkCommandList& clist); + void RdmaPostExecCB(int stat, size_t ndone, + RlinkCommandList& clist, size_t ncmd); + void LogRler(uint16_t rlerr); + void AddSetStatus(RlinkCommandList& clist, size_t ind, + uint16_t sta); + void AddSetPosition(RlinkCommandList& clist, size_t ind, + uint16_t pos); + void AddErrorExit(RlinkCommandList& clist, uint16_t rlerr); + void AddNormalExit(RlinkCommandList& clist, size_t ndone, + uint16_t rlerr=0); + uint16_t CalcCrc(size_t size, const uint16_t* data); + + protected: + size_t fPC_rlcs; //!< PrimClist: rlcs index + size_t fPC_rlba; //!< PrimClist: rlba index + size_t fPC_rlda; //!< PrimClist: rlda index + size_t fPC_imp; //!< PrimClist: imp index + size_t fPC_wc; //!< PrimClist: wc index + size_t fPC_sta; //!< PrimClist: sta index + size_t fPC_pos; //!< PrimClist: pos index + + uint16_t fRd_rlcs; //!< Rdma: request rlcs + uint16_t fRd_rlda; //!< Rdma: request rlda + uint16_t fRd_rlmp; //!< Rdma: request rlmp (~wc) + uint16_t fRd_sta; //!< Rdma: initial drive status + uint16_t fRd_pos; //!< Rdma: initial drive position + uint32_t fRd_addr; //!< Rdma: current addr + uint32_t fRd_lba; //!< Rdma: current lba + uint32_t fRd_nwrd; //!< Rdma: current nwrd + uint16_t fRd_fu; //!< Rdma: request fu code + bool fRd_ovr; //!< Rdma: overrun condition found + Rw11RdmaDisk fRdma; //!< Rdma controller + }; + +} // end namespace Retro + +#include "Rw11CntlRL11.ipp" + +#endif diff --git a/tools/src/librw11/Rw11CntlRL11.ipp b/tools/src/librw11/Rw11CntlRL11.ipp new file mode 100644 index 00000000..6dcdff2a --- /dev/null +++ b/tools/src/librw11/Rw11CntlRL11.ipp @@ -0,0 +1,55 @@ +// $Id: Rw11CntlRL11.ipp 632 2015-01-11 12:30:03Z mueller $ +// +// Copyright 2015- by Walter F.J. Mueller +// +// This program is free software; you may redistribute and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation, either version 2, or at your option any later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for complete details. +// +// Revision History: +// Date Rev Version Comment +// 2015-01-10 632 1.0 Initial version +// --------------------------------------------------------------------------- + +/*! + \file + \version $Id: Rw11CntlRL11.ipp 632 2015-01-11 12:30:03Z mueller $ + \brief Implemenation (inline) of Rw11CntlRL11. +*/ + + +// all method definitions in namespace Retro +namespace Retro { + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline void Rw11CntlRL11::SetChunkSize(size_t chunk) +{ + fRdma.SetChunkSize(chunk); + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline size_t Rw11CntlRL11::ChunkSize() const +{ + return fRdma.ChunkSize(); +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline const Rstats& Rw11CntlRL11::RdmaStats() const +{ + return fRdma.Stats(); +} + + +} // end namespace Retro diff --git a/tools/src/librw11/Rw11Cpu.cpp b/tools/src/librw11/Rw11Cpu.cpp index 9c3e8f88..fce9ab2f 100644 --- a/tools/src/librw11/Rw11Cpu.cpp +++ b/tools/src/librw11/Rw11Cpu.cpp @@ -1,4 +1,4 @@ -// $Id: Rw11Cpu.cpp 626 2015-01-03 14:41:37Z mueller $ +// $Id: Rw11Cpu.cpp 632 2015-01-11 12:30:03Z mueller $ // // Copyright 2013-2014 by Walter F.J. Mueller // @@ -23,7 +23,7 @@ /*! \file - \version $Id: Rw11Cpu.cpp 626 2015-01-03 14:41:37Z mueller $ + \version $Id: Rw11Cpu.cpp 632 2015-01-11 12:30:03Z mueller $ \brief Implemenation of Rw11Cpu. */ #include @@ -109,7 +109,7 @@ const uint16_t Rw11Cpu::kCp_membe_m_be; //! Constructor Rw11Cpu::Rw11Cpu(const std::string& type) - : fpW11(0), + : fpW11(nullptr), fType(type), fIndex(0), fBase(0), @@ -436,7 +436,6 @@ bool Rw11Cpu::ProbeCntl(Rw11Probe& dsc) } Server().Exec(clist); - // FIXME_code: handle errors if (dsc.fProbeInt) { dsc.fFoundInt = (clist[iib].Status() & @@ -751,8 +750,8 @@ void Rw11Cpu::W11AttnHandler() { RlinkCommandList clist; clist.AddRreg(fBase+kCp_addr_stat); - if (Server().Exec(clist)) - SetCpuGoDown(clist[0].Data()); + Server().Exec(clist); + SetCpuGoDown(clist[0].Data()); return; } diff --git a/tools/src/librw11/Rw11Rdma.cpp b/tools/src/librw11/Rw11Rdma.cpp index 07220ef1..5dfc8234 100644 --- a/tools/src/librw11/Rw11Rdma.cpp +++ b/tools/src/librw11/Rw11Rdma.cpp @@ -1,4 +1,4 @@ -// $Id: Rw11Rdma.cpp 627 2015-01-04 11:36:37Z mueller $ +// $Id: Rw11Rdma.cpp 648 2015-02-20 20:16:21Z mueller $ // // Copyright 2015- by Walter F.J. Mueller // @@ -13,12 +13,13 @@ // // Revision History: // Date Rev Version Comment +// 2015-02-17 647 1.1 PreExecCB with nwdone and nwnext // 2015-01-04 627 1.0 Initial version // --------------------------------------------------------------------------- /*! \file - \version $Id: Rw11Rdma.cpp 627 2015-01-04 11:36:37Z mueller $ + \version $Id: Rw11Rdma.cpp 648 2015-02-20 20:16:21Z mueller $ \brief Implemenation of Rw11Rdma. */ @@ -168,33 +169,32 @@ int Rw11Rdma::RdmaHandler() PreRdmaHook(); } - size_t nword = min(fNWordRest, fNWordMax); + size_t nwnext = min(fNWordRest, fNWordMax); if (fIsWMem) { fStats.Inc(kStatNRdmaWMem); - Cpu().AddWMem(clist, fAddr, fpBlock, nword, fMode, true); + Cpu().AddWMem(clist, fAddr, fpBlock, nwnext, fMode, true); } else { fStats.Inc(kStatNRdmaRMem); - Cpu().AddRMem(clist, fAddr, fpBlock, nword, fMode, true); + Cpu().AddRMem(clist, fAddr, fpBlock, nwnext, fMode, true); } size_t ncmd = clist.Size(); - if (nword == fNWordRest) fStatus = kStatusBusyLast; + if (nwnext == fNWordRest) fStatus = kStatusBusyLast; - fPreExecCB(fStatus, nword, clist); + fPreExecCB(fStatus, fNWordDone, nwnext, clist); if (clist.Size() != ncmd) fStats.Inc(kStatNExtClist); - // FIXME_code: check return code Server().Exec(clist); - size_t nworddone = clist[ncmd-1].BlockDone(); + size_t nwdone = clist[ncmd-1].BlockDone(); - fAddr += 2*nworddone; - fNWordRest -= nworddone; - fNWordDone += nworddone; - fpBlock += nworddone; + fAddr += 2*nwdone; + fNWordRest -= nwdone; + fNWordDone += nwdone; + fpBlock += nwdone; bool islast = false; - if (nword != nworddone) { + if (nwnext != nwdone) { fStats.Inc(kStatNFailRdma); fStatus = kStatusFailRdma; islast = true; @@ -227,7 +227,7 @@ void Rw11Rdma::PreRdmaHook() //------------------------------------------+----------------------------------- //! FIXME_docs -void Rw11Rdma::PostRdmaHook(size_t ndone) +void Rw11Rdma::PostRdmaHook(size_t nwdone) { return; } diff --git a/tools/src/librw11/Rw11Rdma.hpp b/tools/src/librw11/Rw11Rdma.hpp index 791104ee..2417ec05 100644 --- a/tools/src/librw11/Rw11Rdma.hpp +++ b/tools/src/librw11/Rw11Rdma.hpp @@ -1,4 +1,4 @@ -// $Id: Rw11Rdma.hpp 627 2015-01-04 11:36:37Z mueller $ +// $Id: Rw11Rdma.hpp 648 2015-02-20 20:16:21Z mueller $ // // Copyright 2015- by Walter F.J. Mueller // @@ -13,13 +13,14 @@ // // Revision History: // Date Rev Version Comment +// 2015-02-17 647 1.1 PreExecCB with nwdone and nwnext // 2015-01-04 627 1.0 Initial version // --------------------------------------------------------------------------- /*! \file - \version $Id: Rw11Rdma.hpp 627 2015-01-04 11:36:37Z mueller $ + \version $Id: Rw11Rdma.hpp 648 2015-02-20 20:16:21Z mueller $ \brief Declaration of class Rw11Rdma. */ @@ -40,9 +41,10 @@ namespace Retro { class Rw11Rdma : public Rbits, private boost::noncopyable { public: - typedef boost::function precb_t; - typedef boost::function postcb_t; + typedef boost::function precb_t; + typedef boost::function postcb_t; Rw11Rdma(Rw11Cntl* pcntl, const precb_t& precb, const postcb_t& postcb); @@ -92,7 +94,7 @@ namespace Retro { size_t size, uint16_t mode); int RdmaHandler(); virtual void PreRdmaHook(); - virtual void PostRdmaHook(size_t ndone); + virtual void PostRdmaHook(size_t nwdone); protected: Rw11Cntl* fpCntlBase; //!< plain Rw11Cntl ptr diff --git a/tools/src/librw11/Rw11RdmaDisk.cpp b/tools/src/librw11/Rw11RdmaDisk.cpp index c72d2f48..a066415b 100644 --- a/tools/src/librw11/Rw11RdmaDisk.cpp +++ b/tools/src/librw11/Rw11RdmaDisk.cpp @@ -1,4 +1,4 @@ -// $Id: Rw11RdmaDisk.cpp 628 2015-01-04 16:22:09Z mueller $ +// $Id: Rw11RdmaDisk.cpp 648 2015-02-20 20:16:21Z mueller $ // // Copyright 2015- by Walter F.J. Mueller // @@ -18,7 +18,7 @@ /*! \file - \version $Id: Rw11RdmaDisk.cpp 628 2015-01-04 16:22:09Z mueller $ + \version $Id: Rw11RdmaDisk.cpp 648 2015-02-20 20:16:21Z mueller $ \brief Implemenation of Rw11RdmaDisk. */ @@ -97,12 +97,12 @@ void Rw11RdmaDisk::QueueDiskWriteCheck(uint32_t addr, size_t size, //------------------------------------------+----------------------------------- //! FIXME_docs -size_t Rw11RdmaDisk::WriteCheck(size_t ndone) +size_t Rw11RdmaDisk::WriteCheck(size_t nwdone) { - if (ndone == 0) return 0; + if (nwdone == 0) return 0; size_t bszwrd = fpUnit->BlockSize()/2; // block size in words - size_t nblk = (ndone+bszwrd-1)/bszwrd; + size_t nblk = (nwdone+bszwrd-1)/bszwrd; size_t dsize = nblk*bszwrd; std::vector dbuf(dsize); @@ -114,14 +114,14 @@ size_t Rw11RdmaDisk::WriteCheck(size_t ndone) uint16_t* pdsk = dbuf.data(); uint16_t* pmem = fBuf.data(); - for (size_t i=0; iBlockSize()/2; // block size in words - size_t nblock = (ndone+bszwrd-1)/bszwrd; - size_t npad = nblock*bszwrd - ndone; + size_t nblock = (nwdone+bszwrd-1)/bszwrd; + size_t npad = nblock*bszwrd - nwdone; // if an incomplete block was read, pad it with hex dead if (npad) { fStats.Inc(kStatNWritePadded); - uint16_t* p = fBuf.data()+ndone; + uint16_t* p = fBuf.data()+nwdone; for (size_t i=0; i // @@ -19,7 +19,7 @@ /*! \file - \version $Id: Rw11RdmaDisk.hpp 628 2015-01-04 16:22:09Z mueller $ + \version $Id: Rw11RdmaDisk.hpp 648 2015-02-20 20:16:21Z mueller $ \brief Declaration of class Rw11RdmaDisk. */ @@ -47,7 +47,7 @@ namespace Retro { uint16_t mode, uint32_t lba, Rw11UnitDisk* punit); - size_t WriteCheck(size_t ndone); + size_t WriteCheck(size_t nwdone); virtual void Dump(std::ostream& os, int ind=0, const char* text=0) const; @@ -69,7 +69,7 @@ namespace Retro { void SetupDisk(size_t size, uint32_t lba, Rw11UnitDisk* punit, Rw11RdmaDisk::func func); virtual void PreRdmaHook(); - virtual void PostRdmaHook(size_t ndone); + virtual void PostRdmaHook(size_t nwdone); protected: std::vector fBuf; //!< data buffer diff --git a/tools/src/librw11/Rw11UnitDisk.hpp b/tools/src/librw11/Rw11UnitDisk.hpp index 4372f5b9..5ca3d487 100644 --- a/tools/src/librw11/Rw11UnitDisk.hpp +++ b/tools/src/librw11/Rw11UnitDisk.hpp @@ -1,6 +1,6 @@ -// $Id: Rw11UnitDisk.hpp 509 2013-04-21 20:46:20Z mueller $ +// $Id: Rw11UnitDisk.hpp 647 2015-02-17 22:35:36Z mueller $ // -// Copyright 2013- by Walter F.J. Mueller +// Copyright 2013-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-02-18 647 1.0.1 add Nwrd2Nblk() // 2013-04-19 507 1.0 Initial version // 2013-02-19 490 0.1 First draft // --------------------------------------------------------------------------- @@ -20,7 +21,7 @@ /*! \file - \version $Id: Rw11UnitDisk.hpp 509 2013-04-21 20:46:20Z mueller $ + \version $Id: Rw11UnitDisk.hpp 647 2015-02-17 22:35:36Z mueller $ \brief Declaration of class Rw11UnitDisk. */ @@ -50,6 +51,7 @@ namespace Retro { uint32_t Chs2Lba(uint16_t cy, uint16_t hd, uint16_t se); void Lba2Chs(uint32_t lba, uint16_t& cy, uint16_t& hd, uint16_t& se); + uint32_t Nwrd2Nblk(uint32_t nwrd); void SetWProt(bool wprot); bool WProt() const; diff --git a/tools/src/librw11/Rw11UnitDisk.ipp b/tools/src/librw11/Rw11UnitDisk.ipp index 91230a67..0743ce8c 100644 --- a/tools/src/librw11/Rw11UnitDisk.ipp +++ b/tools/src/librw11/Rw11UnitDisk.ipp @@ -1,6 +1,6 @@ -// $Id: Rw11UnitDisk.ipp 509 2013-04-21 20:46:20Z mueller $ +// $Id: Rw11UnitDisk.ipp 647 2015-02-17 22:35:36Z mueller $ // -// Copyright 2013- by Walter F.J. Mueller +// Copyright 2013-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,13 +13,14 @@ // // Revision History: // Date Rev Version Comment +// 2015-02-18 647 1.0.1 add Nwrd2Nblk() // 2013-04-19 507 1.0 Initial version // 2013-02-19 490 0.1 First draft // --------------------------------------------------------------------------- /*! \file - \version $Id: Rw11UnitDisk.ipp 509 2013-04-21 20:46:20Z mueller $ + \version $Id: Rw11UnitDisk.ipp 647 2015-02-17 22:35:36Z mueller $ \brief Implemenation (inline) of Rw11UnitDisk. */ @@ -94,6 +95,13 @@ inline void Rw11UnitDisk::Lba2Chs(uint32_t lba, uint16_t& cy, uint16_t& hd, return; } +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline uint32_t Rw11UnitDisk::Nwrd2Nblk(uint32_t nwrd) +{ + return (2*nwrd+BlockSize()-1) / BlockSize(); +} //------------------------------------------+----------------------------------- //! FIXME_docs diff --git a/tools/src/librw11/Rw11UnitRL11.cpp b/tools/src/librw11/Rw11UnitRL11.cpp new file mode 100644 index 00000000..12a28d43 --- /dev/null +++ b/tools/src/librw11/Rw11UnitRL11.cpp @@ -0,0 +1,102 @@ +// $Id: Rw11UnitRL11.cpp 653 2015-03-01 12:53:01Z mueller $ +// +// Copyright 2014- by Walter F.J. Mueller +// +// This program is free software; you may redistribute and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation, either version 2, or at your option any later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for complete details. +// +// Revision History: +// Date Rev Version Comment +// 2014-06-08 561 1.0 Initial version +// --------------------------------------------------------------------------- + +/*! + \file + \version $Id: Rw11UnitRL11.cpp 653 2015-03-01 12:53:01Z mueller $ + \brief Implemenation of Rw11UnitRL11. +*/ + +#include "boost/bind.hpp" + +#include "librtools/Rexception.hpp" +#include "librtools/RosFill.hpp" +#include "Rw11CntlRL11.hpp" + +#include "Rw11UnitRL11.hpp" + +using namespace std; + +/*! + \class Retro::Rw11UnitRL11 + \brief FIXME_docs +*/ + +// all method definitions in namespace Retro +namespace Retro { + +//------------------------------------------+----------------------------------- +//! Constructor + +Rw11UnitRL11::Rw11UnitRL11(Rw11CntlRL11* pcntl, size_t index) + : Rw11UnitDiskBase(pcntl, index), + fRlsta(0), + fRlpos(0) +{ + // setup disk geometry: rl01 and rl02 supported, default rl02 + fType = "rl02"; + fNCyl = 512; + fNHead = 2; + fNSect = 40; + fBlksize = 256; + fNBlock = fNCyl*fNHead*fNSect; +} + +//------------------------------------------+----------------------------------- +//! Destructor + +Rw11UnitRL11::~Rw11UnitRL11() +{} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +void Rw11UnitRL11::SetType(const std::string& type) +{ + if (Virt()) { + throw Rexception("Rw11UnitRL11::SetType", + string("Bad state: file attached")); + } + + if (type == "rl01") { + fNCyl = 256; + } else if (type == "rl02") { + fNCyl = 512; + } else { + throw Rexception("Rw11UnitRL11::SetType", + string("Bad args: only types 'rl01' and 'rl02' supported")); + } + fNBlock = fNCyl*fNHead*fNSect; + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +void Rw11UnitRL11::Dump(std::ostream& os, int ind, const char* text) const +{ + RosFill bl(ind); + os << bl << (text?text:"--") << "Rw11UnitRL11 @ " << this << endl; + os << bl << " fRlsta: " << RosPrintf(fRlsta,"o",6) << endl; + os << bl << " fRlpos: " << RosPrintf(fRlpos,"o",6) << endl; + + Rw11UnitDiskBase::Dump(os, ind, " ^"); + return; +} + +} // end namespace Retro diff --git a/tools/src/librw11/Rw11UnitRL11.hpp b/tools/src/librw11/Rw11UnitRL11.hpp new file mode 100644 index 00000000..d2becc17 --- /dev/null +++ b/tools/src/librw11/Rw11UnitRL11.hpp @@ -0,0 +1,58 @@ +// $Id: Rw11UnitRL11.hpp 653 2015-03-01 12:53:01Z mueller $ +// +// Copyright 2014- by Walter F.J. Mueller +// +// This program is free software; you may redistribute and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation, either version 2, or at your option any later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for complete details. +// +// Revision History: +// Date Rev Version Comment +// 2014-06-08 561 1.0 Initial version +// --------------------------------------------------------------------------- + + +/*! + \file + \version $Id: Rw11UnitRL11.hpp 653 2015-03-01 12:53:01Z mueller $ + \brief Declaration of class Rw11UnitRL11. +*/ + +#ifndef included_Retro_Rw11UnitRL11 +#define included_Retro_Rw11UnitRL11 1 + +#include "Rw11UnitDiskBase.hpp" + +namespace Retro { + + class Rw11CntlRL11; // forw decl to avoid circular incl + + class Rw11UnitRL11 : public Rw11UnitDiskBase { + public: + Rw11UnitRL11(Rw11CntlRL11* pcntl, size_t index); + ~Rw11UnitRL11(); + + virtual void SetType(const std::string& type); + + void SetRlsta(uint16_t rlsta); + void SetRlpos(uint16_t rlpos); + uint16_t Rlsta() const; + uint16_t Rlpos() const; + + virtual void Dump(std::ostream& os, int ind=0, const char* text=0) const; + + protected: + uint16_t fRlsta; + uint16_t fRlpos; + }; + +} // end namespace Retro + +#include "Rw11UnitRL11.ipp" + +#endif diff --git a/tools/src/librw11/Rw11UnitRL11.ipp b/tools/src/librw11/Rw11UnitRL11.ipp new file mode 100644 index 00000000..9e0b08a9 --- /dev/null +++ b/tools/src/librw11/Rw11UnitRL11.ipp @@ -0,0 +1,69 @@ +// $Id: Rw11UnitRL11.ipp 653 2015-03-01 12:53:01Z mueller $ +// +// Copyright 2014- by Walter F.J. Mueller +// +// This program is free software; you may redistribute and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation, either version 2, or at your option any later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for complete details. +// +// Revision History: +// Date Rev Version Comment +// 2014-06-08 561 1.0 Initial version +// --------------------------------------------------------------------------- + +/*! + \file + \version $Id: Rw11UnitRL11.ipp 653 2015-03-01 12:53:01Z mueller $ + \brief Implemenation (inline) of Rw11UnitRL11. +*/ + +#include "Rw11UnitRL11.hpp" + +/*! + \class Retro::Rw11UnitRL11 + \brief FIXME_docs +*/ + +// all method definitions in namespace Retro +namespace Retro { + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline void Rw11UnitRL11::SetRlsta(uint16_t rlsta) +{ + fRlsta = rlsta; + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline void Rw11UnitRL11::SetRlpos(uint16_t rlpos) +{ + fRlpos = rlpos; + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline uint16_t Rw11UnitRL11::Rlsta() const +{ + return fRlsta; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline uint16_t Rw11UnitRL11::Rlpos() const +{ + return fRlpos; +} + +} // end namespace Retro diff --git a/tools/src/librw11/Rw11VirtTermPty.cpp b/tools/src/librw11/Rw11VirtTermPty.cpp index d9f84462..e43e7fa6 100644 --- a/tools/src/librw11/Rw11VirtTermPty.cpp +++ b/tools/src/librw11/Rw11VirtTermPty.cpp @@ -1,4 +1,4 @@ -// $Id: Rw11VirtTermPty.cpp 504 2013-04-13 15:37:24Z mueller $ +// $Id: Rw11VirtTermPty.cpp 632 2015-01-11 12:30:03Z mueller $ // // Copyright 2013- by Walter F.J. Mueller // @@ -19,7 +19,7 @@ /*! \file - \version $Id: Rw11VirtTermPty.cpp 504 2013-04-13 15:37:24Z mueller $ + \version $Id: Rw11VirtTermPty.cpp 632 2015-01-11 12:30:03Z mueller $ \brief Implemenation of Rw11VirtTermPty. */ #define _XOPEN_SOURCE 600 @@ -89,7 +89,7 @@ bool Rw11VirtTermPty::Open(const std::string& url, RerrMsg& emsg) } char* pname = ptsname(fd); - if (pname == 0) { + if (pname == nullptr) { emsg.InitErrno("Rw11VirtTermPty::Open", "ptsname() failed: ", errno); close(fd); return false; diff --git a/tools/src/librw11/Rw11VirtTermTcp.cpp b/tools/src/librw11/Rw11VirtTermTcp.cpp index 9ec3ebd2..1f5e8eac 100644 --- a/tools/src/librw11/Rw11VirtTermTcp.cpp +++ b/tools/src/librw11/Rw11VirtTermTcp.cpp @@ -1,4 +1,4 @@ -// $Id: Rw11VirtTermTcp.cpp 584 2014-08-22 19:38:12Z mueller $ +// $Id: Rw11VirtTermTcp.cpp 632 2015-01-11 12:30:03Z mueller $ // // Copyright 2013-2014 by Walter F.J. Mueller // @@ -23,7 +23,7 @@ /*! \file - \version $Id: Rw11VirtTermTcp.cpp 584 2014-08-22 19:38:12Z mueller $ + \version $Id: Rw11VirtTermTcp.cpp 632 2015-01-11 12:30:03Z mueller $ \brief Implemenation of Rw11VirtTermTcp. */ @@ -131,7 +131,7 @@ bool Rw11VirtTermTcp::Open(const std::string& url, RerrMsg& emsg) if (!Rtools::String2Long(port, portno, emsg)) return false; protoent* pe = getprotobyname("tcp"); - if (pe == 0) { + if (pe == nullptr) { emsg.Init("Rw11VirtTermTcp::Open","getprotobyname(\"tcp\") failed"); return false; } diff --git a/tools/src/librwxxtpp/Makefile b/tools/src/librwxxtpp/Makefile index 1484b3a8..7911ac55 100644 --- a/tools/src/librwxxtpp/Makefile +++ b/tools/src/librwxxtpp/Makefile @@ -36,6 +36,7 @@ OBJ_all += RtclRw11CntlDL11.o RtclRw11UnitDL11.o OBJ_all += RtclRw11CntlLP11.o RtclRw11UnitLP11.o OBJ_all += RtclRw11CntlPC11.o RtclRw11UnitPC11.o OBJ_all += RtclRw11CntlRK11.o RtclRw11UnitRK11.o +OBJ_all += RtclRw11CntlRL11.o RtclRw11UnitRL11.o # DEP_all = $(OBJ_all:.o=.dep) # diff --git a/tools/src/librwxxtpp/RtclRw11.cpp b/tools/src/librwxxtpp/RtclRw11.cpp index 5c1e3a07..b10f5509 100644 --- a/tools/src/librwxxtpp/RtclRw11.cpp +++ b/tools/src/librwxxtpp/RtclRw11.cpp @@ -1,4 +1,4 @@ -// $Id: RtclRw11.cpp 621 2014-12-26 21:20:05Z mueller $ +// $Id: RtclRw11.cpp 632 2015-01-11 12:30:03Z mueller $ // // Copyright 2013-2014 by Walter F.J. Mueller // @@ -20,7 +20,7 @@ /*! \file - \version $Id: RtclRw11.cpp 621 2014-12-26 21:20:05Z mueller $ + \version $Id: RtclRw11.cpp 632 2015-01-11 12:30:03Z mueller $ \brief Implemenation of class RtclRw11. */ @@ -80,7 +80,7 @@ int RtclRw11::ClassCmdConfig(RtclArgs& args) RtclProxyBase* pprox = RtclContext::Find(args.Interp()).FindProxy( "RlinkServer", parent); - if (pprox == 0) + if (pprox == nullptr) return args.Quit(string("-E: object '") + parent + "' not found or not type RlinkServer"); diff --git a/tools/src/librwxxtpp/RtclRw11CntlFactory.cpp b/tools/src/librwxxtpp/RtclRw11CntlFactory.cpp index a1439454..b6779ea2 100644 --- a/tools/src/librwxxtpp/RtclRw11CntlFactory.cpp +++ b/tools/src/librwxxtpp/RtclRw11CntlFactory.cpp @@ -1,6 +1,6 @@ -// $Id: RtclRw11CntlFactory.cpp 565 2014-06-28 12:54:08Z mueller $ +// $Id: RtclRw11CntlFactory.cpp 630 2015-01-04 22:43:32Z mueller $ // -// Copyright 2013-2014 by Walter F.J. Mueller +// Copyright 2013-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-01-04 630 1.1.2 RL11 back in // 2014-06-27 565 1.1.1 temporarily hide RL11 // 2014-06-08 561 1.1.0 add RL11 // 2013-05-01 513 1.0.1 add LP11 @@ -22,7 +23,7 @@ /*! \file - \version $Id: RtclRw11CntlFactory.cpp 565 2014-06-28 12:54:08Z mueller $ + \version $Id: RtclRw11CntlFactory.cpp 630 2015-01-04 22:43:32Z mueller $ \brief Implemenation of global function RtclRw11CntlFactory. */ @@ -32,7 +33,7 @@ #include "RtclRw11CntlDL11.hpp" #include "RtclRw11CntlRK11.hpp" -//#include "RtclRw11CntlRL11.hpp" +#include "RtclRw11CntlRL11.hpp" #include "RtclRw11CntlLP11.hpp" #include "RtclRw11CntlPC11.hpp" @@ -60,10 +61,10 @@ int RtclRw11CntlFactory(RtclArgs& args, RtclRw11Cpu& cpu) if(pobj->FactoryCmdConfig(args, cpu) != TCL_OK) return TCL_ERROR; pobj.release(); -// } else if (type == "rl11") { // rl11 -------------------------- -// unique_ptr pobj(new RtclRw11CntlRL11()); -// if(pobj->FactoryCmdConfig(args, cpu) != TCL_OK) return TCL_ERROR; -// pobj.release(); + } else if (type == "rl11") { // rl11 -------------------------- + unique_ptr pobj(new RtclRw11CntlRL11()); + if(pobj->FactoryCmdConfig(args, cpu) != TCL_OK) return TCL_ERROR; + pobj.release(); } else if (type == "lp11") { // lp11 -------------------------- unique_ptr pobj(new RtclRw11CntlLP11()); diff --git a/tools/src/librwxxtpp/RtclRw11CntlRK11.cpp b/tools/src/librwxxtpp/RtclRw11CntlRK11.cpp index 4723fdf7..2a0e89e1 100644 --- a/tools/src/librwxxtpp/RtclRw11CntlRK11.cpp +++ b/tools/src/librwxxtpp/RtclRw11CntlRK11.cpp @@ -1,6 +1,6 @@ -// $Id: RtclRw11CntlRK11.cpp 627 2015-01-04 11:36:37Z mueller $ +// $Id: RtclRw11CntlRK11.cpp 632 2015-01-11 12:30:03Z mueller $ // -// Copyright 2013- by Walter F.J. Mueller +// Copyright 2013-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,13 +13,14 @@ // // Revision History: // Date Rev Version Comment +// 2015-01-04 627 1.1 add Get/Set for chunksize // 2013-03-06 495 1.0 Initial version // 2013-02-02 480 0.1 First draft // --------------------------------------------------------------------------- /*! \file - \version $Id: RtclRw11CntlRK11.cpp 627 2015-01-04 11:36:37Z mueller $ + \version $Id: RtclRw11CntlRK11.cpp 632 2015-01-11 12:30:03Z mueller $ \brief Implemenation of RtclRw11CntlRK11. */ diff --git a/tools/src/librwxxtpp/RtclRw11CntlRL11.cpp b/tools/src/librwxxtpp/RtclRw11CntlRL11.cpp new file mode 100644 index 00000000..5667fec3 --- /dev/null +++ b/tools/src/librwxxtpp/RtclRw11CntlRL11.cpp @@ -0,0 +1,112 @@ +// $Id: RtclRw11CntlRL11.cpp 632 2015-01-11 12:30:03Z mueller $ +// +// Copyright 2014-2015 by Walter F.J. Mueller +// +// This program is free software; you may redistribute and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation, either version 2, or at your option any later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for complete details. +// +// Revision History: +// Date Rev Version Comment +// 2015-01-10 632 1.0 Initial version +// 2014-06-08 561 0.1 First draft +// --------------------------------------------------------------------------- + +/*! + \file + \version $Id: RtclRw11CntlRL11.cpp 632 2015-01-11 12:30:03Z mueller $ + \brief Implemenation of RtclRw11CntlRL11. +*/ + +#include "librtcltools/RtclNameSet.hpp" + +#include "RtclRw11CntlRL11.hpp" +#include "RtclRw11UnitRL11.hpp" + +using namespace std; + +/*! + \class Retro::RtclRw11CntlRL11 + \brief FIXME_docs +*/ + +// all method definitions in namespace Retro +namespace Retro { + +//------------------------------------------+----------------------------------- +//! Constructor + +RtclRw11CntlRL11::RtclRw11CntlRL11() + : RtclRw11CntlBase("Rw11CntlRL11") +{ + Rw11CntlRL11* pobj = &Obj(); + fGets.Add ("chunksize", + boost::bind(&Rw11CntlRL11::ChunkSize, pobj)); + fSets.Add ("chunksize", + boost::bind(&Rw11CntlRL11::SetChunkSize, pobj, _1)); +} + +//------------------------------------------+----------------------------------- +//! Destructor + +RtclRw11CntlRL11::~RtclRw11CntlRL11() +{} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +int RtclRw11CntlRL11::FactoryCmdConfig(RtclArgs& args, RtclRw11Cpu& cpu) +{ + static RtclNameSet optset("-base|-lam"); + + string cntlname(cpu.Obj().NextCntlName("rl")); + string cntlcmd = cpu.CommandName() + cntlname; + + uint16_t base = Rw11CntlRL11::kIbaddr; + int lam = Rw11CntlRL11::kLam; + + string opt; + while (args.NextOpt(opt, optset)) { + if (opt == "-base") { + if (!args.GetArg("base", base, 0177776, 0160000)) return kERR; + } else if (opt == "-lam") { + if (!args.GetArg("lam", lam, 0, 15)) return kERR; + } + } + if (!args.AllDone()) return kERR; + + // configure controller + Obj().Config(cntlname, base, lam); + + // install in CPU + cpu.Obj().AddCntl(dynamic_pointer_cast(ObjSPtr())); + // finally create tcl command + CreateObjectCmd(args.Interp(), cntlcmd.c_str()); + + // and create unit commands + for (size_t i=0; i +// +// This program is free software; you may redistribute and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation, either version 2, or at your option any later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for complete details. +// +// Revision History: +// Date Rev Version Comment +// 2015-01-10 632 1.0 Initial version +// 2014-06-10 561 0.1 First draft +// --------------------------------------------------------------------------- + + +/*! + \file + \version $Id: RtclRw11CntlRL11.hpp 647 2015-02-17 22:35:36Z mueller $ + \brief Declaration of class RtclRw11CntlRL11. +*/ + +#ifndef included_Retro_RtclRw11CntlRL11 +#define included_Retro_RtclRw11CntlRL11 1 + +#include "RtclRw11CntlBase.hpp" +#include "librw11/Rw11CntlRL11.hpp" + +namespace Retro { + + class RtclRw11CntlRL11 : public RtclRw11CntlBase { + public: + RtclRw11CntlRL11(); + ~RtclRw11CntlRL11(); + + virtual int FactoryCmdConfig(RtclArgs& args, RtclRw11Cpu& cpu); + + protected: + virtual int M_stats(RtclArgs& args); + }; + +} // end namespace Retro + +//#include "RtclRw11CntlRL11.ipp" + +#endif diff --git a/tools/src/librwxxtpp/RtclRw11Cpu.cpp b/tools/src/librwxxtpp/RtclRw11Cpu.cpp index be8d4c94..c1dc5563 100644 --- a/tools/src/librwxxtpp/RtclRw11Cpu.cpp +++ b/tools/src/librwxxtpp/RtclRw11Cpu.cpp @@ -1,4 +1,4 @@ -// $Id: RtclRw11Cpu.cpp 628 2015-01-04 16:22:09Z mueller $ +// $Id: RtclRw11Cpu.cpp 631 2015-01-09 21:36:51Z mueller $ // // Copyright 2013-2014 by Walter F.J. Mueller // @@ -27,7 +27,7 @@ /*! \file - \version $Id: RtclRw11Cpu.cpp 628 2015-01-04 16:22:09Z mueller $ + \version $Id: RtclRw11Cpu.cpp 631 2015-01-09 21:36:51Z mueller $ \brief Implemenation of RtclRw11Cpu. */ @@ -557,9 +557,9 @@ int RtclRw11Cpu::M_cp(RtclArgs& args) if (!varprint.empty()) { ostringstream sos; - const RlinkConnect::LogOpts& logopts = Connect().GetLogOpts(); clist.Print(sos, Connect().Context(), &Connect().AddrMap(), - logopts.baseaddr, logopts.basedata, logopts.basestat); + Connect().LogBaseAddr(), Connect().LogBaseData(), + Connect().LogBaseStat()); RtclOPtr pobj(Rtcl::NewLinesObj(sos)); if (!Rtcl::SetVarOrResult(args.Interp(), varprint, pobj)) return kERR; } @@ -612,7 +612,7 @@ int RtclRw11Cpu::M_wtcpu(RtclArgs& args) } if (twait < 0.) { // timeout - if (Connect().GetLogOpts().printlevel >= 1) { + if (Connect().PrintLevel() >= 1) { RlogMsg lmsg(Connect().LogFile()); lmsg << "-- wtcpu to=" << RosPrintf(tout, "f", 0,3) << " FAIL timeout"; } @@ -625,7 +625,7 @@ int RtclRw11Cpu::M_wtcpu(RtclArgs& args) if (!Connect().Exec(clist, emsg)) return args.Quit(emsg); } } else { // no timeout - if (Connect().GetLogOpts().printlevel >= 3) { + if (Connect().PrintLevel() >= 3) { RlogMsg lmsg(Connect().LogFile()); lmsg << "-- wtcpu to=" << RosPrintf(tout, "f", 0,3) << " T=" << RosPrintf(twait, "f", 0,3) diff --git a/tools/src/librwxxtpp/RtclRw11UnitRL11.cpp b/tools/src/librwxxtpp/RtclRw11UnitRL11.cpp new file mode 100644 index 00000000..1e940964 --- /dev/null +++ b/tools/src/librwxxtpp/RtclRw11UnitRL11.cpp @@ -0,0 +1,55 @@ +// $Id: RtclRw11UnitRL11.cpp 561 2014-06-09 17:22:50Z mueller $ +// +// Copyright 2014- by Walter F.J. Mueller +// +// This program is free software; you may redistribute and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation, either version 2, or at your option any later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for complete details. +// +// Revision History: +// Date Rev Version Comment +// 2014-06-08 561 1.0 Initial version +// --------------------------------------------------------------------------- + +/*! + \file + \version $Id: RtclRw11UnitRL11.cpp 561 2014-06-09 17:22:50Z mueller $ + \brief Implemenation of RtclRw11UnitRL11. +*/ + +#include "RtclRw11UnitRL11.hpp" + +using namespace std; + +/*! + \class Retro::RtclRw11UnitRL11 + \brief FIXME_docs +*/ + +// all method definitions in namespace Retro +namespace Retro { + +//------------------------------------------+----------------------------------- +//! Constructor + +RtclRw11UnitRL11::RtclRw11UnitRL11( + Tcl_Interp* interp, const std::string& unitcmd, + const boost::shared_ptr& spunit) + : RtclRw11UnitBase("Rw11UnitRL11", spunit), + RtclRw11UnitDisk(this, spunit.get()) +{ + CreateObjectCmd(interp, unitcmd.c_str()); +} + +//------------------------------------------+----------------------------------- +//! Destructor + +RtclRw11UnitRL11::~RtclRw11UnitRL11() +{} + +} // end namespace Retro diff --git a/tools/src/librwxxtpp/RtclRw11UnitRL11.hpp b/tools/src/librwxxtpp/RtclRw11UnitRL11.hpp new file mode 100644 index 00000000..57c7cc8f --- /dev/null +++ b/tools/src/librwxxtpp/RtclRw11UnitRL11.hpp @@ -0,0 +1,52 @@ +// $Id: RtclRw11UnitRL11.hpp 647 2015-02-17 22:35:36Z mueller $ +// +// Copyright 2014- by Walter F.J. Mueller +// +// This program is free software; you may redistribute and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation, either version 2, or at your option any later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for complete details. +// +// Revision History: +// Date Rev Version Comment +// 2014-06-08 561 1.0 Initial version +// --------------------------------------------------------------------------- + + +/*! + \file + \version $Id: RtclRw11UnitRL11.hpp 647 2015-02-17 22:35:36Z mueller $ + \brief Declaration of class RtclRw11UnitRL11. +*/ + +#ifndef included_Retro_RtclRw11UnitRL11 +#define included_Retro_RtclRw11UnitRL11 1 + +#include "librw11/Rw11UnitRL11.hpp" +#include "librw11/Rw11CntlRL11.hpp" + +#include "RtclRw11UnitDisk.hpp" +#include "RtclRw11UnitBase.hpp" + +namespace Retro { + + class RtclRw11UnitRL11 : public RtclRw11UnitBase, + public RtclRw11UnitDisk { + public: + RtclRw11UnitRL11(Tcl_Interp* interp, + const std::string& unitcmd, + const boost::shared_ptr& spunit); + ~RtclRw11UnitRL11(); + + protected: + }; + +} // end namespace Retro + +//#include "RtclRw11UnitRL11.ipp" + +#endif diff --git a/tools/tcl/rbbram/perf.tcl b/tools/tcl/rbbram/perf.tcl index 065ed3bc..3519b916 100644 --- a/tools/tcl/rbbram/perf.tcl +++ b/tools/tcl/rbbram/perf.tcl @@ -1,4 +1,4 @@ -# $Id: perf.tcl 622 2014-12-28 20:45:26Z mueller $ +# $Id: perf.tcl 643 2015-02-07 17:41:53Z mueller $ # # Copyright 2011-2014 by Walter F.J. Mueller # @@ -13,6 +13,7 @@ # # Revision History: # Date Rev Version Comment +# 2015-02-07 643 1.1.2 perf_blk(): use proper rbmax, add nmax argument # 2014-12-27 622 1.1.1 don't use read buffers in rblk speed test # 2014-12-06 609 1.1 test 512,1024,2000 word wblk/rbld; retra buffer cut # 2013-01-04 469 1.0.2 perf_blk: add optional 2nd arg: trace @@ -26,8 +27,8 @@ namespace eval rbbram { # # perf_blk: determine wblk/rblk write performance # - proc perf_blk {{tmax 1000} {trace 0}} { - set rbmax 2000; # FIXME_code: get proper buffer max + proc perf_blk {{tmax 1000} {trace 0} {nmax 2000}} { + set rbmax [expr {[rlc get bsizemax] - 32}] if {$tmax < 1} { error "-E: perf_blk: tmax argument must be >= 1" } @@ -39,6 +40,7 @@ namespace eval rbbram { # 256 512 1024 foreach nblk {1 2 4 8 16 32 64 128 256 512 768 1024 1536 2000} { + if {$nblk > $nmax} {break} set wbuf0 {} set wbuf1 {} set wbuf2 {} diff --git a/tools/tcl/rbemon/util.tcl b/tools/tcl/rbemon/util.tcl index 7abf3336..0c289bb4 100644 --- a/tools/tcl/rbemon/util.tcl +++ b/tools/tcl/rbemon/util.tcl @@ -1,4 +1,4 @@ -# $Id: util.tcl 620 2014-12-25 10:48:35Z mueller $ +# $Id: util.tcl 643 2015-02-07 17:41:53Z mueller $ # # Copyright 2011-2013 by Walter F.J. Mueller # @@ -13,6 +13,7 @@ # # Revision History: # Date Rev Version Comment +# 2015-02-07 642 1.1 add print() # 2011-04-17 376 1.0.1 add proc read # 2011-04-02 375 1.0 Initial version # @@ -102,5 +103,24 @@ namespace eval rbemon { } return $rval } - + # + # print: pretty print eyemon data + # + proc print {{nval 512}} { + set edat [read $nval] + set emax 0 + foreach {dat} $edat { + if {$dat > $emax} {set emax $dat} + } + set lemax [expr {$emax > 0 ? log($emax) : 1.}] + set rval " ind data" + set i 0 + foreach {dat} $edat { + append rval [format "\n%4d : %9d :" $i $dat] + set nh [expr {$dat > 0 ? 60. * log($dat) / $lemax : 0 }] + for {set j 1} {$j < $nh} {incr j} { append rval "=" } + incr i + } + return $rval + } } diff --git a/tools/tcl/rbs3hio/util.tcl b/tools/tcl/rbs3hio/util.tcl index 9952df48..bd8b5885 100644 --- a/tools/tcl/rbs3hio/util.tcl +++ b/tools/tcl/rbs3hio/util.tcl @@ -1,6 +1,6 @@ -# $Id: util.tcl 620 2014-12-25 10:48:35Z mueller $ +# $Id: util.tcl 640 2015-02-01 09:56:53Z mueller $ # -# Copyright 2011-2013 by Walter F.J. Mueller +# Copyright 2011-2015 by Walter F.J. Mueller # # This program is free software; you may redistribute and/or modify it under # the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ # # Revision History: # Date Rev Version Comment +# 2015-01-31 640 1.1 adopt to new register layout # 2011-08-14 406 1.0.2 adopt to common register layout # 2011-04-17 376 1.0.1 print: show also switch values; add proc disptest # 2011-03-27 374 1.0 Initial version @@ -28,17 +29,21 @@ namespace eval rbs3hio { # # setup register descriptions for s3_humanio_rbus # - regdsc CNTL {btn 12 4} {dspen 3} {dpen 2} {leden 1} {swien 0} - regdsc LED {dp 15 4} {led 7 8} + regdsc STAT {hdig 14 3} {hled 11 4} {hbtn 7 4} {hswi 3 4} + regdsc CNTL {dsp1en 4} {dsp0en 3} {dpen 2} {leden 1} {swien 0} # # setup: amap definitions for s3_humanio_rbus # proc setup {{base 0xfef0}} { - rlc amap -insert hi.cntl [expr {$base + 0x00}] - rlc amap -insert hi.swi [expr {$base + 0x01}] - rlc amap -insert hi.led [expr {$base + 0x02}] - rlc amap -insert hi.dsp [expr {$base + 0x03}] + rlc amap -insert hi.stat [expr {$base + 0x00}] + rlc amap -insert hi.cntl [expr {$base + 0x01}] + rlc amap -insert hi.btn [expr {$base + 0x02}] + rlc amap -insert hi.swi [expr {$base + 0x03}] + rlc amap -insert hi.led [expr {$base + 0x04}] + rlc amap -insert hi.dp [expr {$base + 0x05}] + rlc amap -insert hi.dsp0 [expr {$base + 0x06}] + rlc amap -insert hi.dsp1 [expr {$base + 0x07}] } # @@ -54,23 +59,36 @@ namespace eval rbs3hio { proc print {} { set rval {} rlc exec \ + -rreg hi.stat r_stat \ -rreg hi.cntl r_cntl \ + -rreg hi.btn r_btn \ -rreg hi.swi r_swi \ -rreg hi.led r_led \ - -rreg hi.dsp r_dsp - set led [regget rbs3hio::LED(led) $r_led] - set dp [regget rbs3hio::LED(dp) $r_led] - append rval " cntl: [regtxt rbs3hio::CNTL $r_cntl]" - append rval "\n swi: [pbvi b8 $r_swi]" - append rval "\n led: [pbvi b8 $led]" + -rreg hi.dp r_dp \ + -rreg hi.dsp0 r_dsp0 \ + -rreg hi.dsp1 r_dsp1 + + set ndig [expr {[regget rbs3hio::STAT(hdig) $r_stat] + 1}] + set nled [expr {[regget rbs3hio::STAT(hled) $r_stat] + 1}] + set nbtn [expr {[regget rbs3hio::STAT(hbtn) $r_stat] + 1}] + set nswi [expr {[regget rbs3hio::STAT(hswi) $r_stat] + 1}] + + append rval [format " stat: ndig:%d nled:%d nbtn:%d nswi:%d" \ + $ndig $nled $nbtn $nswi] + append rval "\n cntl: [regtxt rbs3hio::CNTL $r_cntl]" + append rval "\n btn: [pbvi b$nbtn $r_btn]" + append rval "\n swi: [pbvi b$nswi $r_swi]" + append rval "\n led: [pbvi b$nled $r_led]" + set r_dsp [expr {( $r_dsp1 << 16 ) + $r_dsp0}] set dspval "" - for {set i 3} {$i >= 0} {incr i -1} { + for {set i [expr {$ndig - 1}]} {$i >= 0} {incr i -1} { set digval [expr {( $r_dsp >> ( 4 * $i ) ) & 0x0f}] - set digdp [expr {( $dp >> $i ) & 0x01}] + set digdp [expr {( $r_dp >> $i ) & 0x01}] append dspval [format "%x" $digval] if {$digdp} {append dspval "."} else {append dspval " "} } - append rval "\n disp: [pbvi b16 $r_dsp] - [pbvi b4 $dp] -> \"$dspval\"" + set ndspbit [expr {4 * $ndig}] + append rval "\n disp: [pbvi b$ndspbit $r_dsp] - [pbvi b$ndig $r_dp] -> \"$dspval\"" return $rval } @@ -78,45 +96,48 @@ namespace eval rbs3hio { # disptest: blink through the leds # proc disptest {} { - rlc exec -rreg hi.cntl r_cntl + rlc exec -rreg hi.stat r_stat -rreg hi.cntl r_cntl + + set ndig [expr {[regget rbs3hio::STAT(hdig) $r_stat] + 1}] + set nled [expr {[regget rbs3hio::STAT(hled) $r_stat] + 1}] + set nbtn [expr {[regget rbs3hio::STAT(hbtn) $r_stat] + 1}] + set nswi [expr {[regget rbs3hio::STAT(hswi) $r_stat] + 1}] + set swien [regget rbs3hio::CNTL(swien) $r_cntl] - rlc exec -wreg hi.cntl [regbld rbs3hio::CNTL dspen dpen leden \ + rlc exec -wreg hi.cntl [regbld rbs3hio::CNTL dsp1en dsp0en dpen leden \ [list swien $swien] ] - foreach ledval {0x0f 0xf0 0xff} { - set dpval [expr {$ledval & 0x0f}] - set hiled [regbld rbs3hio::LED [list led $ledval] [list dp $dpval]] + rlc exec \ + -wreg hi.dsp1 0 \ + -wreg hi.dsp0 0 \ + -wreg hi.dp 0 \ + -wreg hi.led 0 + + puts "test LEDs + DSP0" + + foreach val {0x0000 0xaaaa 0x5555 0xffff 0x0000} { rlc exec \ - -wreg hi.led $hiled \ - -wreg hi.dsp 0xffff + -wreg hi.led $val \ + -wreg hi.dsp0 $val after 250 } + puts "test LEDs + DSP0 + DP" + for {set i 0} {$i <= 0xf} {incr i} { - set ledval [expr {( $i << 4 ) | $i}] - set dspval [expr {( $ledval << 8 ) | $ledval}] - set hiled [regbld rbs3hio::LED [list led $ledval] [list dp $i]] + set val [expr {( $i << 12 ) | ( $i << 8 ) | ( $i << 4 ) | $i}] rlc exec \ - -wreg hi.led $hiled \ - -wreg hi.dsp $dspval + -wreg hi.led $val \ + -wreg hi.dsp0 $val \ + -wreg hi.dp $i after 250 } - set ledval 0x01 - for {set i 0} {$i < 32} {incr i} { - set dpval [expr {$ledval & 0x0f}] - set hiled [regbld rbs3hio::LED [list led $ledval] [list dp $dpval]] - rlc exec \ - -wreg hi.led $hiled \ - -wreg hi.dsp $i - after 50 - set ledval [expr {$ledval << 1}] - if {$ledval & 0x100} {set ledval [expr {( $ledval & 0xff ) | 0x01}] } - } - rlc exec \ -wreg hi.cntl $r_cntl \ - -wreg hi.led 0x0 \ - -wreg hi.dsp 0x0 + -wreg hi.dsp1 0 \ + -wreg hi.dsp0 0 \ + -wreg hi.dp 0 \ + -wreg hi.led 0 } } diff --git a/tools/tcl/rw11/util.tcl b/tools/tcl/rw11/util.tcl index d1de1a8f..d408df35 100644 --- a/tools/tcl/rw11/util.tcl +++ b/tools/tcl/rw11/util.tcl @@ -1,6 +1,6 @@ -# $Id: util.tcl 607 2014-11-30 20:02:48Z mueller $ +# $Id: util.tcl 632 2015-01-11 12:30:03Z mueller $ # -# Copyright 2013-2014 by Walter F.J. Mueller +# Copyright 2013-2015 by Walter F.J. Mueller # # This program is free software; you may redistribute and/or modify it under # the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ # # Revision History: # Date Rev Version Comment +# 2015-01-09 632 1.2.3 setup_sys: use rlc set; setup_sys: add rl11 # 2014-07-26 575 1.2.2 run_pdpcp: add tout argument # 2014-06-27 565 1.2.1 temporarily hide RL11 # 2014-06-08 561 1.2 setup_sys: add RL11 @@ -33,7 +34,9 @@ namespace eval rw11 { # setup_cpu: create w11 cpu system # proc setup_cpu {} { - rlc config -basestat 2 -baseaddr 8 -basedata 8 + rlc set baseaddr 16 + rlc set basedata 8 + rlc set basestat 2 rlink::setup; # basic rlink defs rw11 rlw rls w11a 1; # create 1 w11a cpu cpu0 cp -reset; # reset CPU @@ -50,7 +53,7 @@ namespace eval rw11 { cpu0 add dl11 cpu0 add dl11 -base 0176500 -lam 2 cpu0 add rk11 - ## cpu0 add rl11 + cpu0 add rl11 cpu0 add lp11 cpu0 add pc11 rlw start