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- interim release w11a_V0.54 (untagged)

Browse Source 
- add Nexys3 port of w11a
This commit is contained in:
Walter F.J. Mueller
2011-12-04 21:25:09 +00:00
parent d76323ec6c
commit f2d0f39621
89 changed files with 2895 additions and 239 deletions
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7
rtl/bplib/nexys2/nexys2_pins.ucf
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@@ -1,4 +1,4 @@
## $Id: nexys2_pins.ucf 402 2011-08-05 18:56:44Z mueller $
## $Id: nexys2_pins.ucf 432 2011-11-25 20:16:28Z mueller $
##
## Pin locks for Nexys 2 core functionality (for 1200k FPGA)
## - internal RS232
@@ -82,8 +82,6 @@ NET "O_MEM_CLK" LOC = "h5" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
NET "O_MEM_CRE" LOC = "p7" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
NET "I_MEM_WAIT" LOC = "f5" | IOSTANDARD=LVCMOS33 | PULLDOWN;
##
NET "O_FLA_CE_N" LOC = "r5" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
##
NET "O_MEM_ADDR<0>" LOC = "j1" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<1>" LOC = "j2" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<2>" LOC = "h4" | IOSTANDARD=LVCMOS33;
@@ -127,3 +125,6 @@ NET "IO_MEM_DATA<14>" LOC = "r3" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<15>" LOC = "t1" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<*>" DRIVE=6 | SLEW=SLOW | KEEPER;
##
## Flash ---------------------------------------------------------------------
NET "O_FLA_CE_N" LOC = "r5" | IOSTANDARD=LVCMOS33 | DRIVE=6 | SLEW=SLOW;
##

75
rtl/bplib/nexys2/nexys2lib.vhd
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@@ -1,6 +1,6 @@
-- $Id: nexys2lib.vhd 389 2011-07-07 21:59:00Z mueller $
-- $Id: nexys2lib.vhd 433 2011-11-27 22:04:39Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -16,10 +16,12 @@
-- Description: Nexys 2 components
--
-- Dependencies: -
-- Tool versions: xst 11.4, 12.1; ghdl 0.26-0.29
-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-26 433 1.2 remove n2_cram_* modules, now in nxcramlib
-- 2011-11-23 432 1.1 remove O_FLA_CE_N port in cram driver/dummy
-- 2010-11-13 338 1.0.2 add O_CLKSYS to aif's (DCM derived system clock)
-- 2010-11-06 336 1.0.4 rename input pin CLK -> I_CLK50
-- 2010-05-28 295 1.0.3 use _ADV_N also for n2_cram_dummy
@@ -41,9 +43,9 @@ component nexys2_aif is -- NEXYS 2, abstract iface, base
O_CLKSYS : out slbit; -- DCM derived system clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- s3 switches
I_BTN : in slv4; -- s3 buttons
O_LED : out slv8; -- s3 leds
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
@@ -54,9 +56,9 @@ component nexys2_aif is -- NEXYS 2, abstract iface, base
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16 -- cram: data lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit -- flash ce.. (act.low)
);
end component;
@@ -66,9 +68,9 @@ component nexys2_fusp_aif is -- NEXYS 2, abstract iface, base+fusp
O_CLKSYS : out slbit; -- DCM derived system clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- s3 switches
I_BTN : in slv4; -- s3 buttons
O_LED : out slv8; -- s3 leds
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
@@ -79,9 +81,9 @@ component nexys2_fusp_aif is -- NEXYS 2, abstract iface, base+fusp
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
@@ -89,53 +91,4 @@ component nexys2_fusp_aif is -- NEXYS 2, abstract iface, base+fusp
);
end component;
component n2_cram_dummy is -- CRAM protection dummy
port (
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16 -- cram: data lines
);
end component;
component n2_cram_memctl_as is -- CRAM driver (async+page mode)
generic (
READ0DELAY : positive := 2; -- read word 0 delay in clock cycles
READ1DELAY : positive := 2; -- read word 1 delay in clock cycles
WRITEDELAY : positive := 3); -- write delay in clock cycles
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
REQ : in slbit; -- request
WE : in slbit; -- write enable
BUSY : out slbit; -- controller busy
ACK_R : out slbit; -- acknowledge read
ACK_W : out slbit; -- acknowledge write
ACT_R : out slbit; -- signal active read
ACT_W : out slbit; -- signal active write
ADDR : in slv22; -- address (32 bit word address)
BE : in slv4; -- byte enable
DI : in slv32; -- data in (memory view)
DO : out slv32; -- data out (memory view)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16 -- cram: data lines
);
end component;
end package nexys2lib;

5
rtl/bplib/nexys2/tb/.cvsignore
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@@ -1,7 +1,2 @@
tb_nexys2_dummy
tb_nexys2_fusp_dummy
tb_n2_cram_memctl_as
tb_n2_cram_memctl_as_[sft]sim
tb_n2_cram_memctl_as_ISim
tb_n2_cram_memctl_as_ISim_[sft]sim
tb_n2_cram_memctl_stim

5
rtl/bplib/nexys2/tb/Makefile
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@@ -1,13 +1,14 @@
# $Id: Makefile 405 2011-08-14 08:16:28Z mueller $
# $Id: Makefile 433 2011-11-27 22:04:39Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-11-26 433 1.2 remove tb_n2_cram_memctl_as (moved to nxcramlib)
# 2011-08-13 405 1.1 use includes from rtl/make
# 2010-05-30 297 1.0.2 use tb_n2_cram_memctl_as now
# 2010-05-28 295 1.0.1 add tb_.._dummy's
# 2007-09-23 84 1.0 Initial version
#
EXE_all = tb_nexys2_dummy tb_nexys2_fusp_dummy tb_n2_cram_memctl_as
EXE_all = tb_nexys2_dummy tb_nexys2_fusp_dummy
#
ISE_PATH = xc3s1200e-fg320-4
#

4
rtl/bplib/nexys2/tb/nexys2_fusp_dummy.vbom
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@@ -1,7 +1,7 @@
# libs
../../../vlib/slvtypes.vhd
../nexys2lib.vhd
../../nxcramlib/nxcramlib.vhd
# components
../n2_cram_dummy.vbom
../../nxcramlib/nx_cram_dummy.vbom
# design
nexys2_fusp_dummy.vhd

23
rtl/bplib/nexys2/tb/nexys2_fusp_dummy.vhd
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@@ -1,6 +1,6 @@
-- $Id: nexys2_fusp_dummy.vhd 338 2010-11-13 22:19:25Z mueller $
-- $Id: nexys2_fusp_dummy.vhd 433 2011-11-27 22:04:39Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -18,10 +18,12 @@
-- Dependencies: -
-- To test: tb_nexys2
-- Target Devices: generic
-- Tool versions: xst 11.4, 12.1; ghdl 0.26-0.29
-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-26 433 1.2 use nxcramlib
-- 2011-11-23 432 1.1 remove O_FLA_CE_N port from n2_cram_dummy
-- 2010-11-13 338 1.0.2 add O_CLKSYS (for DCM derived system clock)
-- 2010-11-06 336 1.0.1 rename input pin CLK -> I_CLK50
-- 2010-05-28 295 1.0 Initial version (derived from s3board_fusp_dummy)
@@ -31,7 +33,7 @@ library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.nexys2lib.all;
use work.nxcramlib.all;
entity nexys2_fusp_dummy is -- NEXYS 2 dummy (base+fusp; loopback)
-- implements nexys2_fusp_aif
@@ -40,9 +42,9 @@ entity nexys2_fusp_dummy is -- NEXYS 2 dummy (base+fusp; loopback)
O_CLKSYS : out slbit; -- DCM derived system clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- s3 switches
I_BTN : in slv4; -- s3 buttons
O_LED : out slv8; -- s3 leds
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
@@ -53,9 +55,9 @@ entity nexys2_fusp_dummy is -- NEXYS 2 dummy (base+fusp; loopback)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
@@ -72,7 +74,7 @@ begin
O_FUSP_TXD <= I_FUSP_RXD;
O_FUSP_RTS_N <= I_FUSP_CTS_N;
CRAM : n2_cram_dummy -- connect CRAM to protection dummy
CRAM : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
@@ -82,9 +84,10 @@ begin
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_FLA_CE_N => O_FLA_CE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_FLA_CE_N <= '1'; -- keep Flash memory disabled
end syn;

5
rtl/bplib/nexys2/tb/tb_nexys2_core.vhd
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@@ -1,4 +1,4 @@
-- $Id: tb_nexys2_core.vhd 427 2011-11-19 21:04:11Z mueller $
-- $Id: tb_nexys2_core.vhd 433 2011-11-27 22:04:39Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -23,6 +23,8 @@
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-26 433 1.1.1 remove O_FLA_CE_N from tb_nexys2_core
-- 2011-11-21 432 1.1 update O_FLA_CE_N usage
-- 2011-11-19 427 1.0.1 now numeric_std clean
-- 2010-05-23 294 1.0 Initial version (derived from tb_s3board_core)
------------------------------------------------------------------------------
@@ -49,7 +51,6 @@ entity tb_nexys2_core is
O_MEM_CLK : in slbit; -- cram: clock
O_MEM_CRE : in slbit; -- cram: command register enable
I_MEM_WAIT : out slbit; -- cram: mem wait
O_FLA_CE_N : in slbit; -- flash ce.. (act.low)
O_MEM_ADDR : in slv23; -- cram: address lines
IO_MEM_DATA : inout slv16 -- cram: data lines
);

9
rtl/bplib/nexys2/tb/tb_nexys2_fusp.vhd
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@@ -1,4 +1,4 @@
-- $Id: tb_nexys2_fusp.vhd 427 2011-11-19 21:04:11Z mueller $
-- $Id: tb_nexys2_fusp.vhd 433 2011-11-27 22:04:39Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -27,6 +27,8 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-26 433 3.1.1 remove O_FLA_CE_N from tb_nexys2_core
-- 2011-11-21 432 3.1 update O_FLA_CE_N usage
-- 2011-11-19 427 3.0.1 now numeric_std clean
-- 2010-12-29 351 3.0 use rlink/tb now
-- 2010-11-13 338 1.0.2 now dcm aware: add O_CLKSYS, use rritb_core_dcm
@@ -84,9 +86,9 @@ architecture sim of tb_nexys2_fusp is
signal O_MEM_CLK : slbit := '0';
signal O_MEM_CRE : slbit := '0';
signal I_MEM_WAIT : slbit := '0';
signal O_FLA_CE_N : slbit := '0';
signal O_MEM_ADDR : slv23 := (others=>'Z');
signal IO_MEM_DATA : slv16 := (others=>'0');
signal O_FLA_CE_N : slbit := '0';
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
@@ -140,7 +142,6 @@ begin
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_FLA_CE_N => O_FLA_CE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
@@ -164,9 +165,9 @@ begin
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_FLA_CE_N => O_FLA_CE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA,
O_FLA_CE_N => O_FLA_CE_N,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,

4
rtl/bplib/nexys2/tb/tbw.dat
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@@ -1,4 +0,0 @@
# $Id: tbw.dat 297 2010-05-30 20:10:16Z mueller $
#
[tb_n2_cram_memctl_as]
tb_n2_cram_memctl_stim = tb_n2_cram_memctl_stim.dat

135
rtl/bplib/nexys3/nexys3_pins.ucf Normal file
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@@ -0,0 +1,135 @@
## $Id: nexys3_pins.ucf 432 2011-11-25 20:16:28Z mueller $
##
## Pin locks for Nexys 3 core functionality
## - USB UART
## - human I/O (switches, buttons, leds, display)
## - cram
##
## Revision History:
## Date Rev Version Comment
## 2011-11-23 432 1.0.2 add PPCM controls
## 2011-10-10 413 1.0.1 new BTN sequence: clockwise(U-R-D-L) - middle
## 2011-07-04 388 1.0 Initial version
##
## Note: default is DRIVE=12 | SLEW=SLOW
##
## Assume that VCCB0 is jumpered for 2.5 V (for VHDCI LVDS usage)
##
## clocks -- in bank 2 -------------------------------------------------------
NET "I_CLK100" LOC = "v10" | IOSTANDARD=LVCMOS33;
##
## USB UART Interface -- in bank 1--------------------------------------------
## I_RXD -> signal MCU_RX -> TXD pin of FT232R
## O_TXD -> signal MCU_TX -> RXD pin of FT232R
## I_CTS_N ?? signal RTS -> RTS pin of FT232R (only on J14)
## O_RTS_N ?? signal CTS -> CTS pin of FT232R (only on J14)
NET "I_RXD" LOC = "n17" | IOSTANDARD=LVCMOS33;
NET "O_TXD" LOC = "n18" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=SLOW;
##
## switches -- in bank 2 -----------------------------------------------------
NET "I_SWI<0>" LOC = "t10" | IOSTANDARD=LVCMOS33;
NET "I_SWI<1>" LOC = "t9" | IOSTANDARD=LVCMOS33;
NET "I_SWI<2>" LOC = "v9" | IOSTANDARD=LVCMOS33;
NET "I_SWI<3>" LOC = "m8" | IOSTANDARD=LVCMOS33;
NET "I_SWI<4>" LOC = "n8" | IOSTANDARD=LVCMOS33;
NET "I_SWI<5>" LOC = "u8" | IOSTANDARD=LVCMOS33;
NET "I_SWI<6>" LOC = "v8" | IOSTANDARD=LVCMOS33;
NET "I_SWI<7>" LOC = "t5" | IOSTANDARD=LVCMOS33;
##
## buttons -- in bank 0-------------------------------------------------------
## sequence: clockwise(U-R-D-L) - middle
NET "I_BTN<0>" LOC = "a8" | IOSTANDARD=LVCMOS25; # BTNU
NET "I_BTN<1>" LOC = "d9" | IOSTANDARD=LVCMOS25; # BTNR
NET "I_BTN<2>" LOC = "c9" | IOSTANDARD=LVCMOS25; # BTND
NET "I_BTN<3>" LOC = "c4" | IOSTANDARD=LVCMOS25; # BTNL
NET "I_BTN<4>" LOC = "b8" | IOSTANDARD=LVCMOS25; # BTNS
##
## LEDs -- in bank 2 ---------------------------------------------------------
NET "O_LED<0>" LOC = "u16" | IOSTANDARD=LVCMOS33;
NET "O_LED<1>" LOC = "v16" | IOSTANDARD=LVCMOS33;
NET "O_LED<2>" LOC = "u15" | IOSTANDARD=LVCMOS33;
NET "O_LED<3>" LOC = "v15" | IOSTANDARD=LVCMOS33;
NET "O_LED<4>" LOC = "m11" | IOSTANDARD=LVCMOS33;
NET "O_LED<5>" LOC = "n11" | IOSTANDARD=LVCMOS33;
NET "O_LED<6>" LOC = "r11" | IOSTANDARD=LVCMOS33;
NET "O_LED<7>" LOC = "t11" | IOSTANDARD=LVCMOS33;
NET "O_LED<*>" DRIVE=12 | SLEW=SLOW;
##
## 7 segment display -- in bank 1 --------------------------------------------
NET "O_ANO_N<0>" LOC = "n16" | IOSTANDARD=LVCMOS33;
NET "O_ANO_N<1>" LOC = "n15" | IOSTANDARD=LVCMOS33;
NET "O_ANO_N<2>" LOC = "p18" | IOSTANDARD=LVCMOS33;
NET "O_ANO_N<3>" LOC = "p17" | IOSTANDARD=LVCMOS33;
NET "O_ANO_N<*>" DRIVE=12 | SLEW=SLOW;
##
NET "O_SEG_N<0>" LOC = "t17" | IOSTANDARD=LVCMOS33; # CA
NET "O_SEG_N<1>" LOC = "t18" | IOSTANDARD=LVCMOS33; # CB
NET "O_SEG_N<2>" LOC = "u17" | IOSTANDARD=LVCMOS33; # CC
NET "O_SEG_N<3>" LOC = "u18" | IOSTANDARD=LVCMOS33; # CD
NET "O_SEG_N<4>" LOC = "m14" | IOSTANDARD=LVCMOS33; # CE
NET "O_SEG_N<5>" LOC = "n14" | IOSTANDARD=LVCMOS33; # CF
NET "O_SEG_N<6>" LOC = "l14" | IOSTANDARD=LVCMOS33; # CG
NET "O_SEG_N<7>" LOC = "m13" | IOSTANDARD=LVCMOS33; # DP
NET "O_SEG_N<*>" DRIVE=12 | SLEW=SLOW;
##
## CRAM -- in bank 2 (data) and 1 (addr) -------------------------------------
NET "O_MEM_CE_N" LOC = "l15" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
NET "O_MEM_WE_N" LOC = "m16" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
NET "O_MEM_OE_N" LOC = "l18" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
##
NET "O_MEM_BE_N<0>" LOC = "k16" | IOSTANDARD=LVCMOS33;
NET "O_MEM_BE_N<1>" LOC = "k15" | IOSTANDARD=LVCMOS33;
NET "O_MEM_BE_N<*>" DRIVE=12 | SLEW=FAST;
##
NET "O_MEM_ADV_N" LOC = "h18" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
NET "O_MEM_CLK" LOC = "r10" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
NET "O_MEM_CRE" LOC = "m18" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
NET "I_MEM_WAIT" LOC = "v4" | IOSTANDARD=LVCMOS33 | PULLDOWN;
##
NET "O_MEM_ADDR<0>" LOC = "k18" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<1>" LOC = "k17" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<2>" LOC = "j18" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<3>" LOC = "j16" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<4>" LOC = "g18" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<5>" LOC = "g16" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<6>" LOC = "h16" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<7>" LOC = "h15" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<8>" LOC = "h14" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<9>" LOC = "h13" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<10>" LOC = "f18" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<11>" LOC = "f17" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<12>" LOC = "k13" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<13>" LOC = "k12" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<14>" LOC = "e18" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<15>" LOC = "e16" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<16>" LOC = "g13" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<17>" LOC = "h12" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<18>" LOC = "d18" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<19>" LOC = "d17" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<20>" LOC = "g14" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<21>" LOC = "f14" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<22>" LOC = "c18" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<*>" DRIVE=6 | SLEW=FAST;
##
NET "IO_MEM_DATA<0>" LOC = "r13" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<1>" LOC = "t14" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<2>" LOC = "v14" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<3>" LOC = "u5" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<4>" LOC = "v5" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<5>" LOC = "r3" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<6>" LOC = "t3" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<7>" LOC = "r5" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<8>" LOC = "n5" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<9>" LOC = "p6" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<10>" LOC = "p12" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<11>" LOC = "u13" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<12>" LOC = "v13" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<13>" LOC = "u10" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<14>" LOC = "r8" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<15>" LOC = "t8" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<*>" DRIVE=6 | SLEW=SLOW | KEEPER;
##
## PPCM -- parallel PCM memory -----------------------------------------------
NET "O_PPCM_CE_N" LOC = "l17" | IOSTANDARD=LVCMOS33 | DRIVE=6 | SLEW=SLOW;
NET "O_PPCM_RST_N" LOC = "t4" | IOSTANDARD=LVCMOS33 | DRIVE=6 | SLEW=SLOW;
##

12
rtl/bplib/nexys3/nexys3_pins_pmb0_rs232.ucf Normal file
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## $Id: nexys3_pins_pmb0_rs232.ucf 430 2011-11-20 20:48:39Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2011-11-20 430 1.0 Initial version
##
## Pmod connector B top / usage RS232 for FTDI USB serport -------------------
##
NET "O_FUSP_RTS_N" LOC = "k2" | IOSTANDARD=LVCMOS33 | DRIVE=4 | SLEW=SLOW;
NET "I_FUSP_CTS_N" LOC = "k1" | IOSTANDARD=LVCMOS33 | PULLDOWN;
NET "I_FUSP_RXD" LOC = "l4" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "O_FUSP_TXD" LOC = "l3" | IOSTANDARD=LVCMOS33 | DRIVE=4 | SLEW=SLOW;

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-- $Id: nexys3lib.vhd 432 2011-11-25 20:16:28Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: nexys3lib
-- Description: Nexys 3 components
--
-- Dependencies: -
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-25 432 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package nexys3lib is
component nexys3_aif is -- NEXYS 3, abstract iface, base
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit -- ppcm: ...
);
end component;
component nexys3_fusp_aif is -- NEXYS 2, abstract iface, base+fusp
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit; -- ppcm: ...
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end component;
end package nexys3lib;

7
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tb_nexys3_dummy
tb_nexys3_fusp_dummy
tb_n3_cram_memctl_as
tb_n3_cram_memctl_as_[sft]sim
tb_n3_cram_memctl_as_ISim
tb_n3_cram_memctl_as_ISim_[sft]sim
tb_n3_cram_memctl_stim

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# $Id: Makefile 433 2011-11-27 22:04:39Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-11-26 432 1.0 Initial version
#
EXE_all = tb_nexys3_fusp_dummy
#
ISE_PATH = xc6slx16-csg324-2
#
XFLOWOPT_SYN = syn_s6_speed.opt
XFLOWOPT_IMP = imp_s6_speed.opt
#
.PHONY : all all_ssim all_tsim clean
#
all : $(EXE_all)
all_ssim : $(EXE_all:=_ssim)
all_tsim : $(EXE_all:=_tsim)
#
clean : ise_clean ghdl_clean isim_clean
#
#-----
#
include $(RETROBASE)/rtl/make/generic_ghdl.mk
include $(RETROBASE)/rtl/make/generic_isim.mk
include $(RETROBASE)/rtl/make/generic_xflow.mk
#
VBOM_all = $(wildcard *.vbom)
#
include $(VBOM_all:.vbom=.dep_xst)
include $(VBOM_all:.vbom=.dep_ghdl)
include $(VBOM_all:.vbom=.dep_isim)
include $(wildcard *.o.dep_ghdl)
#

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rtl/bplib/nexys3/tb/nexys3_fusp_dummy.vbom Normal file
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# libs
../../../vlib/slvtypes.vhd
../../nxcramlib/nxcramlib.vhd
# components
../../nxcramlib/nx_cram_dummy.vbom
# design
nexys3_fusp_dummy.vhd

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-- $Id: nexys3_fusp_dummy.vhd 433 2011-11-27 22:04:39Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: nexys3_dummy - syn
-- Description: nexys3 minimal target (base; serport loopback)
--
-- Dependencies: -
-- To test: tb_nexys3
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-26 433 1.1 use nxcramlib
-- 2011-11-25 432 1.0 Initial version (derived from nexys2_fusp_dummy)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.nxcramlib.all;
entity nexys3_fusp_dummy is -- NEXYS 3 dummy (base+fusp; loopback)
-- implements nexys3_fusp_aif
port (
I_CLK100 : in slbit; -- 100 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit; -- ppcm: ...
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end nexys3_fusp_dummy;
architecture syn of nexys3_fusp_dummy is
begin
O_TXD <= I_RXD; -- loop back
O_FUSP_TXD <= I_FUSP_RXD;
O_FUSP_RTS_N <= I_FUSP_CTS_N;
CRAM : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
O_PPCM_RST_N <= '1'; --
end syn;

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# libs
../../../vlib/slvtypes.vhd
../../../vlib/serport/serport.vhd
../../../vlib/simlib/simbus.vhd
# components
../../../vlib/serport/serport_uart_rx.vbom
../../../vlib/serport/serport_uart_tx.vbom
../../micron/mt45w8mw16b.vbom
# design
tb_nexys3_core.vhd

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-- $Id: tb_nexys3_core.vhd 432 2011-11-25 20:16:28Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys3_core - sim
-- Description: Test bench for nexys3 - core device handling
--
-- Dependencies: vlib/parts/micron/mt45w8mw16b
--
-- To test: generic, any nexys3 target
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-25 432 1.0 Initial version (derived from tb_nexys2_core)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.serport.all;
use work.simbus.all;
entity tb_nexys3_core is
port (
I_SWI : out slv8; -- n3 switches
I_BTN : out slv5; -- n3 buttons
O_MEM_CE_N : in slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : in slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : in slbit; -- cram: write enable (act.low)
O_MEM_OE_N : in slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : in slbit; -- cram: address valid (act.low)
O_MEM_CLK : in slbit; -- cram: clock
O_MEM_CRE : in slbit; -- cram: command register enable
I_MEM_WAIT : out slbit; -- cram: mem wait
O_MEM_ADDR : in slv23; -- cram: address lines
IO_MEM_DATA : inout slv16 -- cram: data lines
);
end tb_nexys3_core;
architecture sim of tb_nexys3_core is
signal R_SWI : slv8 := (others=>'0');
signal R_BTN : slv5 := (others=>'0');
constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
begin
MEM : entity work.mt45w8mw16b
port map (
CLK => O_MEM_CLK,
CE_N => O_MEM_CE_N,
OE_N => O_MEM_OE_N,
WE_N => O_MEM_WE_N,
UB_N => O_MEM_BE_N(1),
LB_N => O_MEM_BE_N(0),
ADV_N => O_MEM_ADV_N,
CRE => O_MEM_CRE,
MWAIT => I_MEM_WAIT,
ADDR => O_MEM_ADDR,
DATA => IO_MEM_DATA
);
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_swi then
R_SWI <= to_x01(SB_DATA(R_SWI'range));
end if;
if SB_ADDR = sbaddr_btn then
R_BTN <= to_x01(SB_DATA(R_BTN'range));
end if;
end if;
end process proc_simbus;
I_SWI <= R_SWI;
I_BTN <= R_BTN;
end sim;

23
rtl/bplib/nexys3/tb/tb_nexys3_fusp.vbom Normal file
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# Not meant for direct top level usage. Used with
# tb_nexys3_fusp_(....)[_ssim].vbom and config
# lines to generate the different cases.
#
# libs
../../../vlib/slvtypes.vhd
../../../vlib/rlink/rlinklib.vbom
../../../vlib/rlink/tb/rlinktblib.vhd
../../../vlib/serport/serport.vhd
../../../vlib/xlib/xlib.vhd
../nexys3lib.vhd
../../../vlib/simlib/simlib.vhd
../../../vlib/simlib/simbus.vhd
sys_conf : sys_conf_sim.vhd
# components
../../../vlib/rlink/tb/tbcore_rlink_dcm.vbom
../../../vlib/xlib/dcm_sfs_gsim.vbom
tb_nexys3_core.vbom
../../../vlib/serport/serport_uart_rxtx.vbom
nexys3_fusp_aif : nexys3_fusp_dummy.vbom
# design
tb_nexys3_fusp.vhd
@top:tb_nexys3_fusp

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rtl/bplib/nexys3/tb/tb_nexys3_fusp.vhd Normal file
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-- $Id: tb_nexys3_fusp.vhd 433 2011-11-27 22:04:39Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys3_fusp - sim
-- Description: Test bench for nexys3 (base+fusp)
--
-- Dependencies: vlib/rlink/tb/tbcore_rlink_dcm
-- vlib/xlib/dcm_sfs
-- tb_nexys3_core
-- vlib/serport/serport_uart_rxtx
-- nexys3_fusp_aif [UUT]
--
-- To test: generic, any nexys3_fusp_aif target
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-25 432 1.0 Initial version (derived from tb_nexys2_fusp)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.rlinktblib.all;
use work.serport.all;
use work.xlib.all;
use work.nexys3lib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_nexys3_fusp is
end tb_nexys3_fusp;
architecture sim of tb_nexys3_fusp is
signal CLKOSC : slbit := '0';
signal CLKSYS : slbit := '0';
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal RX_HOLD : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv5 := (others=>'0');
signal O_LED : slv8 := (others=>'0');
signal O_ANO_N : slv4 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal O_MEM_CE_N : slbit := '1';
signal O_MEM_BE_N : slv2 := (others=>'1');
signal O_MEM_WE_N : slbit := '1';
signal O_MEM_OE_N : slbit := '1';
signal O_MEM_ADV_N : slbit := '1';
signal O_MEM_CLK : slbit := '0';
signal O_MEM_CRE : slbit := '0';
signal I_MEM_WAIT : slbit := '0';
signal O_MEM_ADDR : slv23 := (others=>'Z');
signal IO_MEM_DATA : slv16 := (others=>'0');
signal O_PPCM_CE_N : slbit := '0';
signal O_PPCM_RST_N : slbit := '0';
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
signal UART_RESET : slbit := '0';
signal UART_RXD : slbit := '1';
signal UART_TXD : slbit := '1';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal R_PORTSEL : slbit := '0';
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clockosc_period : time := 10 ns;
constant clockosc_offset : time := 200 ns;
constant setup_time : time := 5 ns;
constant c2out_time : time := 9 ns;
begin
TBCORE : tbcore_rlink_dcm
generic map (
CLKOSC_PERIOD => clockosc_period,
CLKOSC_OFFSET => clockosc_offset,
SETUP_TIME => setup_time,
C2OUT_TIME => c2out_time)
port map (
CLKOSC => CLKOSC,
CLKSYS => CLKSYS,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => RX_HOLD,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
DCM_SYS : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 10.0)
port map (
CLKIN => CLKOSC,
CLKFX => CLKSYS,
LOCKED => open
);
RX_HOLD <= TXBUSY or RTS_N; -- back preasure for data flow to tb
N3CORE : entity work.tb_nexys3_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
UUT : nexys3_fusp_aif
port map (
I_CLK100 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA,
O_PPCM_CE_N => O_PPCM_CE_N,
O_PPCM_RST_N => O_PPCM_RST_N,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD
);
UART : serport_uart_rxtx
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKSYS,
RESET => UART_RESET,
CLKDIV => CLKDIV,
RXSD => UART_RXD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => UART_TXD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
proc_port_mux: process (R_PORTSEL, UART_TXD, CTS_N,
O_TXD, O_FUSP_TXD, O_FUSP_RTS_N)
begin
if R_PORTSEL = '0' then -- use main board rs232, no flow cntl
I_RXD <= UART_TXD; -- write port 0 inputs
UART_RXD <= O_TXD; -- get port 0 outputs
RTS_N <= '0';
I_FUSP_RXD <= '1'; -- port 1 inputs to idle state
I_FUSP_CTS_N <= '0';
else -- otherwise use pmod1 rs232
I_FUSP_RXD <= UART_TXD; -- write port 1 inputs
I_FUSP_CTS_N <= CTS_N;
UART_RXD <= O_FUSP_TXD; -- get port 1 outputs
RTS_N <= O_FUSP_RTS_N;
I_RXD <= '1'; -- port 0 inputs to idle state
end if;
end process proc_port_mux;
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKSYS);
wait for c2out_time;
if RXERR = '1' then
writetimestamp(oline, SB_CLKCYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL <= to_x01(SB_DATA(0));
end if;
end if;
end process proc_simbus;
end sim;

23
rtl/bplib/nxcramlib/Makefile Normal file
View File

@@ -0,0 +1,23 @@
# $Id: Makefile 433 2011-11-27 22:04:39Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-11-26 433 1.0 Initial version (cloned..)
#
VBOM_all = $(wildcard *.vbom)
NGC_all = $(VBOM_all:.vbom=.ngc)
#
ISE_PATH = xc3s1200e-fg320-4
#
.PHONY : all clean
#
all : $(NGC_all)
#
clean : ise_clean
#
#----
#
include $(RETROBASE)/rtl/make/generic_xflow.mk
#
include $(VBOM_all:.vbom=.dep_xst)
#

2
rtl/bplib/nexys2/n2_cram_dummy.vbom → rtl/bplib/nxcramlib/nx_cram_dummy.vbom
View File

@@ -2,4 +2,4 @@
../../vlib/slvtypes.vhd
# components
# design
n2_cram_dummy.vhd
nx_cram_dummy.vhd

20
rtl/bplib/nexys2/n2_cram_dummy.vhd → rtl/bplib/nxcramlib/nx_cram_dummy.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: n2_cram_dummy.vhd 426 2011-11-18 18:14:08Z mueller $
-- $Id: nx_cram_dummy.vhd 433 2011-11-27 22:04:39Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -12,15 +12,17 @@
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: n2_cram_dummy - syn
-- Description: nexys2: CRAM protection dummy
-- Module Name: nx_cram_dummy - syn
-- Description: nexys2/3: CRAM protection dummy
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 11.4; ghdl 0.26
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-26 433 1.2 renamed from n2_cram_dummy
-- 2011-11-23 432 1.1 remove O_FLA_CE_N port
-- 2010-05-28 295 1.0.1 use _ADV_N
-- 2010-05-21 292 1.0 Initial version
------------------------------------------------------------------------------
@@ -30,7 +32,7 @@ use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity n2_cram_dummy is -- CRAM protection dummy
entity nx_cram_dummy is -- CRAM protection dummy
port (
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
@@ -40,14 +42,13 @@ entity n2_cram_dummy is -- CRAM protection dummy
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16 -- cram: data lines
);
end n2_cram_dummy;
end nx_cram_dummy;
architecture syn of n2_cram_dummy is
architecture syn of nx_cram_dummy is
begin
O_MEM_CE_N <= '1'; -- disable cram chip
@@ -57,7 +58,6 @@ begin
O_MEM_ADV_N <= '1';
O_MEM_CLK <= '0';
O_MEM_CRE <= '0';
O_FLA_CE_N <= '1';
O_MEM_ADDR <= (others=>'0');
IO_MEM_DATA <= (others=>'0');

2
rtl/bplib/nexys2/n2_cram_memctl_as.vbom → rtl/bplib/nxcramlib/nx_cram_memctl_as.vbom
View File

@@ -6,4 +6,4 @@
../../vlib/xlib/iob_reg_o_gen.vbom
../../vlib/xlib/iob_reg_io_gen.vbom
# design
n2_cram_memctl_as.vhd
nx_cram_memctl_as.vhd

20
rtl/bplib/nexys2/n2_cram_memctl_as.vhd → rtl/bplib/nxcramlib/nx_cram_memctl_as.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: n2_cram_memctl_as.vhd 427 2011-11-19 21:04:11Z mueller $
-- $Id: nx_cram_memctl_as.vhd 433 2011-11-27 22:04:39Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -12,14 +12,14 @@
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: n2_cram_memctl_as - syn
-- Description: nexys2: CRAM driver - async and page mode
-- Module Name: nx_cram_memctl_as - syn
-- Description: nexys2/3: CRAM driver - async and page mode
--
-- Dependencies: vlib/xlib/iob_reg_o
-- vlib/xlib/iob_reg_o_gen
-- vlib/xlib/iob_reg_io_gen
-- Test bench: tb/tb_n2_cram_memctl
-- fw_gen/tst_sram/nexys2/tb/tb_tst_sram_n2
-- Test bench: tb/tb_nx_cram_memctl_as
-- sys_gen/tst_sram/nexys2/tb/tb_tst_sram_n2
-- Target Devices: generic
-- Tool versions: xst 11.4, 13.1; ghdl 0.26
--
@@ -31,6 +31,8 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-26 433 1.2 renamed from n2_cram_memctl_as
-- 2011-11-19 432 1.1 remove O_FLA_CE_N port
-- 2011-11-19 427 1.0.5 now numeric_std clean
-- 2010-11-22 339 1.0.4 cntdly now 3 bit; add assert for DELAY generics
-- 2010-06-03 299 1.0.3 add "KEEP" for data iob; MEM_OE='1' on first read
@@ -117,7 +119,7 @@ use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
entity n2_cram_memctl_as is -- CRAM driver (async+page mode)
entity nx_cram_memctl_as is -- CRAM driver (async+page mode)
generic (
READ0DELAY : positive := 2; -- read word 0 delay in clock cycles
READ1DELAY : positive := 2; -- read word 1 delay in clock cycles
@@ -144,14 +146,13 @@ entity n2_cram_memctl_as is -- CRAM driver (async+page mode)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16 -- cram: data lines
);
end n2_cram_memctl_as;
end nx_cram_memctl_as;
architecture syn of n2_cram_memctl_as is
architecture syn of nx_cram_memctl_as is
type state_type is (
s_idle, -- s_idle: wait for req
@@ -300,7 +301,6 @@ begin
O_MEM_ADV_N <= '0';
O_MEM_CLK <= '0';
O_MEM_CRE <= '0';
O_FLA_CE_N <= '1';
proc_regs: process (CLK)
begin

80
rtl/bplib/nxcramlib/nxcramlib.vhd Normal file
View File

@@ -0,0 +1,80 @@
-- $Id: nxcramlib.vhd 433 2011-11-27 22:04:39Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: nxcramlib
-- Description: Nexys 2/3 CRAM drivers
--
-- Dependencies: -
-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-26 433 1.0 Initial version (extracted from nexys2lib)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package nxcramlib is
component nx_cram_dummy is -- CRAM protection dummy
port (
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16 -- cram: data lines
);
end component;
component nx_cram_memctl_as is -- CRAM driver (async+page mode)
generic (
READ0DELAY : positive := 2; -- read word 0 delay in clock cycles
READ1DELAY : positive := 2; -- read word 1 delay in clock cycles
WRITEDELAY : positive := 3); -- write delay in clock cycles
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
REQ : in slbit; -- request
WE : in slbit; -- write enable
BUSY : out slbit; -- controller busy
ACK_R : out slbit; -- acknowledge read
ACK_W : out slbit; -- acknowledge write
ACT_R : out slbit; -- signal active read
ACT_W : out slbit; -- signal active write
ADDR : in slv22; -- address (32 bit word address)
BE : in slv4; -- byte enable
DI : in slv32; -- data in (memory view)
DO : out slv32; -- data out (memory view)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16 -- cram: data lines
);
end component;
end package nxcramlib;