From f40108cb95af3fb77cddb783fda5b8dbd5fc178c Mon Sep 17 00:00:00 2001 From: wfjm Date: Sun, 7 Oct 2018 08:48:24 +0200 Subject: [PATCH] drop DM_STAT_SY, add DM_STAT_CA and cache monitoring --- doc/CHANGELOG.md | 8 +- rtl/w11a/pdp11.vhd | 36 +- rtl/w11a/pdp11_cache.vhd | 44 ++- rtl/w11a/pdp11_sequencer.vhd | 25 +- rtl/w11a/pdp11_sys70.vhd | 71 ++-- rtl/w11a/pdp11_tmu.vhd | 27 +- rtl/w11a/pdp11_tmu_sb.vhd | 11 +- rtl/w11a/tb/tbd_pdp11core.vhd | 13 +- tools/bin/tmuconv | 34 +- tools/tbench/w11a_pcnt/test_pcnt_basics.tcl | 41 +-- tools/tbench/w11a_pcnt/test_pcnt_codes.tcl | 359 ++++++++++++++++++++ tools/tbench/w11a_pcnt/test_pcnt_regs.tcl | 10 +- tools/tbench/w11a_pcnt/w11a_pcnt_all.dat | 3 +- tools/tcl/rw11/dmpcnt.tcl | 28 +- 14 files changed, 579 insertions(+), 131 deletions(-) create mode 100644 tools/tbench/w11a_pcnt/test_pcnt_codes.tcl diff --git a/doc/CHANGELOG.md b/doc/CHANGELOG.md index 6deef34e..b3ce1567 100644 --- a/doc/CHANGELOG.md +++ b/doc/CHANGELOG.md @@ -49,7 +49,13 @@ The full set of tests is only run for tagged releases. ### Changes - sys_w11_n4: reduce cache from 64 to 32 kB to keep timing closure - changes for DM_STAT_* signals (debug and monitoring) - - DM_STAT_SE: add cpbusy and idec + - DM_STAT_SE: add elements cpbusy,idec,pcload + - DM_STAT_CA: added, used for cache monitoring + - DM_STAT_SY: removed, now replaced by DM_STAT_CA +- pdp11_sys70: instantiate pdp11_dmpcnt, setup performance counter sigs +- pdp11_sequencer: drive DM_STAT_SE.(cpbusy,idec,pcload) +- pdp11_cache: drop CHIT, add DM_STAT_CA port, add detailed monitoring +- pdp11_tmu(_sb): use DM_STAT_CA instead of DM_STAT_SY - RtclRw11Unit: fix for clang: M_virt() now public - backend code review: - use for C++ compiles also `-Wpedantic` diff --git a/rtl/w11a/pdp11.vhd b/rtl/w11a/pdp11.vhd index b1aa87e4..ca7bb9d2 100644 --- a/rtl/w11a/pdp11.vhd +++ b/rtl/w11a/pdp11.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11.vhd 1051 2018-09-29 15:29:11Z mueller $ +-- $Id: pdp11.vhd 1053 2018-10-06 20:34:52Z mueller $ -- -- Copyright 2006-2018 by Walter F.J. Mueller -- @@ -20,6 +20,8 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2018-10-05 1053 1.6.9 drop DM_STAT_SY; add DM_STAT_CA, use in pdp11_cache +-- add DM_STAT_SE.pcload -- 2018-09-29 1051 1.6.8 add pdp11_dmpcnt; add DM_STAT_SE.(cpbusy,idec) -- 2017-04-22 884 1.6.7 dm_stat_se: add idle; pdp11_dmcmon: add SNUM generic -- 2016-12-26 829 1.6.6 BUGFIX: psw init with pri=0, as on real 11/70 @@ -610,12 +612,14 @@ package pdp11 is istart : slbit; -- instruction start idec : slbit; -- instruction decode idone : slbit; -- instruction done + pcload : slbit; -- PC loaded (flow change) vfetch : slbit; -- vector fetch snum : slv8; -- current state number end record dm_stat_se_type; constant dm_stat_se_init : dm_stat_se_type := ( - '0','0','0','0','0','0', -- idle,cpbusy,istart,idec,idone,vfetch + '0','0', -- idle,cpbusy + '0','0','0','0','0', -- istart,idec,idone,pcload,vfetch (others=>'0') -- snum ); @@ -695,14 +699,20 @@ package pdp11 is '0','0' -- susp... ); - type dm_stat_sy_type is record -- debug and monitor status - system - chit : slbit; -- cache hit - dummy : slbit; -- ... sorry records must have two ... - end record dm_stat_sy_type; + type dm_stat_ca_type is record -- debug and monitor status - cache + rd : slbit; -- read request + wr : slbit; -- write request + rdhit : slbit; -- read hit + wrhit : slbit; -- write hit + rdmem : slbit; -- read memory + wrmem : slbit; -- write memory + rdwait : slbit; -- read wait + wrwait : slbit; -- write wait + end record dm_stat_ca_type; - constant dm_stat_sy_init : dm_stat_sy_type := ( - '0', -- chit - '0' + constant dm_stat_ca_init : dm_stat_ca_type := ( + '0','0','0','0', -- rd,wr,rdhit,wrhit + '0','0','0','0' -- rdmem,wrmem,rdwait,wrwait ); -- rbus interface definitions ------------------------------------------------ @@ -1076,7 +1086,6 @@ component pdp11_cache is -- cache EM_MREQ : in em_mreq_type; -- em request EM_SRES : out em_sres_type; -- em response FMISS : in slbit; -- force miss - CHIT : out slbit; -- cache hit flag MEM_REQ : out slbit; -- memory: request MEM_WE : out slbit; -- memory: write enable MEM_BUSY : in slbit; -- memory: controller busy @@ -1084,7 +1093,8 @@ component pdp11_cache is -- cache MEM_ADDR : out slv20; -- memory: address MEM_BE : out slv4; -- memory: byte enable MEM_DI : out slv32; -- memory: data in (memory view) - MEM_DO : in slv32 -- memory: data out (memory view) + MEM_DO : in slv32; -- memory: data out (memory view) + DM_STAT_CA : out dm_stat_ca_type -- debug and monitor status - cache ); end component; @@ -1124,7 +1134,7 @@ component pdp11_tmu is -- trace and monitor unit DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath DM_STAT_VM : in dm_stat_vm_type; -- debug and monitor status - vmbox DM_STAT_CO : in dm_stat_co_type; -- debug and monitor status - core - DM_STAT_SY : in dm_stat_sy_type -- debug and monitor status - system + DM_STAT_CA : in dm_stat_ca_type -- debug and monitor status - cache ); end component; @@ -1140,7 +1150,7 @@ component pdp11_tmu_sb is -- trace and mon. unit; simbus wrapper DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath DM_STAT_VM : in dm_stat_vm_type; -- debug and monitor status - vmbox DM_STAT_CO : in dm_stat_co_type; -- debug and monitor status - core - DM_STAT_SY : in dm_stat_sy_type -- debug and monitor status - system + DM_STAT_CA : in dm_stat_ca_type -- debug and monitor status - cache ); end component; diff --git a/rtl/w11a/pdp11_cache.vhd b/rtl/w11a/pdp11_cache.vhd index 05f00906..60e61c41 100644 --- a/rtl/w11a/pdp11_cache.vhd +++ b/rtl/w11a/pdp11_cache.vhd @@ -1,6 +1,6 @@ --- $Id: pdp11_cache.vhd 984 2018-01-02 20:56:27Z mueller $ +-- $Id: pdp11_cache.vhd 1053 2018-10-06 20:34:52Z mueller $ -- --- Copyright 2008-2016 by Walter F.J. Mueller +-- Copyright 2008-2018 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,21 +18,22 @@ -- Dependencies: memlib/ram_2swsr_rfirst_gen -- Test bench: - -- Target Devices: generic --- Tool versions: ise 8.2-14.7; viv 2014.4-2016.1; ghdl 0.18-0.33 +-- Tool versions: ise 8.2-14.7; viv 2014.4-2018.2; ghdl 0.18-0.34 -- -- Synthesis results -- clw = cache line width (tag+data) -- eff = efficiency (fraction of used BRAM colums) -- - 2016-03-22 (r750) with viv 2015.4 for xc7a100t-1 --- TWIDTH flop lutl lutm RAMB36 RAMB18 bram clw eff --- 9 43 106 0 0 5 2.5 45 100% --- 8 43 109 0 5 0 5.0 44 97% --- 7 43 107 0 10 4 12.0 43 89% --- 6 43 106 0 19 4 21.0 42 100% --- 5 58! 106 0 41 0 41.0 41 100% +-- TWIDTH size flop lutl lutm RAMB36 RAMB18 bram clw eff +-- 9 8k 43 106 0 0 5 2.5 45 100% +-- 8 16k 43 109 0 5 0 5.0 44 97% +-- 7 32k 43 107 0 10 4 12.0 43 89% +-- 6 64k 43 106 0 19 4 21.0 42 100% +-- 5 128k 58! 106 0 41 0 41.0 41 100% -- -- Revision History: -- Date Rev Version Comment +-- 2018-10-06 1053 1.2 drop CHIT, use DM_STAT_CA, detailed monitoring -- 2016-05-22 767 1.1.1 don't init N_REGS (vivado fix for fsm inference) -- 2016-03-22 751 1.1 now configurable size (8,16,32,64,128 kB) -- 2011-11-18 427 1.0.3 now numeric_std clean @@ -60,7 +61,6 @@ entity pdp11_cache is -- cache EM_MREQ : in em_mreq_type; -- em request EM_SRES : out em_sres_type; -- em response FMISS : in slbit; -- force miss - CHIT : out slbit; -- cache hit flag MEM_REQ : out slbit; -- memory: request MEM_WE : out slbit; -- memory: write enable MEM_BUSY : in slbit; -- memory: controller busy @@ -68,7 +68,8 @@ entity pdp11_cache is -- cache MEM_ADDR : out slv20; -- memory: address MEM_BE : out slv4; -- memory: byte enable MEM_DI : out slv32; -- memory: data in (memory view) - MEM_DO : in slv32 -- memory: data out (memory view) + MEM_DO : in slv32; -- memory: data out (memory view) + DM_STAT_CA : out dm_stat_ca_type -- debug and monitor status - cache ); end pdp11_cache; @@ -287,8 +288,8 @@ begin variable iackr : slbit := '0'; variable iackw : slbit := '0'; - variable ichit : slbit := '0'; variable iosel : slv2 := "11"; + variable istat : dm_stat_ca_type := dm_stat_ca_init; variable imem_reqr : slbit := '0'; variable imem_reqw : slbit := '0'; @@ -335,11 +336,12 @@ begin iackr := '0'; iackw := '0'; - ichit := '0'; iosel := "11"; -- default to ext. mem data -- this prevents U's from cache bram's -- to propagate to dout in beginning... + istat := dm_stat_ca_init; + imem_reqr := '0'; imem_reqw := '0'; imem_be := r.be; @@ -375,13 +377,18 @@ begin imem_be := "1111"; -- mem read: all 4 bytes if EM_MREQ.cancel = '0' then if FMISS='0' and itagok='1' and ivalok='1' then -- read tag&val hit + istat.rd := '1'; -- moni read request (hit) iackr := '1'; -- signal read acknowledge - ichit := '1'; -- signal cache hit + istat.rdhit := '1'; -- moni read hit n.state := s_idle; -- next: back to idle else -- read miss if MEM_BUSY = '0' then -- if mem not busy + istat.rd := '1'; -- moni read request (!hit & !wait) imem_reqr :='1'; -- request mem read + istat.rdmem := '1'; -- moni mem read n.state := s_rmiss; -- next: rmiss, wait for mem data + else -- else mem busy + istat.wrwait := '1'; -- moni mem busy end if; end if; else @@ -395,6 +402,7 @@ begin icmem_val_dib := "1111"; -- cache update: all valid icmem_dat_dib := MEM_DO; -- cache update: data from mem icmem_dat_web := "1111"; -- cache update: write all 4 bytes + istat.rdwait := '1'; -- moni read wait if MEM_ACK_R = '1' then -- mem data valid iackr := '1'; -- signal read acknowledge icmem_tag_ceb := '1'; -- access cache tag port B @@ -407,14 +415,20 @@ begin icmem_dat_dib := icmem_dat_doa; -- cache restore: last state if EM_MREQ.cancel = '0' then -- request ok if MEM_BUSY = '0' then -- if mem not busy + istat.wr := '1'; -- moni write request if itagok = '0' then -- if write tag miss icmem_dat_ceb := '1'; -- access cache (invalidate) icmem_dat_web := not r.be; -- write missed bytes icmem_val_dib := "0000"; -- invalidate missed bytes + else + istat.wrhit := '1'; -- moni write hit end if; imem_reqw := '1'; -- write back to main memory + istat.wrmem := '1'; -- moni mem write iackw := '1'; -- and done n.state := s_idle; -- next: back to idle + else -- else mem busy + istat.wrwait := '1'; -- moni mem busy end if; else -- request canceled -> restore @@ -470,7 +484,7 @@ begin when others => null; end case; - CHIT <= ichit; + DM_STAT_CA <= istat; MEM_REQ <= imem_reqr or imem_reqw; MEM_WE <= imem_reqw; diff --git a/rtl/w11a/pdp11_sequencer.vhd b/rtl/w11a/pdp11_sequencer.vhd index 1b9978b0..105c0939 100644 --- a/rtl/w11a/pdp11_sequencer.vhd +++ b/rtl/w11a/pdp11_sequencer.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11_sequencer.vhd 1051 2018-09-29 15:29:11Z mueller $ +-- $Id: pdp11_sequencer.vhd 1053 2018-10-06 20:34:52Z mueller $ -- -- Copyright 2006-2018 by Walter F.J. Mueller -- @@ -22,7 +22,7 @@ -- -- Revision History: -- Date Rev Version Comment --- 2018-09-29 1051 1.6.10 add DM_STAT_SE.(cpbusy,idec) +-- 2018-10-06 1053 1.6.10 add DM_STAT_SE.(cpbusy,idec,pcload) -- 2017-04-23 885 1.6.9 not sys_conf_dmscnt: set SNUM from state category; -- change waitsusp logic; add WAIT to idm_idone -- 2016-12-27 831 1.6.8 CPUERR now cleared with creset @@ -370,11 +370,12 @@ begin variable int_pending : slbit := '0'; -- an interrupt is pending - variable idm_idle : slbit := '0'; -- idle for dm_stat_se - variable idm_cpbusy : slbit := '0'; -- cpbusy for dm_stat_se - variable idm_idec : slbit := '0'; -- idec for dm_stat_se - variable idm_idone : slbit := '0'; -- idone for dm_stat_se - variable idm_vfetch : slbit := '0'; -- vfetch for dm_stat_se + variable idm_idle : slbit := '0'; -- idle for dm_stat_se + variable idm_cpbusy : slbit := '0'; -- cpbusy for dm_stat_se + variable idm_idec : slbit := '0'; -- idec for dm_stat_se + variable idm_idone : slbit := '0'; -- idone for dm_stat_se + variable idm_pcload : slbit := '0'; -- pcload for dm_stat_se + variable idm_vfetch : slbit := '0'; -- vfetch for dm_stat_se alias SRCMOD : slv2 is IREG(11 downto 10); -- src register mode high alias SRCDEF : slbit is IREG(9); -- src register mode defered @@ -626,6 +627,7 @@ begin idm_cpbusy := '0'; idm_idec := '0'; idm_idone := '0'; + idm_pcload := '0'; idm_vfetch := '0'; imemok := false; @@ -1620,6 +1622,7 @@ begin ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT ndpcntl.gpr_adst := c_gpr_pc; ndpcntl.gpr_we := '1'; -- load PC with reg(dst) + idm_pcload := '1'; -- signal flow change nstate := s_op_rts_pop; when s_op_rts_pop => -- ----------------------------------- @@ -1688,6 +1691,7 @@ begin idm_idone := '1'; -- instruction done if brcond = brcode(0) then -- this coding creates redundant code ndpcntl.gpr_we := '1'; -- but synthesis optimizes this way ! + idm_pcload := '1'; -- signal flow change do_fork_next(nstate, nstatus, nmmumoni); else do_fork_next_pref(nstate, nstatus, ndpcntl, nvmcntl, nmmumoni); @@ -1710,6 +1714,7 @@ begin ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT ndpcntl.gpr_adst := c_gpr_pc; ndpcntl.gpr_we := '1'; -- load PC with r5 + idm_pcload := '1'; -- signal flow change nstate := s_op_mark_pop; when s_op_mark_pop => -- ----------------------------------- @@ -1750,6 +1755,7 @@ begin ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT ndpcntl.gpr_adst := c_gpr_pc; ndpcntl.gpr_we := '1'; + idm_pcload := '1'; -- signal flow change idm_idone := '1'; -- instruction done do_fork_next(nstate, nstatus, nmmumoni); -- fetch next @@ -1997,6 +2003,7 @@ begin ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT ndpcntl.gpr_adst := c_gpr_pc; ndpcntl.gpr_we := '1'; -- load PC with dsta + idm_pcload := '1'; -- signal flow change idm_idone := '1'; -- instruction done do_fork_next(nstate, nstatus, nmmumoni); -- fetch next @@ -2009,6 +2016,7 @@ begin nstate := s_trap_10; -- trap 10 like 11/70 else ndpcntl.gpr_we := '1'; -- load PC with dsta + idm_pcload := '1'; -- signal flow change idm_idone := '1'; -- instruction done do_fork_next(nstate, nstatus, nmmumoni); -- fetch next end if; @@ -2266,6 +2274,7 @@ begin if imemok then nstatus.do_intrsv := '0'; -- signal end of rsv ndpcntl.gpr_we := '1'; -- load new PC + idm_pcload := '1'; -- signal flow change do_fork_next(nstate, nstatus, nmmumoni); -- ??? end if; @@ -2309,6 +2318,7 @@ begin ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT ndpcntl.gpr_adst := c_gpr_pc; ndpcntl.gpr_we := '1'; -- load new PC + idm_pcload := '1'; -- signal flow change idm_idone := '1'; -- instruction done if R_IDSTAT.op_rtt = '1' then -- if RTT instruction nstate := s_ifetch; -- force fetch @@ -2425,6 +2435,7 @@ begin DM_STAT_SE.istart <= nmmumoni.istart; DM_STAT_SE.idec <= idm_idec; DM_STAT_SE.idone <= idm_idone; + DM_STAT_SE.pcload <= idm_pcload; DM_STAT_SE.vfetch <= idm_vfetch; end process proc_next; diff --git a/rtl/w11a/pdp11_sys70.vhd b/rtl/w11a/pdp11_sys70.vhd index 8b7b95c7..9c3b7cf8 100644 --- a/rtl/w11a/pdp11_sys70.vhd +++ b/rtl/w11a/pdp11_sys70.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11_sys70.vhd 1051 2018-09-29 15:29:11Z mueller $ +-- $Id: pdp11_sys70.vhd 1053 2018-10-06 20:34:52Z mueller $ -- -- Copyright 2015-2018 by Walter F.J. Mueller -- @@ -35,6 +35,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2018-10-06 1053 1.2.3 drop DM_STAT_SY; add DM_STAT_CA; use _SE.pcload -- 2018-09-29 1051 1.2.2 add pdp11_dmpcnt -- 2017-04-22 884 1.2.1 pdp11_dmcmon: use SNUM and AWIDTH generics -- 2016-03-22 750 1.2 pdp11_cache now configurable size @@ -116,7 +117,6 @@ architecture syn of pdp11_sys70 is signal HM_ENA : slbit := '0'; signal MEM70_FMISS : slbit := '0'; signal CACHE_FMISS : slbit := '0'; - signal CACHE_CHIT : slbit := '0'; signal HBPT : slbit := '0'; @@ -124,7 +124,7 @@ architecture syn of pdp11_sys70 is signal DM_STAT_DP_L : dm_stat_dp_type := dm_stat_dp_init; signal DM_STAT_VM : dm_stat_vm_type := dm_stat_vm_init; signal DM_STAT_CO : dm_stat_co_type := dm_stat_co_init; - signal DM_STAT_SY : dm_stat_sy_type := dm_stat_sy_init; + signal DM_STAT_CA : dm_stat_ca_type := dm_stat_ca_init; signal IB_MREQ_M : ib_mreq_type := ib_mreq_init; signal IB_SRES_M : ib_sres_type := ib_sres_init; @@ -187,20 +187,20 @@ begin generic map ( TWIDTH => sys_conf_cache_twidth) port map ( - CLK => CLK, - GRESET => GRESET_L, - EM_MREQ => EM_MREQ, - EM_SRES => EM_SRES, - FMISS => CACHE_FMISS, - CHIT => CACHE_CHIT, - MEM_REQ => MEM_REQ, - MEM_WE => MEM_WE, - MEM_BUSY => MEM_BUSY, - MEM_ACK_R => MEM_ACK_R, - MEM_ADDR => MEM_ADDR, - MEM_BE => MEM_BE, - MEM_DI => MEM_DI, - MEM_DO => MEM_DO + CLK => CLK, + GRESET => GRESET_L, + EM_MREQ => EM_MREQ, + EM_SRES => EM_SRES, + FMISS => CACHE_FMISS, + MEM_REQ => MEM_REQ, + MEM_WE => MEM_WE, + MEM_BUSY => MEM_BUSY, + MEM_ACK_R => MEM_ACK_R, + MEM_ADDR => MEM_ADDR, + MEM_BE => MEM_BE, + MEM_DI => MEM_DI, + MEM_DO => MEM_DO, + DM_STAT_CA => DM_STAT_CA ); MEM70: pdp11_mem70 @@ -208,7 +208,7 @@ begin CLK => CLK, CRESET => BRESET_L, HM_ENA => HM_ENA, - HM_VAL => CACHE_CHIT, + HM_VAL => DM_STAT_CA.rdhit, CACHE_FMISS => MEM70_FMISS, IB_MREQ => IB_MREQ_M, IB_SRES => IB_SRES_MEM70 @@ -298,7 +298,7 @@ begin signal PERFSIG : slv32 := (others=>'0'); begin proc_sig: process (CP_STAT_L, DM_STAT_SE, DM_STAT_DP_L, DM_STAT_DP_L.psw, - DM_STAT_VM.vmcntl, DM_STAT_VM.vmstat, RB_MREQ, RB_SRES_L, + DM_STAT_CA, RB_MREQ, RB_SRES_L, DM_STAT_VM.ibmreq, DM_STAT_VM.ibsres) variable isig : slv32 := (others=>'0'); begin @@ -326,21 +326,18 @@ begin end if; isig(6) := DM_STAT_SE.idec; -- cpu_idec - isig(7) := DM_STAT_SE.vfetch; -- cpu_vfetch - isig(8) := EI_ACKM_L; -- cpu_irupt (not counting PIRQ!) - if DM_STAT_DP_L.gpr_adst = c_gpr_pc and DM_STAT_DP_L.gpr_we = '1' then - isig(9) := '1'; -- cpu_pcload - end if; + isig(7) := DM_STAT_SE.pcload; -- cpu_pcload + isig(8) := DM_STAT_SE.vfetch; -- cpu_vfetch + isig(9) := EI_ACKM_L; -- cpu_irupt (not counting PIRQ!) - -- hack to roughly emulate cache request data - isig(10) := DM_STAT_VM.vmcntl.req and not DM_STAT_VM.vmcntl.wacc;-- ca_rd - isig(11) := DM_STAT_VM.vmcntl.req and DM_STAT_VM.vmcntl.wacc;-- ca_wr - isig(12) := CACHE_CHIT; -- ca_rdhit - isig(13) := '0'; -- ca_wrhit - isig(14) := '0'; -- ca_rdmem - isig(15) := '0'; -- ca_wrmem - isig(16) := '0'; -- ca_rdwait - isig(17) := '0'; -- ca_wrwait + isig(10) := DM_STAT_CA.rd; -- ca_rd + isig(11) := DM_STAT_CA.wr; -- ca_wr + isig(12) := DM_STAT_CA.rdhit; -- ca_rdhit + isig(13) := DM_STAT_CA.wrhit; -- ca_wrhit + isig(14) := DM_STAT_CA.rdmem; -- ca_rdmem + isig(15) := DM_STAT_CA.wrmem; -- ca_wrmem + isig(16) := DM_STAT_CA.rdwait; -- ca_rdwait + isig(17) := DM_STAT_CA.wrwait; -- ca_wrwait if DM_STAT_VM.ibmreq.aval='1' then if DM_STAT_VM. ibsres.busy='0' then @@ -369,7 +366,7 @@ begin isig(28) := '0'; -- ext_rlrdback isig(29) := '0'; -- ext_rlwrbusy isig(30) := '0'; -- ext_rlwrback - isig(31) := '1'; -- usec + isig(31) := '1'; -- usec (now clock) PERFSIG <= isig; end process proc_sig; @@ -381,7 +378,7 @@ begin VERS => slv(to_unsigned(1, 8)), -- counter layout version -- 33222222222211111111110000000000 -- 10987654321098765432109876543210 - CENA => "10000000111111000001111111111111") -- counter enables + CENA => "10000000111111111111111111111111") -- counter enables port map ( CLK => CLK, RESET => RESET, @@ -416,8 +413,6 @@ begin EI_ACKM <= EI_ACKM_L; DM_STAT_DP <= DM_STAT_DP_L; - DM_STAT_SY.chit <= CACHE_CHIT; - -- synthesis translate_off TMU : pdp11_tmu_sb @@ -428,7 +423,7 @@ begin DM_STAT_DP => DM_STAT_DP_L, DM_STAT_VM => DM_STAT_VM, DM_STAT_CO => DM_STAT_CO, - DM_STAT_SY => DM_STAT_SY + DM_STAT_CA => DM_STAT_CA ); -- synthesis translate_on diff --git a/rtl/w11a/pdp11_tmu.vhd b/rtl/w11a/pdp11_tmu.vhd index 986d9490..ad001d34 100644 --- a/rtl/w11a/pdp11_tmu.vhd +++ b/rtl/w11a/pdp11_tmu.vhd @@ -1,6 +1,6 @@ --- $Id: pdp11_tmu.vhd 984 2018-01-02 20:56:27Z mueller $ +-- $Id: pdp11_tmu.vhd 1053 2018-10-06 20:34:52Z mueller $ -- --- Copyright 2008-2016 by Walter F.J. Mueller +-- Copyright 2008-2018 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -19,10 +19,11 @@ -- -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: ghdl 0.18-0.33 +-- Tool versions: viv 2016.2-2018.2; ghdl 0.18-0.34 -- -- Revision History: -- Date Rev Version Comment +-- 2018-10-05 1053 1.3.1 use DM_STAT_CA instead of DM_STAT_SY -- 2016-12-28 833 1.3 open tmu_ofile only when used -- 2015-07-03 697 1.2.1 adapt to new DM_STAT_SY/DM_STAT_VM -- 2015-05-03 674 1.2 start/stop/suspend overhaul @@ -57,7 +58,7 @@ entity pdp11_tmu is -- trace and monitor unit DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath DM_STAT_VM : in dm_stat_vm_type; -- debug and monitor status - vmbox DM_STAT_CO : in dm_stat_co_type; -- debug and monitor status - core - DM_STAT_SY : in dm_stat_sy_type -- debug and monitor status - system + DM_STAT_CA : in dm_stat_ca_type -- debug and monitor status - cache ); end pdp11_tmu; @@ -136,7 +137,14 @@ begin write(oline, string'(" co.suspint:b")); write(oline, string'(" co.suspext:b")); - write(oline, string'(" sy.chit:b")); + write(oline, string'(" ca.rd:b")); + write(oline, string'(" ca.wr:b")); + write(oline, string'(" ca.rdhit:b")); + write(oline, string'(" ca.wrhit:b")); + write(oline, string'(" ca.rdmem:b")); + write(oline, string'(" ca.wrmem:b")); + write(oline, string'(" ca.rdwait:b")); + write(oline, string'(" ca.wrwait:b")); writeline(ofile, oline); end if; @@ -226,7 +234,14 @@ begin write(oline, DM_STAT_CO.suspint, right, 2); write(oline, DM_STAT_CO.suspext, right, 2); - write(oline, DM_STAT_SY.chit, right, 2); + write(oline, DM_STAT_CA.rd, right, 2); + write(oline, DM_STAT_CA.wr, right, 2); + write(oline, DM_STAT_CA.rdhit, right, 2); + write(oline, DM_STAT_CA.wrhit, right, 2); + write(oline, DM_STAT_CA.rdmem, right, 2); + write(oline, DM_STAT_CA.wrmem, right, 2); + write(oline, DM_STAT_CA.rdwait, right, 2); + write(oline, DM_STAT_CA.wrwait, right, 2); writeline(ofile, oline); end if; diff --git a/rtl/w11a/pdp11_tmu_sb.vhd b/rtl/w11a/pdp11_tmu_sb.vhd index 766c9e83..219342fd 100644 --- a/rtl/w11a/pdp11_tmu_sb.vhd +++ b/rtl/w11a/pdp11_tmu_sb.vhd @@ -1,6 +1,6 @@ --- $Id: pdp11_tmu_sb.vhd 984 2018-01-02 20:56:27Z mueller $ +-- $Id: pdp11_tmu_sb.vhd 1053 2018-10-06 20:34:52Z mueller $ -- --- Copyright 2009-2015 by Walter F.J. Mueller +-- Copyright 2009-2018 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -17,9 +17,10 @@ -- -- Dependencies: simbus -- Test bench: - --- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31 +-- Tool versions: xst 8.1-14.7; viv 2016.2-2018.2; ghdl 0.18-0.34 -- Revision History: -- Date Rev Version Comment +-- 2018-10-05 1053 1.0.2 use DM_STAT_CA instead of DM_STAT_SY -- 2015-11-01 712 1.0.1 use sbcntl_sbf_tmu -- 2009-05-10 214 1.0 Initial version ------------------------------------------------------------------------------ @@ -40,7 +41,7 @@ entity pdp11_tmu_sb is -- trace and mon. unit; simbus wrapper DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath DM_STAT_VM : in dm_stat_vm_type; -- debug and monitor status - vmbox DM_STAT_CO : in dm_stat_co_type; -- debug and monitor status - core - DM_STAT_SY : in dm_stat_sy_type -- debug and monitor status - system + DM_STAT_CA : in dm_stat_ca_type -- debug and monitor status - cache ); end pdp11_tmu_sb; @@ -63,7 +64,7 @@ begin DM_STAT_DP => DM_STAT_DP, DM_STAT_VM => DM_STAT_VM, DM_STAT_CO => DM_STAT_CO, - DM_STAT_SY => DM_STAT_SY + DM_STAT_CA => DM_STAT_CA ); end sim; diff --git a/rtl/w11a/tb/tbd_pdp11core.vhd b/rtl/w11a/tb/tbd_pdp11core.vhd index e6f13114..733b49a5 100644 --- a/rtl/w11a/tb/tbd_pdp11core.vhd +++ b/rtl/w11a/tb/tbd_pdp11core.vhd @@ -1,6 +1,6 @@ --- $Id: tbd_pdp11core.vhd 984 2018-01-02 20:56:27Z mueller $ +-- $Id: tbd_pdp11core.vhd 1053 2018-10-06 20:34:52Z mueller $ -- --- Copyright 2007-2015 by Walter F.J. Mueller +-- Copyright 2007-2018 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -26,7 +26,7 @@ -- To test: pdp11_core -- -- Target Devices: generic --- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 +-- Tool versions: xst 8.2-14.7; viv 2016.2-2018.2; ghdl 0.18-0.34 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri @@ -41,6 +41,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2018-10-05 1053 1.6.3 use DM_STAT_CA instead of DM_STAT_SY -- 2015-11-01 712 1.6.2 use sbcntl_sbf_tmu -- 2015-07-03 697 1.6.1 adapt to new DM_STAT_(SY|VM) -- 2015-05-03 674 1.6 start/stop/suspend overhaul @@ -127,7 +128,7 @@ architecture syn of tbd_pdp11core is signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init; signal DM_STAT_VM : dm_stat_vm_type := dm_stat_vm_init; signal DM_STAT_CO : dm_stat_co_type := dm_stat_co_init; - signal DM_STAT_SY : dm_stat_sy_type := dm_stat_sy_init; + signal DM_STAT_CA : dm_stat_ca_type := dm_stat_ca_init; begin @@ -216,7 +217,7 @@ begin DISPREG => open ); - DM_STAT_SY.chit <= '0'; + DM_STAT_CA <= dm_stat_ca_init; -- synthesis translate_off TMU : pdp11_tmu_sb @@ -227,7 +228,7 @@ begin DM_STAT_DP => DM_STAT_DP, DM_STAT_VM => DM_STAT_VM, DM_STAT_CO => DM_STAT_CO, - DM_STAT_SY => DM_STAT_SY + DM_STAT_CA => DM_STAT_CA ); -- synthesis translate_on diff --git a/tools/bin/tmuconv b/tools/bin/tmuconv index 9d8ba2ae..ee0a2d09 100755 --- a/tools/bin/tmuconv +++ b/tools/bin/tmuconv @@ -1,7 +1,7 @@ #!/usr/bin/perl -w -# $Id: tmuconv 985 2018-01-03 08:59:40Z mueller $ +# $Id: tmuconv 1053 2018-10-06 20:34:52Z mueller $ # -# Copyright 2008-2015 by Walter F.J. Mueller +# Copyright 2008-2018 by Walter F.J. Mueller # # This program is free software; you may redistribute and/or modify it under # the terms of the GNU General Public License as published by the Free @@ -14,6 +14,7 @@ # # Revision History: # Date Rev Version Comment +# 2018-10-05 1053 1.1.2 use 'ca.*' instead of 'sy.*' fields # 2015-11-01 712 1.1.1 BUGFIX: fix '.' handling for br/sob instructions # BUGFIX: correct xor (now r,dst, and not src,r) # br/sob offsets now octal; assume --t_id if no opts @@ -71,7 +72,14 @@ # co.cpususp:b # co.suspint:b # co.suspext:b -# sy.chit:b +# ca.rd:b +# ca.wr:b +# ca.rdhit:b +# ca.wrhit:b +# ca.rdmem:b +# ca.wrmem:b +# ca.rdwait:b +# ca.wrwait:b # use 5.14.0; # require Perl 5.14 or higher @@ -140,7 +148,14 @@ my $ind_vm_emsres_ack_r; my $ind_vm_emsres_ack_w; my $ind_vm_emsres_dout; -my $ind_sy_chit; +my $ind_ca_rd; +my $ind_ca_wr; +my $ind_ca_rdhit; +my $ind_ca_wrhit; +my $ind_ca_rdmem; +my $ind_ca_wrmem; +my $ind_ca_rdwait; +my $ind_ca_wrwait; my @pdp11_opcode_tbl = ( {code=>0000000, mask=>0000000, name=>"halt", type=>"0arg"}, @@ -530,7 +545,14 @@ sub do_file { $ind_vm_emsres_ack_w = $name{'vm.emsres.ack_w'}->{ind}; $ind_vm_emsres_dout = $name{'vm.emsres.dout'}->{ind}; - $ind_sy_chit = $name{'sy.chit'}->{ind}; + $ind_ca_rd = $name{'ca.rd'}->{ind}; + $ind_ca_wr = $name{'ca.wr'}->{ind}; + $ind_ca_rdhit = $name{'ca.rdhit'}->{ind}; + $ind_ca_wrhit = $name{'ca.wrhit'}->{ind}; + $ind_ca_rdmem = $name{'ca.rdmem'}->{ind}; + $ind_ca_wrmem = $name{'ca.wrmem'}->{ind}; + $ind_ca_rdwait = $name{'ca.rdwait'}->{ind}; + $ind_ca_wrwait = $name{'ca.wrwait'}->{ind}; } else { @val_last = @val_curr; @@ -684,7 +706,7 @@ sub do_file { $val_curr[$ind_vm_emmreq_cancel], $val_curr[$ind_vm_emsres_ack_r], $val_curr[$ind_vm_emsres_ack_w], - $val_curr[$ind_sy_chit]; + $val_curr[$ind_ca_rdhit]; if ($val_curr[$ind_vm_emmreq_cancel]) { $emreq_str .= " cancel"; $emcurr_we = undef; diff --git a/tools/tbench/w11a_pcnt/test_pcnt_basics.tcl b/tools/tbench/w11a_pcnt/test_pcnt_basics.tcl index d39e3d74..70391fb1 100644 --- a/tools/tbench/w11a_pcnt/test_pcnt_basics.tcl +++ b/tools/tbench/w11a_pcnt/test_pcnt_basics.tcl @@ -1,16 +1,16 @@ -# $Id: test_pcnt_basics.tcl 1050 2018-09-23 15:46:42Z mueller $ +# $Id: test_pcnt_basics.tcl 1053 2018-10-06 20:34:52Z mueller $ # # Copyright 2018- by Walter F.J. Mueller # License disclaimer see License.txt in $RETROBASE directory # # Revision History: # Date Rev Version Comment -# 2018-09-23 1450 1.0 Initial version +# 2018-09-23 1050 1.0 Initial version # # Test basic perf counter functionality # ---------------------------------------------------------------------------- -rlc log "test_pcnt_regs: test register response ------------------------------" +rlc log "test_pcnt_basics: test basic functionality --------------------------" if {[$cpu get haspcnt] == 0} { rlc log " test_pcnt_regs-W: no pcnt unit found, test aborted" @@ -20,13 +20,13 @@ if {[$cpu get haspcnt] == 0} { # -- Section A --------------------------------------------------------------- rlc log " A: simple loop code ---------------------------------------" -cpu0 ldasm -lst lst -sym sym { +$cpu ldasm -lst lst -sym sym { . = 1000 stack: -start: clr r0 - mov #32.,r1 -1$: inc r0 - sob r1,1$ +start: clr r1 + mov #32.,r0 +1$: inc r1 + sob r0,1$ halt stop: } @@ -40,7 +40,7 @@ $cpu cp \ # run code rw11::asmrun $cpu sym rw11::asmwait $cpu sym -rw11::asmtreg $cpu r0 32 r1 0 +rw11::asmtreg $cpu r0 0 r1 32 # stop pcnt $cpu cp \ -wreg pc.cntl [regbld rw11::PC_CNTL {func "STO"}] \ @@ -52,11 +52,11 @@ $cpu cp \ # 4 =0 cpu_sm # 5 =0 cpu_um # 6 67 cpu_inst -# 7 =0 cpu_vfetch -# 8 =0 cpu_irupt -# 9 33 cpu_pcload +# 7 31 cpu_pcload +# 8 =0 cpu_vfetch +# 9 =0 cpu_irupt rlc log " A2: test random access (ainc=0) --------------------" -# read pc(6) twice, (9) once, check status +# read pc(6) twice, (9) once, (7) one, check status $cpu cp \ -wreg pc.cntl [regbldkv rw11::PC_CNTL func "LOA" caddr 6 ainc 0] \ -rreg pc.stat -edata [regbldkv rw11::PC_STAT caddr 6 ainc 0] \ @@ -70,10 +70,13 @@ $cpu cp \ -rreg pc.stat -edata [regbldkv rw11::PC_STAT caddr 6 waddr 0 ainc 0] \ -wreg pc.cntl [regbldkv rw11::PC_CNTL func "LOA" caddr 9 ainc 0] \ -rreg pc.stat -edata [regbldkv rw11::PC_STAT caddr 9 ainc 0] \ - -rreg pc.data -edata 33 \ - -rreg pc.stat -edata [regbldkv rw11::PC_STAT caddr 9 waddr 1 ainc 0] \ -rreg pc.data -edata 0 \ - -rreg pc.stat -edata [regbldkv rw11::PC_STAT caddr 9 waddr 0 ainc 0] + -wreg pc.cntl [regbldkv rw11::PC_CNTL func "LOA" caddr 7 ainc 0] \ + -rreg pc.stat -edata [regbldkv rw11::PC_STAT caddr 7 ainc 0] \ + -rreg pc.data -edata 31 \ + -rreg pc.stat -edata [regbldkv rw11::PC_STAT caddr 7 waddr 1 ainc 0] \ + -rreg pc.data -edata 0 \ + -rreg pc.stat -edata [regbldkv rw11::PC_STAT caddr 7 waddr 0 ainc 0] rlc log " A3: test sequential access (ainc=1) ----------------" # read pc(6) to pc(9) check status @@ -84,11 +87,11 @@ $cpu cp \ -rreg pc.stat -edata [regbldkv rw11::PC_STAT caddr 6 waddr 1 ainc 1] \ -rreg pc.data -edata 0 \ -rreg pc.stat -edata [regbldkv rw11::PC_STAT caddr 7 waddr 0 ainc 1] \ + -rreg pc.data -edata 31 \ -rreg pc.data -edata 0 \ -rreg pc.data -edata 0 \ -rreg pc.data -edata 0 \ -rreg pc.data -edata 0 \ - -rreg pc.data -edata 33 \ -rreg pc.stat -edata [regbldkv rw11::PC_STAT caddr 9 waddr 1 ainc 1] \ -rreg pc.data -edata 0 \ -rreg pc.stat -edata [regbldkv rw11::PC_STAT caddr 10 waddr 0 ainc 1] @@ -98,7 +101,7 @@ rlc log " A3: test block access (ainc=1) ---------------------" $cpu cp \ -wreg pc.cntl [regbldkv rw11::PC_CNTL func "LOA" caddr 3 ainc 1] \ -rreg pc.stat -edata [regbldkv rw11::PC_STAT caddr 3 ainc 1] \ - -rblk pc.data 14 -edata {0 0 0 0 0 0 67 0 0 0 0 0 33 0} \ + -rblk pc.data 14 -edata {0 0 0 0 0 0 67 0 31 0 0 0 0 0} \ -rreg pc.stat -edata [regbldkv rw11::PC_STAT caddr 10 waddr 0 ainc 1] #rlc log " A4: test clear -------------------------------------" @@ -106,5 +109,5 @@ $cpu cp \ -wreg pc.cntl [regbldkv rw11::PC_CNTL func "CLR"] \ -wreg pc.cntl [regbldkv rw11::PC_CNTL func "LOA" caddr 3 ainc 1] \ -rreg pc.stat -edata [regbldkv rw11::PC_STAT caddr 3 ainc 1] \ - -rblk pc.data 14 -edata {0 0 0 0 0 0 0 0 0 0 0 0 0 0} \ + -rblk pc.data 14 -edata {0 0 0 0 0 0 0 0 0 0 0 0 0 0} \ -rreg pc.stat -edata [regbldkv rw11::PC_STAT caddr 10 waddr 0 ainc 1] diff --git a/tools/tbench/w11a_pcnt/test_pcnt_codes.tcl b/tools/tbench/w11a_pcnt/test_pcnt_codes.tcl new file mode 100644 index 00000000..add4765a --- /dev/null +++ b/tools/tbench/w11a_pcnt/test_pcnt_codes.tcl @@ -0,0 +1,359 @@ +# $Id: test_pcnt_codes.tcl 1053 2018-10-06 20:34:52Z mueller $ +# +# Copyright 2018- by Walter F.J. Mueller +# License disclaimer see License.txt in $RETROBASE directory +# +# Revision History: +# Date Rev Version Comment +# 2018-10-06 1053 1.0 Initial version +# +# Test perf counter functionality with test codes + +# ---------------------------------------------------------------------------- +rlc log "test_pcnt_codes: test counters --------------------------------------" + +if {[$cpu get haspcnt] == 0} { + rlc log " test_pcnt_regs-W: no pcnt unit found, test aborted" + return +} + +# define tmpproc for execute test +proc tmpproc_dotest {cpu code args} { + # compile and load code + $cpu cp -creset + $cpu ldasm -lst lst -sym sym $code + + # clear and start dmpcnt + $cpu cp \ + -wreg pc.cntl [regbld rw11::PC_CNTL {func "CLR"}] \ + -wreg pc.cntl [regbld rw11::PC_CNTL {func "STA"}] + + # run code + rw11::asmrun $cpu sym + rw11::asmwait $cpu sym + + # determine pcnt index range to read + set imin 31 + set imax 0 + foreach {nam val} $args { + if {! [info exists rw11::pcnt_cindex($nam)]} { + rlc log "FAIL: invalid counter name '$nam'" + rlc errcnt -inc + return + } + set i $rw11::pcnt_cindex($nam) + set imin [expr {min($imin,$i)}] + set imax [expr {max($imax,$i)}] + } + set nwrd [expr {2*($imax-$imin+1)}] + if {$nwrd <= 0} { + rlc log "FAIL: no counters to inspect" + rlc errcnt -inc + return + } + + # stop dmpcnt and read counters + $cpu cp \ + -wreg pc.cntl [regbld rw11::PC_CNTL {func "STO"}] \ + -wreg pc.cntl [regbldkv rw11::PC_CNTL func "LOA" caddr $imin ainc 1] \ + -rreg pc.stat -edata [regbldkv rw11::PC_STAT caddr $imin waddr 0 ainc 1] \ + -rblk pc.data $nwrd pcnt + + ## puts [rw11::pc_printraw] + + # inspect counters + foreach {nam exp} $args { + set i0 [expr {2*($rw11::pcnt_cindex($nam)-$imin)}] + set i1 [expr {$i0+1}] + set v [expr {[lindex $pcnt $i0] + 65536.*[lindex $pcnt $i1]}] + if {$exp >= 0} { + if {$v != $exp} { + rlc log -bare \ + [format "FAIL: $nam expect == $exp, found %1.0f" $v] + rlc errcnt -inc + } + } else { + if {$v <= -$exp} { + rlc log -bare \ + [format "FAIL: $nam expect >= %d, found %1.0f" [expr {-$exp}] $v] + rlc errcnt -inc + } + } + } +} + +# -- Section A --------------------------------------------------------------- +rlc log " A: plain kernel mode codes---------------------------------" + +rlc log " A1: plain sob loop ---------------------------------" +set code { + . = 1000 +stack: +start: mov #32.,r0 +1$: sob r0,1$ + halt +stop: +} + +# cpu_idec: 34 = 32(sob) + 2(mov+halt) +# ca_rd: 35 = 2(mov) + 32(sob) + 1(halt) +tmpproc_dotest $cpu $code \ + cpu_km_prix 0 \ + cpu_km_pri0 -1 \ + cpu_km_wait 0 \ + cpu_sm 0 \ + cpu_um 0 \ + cpu_idec 34 \ + cpu_vfetch 0 \ + cpu_irupt 0 \ + cpu_pcload 31 \ + ca_rd 35 \ + ca_wr 0 \ + ca_rdhit 35 \ + ca_wrhit 0 \ + ca_rdmem 0 \ + ca_wrmem 0 + +rlc log " A2: sob + inc R loop -------------------------------" +set code { + . = 1000 +stack: +start: mov #32.,r0 + clr r1 +1$: inc r1 + sob r0,1$ + halt +stop: +} + +# cpu_idec: 67 = 64(inc+sob) + 2(mov+clr+halt) +# ca_rd: 68 = 3(mov+clr) + 64(inc+sob) + 1(halt) +tmpproc_dotest $cpu $code \ + cpu_km_prix 0 \ + cpu_km_pri0 -1 \ + cpu_km_wait 0 \ + cpu_sm 0 \ + cpu_um 0 \ + cpu_idec 67 \ + cpu_pcload 31 \ + cpu_vfetch 0 \ + cpu_irupt 0 \ + ca_rd 68 \ + ca_wr 0 \ + ca_rdhit 68 \ + ca_wrhit 0 \ + ca_rdmem 0 \ + ca_wrmem 0 + +rlc log " A3: sob + inc mem loop -----------------------------" +set code { + . = 1000 +stack: +start: mov #32.,r0 + clr cnt +1$: inc cnt + sob r0,1$ + halt +stop: +cnt: .word 0 +} + +# cpu_idec: 67 = 64(inc+sob) + 2(mov+clr+halt) +# ca_rd: 133 = 4(mov+clr) + 128(inc+sob) + 1(halt) +tmpproc_dotest $cpu $code \ + cpu_km_prix 0 \ + cpu_km_pri0 -1 \ + cpu_km_wait 0 \ + cpu_sm 0 \ + cpu_um 0 \ + cpu_idec 67 \ + cpu_pcload 31 \ + cpu_vfetch 0 \ + cpu_irupt 0 \ + ca_rd 133 \ + ca_wr 33 \ + ca_rdhit 133 \ + ca_wrhit 33 \ + ca_rdmem 0 \ + ca_wrmem 33 + +rlc log " A4: dec+bne+inc @#ibus loop (test ibus access) -----" +# use usr d page addr register (16 bit read/write) as easy ibus target +set code { + .include |lib/defs_mmu.mac| + . = 1000 +stack: +start: mov #32.,r0 + clr @#udpar +1$: inc @#udpar + dec r0 + bne 1$ + halt +stop: +cnt: .word 0 +} + +# cpu_idec: 99 = 96(inc+dec+bne) + 3(mov+clr+halt) +# ca_rd: 101 = 4(mov+clr) + 128(inc+dec+bne) + 1(halt) +tmpproc_dotest $cpu $code \ + cpu_km_prix 0 \ + cpu_km_pri0 -1 \ + cpu_km_wait 0 \ + cpu_sm 0 \ + cpu_um 0 \ + cpu_idec 99 \ + cpu_pcload 31 \ + cpu_vfetch 0 \ + cpu_irupt 0 \ + ca_rd 133 \ + ca_wr 0 \ + ca_rdhit 133 \ + ca_wrhit 0 \ + ca_rdmem 0 \ + ca_wrmem 0 \ + ib_rd 32 \ + ib_wr 33 + +# -- Section B --------------------------------------------------------------- +rlc log " B: test kern pri>0, super and user mode -------------------" + +rlc log " B1: kernel pri > 0 ---------------------------------" +set code { + .include |lib/defs_cpu.mac| + . = 1000 +stack: +start: mov #cp.pr7,@#cp.psw + nop + nop + nop + nop + mov #cp.pr0,@#cp.psw + halt +stop: +} + +tmpproc_dotest $cpu $code \ + cpu_km_prix -1 \ + cpu_km_pri0 -4 \ + cpu_km_wait 0 \ + cpu_sm 0 \ + cpu_um 0 \ + cpu_idec 7 \ + cpu_vfetch 0 \ + cpu_irupt 0 \ + cpu_pcload 0 \ + ca_rd 11 \ + ca_wr 0 \ + ca_rdhit 11 \ + ca_wrhit 0 \ + ca_rdmem 0 \ + ca_wrmem 0 + +rlc log " B2: supervisor mode --------------------------------" +set code { + .include |lib/defs_cpu.mac| + . = 1000 +stack: +start: mov #cp.cms,@#cp.psw + nop + nop + nop + nop + mov #cp.pr0,@#cp.psw + halt +stop: +} + +tmpproc_dotest $cpu $code \ + cpu_km_prix 0 \ + cpu_km_pri0 -1 \ + cpu_km_wait 0 \ + cpu_sm -4 \ + cpu_um 0 \ + cpu_idec 7 \ + cpu_vfetch 0 \ + cpu_irupt 0 \ + cpu_pcload 0 \ + ca_rd 11 \ + ca_wr 0 \ + ca_rdhit 11 \ + ca_wrhit 0 \ + ca_rdmem 0 \ + ca_wrmem 0 + +rlc log " B3: user mode --------------------------------------" +set code { + .include |lib/defs_cpu.mac| + . = 1000 +stack: +start: mov #cp.cmu,@#cp.psw + nop + nop + nop + nop + mov #cp.pr0,@#cp.psw + halt +stop: +} + +tmpproc_dotest $cpu $code \ + cpu_km_prix 0 \ + cpu_km_pri0 -1 \ + cpu_km_wait 0 \ + cpu_sm 0 \ + cpu_um -4 \ + cpu_idec 7 \ + cpu_vfetch 0 \ + cpu_irupt 0 \ + cpu_pcload 0 \ + ca_rd 11 \ + ca_wr 0 \ + ca_rdhit 11 \ + ca_wrhit 0 \ + ca_rdmem 0 \ + ca_wrmem 0 + +# -- Section C --------------------------------------------------------------- +rlc log " C: test vector fetch --------------------------------------" + +rlc log " C1: vector via trap instruction --------------------" +set code { + .include |lib/vec_cpucatch.mac| + . = 1000 +stack: +start: mov #vh.trp,@#v..trp + mov #vh.emt,@#v..emt + clr r0 + trap 1 + emt 1 + trap 2 + emt 2 + halt +stop: + +vh.trp: rti + +vh.emt: inc r0 + rti +} + +# cpu_idec: 14 = 8(main) +2*1(trap) + 2*2(emt) +# ca_rd: 34 = 14+4(code) + 4*2(trap+emt) + 4*2(rti) +# ca_wr: 34 = 2(code) + 4*2(trap+emt) +# ca_pcload: 8 = 4(trap+emt) + 4(rti) +tmpproc_dotest $cpu $code \ + cpu_km_prix 0 \ + cpu_km_pri0 -1 \ + cpu_km_wait 0 \ + cpu_sm 0 \ + cpu_um 0 \ + cpu_idec 14 \ + cpu_vfetch 4 \ + cpu_irupt 0 \ + cpu_pcload 8 \ + ca_rd 34 \ + ca_wr 10 \ + ca_rdhit 34 \ + ca_wrhit 10 \ + ca_rdmem 0 \ + ca_wrmem 10 diff --git a/tools/tbench/w11a_pcnt/test_pcnt_regs.tcl b/tools/tbench/w11a_pcnt/test_pcnt_regs.tcl index 559d0241..ffea6d83 100644 --- a/tools/tbench/w11a_pcnt/test_pcnt_regs.tcl +++ b/tools/tbench/w11a_pcnt/test_pcnt_regs.tcl @@ -1,11 +1,12 @@ -# $Id: test_pcnt_regs.tcl 1050 2018-09-23 15:46:42Z mueller $ +# $Id: test_pcnt_regs.tcl 1053 2018-10-06 20:34:52Z mueller $ # # Copyright 2018- by Walter F.J. Mueller # License disclaimer see License.txt in $RETROBASE directory # # Revision History: # Date Rev Version Comment -# 2018-09-23 1450 1.0 Initial version +# 2018-10-06 1053 1.0 Initial version +# 2018-09-23 1050 0.1 First draft # # Test register response @@ -21,14 +22,15 @@ if {[$cpu get haspcnt] == 0} { rlc log " A basic register access tests -----------------------------" rlc log " A1: write cntl, read stat --------------------------" -# test start,stop works and run flag follows +# test start,stop works and run flag follows; test cntl readable (no check) $cpu cp \ -wreg pc.cntl [regbld rw11::PC_CNTL {func "CLR"}] \ -rreg pc.stat -edata [regbld rw11::PC_STAT] \ -wreg pc.cntl [regbld rw11::PC_CNTL {func "STA"}] \ -rreg pc.stat -edata [regbld rw11::PC_STAT run] \ -wreg pc.cntl [regbld rw11::PC_CNTL {func "STO"}] \ - -rreg pc.stat -edata [regbld rw11::PC_STAT] + -rreg pc.stat -edata [regbld rw11::PC_STAT] \ + -rreg pc.cntl # test that load works, caddr and ainc follow in status, and that clr clears $cpu cp \ -wreg pc.cntl [regbldkv rw11::PC_CNTL func "LOA" caddr 0x07 ainc 0] \ diff --git a/tools/tbench/w11a_pcnt/w11a_pcnt_all.dat b/tools/tbench/w11a_pcnt/w11a_pcnt_all.dat index 50ba53f3..5058f774 100644 --- a/tools/tbench/w11a_pcnt/w11a_pcnt_all.dat +++ b/tools/tbench/w11a_pcnt/w11a_pcnt_all.dat @@ -1,7 +1,8 @@ -# $Id: w11a_pcnt_all.dat 1050 2018-09-23 15:46:42Z mueller $ +# $Id: w11a_pcnt_all.dat 1053 2018-10-06 20:34:52Z mueller $ # ## steering file for all w11a_pcnt tests # test_pcnt_regs.tcl test_pcnt_basics.tcl +test_pcnt_codes.tcl # diff --git a/tools/tcl/rw11/dmpcnt.tcl b/tools/tcl/rw11/dmpcnt.tcl index d66f1ed1..9f567dc8 100644 --- a/tools/tcl/rw11/dmpcnt.tcl +++ b/tools/tcl/rw11/dmpcnt.tcl @@ -1,4 +1,4 @@ -# $Id: dmpcnt.tcl 1051 2018-09-29 15:29:11Z mueller $ +# $Id: dmpcnt.tcl 1053 2018-10-06 20:34:52Z mueller $ # # Copyright 2018- by Walter F.J. Mueller # @@ -13,7 +13,7 @@ # # Revision History: # Date Rev Version Comment -# 2018-09-29 1051 1.0 Initial version +# 2018-10-06 1053 1.0 Initial version # 2018-09-23 1050 0.1 First draft # @@ -31,14 +31,22 @@ namespace eval rw11 { regdsc PC_STAT {ainc 15} {caddr 13 5} {waddr 8} {run 0} # preliminary handling of counter names, hack in first version - variable pcnt_cnames {cpu_cpbusy cpu_km_prix cpu_km_pri0 cpu_km_wait \ - cpu_sm cpu_um cpu_idec cpu_vfetch \ - cpu_irupt cpu_pcload ca_rd ca_wr \ - ca_rdhit -ca_wrhit -ca_rdmem -ca_wrmem \ - -ca_rdwait -ca_wrwait ib_rd ib_wr \ - ib_busy rb_rd rb_wr rb_busy \ - -ext_rdrhit -ext_wrrhit -ext_wrflush -ext_rlrdbusy \ - -ext_rlrdback -ext_rlwrbusy -ext_rlwrback clock} + variable pcnt_cnames [list cpu_cpbusy cpu_km_prix cpu_km_pri0 cpu_km_wait \ + cpu_sm cpu_um cpu_idec cpu_pcload \ + cpu_vfetch cpu_irupt ca_rd ca_wr \ + ca_rdhit ca_wrhit ca_rdmem ca_wrmem \ + ca_rdwait ca_wrwait ib_rd ib_wr \ + ib_busy rb_rd rb_wr rb_busy \ + ext_rdrhit ext_wrrhit ext_wrflush ext_rlrdbusy \ + ext_rlrdback ext_rlwrbusy ext_rlwrback clock] + variable pcnt_cindex + set tmp_ind 0 + foreach {nam} $pcnt_cnames { + set pcnt_cindex($nam) $tmp_ind + incr tmp_ind + } + unset tmp_ind + # # pc_setup: rmap definitions for dmpcnt #