mirror of
https://github.com/wfjm/w11.git
synced 2026-05-02 06:26:30 +00:00
- interim release w11a_V0.55 (untagged)
- added xon/xoff (software flow control) support to serport library - added test systems for serport verification - use new serport stack in sys_w11a_* and sys_tst_rlink_* systems
This commit is contained in:
Walter F.J. Mueller
4
rtl/vlib/genlib/cdc_pulse.vbom
Normal file
4
rtl/vlib/genlib/cdc_pulse.vbom
Normal file
@@ -0,0 +1,4 @@
|
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# libs
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../slvtypes.vhd
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# design
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cdc_pulse.vhd
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117
rtl/vlib/genlib/cdc_pulse.vhd
Normal file
117
rtl/vlib/genlib/cdc_pulse.vhd
Normal file
@@ -0,0 +1,117 @@
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-- $Id: cdc_pulse.vhd 426 2011-11-18 18:14:08Z mueller $
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||||
--
|
||||
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
||||
--
|
||||
-- This program is free software; you may redistribute and/or modify it under
|
||||
-- the terms of the GNU General Public License as published by the Free
|
||||
-- Software Foundation, either version 2, or at your option any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful, but
|
||||
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
|
||||
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
-- for complete details.
|
||||
--
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------------------------------------------------------------------------------
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-- Module Name: cdc_pulse - syn
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||||
-- Description: clock domain cross for pulse
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--
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||||
-- Dependencies: -
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-- Test bench: -
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||||
-- Target Devices: generic
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||||
-- Tool versions: xst 13.1; ghdl 0.29
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||||
-- Revision History:
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||||
-- Date Rev Version Comment
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-- 2011-11-09 422 1.0 Initial version
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--
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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entity cdc_pulse is -- clock domain cross for pulse
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generic (
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POUT_SINGLE : boolean := false; -- if true: single cycle pout
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BUSY_WACK : boolean := false); -- if true: busy waits for ack
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port (
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CLKM : in slbit; -- clock master
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RESET : in slbit := '0'; -- M|reset
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CLKS : in slbit; -- clock slave
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PIN : in slbit; -- M|pulse in
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BUSY : out slbit; -- M|busy
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POUT : out slbit -- S|pulse out
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);
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end entity cdc_pulse;
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architecture syn of cdc_pulse is
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signal R_REQ : slbit := '0';
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signal R_REQ_C : slbit := '0';
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signal R_ACK : slbit := '0';
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signal R_ACK_C : slbit := '0';
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signal R_ACK_S : slbit := '0';
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begin
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proc_master: process (CLKM)
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begin
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if rising_edge(CLKM) then
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if RESET = '1' then
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R_REQ <= '0';
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else
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if PIN = '1' then
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R_REQ <= '1';
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||||
elsif R_ACK_S = '1' then
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R_REQ <= '0';
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end if;
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end if;
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R_ACK_C <= R_ACK;
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R_ACK_S <= R_ACK_C;
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end if;
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end process proc_master;
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|
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proc_slave: process (CLKS)
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begin
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if rising_edge(CLKS) then
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R_REQ_C <= R_REQ;
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R_ACK <= R_REQ_C;
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end if;
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end process proc_slave;
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SINGLE1: if POUT_SINGLE = true generate
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signal R_ACK_1 : slbit := '0';
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signal R_POUT : slbit := '0';
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begin
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proc_pout: process (CLKS)
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begin
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if rising_edge(CLKS) then
|
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R_ACK_1 <= R_ACK;
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if R_ACK='1' and R_ACK_1='0' then
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R_POUT <= '1';
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else
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R_POUT <= '0';
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end if;
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end if;
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end process proc_pout;
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POUT <= R_POUT;
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end generate SINGLE1;
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SINGLE0: if POUT_SINGLE = false generate
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begin
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POUT <= R_ACK;
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end generate SINGLE0;
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|
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BUSY1: if BUSY_WACK = true generate
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begin
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BUSY <= R_REQ or R_ACK_S;
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end generate BUSY1;
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BUSY0: if BUSY_WACK = false generate
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begin
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BUSY <= R_REQ;
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end generate BUSY0;
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end syn;
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4
rtl/vlib/genlib/gray2bin_gen.vbom
Normal file
4
rtl/vlib/genlib/gray2bin_gen.vbom
Normal file
@@ -0,0 +1,4 @@
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# libs
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../slvtypes.vhd
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# design
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gray2bin_gen.vhd
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64
rtl/vlib/genlib/gray2bin_gen.vhd
Normal file
64
rtl/vlib/genlib/gray2bin_gen.vhd
Normal file
@@ -0,0 +1,64 @@
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-- $Id: gray2bin_gen.vhd 418 2011-10-23 20:11:40Z mueller $
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--
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-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
||||
--
|
||||
-- This program is free software; you may redistribute and/or modify it under
|
||||
-- the terms of the GNU General Public License as published by the Free
|
||||
-- Software Foundation, either version 2, or at your option any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful, but
|
||||
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
|
||||
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
-- for complete details.
|
||||
--
|
||||
------------------------------------------------------------------------------
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-- Module Name: gray2bin_gen - syn
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-- Description: Gray code to binary converter
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--
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-- Dependencies: -
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-- Test bench: tb/tb_debounce_gen
|
||||
-- Target Devices: generic
|
||||
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
|
||||
-- Revision History:
|
||||
-- Date Rev Version Comment
|
||||
-- 2007-12-26 106 1.0 Initial version
|
||||
------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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entity gray2bin_gen is -- gray->bin converter, generic vector
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generic (
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DWIDTH : positive := 4); -- data width
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port (
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DI : in slv(DWIDTH-1 downto 0); -- gray code input
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DO : out slv(DWIDTH-1 downto 0) -- binary code output
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);
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end entity gray2bin_gen;
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architecture syn of gray2bin_gen is
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begin
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proc_comb: process (DI)
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variable ido : slv(DWIDTH-1 downto 0);
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begin
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ido := (others=>'0');
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ido(DWIDTH-1) := DI(DWIDTH-1);
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for i in DWIDTH-2 downto 0 loop
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ido(i) := ido(i+1) xor DI(i);
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end loop;
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DO <= ido;
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end process proc_comb;
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end syn;
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|
||||
103
rtl/vlib/genlib/gray_cnt_4.vhd
Normal file
103
rtl/vlib/genlib/gray_cnt_4.vhd
Normal file
@@ -0,0 +1,103 @@
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-- $Id: gray_cnt_4.vhd 418 2011-10-23 20:11:40Z mueller $
|
||||
--
|
||||
-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
||||
--
|
||||
-- This program is free software; you may redistribute and/or modify it under
|
||||
-- the terms of the GNU General Public License as published by the Free
|
||||
-- Software Foundation, either version 2, or at your option any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful, but
|
||||
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
|
||||
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
-- for complete details.
|
||||
--
|
||||
------------------------------------------------------------------------------
|
||||
-- Module Name: gray_cnt_4 - syn
|
||||
-- Description: 4 bit Gray code counter (ROM based)
|
||||
--
|
||||
-- Dependencies: -
|
||||
-- Test bench: -
|
||||
-- Target Devices: generic
|
||||
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
|
||||
-- Revision History:
|
||||
-- Date Rev Version Comment
|
||||
-- 2007-12-26 106 1.0 Initial version
|
||||
--
|
||||
-- Some synthesis results:
|
||||
-- - 2007-12-27 ise 8.2.03 for xc3s1000-ft256-4:
|
||||
-- LUT Flop clock(xst est.)
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||||
-- 4 4 365MHz/ 2.76ns
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||||
------------------------------------------------------------------------------
|
||||
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library ieee;
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||||
use ieee.std_logic_1164.all;
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use work.slvtypes.all;
|
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|
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entity gray_cnt_4 is -- 4 bit gray code counter (ROM based)
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||||
port (
|
||||
CLK : in slbit; -- clock
|
||||
RESET : in slbit := '0'; -- reset
|
||||
CE : in slbit := '1'; -- count enable
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||||
DATA : out slv4 -- data out
|
||||
);
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end entity gray_cnt_4;
|
||||
|
||||
|
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architecture syn of gray_cnt_4 is
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||||
|
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signal R_DATA : slv4 := (others=>'0');
|
||||
signal N_DATA : slv4 := (others=>'0');
|
||||
|
||||
-- Note: in xst 8.2.03 fsm_extract="no" is needed. Otherwise an fsm is
|
||||
-- inferred. For 4 bit the coding was 'Gray', but see remarks in
|
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-- gray_cnt_5. To be save, disallow fsm inferal, enforce reg+rom.
|
||||
|
||||
attribute fsm_extract : string;
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attribute fsm_extract of R_DATA : signal is "no";
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attribute rom_style : string;
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attribute rom_style of N_DATA : signal is "distributed";
|
||||
|
||||
begin
|
||||
|
||||
proc_regs: process (CLK)
|
||||
begin
|
||||
|
||||
if rising_edge(CLK) then
|
||||
if RESET = '1' then
|
||||
R_DATA <= (others=>'0');
|
||||
elsif CE = '1' then
|
||||
R_DATA <= N_DATA;
|
||||
end if;
|
||||
end if;
|
||||
end process proc_regs;
|
||||
|
||||
proc_next: process (R_DATA)
|
||||
begin
|
||||
|
||||
N_DATA <= (others=>'0');
|
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case R_DATA is
|
||||
when "0000" => N_DATA <= "0001"; -- 0
|
||||
when "0001" => N_DATA <= "0011"; -- 1
|
||||
when "0011" => N_DATA <= "0010"; -- 2
|
||||
when "0010" => N_DATA <= "0110"; -- 3
|
||||
when "0110" => N_DATA <= "0111"; -- 4
|
||||
when "0111" => N_DATA <= "0101"; -- 5
|
||||
when "0101" => N_DATA <= "0100"; -- 6
|
||||
when "0100" => N_DATA <= "1100"; -- 7
|
||||
when "1100" => N_DATA <= "1101"; -- 8
|
||||
when "1101" => N_DATA <= "1111"; -- 9
|
||||
when "1111" => N_DATA <= "1110"; -- 10
|
||||
when "1110" => N_DATA <= "1010"; -- 11
|
||||
when "1010" => N_DATA <= "1011"; -- 12
|
||||
when "1011" => N_DATA <= "1001"; -- 13
|
||||
when "1001" => N_DATA <= "1000"; -- 14
|
||||
when "1000" => N_DATA <= "0000"; -- 15
|
||||
when others => null;
|
||||
end case;
|
||||
end process proc_next;
|
||||
|
||||
DATA <= R_DATA;
|
||||
|
||||
end syn;
|
||||
|
||||
121
rtl/vlib/genlib/gray_cnt_5.vhd
Normal file
121
rtl/vlib/genlib/gray_cnt_5.vhd
Normal file
@@ -0,0 +1,121 @@
|
||||
-- $Id: gray_cnt_5.vhd 418 2011-10-23 20:11:40Z mueller $
|
||||
--
|
||||
-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
||||
--
|
||||
-- This program is free software; you may redistribute and/or modify it under
|
||||
-- the terms of the GNU General Public License as published by the Free
|
||||
-- Software Foundation, either version 2, or at your option any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful, but
|
||||
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
|
||||
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
-- for complete details.
|
||||
--
|
||||
------------------------------------------------------------------------------
|
||||
-- Module Name: gray_cnt_5 - syn
|
||||
-- Description: 5 bit Gray code counter (ROM based)
|
||||
--
|
||||
-- Dependencies: -
|
||||
-- Test bench: -
|
||||
-- Target Devices: generic
|
||||
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
|
||||
-- Revision History:
|
||||
-- Date Rev Version Comment
|
||||
-- 2007-12-26 106 1.0 Initial version
|
||||
--
|
||||
-- Some synthesis results:
|
||||
-- - 2007-12-27 ise 8.2.03 for xc3s1000-ft256-4:
|
||||
-- LUT Flop clock(xst est.)
|
||||
-- 9 5 302MHz/ 3.31ns
|
||||
------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
use work.slvtypes.all;
|
||||
|
||||
entity gray_cnt_5 is -- 5 bit gray code counter (ROM based)
|
||||
port (
|
||||
CLK : in slbit; -- clock
|
||||
RESET : in slbit := '0'; -- reset
|
||||
CE : in slbit := '1'; -- count enable
|
||||
DATA : out slv5 -- data out
|
||||
);
|
||||
end entity gray_cnt_5;
|
||||
|
||||
|
||||
architecture syn of gray_cnt_5 is
|
||||
|
||||
signal R_DATA : slv5 := (others=>'0');
|
||||
signal N_DATA : slv5 := (others=>'0');
|
||||
|
||||
-- Note: in xst 8.2.03 fsm_extract="no" is needed. Otherwise an fsm
|
||||
-- is inferred, using 'Johnson' encoding. DATA will be deduced
|
||||
-- in a combinatorial logic, and will thus have very likely some
|
||||
-- glitches at the clock transitions, rendering the whole Gray
|
||||
-- coding useless.
|
||||
|
||||
attribute fsm_extract : string;
|
||||
attribute fsm_extract of R_DATA : signal is "no";
|
||||
attribute rom_style : string;
|
||||
attribute rom_style of N_DATA : signal is "distributed";
|
||||
|
||||
begin
|
||||
|
||||
proc_regs: process (CLK)
|
||||
begin
|
||||
|
||||
if rising_edge(CLK) then
|
||||
if RESET = '1' then
|
||||
R_DATA <= (others=>'0');
|
||||
elsif CE = '1' then
|
||||
R_DATA <= N_DATA;
|
||||
end if;
|
||||
end if;
|
||||
end process proc_regs;
|
||||
|
||||
proc_next: process (R_DATA)
|
||||
begin
|
||||
|
||||
N_DATA <= (others=>'0');
|
||||
case R_DATA is
|
||||
when "00000" => N_DATA <= "00001"; -- 0
|
||||
when "00001" => N_DATA <= "00011"; -- 1
|
||||
when "00011" => N_DATA <= "00010"; -- 2
|
||||
when "00010" => N_DATA <= "00110"; -- 3
|
||||
when "00110" => N_DATA <= "00111"; -- 4
|
||||
when "00111" => N_DATA <= "00101"; -- 5
|
||||
when "00101" => N_DATA <= "00100"; -- 6
|
||||
when "00100" => N_DATA <= "01100"; -- 7
|
||||
when "01100" => N_DATA <= "01101"; -- 8
|
||||
when "01101" => N_DATA <= "01111"; -- 9
|
||||
when "01111" => N_DATA <= "01110"; -- 10
|
||||
when "01110" => N_DATA <= "01010"; -- 11
|
||||
when "01010" => N_DATA <= "01011"; -- 12
|
||||
when "01011" => N_DATA <= "01001"; -- 13
|
||||
when "01001" => N_DATA <= "01000"; -- 14
|
||||
when "01000" => N_DATA <= "11000"; -- 15
|
||||
when "11000" => N_DATA <= "11001"; -- 16
|
||||
when "11001" => N_DATA <= "11011"; -- 17
|
||||
when "11011" => N_DATA <= "11010"; -- 18
|
||||
when "11010" => N_DATA <= "11110"; -- 19
|
||||
when "11110" => N_DATA <= "11111"; -- 20
|
||||
when "11111" => N_DATA <= "11101"; -- 21
|
||||
when "11101" => N_DATA <= "11100"; -- 22
|
||||
when "11100" => N_DATA <= "10100"; -- 23
|
||||
when "10100" => N_DATA <= "10101"; -- 24
|
||||
when "10101" => N_DATA <= "10111"; -- 25
|
||||
when "10111" => N_DATA <= "10110"; -- 26
|
||||
when "10110" => N_DATA <= "10010"; -- 27
|
||||
when "10010" => N_DATA <= "10011"; -- 28
|
||||
when "10011" => N_DATA <= "10001"; -- 29
|
||||
when "10001" => N_DATA <= "10000"; -- 30
|
||||
when "10000" => N_DATA <= "00000"; -- 31
|
||||
when others => null;
|
||||
end case;
|
||||
end process proc_next;
|
||||
|
||||
DATA <= R_DATA;
|
||||
|
||||
end syn;
|
||||
|
||||
9
rtl/vlib/genlib/gray_cnt_gen.vbom
Normal file
9
rtl/vlib/genlib/gray_cnt_gen.vbom
Normal file
@@ -0,0 +1,9 @@
|
||||
# libs
|
||||
../slvtypes.vhd
|
||||
genlib.vhd
|
||||
# components
|
||||
gray_cnt_4.vhd
|
||||
gray_cnt_5.vhd
|
||||
gray_cnt_n.vhd
|
||||
# design
|
||||
gray_cnt_gen.vhd
|
||||
90
rtl/vlib/genlib/gray_cnt_gen.vhd
Normal file
90
rtl/vlib/genlib/gray_cnt_gen.vhd
Normal file
@@ -0,0 +1,90 @@
|
||||
-- $Id: gray_cnt_gen.vhd 418 2011-10-23 20:11:40Z mueller $
|
||||
--
|
||||
-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
||||
--
|
||||
-- This program is free software; you may redistribute and/or modify it under
|
||||
-- the terms of the GNU General Public License as published by the Free
|
||||
-- Software Foundation, either version 2, or at your option any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful, but
|
||||
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
|
||||
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
-- for complete details.
|
||||
--
|
||||
------------------------------------------------------------------------------
|
||||
-- Module Name: gray_cnt_gen - syn
|
||||
-- Description: Generic width Gray code counter
|
||||
--
|
||||
-- Dependencies: -
|
||||
-- Test bench: -
|
||||
-- Target Devices: generic
|
||||
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
|
||||
-- Revision History:
|
||||
-- Date Rev Version Comment
|
||||
-- 2007-12-26 106 1.0 Initial version
|
||||
------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
use work.slvtypes.all;
|
||||
use work.genlib.all;
|
||||
|
||||
entity gray_cnt_gen is -- gray code counter, generic vector
|
||||
generic (
|
||||
DWIDTH : positive := 4); -- data width
|
||||
port (
|
||||
CLK : in slbit; -- clock
|
||||
RESET : in slbit := '0'; -- reset
|
||||
CE : in slbit := '1'; -- count enable
|
||||
DATA : out slv(DWIDTH-1 downto 0) -- data out
|
||||
);
|
||||
end entity gray_cnt_gen;
|
||||
|
||||
|
||||
architecture syn of gray_cnt_gen is
|
||||
|
||||
begin
|
||||
|
||||
assert DWIDTH>=4
|
||||
report "assert(DWIDTH>=4): only 4 or more bit width supported"
|
||||
severity failure;
|
||||
|
||||
|
||||
GRAY_4: if DWIDTH=4 generate
|
||||
begin
|
||||
CNT : gray_cnt_4
|
||||
port map (
|
||||
CLK => CLK,
|
||||
RESET => RESET,
|
||||
CE => CE,
|
||||
DATA => DATA
|
||||
);
|
||||
end generate GRAY_4;
|
||||
|
||||
GRAY_5: if DWIDTH=5 generate
|
||||
begin
|
||||
CNT : gray_cnt_5
|
||||
port map (
|
||||
CLK => CLK,
|
||||
RESET => RESET,
|
||||
CE => CE,
|
||||
DATA => DATA
|
||||
);
|
||||
end generate GRAY_5;
|
||||
|
||||
GRAY_N: if DWIDTH>5 generate
|
||||
begin
|
||||
CNT : gray_cnt_n
|
||||
generic map (
|
||||
DWIDTH => DWIDTH)
|
||||
port map (
|
||||
CLK => CLK,
|
||||
RESET => RESET,
|
||||
CE => CE,
|
||||
DATA => DATA
|
||||
);
|
||||
end generate GRAY_N;
|
||||
|
||||
end syn;
|
||||
|
||||
112
rtl/vlib/genlib/gray_cnt_n.vhd
Normal file
112
rtl/vlib/genlib/gray_cnt_n.vhd
Normal file
@@ -0,0 +1,112 @@
|
||||
-- $Id: gray_cnt_n.vhd 418 2011-10-23 20:11:40Z mueller $
|
||||
--
|
||||
-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
||||
--
|
||||
-- This program is free software; you may redistribute and/or modify it under
|
||||
-- the terms of the GNU General Public License as published by the Free
|
||||
-- Software Foundation, either version 2, or at your option any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful, but
|
||||
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
|
||||
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
-- for complete details.
|
||||
--
|
||||
------------------------------------------------------------------------------
|
||||
-- Module Name: gray_cnt_n - syn
|
||||
-- Description: Genric width Gray code counter
|
||||
--
|
||||
-- Dependencies: -
|
||||
-- Test bench: tb/tb_debounce_gen
|
||||
-- Target Devices: generic
|
||||
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
|
||||
-- Revision History:
|
||||
-- Date Rev Version Comment
|
||||
-- 2007-12-26 106 1.0 Initial version
|
||||
--
|
||||
-- Some synthesis results:
|
||||
-- - 2007-12-27 ise 8.2.03 for xc3s1000-ft256-4:
|
||||
-- DWIDTH LUT Flop clock(xst est.)
|
||||
-- 4 6 5 305MHz/ 3.28ns
|
||||
-- 5 8 6 286MHz/ 2.85ns
|
||||
-- 8 13 9 234MHz/ 4.26ns
|
||||
-- 16 56 17 149MHz/ 6.67ns
|
||||
-- 32 95 33 161MHz/ 6.19ns
|
||||
-- 64 188 68 126MHz/ 7.90ns
|
||||
------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
use work.slvtypes.all;
|
||||
use work.genlib.all;
|
||||
|
||||
entity gray_cnt_n is -- n bit gray code counter
|
||||
generic (
|
||||
DWIDTH : positive := 8); -- data width
|
||||
port (
|
||||
CLK : in slbit; -- clock
|
||||
RESET : in slbit := '0'; -- reset
|
||||
CE : in slbit := '1'; -- count enable
|
||||
DATA : out slv(DWIDTH-1 downto 0) -- data out
|
||||
);
|
||||
end entity gray_cnt_n;
|
||||
|
||||
|
||||
architecture syn of gray_cnt_n is
|
||||
|
||||
signal R_AUX : slbit := '1';
|
||||
signal R_DATA : slv(DWIDTH-1 downto 0) := (others=>'0');
|
||||
signal N_DATA : slv(DWIDTH-1 downto 0) := (others=>'0');
|
||||
|
||||
begin
|
||||
|
||||
assert DWIDTH>=3
|
||||
report "assert(DWIDTH>=3): only 3 bit or larger supported"
|
||||
severity failure;
|
||||
|
||||
proc_regs: process (CLK)
|
||||
begin
|
||||
|
||||
if rising_edge(CLK) then
|
||||
if RESET = '1' then
|
||||
R_AUX <= '1';
|
||||
R_DATA <= (others=>'0');
|
||||
elsif CE = '1' then
|
||||
R_AUX <= not R_AUX;
|
||||
R_DATA <= N_DATA;
|
||||
end if;
|
||||
end if;
|
||||
end process proc_regs;
|
||||
|
||||
proc_next: process (R_AUX, R_DATA)
|
||||
variable r : slv(DWIDTH-1 downto 0) := (others=>'0');
|
||||
variable n : slv(DWIDTH-1 downto 0) := (others=>'0');
|
||||
variable s : slbit := '0';
|
||||
begin
|
||||
|
||||
r := R_DATA;
|
||||
n := R_DATA;
|
||||
s := '1';
|
||||
|
||||
if R_AUX = '1' then
|
||||
n(0) := not r(0);
|
||||
else
|
||||
for i in 1 to DWIDTH-2 loop
|
||||
if s='1' and r(i-1)='1' then
|
||||
n(i) := not r(i);
|
||||
end if;
|
||||
s := s and not r(i-1);
|
||||
end loop;
|
||||
if s = '1' then
|
||||
n(DWIDTH-1) := r(DWIDTH-2);
|
||||
end if;
|
||||
end if;
|
||||
|
||||
N_DATA <= n;
|
||||
|
||||
end process proc_next;
|
||||
|
||||
DATA <= R_DATA;
|
||||
|
||||
end syn;
|
||||
|
||||
Reference in New Issue
Block a user