From f6ff0fa701e3ac07a1bc3d776d9c8ab1fe95ff60 Mon Sep 17 00:00:00 2001 From: wfjm Date: Tue, 29 Nov 2022 08:41:18 +0100 Subject: [PATCH] pdp11_sequencer: BUGFIX: correct mmu trap vs interrupt priority - rtl/w11a/pdp11_sequencer: BUGFIX: correct mmu trap vs interrupt priority - tools/asm-11/lib/halt_checks.mac: add htstge - tools/tcode - cpu_details.mac: add test A1.2 - cpu_mmu.mac: add test E2.1 --- doc/CHANGELOG.md | 1 + rtl/w11a/pdp11_sequencer.vhd | 15 +++--- tools/asm-11/lib/halt_checks.mac | 8 ++- tools/tcode/cpu_details.mac | 23 ++++++++- tools/tcode/cpu_mmu.mac | 89 +++++++++++++++++++++++++++++--- 5 files changed, 119 insertions(+), 17 deletions(-) diff --git a/doc/CHANGELOG.md b/doc/CHANGELOG.md index a611c350..b7d3b199 100644 --- a/doc/CHANGELOG.md +++ b/doc/CHANGELOG.md @@ -46,6 +46,7 @@ The full set of tests is only run for tagged releases. - BUGFIX: use is_kstackdst1246 also in dstr flow - BUGFIX: correct ysv flow implementation - BUGFIX: correct mmu trap handing in s_idecode + - BUGFIX: correct mmu trap vs interrupt priority - pdp11_vmbox: BUGFIX: correct red/yellow zone boundary diff --git a/rtl/w11a/pdp11_sequencer.vhd b/rtl/w11a/pdp11_sequencer.vhd index 1c77d2dc..5227c79c 100644 --- a/rtl/w11a/pdp11_sequencer.vhd +++ b/rtl/w11a/pdp11_sequencer.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11_sequencer.vhd 1321 2022-11-24 15:06:47Z mueller $ +-- $Id: pdp11_sequencer.vhd 1322 2022-11-28 19:31:57Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later -- Copyright 2006-2022 by Walter F.J. Mueller -- @@ -13,6 +13,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2022-11-28 1322 1.6.21 BUGFIX: correct mmu trap vs interrupt priority -- 2022-11-24 1321 1.6.20 BUGFIX: correct mmu trap handing in s_idecode -- 2022-11-21 1320 1.6.19 rename some rsv->ser and cpustat_type trap_->treq_; -- remove vm_cntl_type.trap_done; @@ -538,12 +539,12 @@ begin pnmmumoni : inout mmu_moni_type) is begin pnmmumoni.idone := '1'; - if unsigned(INT_PRI) > unsigned(PSW.pri) then - pnstate := s_idle; - elsif R_STATUS.treq_mmu='1' or pnstatus.treq_mmu='1' or + if R_STATUS.treq_mmu='1' or pnstatus.treq_mmu='1' or R_STATUS.treq_ysv='1' or pnstatus.treq_ysv='1' or PSW.tflag='1' then pnstate := s_trap_disp; + elsif unsigned(INT_PRI) > unsigned(PSW.pri) then + pnstate := s_idle; elsif R_STATUS.cpugo='1' and -- running R_STATUS.cpususp='0' and -- and not suspended not R_STATUS.cmdbusy='1' then -- and no cmd pending @@ -562,12 +563,12 @@ begin pndpcntl := pndpcntl; -- dummy to add driver (vivado) pnvmcntl := pnvmcntl; -- " pnmmumoni.idone := '1'; - if unsigned(INT_PRI) > unsigned(PSW.pri) then - pnstate := s_idle; - elsif R_STATUS.treq_mmu='1' or pnstatus.treq_mmu='1' or + if R_STATUS.treq_mmu='1' or pnstatus.treq_mmu='1' or R_STATUS.treq_ysv='1' or pnstatus.treq_ysv='1' or PSW.tflag='1' then pnstate := s_trap_disp; + elsif unsigned(INT_PRI) > unsigned(PSW.pri) then + pnstate := s_idle; elsif R_STATUS.cpugo='1' and -- running R_STATUS.cpususp='0' and -- and not suspended not R_STATUS.cmdbusy='1' then -- and no cmd pending diff --git a/tools/asm-11/lib/halt_checks.mac b/tools/asm-11/lib/halt_checks.mac index 2e67b9b8..56d206c7 100644 --- a/tools/asm-11/lib/halt_checks.mac +++ b/tools/asm-11/lib/halt_checks.mac @@ -1,4 +1,4 @@ -; $Id: halt_checks.mac 1316 2022-11-18 15:26:40Z mueller $ +; $Id: halt_checks.mac 1322 2022-11-28 19:31:57Z mueller $ ; SPDX-License-Identifier: GPL-3.0-or-later ; Copyright 2022- by Walter F.J. Mueller ; @@ -52,3 +52,9 @@ bne .+4 halt .endm +; tst on ge + .macro htstge,src + tst src + bge .+4 + halt + .endm diff --git a/tools/tcode/cpu_details.mac b/tools/tcode/cpu_details.mac index 1ea9595a..2919c2d9 100644 --- a/tools/tcode/cpu_details.mac +++ b/tools/tcode/cpu_details.mac @@ -1,4 +1,4 @@ -; $Id: cpu_details.mac 1320 2022-11-22 18:52:59Z mueller $ +; $Id: cpu_details.mac 1322 2022-11-28 19:31:57Z mueller $ ; SPDX-License-Identifier: GPL-3.0-or-later ; Copyright 2022- by Walter F.J. Mueller ; @@ -143,6 +143,25 @@ ta0101: mov #1000$,v..pir ; set up handler ; 9999$: iot ; end of test A1.1 ; +; Test A1.2 -- PIRQ and immediate interrupt ++++++++++++++++++++++++++ +; This test verifies that an interrupt is taken immediately after the +; write of the PIRQ register +; +ta0102: spl 0 ; ensure execution at PR0 + mov #1000$,v..pir ; set up handler + mov #cp.pr7,v..pir+2 ; which runs at pr7 + mov #pi.r03,cp.pir ; request PIRQ 3 + halt ; halt if not taken immediatly +; +1000$: clr cp.pir ; cancel all PIRQ levels + mov #1100$,(sp) ; continue + rti +; +1100$: mov #v..pir+2,v..pir; restore pirq vector catcher + clr v..pir+2 +; +9999$: iot ; end of test A1.2 +; ; Test A2: CPUERR +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ; This sub-section verifies operation of CPUERR register ; @@ -947,7 +966,7 @@ tc0103: mov #vhugen,v..iit ; set iit handler ; END OF ALL TESTS - loop closure ============================================ ; mov tstno,r0 ; hack, for easy monitoring ... - hcmpeq tstno,#23. ; all tests done ? + hcmpeq tstno,#24. ; all tests done ? ; jmp loop ; diff --git a/tools/tcode/cpu_mmu.mac b/tools/tcode/cpu_mmu.mac index 472e7f81..073a4f12 100644 --- a/tools/tcode/cpu_mmu.mac +++ b/tools/tcode/cpu_mmu.mac @@ -1,4 +1,4 @@ -; $Id: cpu_mmu.mac 1321 2022-11-24 15:06:47Z mueller $ +; $Id: cpu_mmu.mac 1322 2022-11-28 19:31:57Z mueller $ ; SPDX-License-Identifier: GPL-3.0-or-later ; Copyright 2022- by Walter F.J. Mueller ; @@ -1408,6 +1408,7 @@ td0101: ; Section E: traps and pdr aia and aiw bits ================================== ; ; Test E1: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +; Check basic MMU trap and PDR aia/aiw logic ; ; Test E1.1 -- test m0.trp, pdr aia/aiw transitions ++++++++++++++++++ ; Summary @@ -1757,7 +1758,7 @@ te0104: mov #<127.*md.plf>!md.att,kipdr5 ; enable traps (afc=4) mov #1000$,r3 ; ptr to failed landing mov #vhmmut,v..mmu ; setup MMU trap handler mov #1100$,vhvmmu - jmp @#p5base-6 ; start test code + jmp @#p5ce14 ; start test code ; 1000$: nop ; lands here if no trap halt @@ -1767,6 +1768,54 @@ te0104: mov #<127.*md.plf>!md.att,kipdr5 ; enable traps (afc=4) mov #<127.*md.plf>!md.arw,kipdr5 ; reset kipdr5 mov #v..mmu+2,v..mmu ; +9999$: iot ; end of test E1.4 +; +; Test E2: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +; Check MMU trap priority behavior +; +; common handler setup for trap and interrupt priority tests +; + mov #vhtmmu,v..mmu ; mmu trap handler + mov #cp.pr7,v..mmu+2 ; run at PR7 (lockout PIRQ) + mov #vhtpir,v..pir ; PIRQ handler + mov #cp.pr7,v..pir+2 ; run at PR7 (prevent retrigger) + mov #<127.*md.plf>!md.att,kipdr5 ; enable traps in page 5 (afc=4) +; +; Test E2.1 -- mmu trap + interrupt priority +++++++++++++++++++++++++ +; +te0201: mov #m0.ent!m0.ena,mmr0 ; enable mmu with traps ;! MMU 18 + mov #1500$,r5 ; set up data pointer +; + spl 0 ; ensure PR0 + call p5ce21 ; start probe code in page 5 +1000$: br 2000$ ; rts will land here +; +1500$: .word 0,0 ; 1st marker (MMU for movb) + .word 0,0 ; 2nd marker (PIRQ) + .word 0,0 ; 3rd marker (MMU for rts) + .word -1,-1 ; fence +; +2000$: hcmpeq #1500$+12.,r5 ; check 3 markers expected + mov #1500$,r5 + hcmpeq #250,(r5)+ ; 1st: MMU for movb + hcmpeq #p5ce21+6,(r5)+ ; PC after movb + hcmpeq #240,(r5)+ ; 2nd: PIRQ + hcmpeq #p5ce21+6,(r5)+ ; PC after movb + hcmpeq #250,(r5)+ ; 3rd: MMU for rts + hcmpeq #1000$,(r5)+ ; PC after rts (the return address) +; + reset ; mmu off ;! MMU off +; +9999$: iot ; end of test E2.1 +; +; common restore for section E2 -------------------------------------- +; + mov #<127.*md.plf>!md.arw,kipdr5 ; reset kipdr5 + mov #v..mmu+2,v..mmu ; restore v..mmu to catcher + clr v..mmu+2 + mov #v..pir+2,v..pir ; restore v..pir to catcher + clr v..pir+2 +; ; Section F: miscellaneous =================================================== ; ; Test F1: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ @@ -1880,11 +1929,11 @@ tf0102: mov #154345,@#p6base ; inititialize target ;; END OF ALL TESTS - loop closure ============================================ ; mov tstno,r0 ; hack, for easy monitoring ... - hcmpeq tstno,#20. ; all tests done ? + hcmpeq tstno,#22. ; all tests done ? ; jmp loop ; -; kernel handlers ============================================================ +; kernel handlers and helpers ================================================ ; ; vhmmua - expected mmu abort handler ++++++++++++++++++++++++++++++++++++++++ ; used to catch expected MMU aborts @@ -1939,6 +1988,28 @@ vhuemt: tst (sp)+ ; discard one word of vector push vhustp: .word vhuhlt vhuhlt: halt ; +; vhtmmu - handler for MMU trap tracing ++++++++++++++++++++++++++++++++++++++ +; Writes signature to data area (ptr in r5). +; Signature is vector address + return PC (PC to test proper context). +; Clears MMR0(trp) bit to allow further MMU traps +; +vhtmmu: htstge (r5) ; r5 at fence ? + bic #m0.trp,mmr0 ; allow further MMU traps + mov #250,(r5)+ ; track MMU vector + mov (sp),(r5)+ ; track PC + rti +; +; vhtpir - handler for PIRQ interrupt tracing ++++++++++++++++++++++++++++++++ +; Writes signature to data area (ptr in r5). +; Signature is vector address + return PC (PC to test proper context). +; Clears all PIRQ requests to prevent interrupt loop. +; +vhtpir: htstge (r5) ; r5 at fence ? + clr cp.pir ; clear all PIRQ interrupts + mov #240,(r5)+ ; track PIRQ vector + mov (sp),(r5)+ ; track PC + rti +; ; Test codes that will be mapped in user or supervisor mode ================== ; They are located in page 4 at 100000 and above and are position-independent ; code. That allows to assemble and load them together with the main code. @@ -2009,12 +2080,11 @@ vc2dat: .word 010111 .word 010333 .word 010444 ; -; Test E1.4 test code +; p5ce14 Test E1.4 test code +++++++++++++++++++++++++++++++++++++++++ ; located at border of page 4 and page 5 (touching both) -; started via @#p5base-6, therefore no explicit label ; . = p5base-6 - inc r2 ; @117772; r2=1 +p5ce14: inc r2 ; @117772; r2=1 inc r2 ; @117774; r2=2 inc r2 ; @117776; r2=3 inc r2 ; @120000; r2=4 <-- should trap here @@ -2022,5 +2092,10 @@ vc2dat: .word 010111 inc r2 ; @120004; r2=6 inc r2 ; @120006; r2=7 jmp (r3) ; return to main code +; +; p5ce21 Test E2.1 test code +++++++++++++++++++++++++++++++++++++++++ +; +p5ce21: movb #bit01,cp.pir+1 ; request PIRQ 1 + return ; and return to main flow ; .end start