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divtst: add w11a data [skip ci]

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wfjm
2022-08-17 08:38:53 +02:00
parent 6dfc0489aa
commit f77e2bef31
5 changed files with 223 additions and 16 deletions
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14
tools/tests/divtst/README.md
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@@ -1,4 +1,4 @@
## divtst: a test program testing DIV instruction response
## divtst: a program testing DIV instruction response
The `divtst` program tests the `DIV` instruction with a set of test
cases and checks whether the response agrees with the expected values.
@@ -44,8 +44,12 @@ The state of the two result registers is also not specified when V=1 is set.
In some CPUs and some cases the registers preserve the original state, in other
cases, they are written. This is flagged with two markers
```
R0MOD for R0 changed when V=1 seen
R1MOD for R1 changed when V=1 seen
R0MOD for R0 changed when V=1 seen (quotient result register)
R1MOD for R1 changed when V=1 seen (remainder result register)
```
These markers do not indicate an error, they just flag how `DIV` behaves in
these unspecified cases.
Notes:
- markers do not indicate an error, they just flag how `DIV` behaves in
these unspecified cases.
- the test `DIV` instruction uses `r0` as destination, quotient and remainder
go to `r0` and `r1`. Better naming for the flags might have been `RQMOD`
and `RRMOD`.

8
tools/tests/divtst/bsd/dotst.s
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@@ -1,4 +1,4 @@
/ $Id: dotst.s 1266 2022-07-30 17:33:07Z mueller $
/ $Id: dotst.s 1276 2022-08-12 10:25:13Z mueller $
/ SPDX-License-Identifier: GPL-3.0-or-later
/ Copyright 2014-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
/
@@ -25,7 +25,7 @@ _dotst: mov r2,-(sp) / save r2 (r0,r1 are volatile)
/ now (sp) -> saved r2
/ 2(sp) -> return address
/ 4(sp) -> 1st arg: idat
/ 6(sp) -> 2ns arg: odat
/ 6(sp) -> 2nd arg: odat
mov 4(sp), r2 / r2 = idat
@@ -42,8 +42,4 @@ _dotst: mov r2,-(sp) / save r2 (r0,r1 are volatile)
mov (sp)+,r2 / restore r2
rts pc

7
tools/tests/divtst/bsd/getpsw.s
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@@ -1,7 +1,7 @@
/ $Id: getpsw.s 1266 2022-07-30 17:33:07Z mueller $
/ $Id: getpsw.s 1276 2022-08-12 10:25:13Z mueller $
/ SPDX-License-Identifier: GPL-3.0-or-later
/ Copyright 2014-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
/
/
/ Revision History:
/ Date Rev Version Comment
/ 2014-07-20 570 1.0 Initial version
@@ -73,6 +73,3 @@ cc111x: bcs cc1111 / branch on N=1,Z=1,V=1,C=1
rts pc
cc1111: mov $017, valpsw / here N=1,Z=1,V=1,C=1
rts pc

208
tools/tests/divtst/data/2022-08-11_w11a_wfjm.log Normal file
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@@ -0,0 +1,208 @@
# test_div: test div instruction
# test basics (via testd2)
# dr>0
000000 000000 000003 : 0100 000000 000000
000000 000001 000003 : 0100 000000 000001
000000 000002 000003 : 0100 000000 000002
000000 000003 000003 : 0000 000001 000000
000000 000004 000003 : 0000 000001 000001
177777 177777 000003 : 0100 000000 177777
177777 177776 000003 : 0100 000000 177776
177777 177775 000003 : 1000 177777 000000
177777 177774 000003 : 1000 177777 177777
# dr<0
000000 000000 177775 : 0100 000000 000000
000000 000001 177775 : 0100 000000 000001
000000 000002 177775 : 0100 000000 000002
000000 000003 177775 : 1000 177777 000000
000000 000004 177775 : 1000 177777 000001
177777 177777 177775 : 0100 000000 177777
177777 177776 177775 : 0100 000000 177776
177777 177775 177775 : 0000 000001 000000
177777 177774 177775 : 0000 000001 177777
# dr==0
000000 000000 000000 : 0111 000000 000000
000000 000001 000000 : 0111 000000 000001
177777 177777 000000 : 0111 177777 177777
# test 4 quadrant basics (via testd2)
000000 000042 000005 : 0000 000006 000004
000000 000042 177773 : 1000 177772 000004
177777 177736 000005 : 1000 177772 177774
177777 177736 177773 : 0000 000006 177774
# test 4 quadrant basics (via testdqr)
000000 000042 000005 : 0000 000006 000004
000000 000042 177773 : 1000 177772 000004
177777 177736 000005 : 1000 177772 177774
177777 177736 177773 : 0000 000006 177774
# test q=100000 boundary cases (q = max neg value)
# case dd>0, dr<0 -- factor 21846
025253 000000 125252 : 1000 100000 000000
025253 000001 125252 : 1000 100000 000001
025253 052524 125252 : 1000 100000 052524
025253 052525 125252 : 1000 100000 052525
025253 052526 125252 : 0010 077777 000000 R0MOD R1MOD
025253 052527 125252 : 0010 077777 000001 R0MOD R1MOD
# case dd<0, dr>0 -- factor 21846
152525 000000 052526 : 1000 100000 000000
152524 177777 052526 : 1000 100000 177777
152524 125254 052526 : 1000 100000 125254
152524 125253 052526 : 1000 100000 125253
152524 125252 052526 : 0010 077777 000000 R0MOD R1MOD
152524 125251 052526 : 0010 077777 177777 R0MOD R1MOD
# case dd>0, dr<0 -- factor 21847
025253 100000 125251 : 1000 100000 000000
025253 100001 125251 : 1000 100000 000001
025253 152525 125251 : 1000 100000 052525
025253 152526 125251 : 1000 100000 052526
025253 152527 125251 : 0010 077777 000000 R0MOD R1MOD
025253 152530 125251 : 0010 077777 000001 R0MOD R1MOD
# case dd<0, dr>0 -- factor 21847
152524 100000 052527 : 1000 100000 000000
152524 077777 052527 : 1000 100000 177777
152524 025253 052527 : 1000 100000 125253
152524 025252 052527 : 1000 100000 125252
152524 025251 052527 : 0010 077777 000000 R0MOD R1MOD
152524 025250 052527 : 0010 077777 177777 R0MOD R1MOD
# test q=077777 boundary cases (q = max pos value)
# case dd>0, dr>0 -- factor 21846
025252 125252 052526 : 0000 077777 000000
025252 125253 052526 : 0000 077777 000001
025252 177776 052526 : 0000 077777 052524
025252 177777 052526 : 0000 077777 052525
025253 000000 052526 : 0010 025253 000000
025253 000001 052526 : 0010 025253 000001
# case dd<0, dr<0 -- factor 21846
152525 052526 125252 : 0000 077777 000000
152525 052525 125252 : 0000 077777 177777
152525 000002 125252 : 0000 077777 125254
152525 000001 125252 : 0000 077777 125253
152525 000000 125252 : 0010 152525 000000
152524 177777 125252 : 0010 152524 177777
# case dd>0, dr>0 -- factor 21847
025253 025251 052527 : 0000 077777 000000
025253 025252 052527 : 0000 077777 000001
025253 077776 052527 : 0000 077777 052525
025253 077777 052527 : 0000 077777 052526
025253 100000 052527 : 0010 025253 100000
025253 100001 052527 : 0010 025253 100001
# case dd<0, dr<0 -- factor 21847
152524 152527 125251 : 0000 077777 000000
152524 152526 125251 : 0000 077777 177777
152524 100002 125251 : 0000 077777 125253
152524 100001 125251 : 0000 077777 125252
152524 100001 125251 : 0000 077777 125252
152524 100000 125251 : 0010 152524 100000
# test dr=100000 boundary cases (dr = max neg value)
# case dd<0, q>0
177777 100000 100000 : 0000 000001 000000
177777 077777 100000 : 0000 000001 177777
177777 000001 100000 : 0000 000001 100001
177777 000000 100000 : 0000 000002 000000
177776 177777 100000 : 0000 000002 177777
177776 100001 100000 : 0000 000002 100001
177776 100000 100000 : 0000 000003 000000
177776 077777 100000 : 0000 000003 177777
177776 000001 100000 : 0000 000003 100001
177776 000000 100000 : 0000 000004 000000
177775 177777 100000 : 0000 000004 177777
177775 100001 100000 : 0000 000004 100001
177775 000000 100000 : 0000 000006 000000
140003 000000 100000 : 0000 077772 000000
140002 000000 100000 : 0000 077774 000000
140001 100000 100000 : 0000 077775 000000
140001 000000 100000 : 0000 077776 000000
140000 177777 100000 : 0000 077776 177777
140000 100001 100000 : 0000 077776 100001
140000 100000 100000 : 0000 077777 000000
140000 077777 100000 : 0000 077777 177777
140000 000001 100000 : 0000 077777 100001
# case dd>0, q<0
000000 100000 100000 : 1000 177777 000000
000000 100001 100000 : 1000 177777 000001
000000 177777 100000 : 1000 177777 077777
000001 000000 100000 : 1000 177776 000000
000001 000001 100000 : 1000 177776 000001
000001 077777 100000 : 1000 177776 077777
037777 100000 100000 : 1000 100001 000000
037777 100001 100000 : 1000 100001 000001
037777 177777 100000 : 1000 100001 077777
040000 000000 100000 : 1000 100000 000000
040000 000001 100000 : 1000 100000 000001
040000 077777 100000 : 1000 100000 077777
# test dr=077777 boundary cases (dr = max pos value)
# case dd>0, q>0
000000 077777 077777 : 0000 000001 000000
000000 100000 077777 : 0000 000001 000001
000000 177775 077777 : 0000 000001 077776
000000 177776 077777 : 0000 000002 000000
000000 177777 077777 : 0000 000002 000001
000001 077774 077777 : 0000 000002 077776
037776 100002 077777 : 0000 077776 000000
037776 100003 077777 : 0000 077776 000001
037777 000000 077777 : 0000 077776 077776
037777 000001 077777 : 0000 077777 000000
037777 000002 077777 : 0000 077777 000001
037777 077777 077777 : 0000 077777 077776
# case dd<0, q<0
177777 100001 077777 : 1000 177777 000000
177777 100000 077777 : 1000 177777 177777
177777 000003 077777 : 1000 177777 100002
177777 000002 077777 : 1000 177776 000000
177777 000001 077777 : 1000 177776 177777
177776 100004 077777 : 1000 177776 100002
140000 177777 077777 : 1000 100001 000000
140000 177776 077777 : 1000 100001 177777
140000 100001 077777 : 1000 100001 100002
140000 100000 077777 : 1000 100000 000000
140000 077777 077777 : 1000 100000 177777
140000 000002 077777 : 1000 100000 100002
# test dd max cases
# case dd>0 dr<0 near nmax*nmax+nmax-1 = +1073774591
037777 177777 100000 : 1000 100001 077777
040000 000000 100000 : 1000 100000 000000
040000 000001 100000 : 1000 100000 000001
040000 077776 100000 : 1000 100000 077776
040000 077777 100000 : 1000 100000 077777
037777 100000 100000 : 1000 100001 000000
037777 100001 100000 : 1000 100001 000001
# case dd>0 dr>0 near pmax*pmax+pmax-1 = +1073709055
037777 000000 077777 : 0000 077776 077776
037777 000001 077777 : 0000 077777 000000
037777 000002 077777 : 0000 077777 000001
037777 077776 077777 : 0000 077777 077775
037777 077777 077777 : 0000 077777 077776
037777 100000 077777 : 0010 037777 100000
037776 100001 077777 : 0000 077775 077776
# case dd<0 dr>0 near nmax*pmax+pmax-1 = -1073741822
140000 100001 077777 : 1000 100001 100002
140000 100000 077777 : 1000 100000 000000
140000 077777 077777 : 1000 100000 177777
140000 000003 077777 : 1000 100000 100003
140000 000002 077777 : 1000 100000 100002
140000 000001 077777 : 0010 077777 000000 R0MOD R1MOD
140000 000000 077777 : 0010 077777 177777 R0MOD R1MOD
# case dd<0 dr<0 near pmax*nmax+nmax-1 = -1073741823
140000 100001 100000 : 0000 077776 100001
140000 100000 100000 : 0000 077777 000000
140000 077777 100000 : 0000 077777 177777
140000 000002 100000 : 0000 077777 100002
140000 000001 100000 : 0000 077777 100001
140000 000000 100000 : 0010 140000 000000
137777 177777 100000 : 0010 137777 177777
# test late div quit cases in 2 quadrant algorithm
177777 100001 177777 : 0000 077777 000000
177777 100000 177777 : 0010 177777 100000
177777 077777 177777 : 0010 177777 077777
177777 000002 177776 : 0000 077777 000000
177777 000001 177776 : 0000 077777 177777
177777 000000 177776 : 0010 177777 000000
177776 177777 177776 : 0010 177776 177777
# test big divident overflow cases
077777 177777 000001 : 0010 077777 177777
077777 177777 000002 : 0010 077777 177777
077777 177777 177777 : 0010 077777 177777
077777 177777 177776 : 0010 077777 177777
100000 000000 000001 : 0010 100000 000000
100000 000000 000002 : 0010 100000 000000
100000 000000 177777 : 0010 100000 000000
100000 000000 177776 : 0010 100000 000000

2
tools/tests/divtst/data/README.md
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@@ -11,6 +11,7 @@ The results are available in
| [2014-08-22_1193_btq](2014-08-22_1170_btq.log) | real | 11/93 (J11) | from Johnny Billquist, node pontus |
| [2014-08-22_e11_1174_btq](2014-08-22_e11_1174_btq.log) | e11 | 11/74 | from Johnny Billquist, node mim |
| [2014-08-22_simh_1194_btq](2014-08-22_simh_1194_btq.log) | SimH | 11/94 (J11) | from Johnny Billquist, node jocke |
| [2022-08-11_w11a_wfjm](2022-08-11_w11a_wfjm.log) | | w11a | from wfjm |
The file name encodes the approximate date of data taking (relevant for
simulators which indeed change over time), the sim/CPU case, and the source
@@ -26,4 +27,5 @@ are indeed different, a good example is
177777 100000 177777 : 0110 000000 100000 real 11/70: Z=1, R0MOD
177777 100000 177777 : 0010 177777 100000 real 11/93: r0,r1 unchanged
177777 100000 177777 : 0010 100000 000000 e11 11/74: R0MOD R1MOD
177777 100000 177777 : 0010 177777 100000 w11a: r0,r1 unchanged
```