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2 Commits

Author SHA1 Message Date
wfjm
d3cce101a7 SPDX: rtl/*/*.vhd 2019-07-12 19:01:49 +02:00
wfjm
0c395856d7 add memlib/fifo_simple_dram + test benches 
- add fifo_simple_dram: simple fifo with CE/WE interface, dram based
- add test benches for fifo_simple_dram, fifo_2c_dram, and fifo_2c_dram2
- add simclkv: test bench clock generator with variable period
 2019-02-22 19:09:42 +01:00