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https://github.com/wfjm/w11.git
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226 lines
7.7 KiB
VHDL
226 lines
7.7 KiB
VHDL
-- $Id: ibdr_lp11.vhd 1181 2019-07-08 17:00:50Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2009-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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------------------------------------------------------------------------------
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-- Module Name: ibdr_lp11 - syn
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-- Description: ibus dev(rem): LP11
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--
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-- Dependencies: -
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-- Test bench: -
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-- Target Devices: generic
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-- Tool versions: ise 8.2-14.7; viv 2014.4-2018.3; ghdl 0.18-0.35
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--
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2010-10-17 333 12.1 M53d xc3s1000-4 12 35 0 24 s 5.6
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-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 11 30 0 19 s 5.8
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2019-04-24 1138 1.3.3 add csr.ir (intreq monitor)
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-- 2019-03-10 1121 1.3.2 ignore buf write if csr.err=1 for lp11_buf compat
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-- 2019-03-03 1118 1.3.1 VAL in bit 15 and 8 for lp11_buf compat
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-- 2013-05-04 515 1.3 BUGFIX: r.err was cleared in racc read !
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-- 2011-11-18 427 1.2.2 now numeric_std clean
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-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM;
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-- 2010-10-17 333 1.2 use ibus V2 interface
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-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
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-- 2009-06-21 228 1.0.1 generate interrupt locally when err=1
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-- 2009-05-30 220 1.0 Initial version
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------------------------------------------------------------------------------
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--
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-- Notes:
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-- - the ERR bit is just a status flag
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-- - no hardware interlock (DONE forced 0 when ERR=1), like in simh
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-- - also no interrupt when ERR goes 1, like in simh
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.iblib.all;
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-- ----------------------------------------------------------------------------
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entity ibdr_lp11 is -- ibus dev(rem): LP11
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-- fixed address: 177514
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- system reset
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BRESET : in slbit; -- ibus reset
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RB_LAM : out slbit; -- remote attention
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IB_MREQ : in ib_mreq_type; -- ibus request
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IB_SRES : out ib_sres_type; -- ibus response
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EI_REQ : out slbit; -- interrupt request
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EI_ACK : in slbit -- interrupt acknowledge
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);
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end ibdr_lp11;
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architecture syn of ibdr_lp11 is
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constant ibaddr_lp11 : slv16 := slv(to_unsigned(8#177514#,16));
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constant ibaddr_csr : slv1 := "0"; -- csr address offset
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constant ibaddr_buf : slv1 := "1"; -- buf address offset
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constant csr_ibf_err : integer := 15;
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constant csr_ibf_done : integer := 7;
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constant csr_ibf_ie : integer := 6;
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constant csr_ibf_ir : integer := 5;
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constant buf_ibf_val : integer := 15;
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constant buf_ibf_val8: integer := 8;
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type regs_type is record -- state registers
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ibsel : slbit; -- ibus select
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err : slbit; -- csr: error flag
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done : slbit; -- csr: done flag
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ie : slbit; -- csr: interrupt enable
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buf : slv7; -- buf:
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intreq : slbit; -- interrupt request
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end record regs_type;
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constant regs_init : regs_type := (
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'0', -- ibsel
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'1', -- err !! is set !!
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'1', -- done !! is set !!
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'0', -- ie
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(others=>'0'), -- buf
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'0' -- intreq
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);
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signal R_REGS : regs_type := regs_init;
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signal N_REGS : regs_type := regs_init;
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begin
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proc_regs: process (CLK)
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begin
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if rising_edge(CLK) then
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if BRESET = '1' then -- BRESET is 1 for system and ibus reset
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R_REGS <= regs_init;
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if RESET = '0' then -- if RESET=0 we do just an ibus reset
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R_REGS.err <= N_REGS.err; -- don't reset ERR flag
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end if;
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else
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R_REGS <= N_REGS;
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end if;
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end if;
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end process proc_regs;
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proc_next : process (R_REGS, IB_MREQ, EI_ACK)
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variable r : regs_type := regs_init;
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variable n : regs_type := regs_init;
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variable idout : slv16 := (others=>'0');
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variable ibreq : slbit := '0';
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variable ibrd : slbit := '0';
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variable ibw0 : slbit := '0';
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variable ibw1 : slbit := '0';
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variable ilam : slbit := '0';
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begin
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r := R_REGS;
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n := R_REGS;
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idout := (others=>'0');
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ibreq := IB_MREQ.re or IB_MREQ.we;
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ibrd := IB_MREQ.re;
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ibw0 := IB_MREQ.we and IB_MREQ.be0;
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ibw1 := IB_MREQ.we and IB_MREQ.be1;
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ilam := '0';
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-- ibus address decoder
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n.ibsel := '0';
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if IB_MREQ.aval='1' and
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IB_MREQ.addr(12 downto 2)=ibaddr_lp11(12 downto 2) then
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n.ibsel := '1';
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end if;
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-- ibus transactions
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if r.ibsel = '1' then
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case IB_MREQ.addr(1 downto 1) is
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when ibaddr_csr => -- CSR -- control status -------------
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idout(csr_ibf_err) := r.err;
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idout(csr_ibf_done) := r.done;
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idout(csr_ibf_ie) := r.ie;
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if IB_MREQ.racc = '0' then -- cpu ---------------------
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if ibw0 = '1' then
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n.ie := IB_MREQ.din(csr_ibf_ie);
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if IB_MREQ.din(csr_ibf_ie) = '1' then
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if r.done='1' and r.ie='0' then -- ie set while done=1
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n.intreq := '1'; -- request interrupt
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end if;
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else
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n.intreq := '0';
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end if;
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end if;
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else -- rri ---------------------
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idout(csr_ibf_ir) := r.intreq;
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if ibw1 = '1' then
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n.err := IB_MREQ.din(csr_ibf_err);
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if IB_MREQ.din(csr_ibf_err) = '1' then
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n.done := '1';
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n.intreq := '0'; -- clear irupt (like simh!)
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end if;
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end if;
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end if;
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when ibaddr_buf => -- BUF -- data buffer ----------------
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if IB_MREQ.racc = '0' then -- cpu ---------------------
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if ibw0 = '1' then
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if r.done = '1' then -- ignore buf write when done=0
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n.buf := IB_MREQ.din(n.buf'range);
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if r.err = '0' then -- if online (handle via rbus)
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ilam := '1'; -- request attention
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n.done := '0'; -- clear done
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n.intreq := '0'; -- clear interrupt
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else -- if offline (discard locally)
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n.done := '1'; -- set done
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if r.ie = '1' then -- if interrupts enabled
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n.intreq := '1'; -- request interrupt
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end if;
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end if; -- r.err = '0'
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end if; -- r.done = '1'
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end if; -- ibw0 = '1'
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else -- rri ---------------------
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idout(r.buf'range) := r.buf;
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idout(buf_ibf_val) := not r.done;
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idout(buf_ibf_val8) := not r.done;
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if ibrd = '1' then
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n.done := '1';
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if r.ie = '1' then
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n.intreq := '1';
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end if;
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end if;
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end if;
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when others => null;
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end case;
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end if;
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-- other state changes
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if EI_ACK = '1' then
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n.intreq := '0';
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end if;
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N_REGS <= n;
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IB_SRES.dout <= idout;
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IB_SRES.ack <= r.ibsel and ibreq;
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IB_SRES.busy <= '0';
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RB_LAM <= ilam;
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EI_REQ <= r.intreq;
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end process proc_next;
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end syn;
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