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125 lines
3.3 KiB
VHDL
125 lines
3.3 KiB
VHDL
-- $Id: debounce_gen.vhd 1181 2019-07-08 17:00:50Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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------------------------------------------------------------------------------
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-- Module Name: debounce_gen - syn
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-- Description: Generic signal debouncer
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--
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-- Dependencies: -
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-- Test bench: tb/tb_debounce_gen
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-- Target Devices: generic
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-- Tool versions: ise 8.2-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33
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-- Revision History:
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-- Date Rev Version Comment
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-- 2011-10-22 418 1.0.3 now numeric_std clean
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-- 2007-12-26 105 1.0.2 add default for RESET
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-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
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-- 2007-06-29 61 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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entity debounce_gen is -- debounce, generic vector
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generic (
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CWIDTH : positive := 2; -- clock interval counter width
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CEDIV : positive := 3; -- clock interval divider
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DWIDTH : positive := 8); -- data width
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port (
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CLK : in slbit; -- clock
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RESET : in slbit := '0'; -- reset
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CE_INT : in slbit; -- clock interval enable (usec or msec)
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DI : in slv(DWIDTH-1 downto 0); -- data in
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DO : out slv(DWIDTH-1 downto 0) -- data out
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);
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end entity debounce_gen;
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architecture syn of debounce_gen is
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constant cntzero : slv(CWIDTH-1 downto 0) := (others=>'0');
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constant datazero : slv(dWIDTH-1 downto 0) := (others=>'0');
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type regs_type is record
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cecnt : slv(CWIDTH-1 downto 0); -- clock interval counter
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dref : slv(DWIDTH-1 downto 0); -- data reference
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dchange : slv(DWIDTH-1 downto 0); -- data change flag
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dout : slv(DWIDTH-1 downto 0); -- data output
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end record regs_type;
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constant regs_init : regs_type := (
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cntzero,
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datazero,
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datazero,
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datazero
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);
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signal R_REGS : regs_type := regs_init; -- state registers
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signal N_REGS : regs_type := regs_init; -- next value state regs
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begin
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assert CEDIV<=2**CWIDTH report "assert(CEDIV<=2**CWIDTH)" severity failure;
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proc_regs: process (CLK)
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begin
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if rising_edge(CLK) then
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if RESET = '1' then
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R_REGS.cecnt <= cntzero;
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R_REGS.dref <= DI;
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R_REGS.dchange <= datazero;
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R_REGS.dout <= DI;
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else
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R_REGS <= N_REGS;
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end if;
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end if;
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end process proc_regs;
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proc_next: process (R_REGS, CE_INT, DI)
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variable r : regs_type := regs_init;
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variable n : regs_type := regs_init;
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begin
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r := R_REGS;
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n := R_REGS;
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for i in DI'range loop
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if DI(i) /= r.dref(i) then
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n.dchange(i) := '1';
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end if;
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end loop;
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if CE_INT = '1' then
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if unsigned(r.cecnt) = 0 then
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n.cecnt := slv(to_unsigned(CEDIV-1,CWIDTH));
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n.dref := DI;
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n.dchange := datazero;
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for i in DI'range loop
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if r.dchange(i) = '0' then
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n.dout(i) := r.dref(i);
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end if;
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end loop;
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else
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n.cecnt := slv(unsigned(r.cecnt) - 1);
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end if;
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end if;
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N_REGS <= n;
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DO <= r.dout;
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end process proc_next;
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end syn;
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