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142 lines
4.4 KiB
VHDL
142 lines
4.4 KiB
VHDL
-- $Id: tbd_tba_ttcombo.vhd 1181 2019-07-08 17:00:50Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2007-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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------------------------------------------------------------------------------
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-- Module Name: tbd_tba_ttcombo - syn
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-- Description: rbtba_aif wrapper for test target
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--
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-- Dependencies: rbd_tester
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-- rbd_bram
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-- rbd_rbmon
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-- rb_sres_or_4
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--
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-- Test bench: tb/tb_rlink_tba_ttcombo
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--
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-- Target Devices: generic
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--
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-- Synthesised (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2010-12-29 351 12.1 M53d xc3s1000-4 192 538 32 342 s 10.1
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-- 2010-12-23 347 12.1 M53d xc3s1000-4 78 204 32 133 s 8.1
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--
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-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.35
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2019-06-02 1159 4.0.1 use rbaddr_ constants
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-- 2014-09-13 593 4.0 use new rlink v4 iface and 4 bit STAT; new addr
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-- 2014-08-15 583 3.5 rb_mreq addr now 16 bit
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-- 2011-11-22 432 3.1.2 now numeric_std clean
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-- 2010-12-29 351 3.1.1 moved in from rbus/rbd_ttcombo; port to rbtba_aif
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-- 2010-12-26 349 3.1 add rbd_bram and rbd_rbmon
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-- 2010-12-23 347 3.0 rename rrirp_ttcombo->rbd_ttcombo; essentially a
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-- rewrite, use rbd_tester;
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-- ---------- old V2 and V1 history removed
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-- 2007-08-16 74 1.0 Initial version
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------------------------------------------------------------------------------
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--
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-- address layout:
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--
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-- rbd_rbmon ffe8/8 -- default
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-- rbd_tester ffe0/8 -- default
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-- rbd_bram fe00/2
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.rblib.all;
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use work.rbdlib.all;
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entity rbd_tba_ttcombo is -- rbtba_aif wrapper for test target
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-- implements rbtba_aif
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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RB_MREQ_aval : in slbit; -- rbus: request - aval
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RB_MREQ_re : in slbit; -- rbus: request - re
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RB_MREQ_we : in slbit; -- rbus: request - we
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RB_MREQ_initt : in slbit; -- rbus: request - init; avoid name coll
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RB_MREQ_addr : in slv16; -- rbus: request - addr
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RB_MREQ_din : in slv16; -- rbus: request - din
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RB_SRES_ack : out slbit; -- rbus: response - ack
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RB_SRES_busy : out slbit; -- rbus: response - busy
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RB_SRES_err : out slbit; -- rbus: response - err
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RB_SRES_dout : out slv16; -- rbus: response - dout
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RB_LAM : out slv16; -- rbus: look at me
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RB_STAT : out slv4 -- rbus: status flags
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);
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end entity rbd_tba_ttcombo;
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architecture syn of rbd_tba_ttcombo is
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signal RB_SRES_TEST : rb_sres_type := rb_sres_init;
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signal RB_SRES_BRAM : rb_sres_type := rb_sres_init;
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signal RB_SRES_MON : rb_sres_type := rb_sres_init;
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signal RB_MREQ : rb_mreq_type := rb_mreq_init;
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signal RB_SRES : rb_sres_type := rb_sres_init;
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begin
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RB_MREQ.aval <= RB_MREQ_aval;
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RB_MREQ.re <= RB_MREQ_re;
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RB_MREQ.we <= RB_MREQ_we;
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RB_MREQ.init <= RB_MREQ_initt;
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RB_MREQ.addr <= RB_MREQ_addr;
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RB_MREQ.din <= RB_MREQ_din;
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RB_SRES_ack <= RB_SRES.ack;
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RB_SRES_busy <= RB_SRES.busy;
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RB_SRES_err <= RB_SRES.err;
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RB_SRES_dout <= RB_SRES.dout;
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TEST: rbd_tester
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generic map (
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RB_ADDR => rbaddr_tester)
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port map (
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CLK => CLK,
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RESET => RESET,
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RB_MREQ => RB_MREQ,
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RB_SRES => RB_SRES_TEST,
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RB_LAM => RB_LAM,
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RB_STAT => RB_STAT
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);
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MON: rbd_rbmon
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generic map (
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RB_ADDR => rbaddr_rbmon,
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AWIDTH => 9)
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port map (
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CLK => CLK,
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RESET => RESET,
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RB_MREQ => RB_MREQ,
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RB_SRES => RB_SRES_MON,
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RB_SRES_SUM => RB_SRES
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);
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BRAM: rbd_bram
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generic map (
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RB_ADDR => x"fe00")
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port map (
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CLK => CLK,
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RESET => RESET,
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RB_MREQ => RB_MREQ,
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RB_SRES => RB_SRES_BRAM
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);
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RB_SRES_OR : rb_sres_or_4
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port map (
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RB_SRES_1 => RB_SRES_TEST,
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RB_SRES_2 => RB_SRES_BRAM,
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RB_SRES_3 => RB_SRES_MON,
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RB_SRES_4 => rb_sres_init,
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RB_SRES_OR => RB_SRES
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);
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end syn;
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