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80 lines
2.5 KiB
VHDL
80 lines
2.5 KiB
VHDL
-- $Id: serport_uart_rxtx.vhd 1181 2019-07-08 17:00:50Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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------------------------------------------------------------------------------
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-- Module Name: serport_uart_rxtx - syn
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-- Description: serial port UART - transmitter + receiver
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--
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-- Dependencies: serport_uart_rx
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-- serport_uart_tx
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-- Test bench: tb/tb_serport_uart_rxtx
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-- Target Devices: generic
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-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.2; ghdl 0.18-0.33
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-- Revision History:
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-- Date Rev Version Comment
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-- 2007-06-24 60 1.0 Initial version
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------------------------------------------------------------------------------
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-- NOTE: for test bench usage a copy of all serport_* entities, with _tb
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-- !!!! appended to the name, has been created in the /tb sub folder.
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-- !!!! Ensure to update the copy when this file is changed !!
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.serportlib.all;
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entity serport_uart_rxtx is -- serial port uart: rx+tx combo
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generic (
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CDWIDTH : positive := 13); -- clk divider width
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
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RXSD : in slbit; -- receive serial data (uart view)
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RXDATA : out slv8; -- receiver data out
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RXVAL : out slbit; -- receiver data valid
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RXERR : out slbit; -- receiver data error (frame error)
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RXACT : out slbit; -- receiver active
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TXSD : out slbit; -- transmit serial data (uart view)
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TXDATA : in slv8; -- transmit data in
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TXENA : in slbit; -- transmit data enable
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TXBUSY : out slbit -- transmit busy
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);
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end serport_uart_rxtx;
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architecture syn of serport_uart_rxtx is
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begin
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RX : serport_uart_rx
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generic map (
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CDWIDTH => CDWIDTH)
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port map (
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CLK => CLK,
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RESET => RESET,
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CLKDIV => CLKDIV,
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RXSD => RXSD,
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RXDATA => RXDATA,
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RXVAL => RXVAL,
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RXERR => RXERR,
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RXACT => RXACT
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);
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TX : serport_uart_tx
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generic map (
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CDWIDTH => CDWIDTH)
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port map (
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CLK => CLK,
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RESET => RESET,
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CLKDIV => CLKDIV,
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TXSD => TXSD,
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TXDATA => TXDATA,
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TXENA => TXENA,
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TXBUSY => TXBUSY
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);
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end syn;
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