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43 lines
1.0 KiB
VHDL
43 lines
1.0 KiB
VHDL
-- $Id: bufg_unisim.vhd 1247 2022-07-06 07:04:33Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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------------------------------------------------------------------------------
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-- Module Name: bufg_unisim - syn
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-- Description: Wrapper for BUFG entity
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--
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-- Dependencies: -
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-- Test bench: -
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-- Target Devices: generic Series-7
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-- Tool versions: viv 2022.1; ghdl 2.0.0
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2022-07-05 1247 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library unisim;
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use unisim.vcomponents.ALL;
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entity bufg_unisim is -- wrapper for BUFG
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port (
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O : out std_ulogic; -- input
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I : in std_ulogic -- output
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);
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end bufg_unisim;
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architecture syn of bufg_unisim is
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begin
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BUF : BUFG
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port map (
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O => O,
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I => I
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);
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end syn;
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