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46 lines
1.1 KiB
VHDL
46 lines
1.1 KiB
VHDL
-- $Id: gsr_pulse.vhd 1181 2019-07-08 17:00:50Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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------------------------------------------------------------------------------
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-- Module Name: gsr_pulse - sim
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-- Description: pulse GSR at startup
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--
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-- Dependencies: -
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-- Test bench: -
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-- Target Devices: generic
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-- Tool versions: viv 2016.2; ghdl 0.33
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-- Revision History:
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-- 2016-09-17 808 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library unisim;
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use unisim.vcomponents.ALL;
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entity gsr_pulse is -- pulse GSR at startup
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generic (
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GSR_WIDTH : Delay_length:= 100 ns); -- GSR pulse length
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end gsr_pulse;
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architecture sim of gsr_pulse is
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begin
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process
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begin
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-- Uses weak driver to prevent a driver clash when glbl.v is loaded too
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-- In case glbl.v is present it will overwrite (to be tested...)
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UNISIM.VCOMPONENTS.GSR <= 'H';
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wait for GSR_WIDTH;
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UNISIM.VCOMPONENTS.GSR <= 'L';
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wait;
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end process;
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end sim;
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