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139 lines
4.2 KiB
VHDL
139 lines
4.2 KiB
VHDL
-- $Id: s6_cmt_sfs_unisim.vhd 1181 2019-07-08 17:00:50Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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------------------------------------------------------------------------------
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-- Module Name: s6_cmt_sfs - syn
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-- Description: Spartan-6 CMT for simple frequency synthesis
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-- Direct instantiation of Xilinx UNISIM primitives
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--
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-- Dependencies: -
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-- Test bench: -
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-- Target Devices: generic Spartan-6
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-- Tool versions: xst 14.5-14.7; ghdl 0.29-0.31
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2013-10-05 537 1.0 Initial version (derived from s7_cmt_sfs)
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library unisim;
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use unisim.vcomponents.ALL;
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use work.slvtypes.all;
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entity s6_cmt_sfs is -- Spartan-6 CMT for simple freq. synth.
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generic (
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VCO_DIVIDE : positive := 1; -- vco clock divide
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VCO_MULTIPLY : positive := 1; -- vco clock multiply
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OUT_DIVIDE : positive := 1; -- output divide
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CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
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CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
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STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
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GEN_TYPE : string := "PLL"); -- PLL or DCM
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port (
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CLKIN : in slbit; -- clock input
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CLKFX : out slbit; -- clock output (synthesized freq.)
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LOCKED : out slbit -- pll/dcm locked
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);
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end s6_cmt_sfs;
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architecture syn of s6_cmt_sfs is
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begin
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assert GEN_TYPE = "PLL" or GEN_TYPE = "DCM"
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report "assert(GEN_TYPE='PLL' or GEN_TYPE='DCM')"
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severity failure;
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NOGEN: if VCO_DIVIDE=1 and VCO_MULTIPLY=1 and OUT_DIVIDE=1 generate
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CLKFX <= CLKIN;
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LOCKED <= '1';
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end generate NOGEN;
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USEPLL: if GEN_TYPE = "PLL" and
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not(VCO_DIVIDE=1 and VCO_MULTIPLY=1 and OUT_DIVIDE=1) generate
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signal CLKFBOUT : slbit;
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signal CLKOUT0 : slbit;
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signal CLKOUT1_UNUSED : slbit;
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signal CLKOUT2_UNUSED : slbit;
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signal CLKOUT3_UNUSED : slbit;
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signal CLKOUT4_UNUSED : slbit;
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signal CLKOUT5_UNUSED : slbit;
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begin
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PLL : pll_base
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generic map (
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BANDWIDTH => "OPTIMIZED",
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CLK_FEEDBACK => "CLKFBOUT",
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COMPENSATION => "INTERNAL",
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DIVCLK_DIVIDE => VCO_DIVIDE,
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CLKFBOUT_MULT => VCO_MULTIPLY,
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CLKFBOUT_PHASE => 0.000,
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CLKOUT0_DIVIDE => OUT_DIVIDE,
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CLKOUT0_PHASE => 0.000,
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CLKOUT0_DUTY_CYCLE => 0.500,
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CLKIN_PERIOD => CLKIN_PERIOD,
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REF_JITTER => CLKIN_JITTER)
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port map (
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CLKFBOUT => CLKFBOUT,
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CLKOUT0 => CLKOUT0,
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CLKOUT1 => CLKOUT1_UNUSED,
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CLKOUT2 => CLKOUT2_UNUSED,
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CLKOUT3 => CLKOUT3_UNUSED,
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CLKOUT4 => CLKOUT4_UNUSED,
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CLKOUT5 => CLKOUT5_UNUSED,
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CLKFBIN => CLKFBOUT,
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CLKIN => CLKIN,
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LOCKED => LOCKED,
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RST => '0'
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);
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BUFG_CLKOUT : bufg
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port map (
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I => CLKOUT0,
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O => CLKFX
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);
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end generate USEPLL;
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USEDCM: if GEN_TYPE = "DCM" and
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not(VCO_DIVIDE=1 and VCO_MULTIPLY=1 and OUT_DIVIDE=1) generate
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signal CLKOUT0 : slbit;
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begin
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DCM : dcm_sp
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generic map (
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CLK_FEEDBACK => "NONE",
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CLKFX_DIVIDE => VCO_DIVIDE,
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CLKFX_MULTIPLY => VCO_MULTIPLY,
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CLKIN_DIVIDE_BY_2 => false,
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CLKIN_PERIOD => CLKIN_PERIOD,
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CLKOUT_PHASE_SHIFT => "NONE",
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DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
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DSS_MODE => "NONE",
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STARTUP_WAIT => STARTUP_WAIT)
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port map (
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CLKIN => CLKIN,
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CLKFX => CLKOUT0,
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LOCKED => LOCKED
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);
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BUFG_CLKOUT : bufg
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port map (
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I => CLKOUT0,
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O => CLKFX
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);
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end generate USEDCM;
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end syn;
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