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1644863a58
- tools/asm-11/lib/defs_mmu.mac: rename md.a??, saner names for ACF - tcode/cpu_mmu.mac: add E1.1, test m0.trp, pdr aia/aiw transitions (verify fix) Closes #34 Closes #33 Closes #26 Closes #25
61 lines
2.8 KiB
Plaintext
61 lines
2.8 KiB
Plaintext
; $Id: defs_mmu.mac 1295 2022-09-07 16:28:55Z mueller $
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; SPDX-License-Identifier: GPL-3.0-or-later
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; Copyright 2015-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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;
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; definitions for mmu registers (as in defs_mmu.das)
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;
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mmr0 = 177572
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mmr1 = 177574
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mmr2 = 177576
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mmr3 = 172516
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;
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uipdr = 177600 ; usr i page dsc base
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udpdr = 177620 ; usr d page dsc base
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uipar = 177640 ; usr i page addr base
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udpar = 177660 ; usr d page addr base
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sipdr = 172200 ; sup i page dsc base
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sdpdr = 172220 ; sup d page dsc base
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sipar = 172240 ; sup i page addr base
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sdpar = 172260 ; sup d page addr base
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kipdr = 172300 ; ker i page dsc base
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kdpdr = 172320 ; ker d page dsc base
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kipar = 172340 ; ker i page addr base
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kdpar = 172360 ; ker d page addr base
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;
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; symbol definitions for mmr0
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;
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m0.anr = 100000 ; abort non-resident
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m0.ale = 040000 ; abort segment length
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m0.ard = 020000 ; abort read-only violation
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m0.trp = 010000 ; trap taken
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m0.ent = 001000 ; enable traps
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m0.mai = 000400 ; maintenance mode
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m0.ico = 000200 ; instruction complete flag
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m0.pmu = 000140 ; page mode user
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m0.pms = 000040 ; page mode supervisor
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m0.dsp = 000020 ; page d space
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m0.pno = 000002 ; page number field lsb
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m0.ena = 000001 ; enable mmu
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;
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; symbol definitions for mmr3
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;
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m3.eub = 000040 ; enable unibus map
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m3.e22 = 000020 ; enable 22bit addressing
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m3.dkm = 000004 ; enable d space kernel
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m3.dsm = 000002 ; enable d space supervisor
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m3.dum = 000001 ; enable d space user
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;
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; symbol definitions for pdr regs
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;
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md.plf = 000400 ; MSB of plf field
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md.aia = 000200 ; access a, any access
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md.aiw = 000100 ; access w, write access
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md.dwn = 000010 ; ed field 1, down expansion
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md.an7 = 000007 ; abort all; reserved
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md.arw = 000006 ; allow r+w; no traps
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md.art = 000005 ; allow r+w; trap w
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md.att = 000004 ; allow r+w; trap r+w
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md.an3 = 000003 ; abort all; reserved
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md.ara = 000002 ; allow r; abort w; no traps
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md.ata = 000001 ; allow r; abort w; trap r
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