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61 lines
1.8 KiB
VHDL
61 lines
1.8 KiB
VHDL
-- $Id: ib_sel.vhd 1181 2019-07-08 17:00:50Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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------------------------------------------------------------------------------
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-- Module Name: ib_sel - syn
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-- Description: ibus: address select logic
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--
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-- Dependencies: -
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-- Test bench: tb/tb_pdp11_core (implicit)
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-- Target Devices: generic
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-- Tool versions: ise 12.1-14.7; viv 2014.4; ghdl 0.29-0.31
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2010-10-23 335 1.0 Initial version (derived from rritb_sres_or_mon)
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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use work.iblib.all;
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-- ----------------------------------------------------------------------------
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entity ib_sel is -- ibus address select logic
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generic (
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IB_ADDR : slv16; -- ibus address base
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SAWIDTH : natural := 0); -- device subaddress space width
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port (
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CLK : in slbit; -- clock
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IB_MREQ : in ib_mreq_type; -- ibus request
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SEL : out slbit -- select state bit
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);
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end ib_sel;
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architecture syn of ib_sel is
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signal R_SEL : slbit := '0';
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begin
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assert SAWIDTH<=10 -- at most 1k words devices
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report "assert(SAWIDTH<=10)" severity failure;
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proc_regs: process (CLK)
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variable isel : slbit := '0';
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begin
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if rising_edge(CLK) then
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isel := '0';
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if IB_MREQ.aval='1' and
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IB_MREQ.addr(12 downto SAWIDTH+1)=IB_ADDR(12 downto SAWIDTH+1) then
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isel := '1';
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end if;
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R_SEL <= isel;
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end if;
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end process proc_regs;
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SEL <= R_SEL;
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end syn;
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