05c7d937c7
- general board support - c7_sram_memctl: SRAM memory controller (incl tb) - is61wv5128bll: simple memory model (incl tb) - sn_humanio_emu_rbus: human IO emulator - 92-retro-usb-persistent.rules: add more board rules - associated changes - sn_humanio_rbus: add stat_rbf_emu (=0); single cycle btn pulses - rgbdrv_analog(_rbus): add ACTLOW generic to invert output polarity - ti_rri: adopt Digilent autodetect for CmodA7 - add systems - tst_rlink: rlink tested - tst_sram: SRAM tester - w11a: w11a system with 672 kB memory (512 SRAM + 160 BRAM)
w11: PDP 11/70 CPU and SoC
Overview
The project contains the VHDL code for a complete DEC PDP-11 system: a PDP-11/70 CPU with memory management unit, but without floating point unit, a complete set of mass storage peripherals (RK11/RK05, RL11/RL02, RK70/RP06, TM11/TU10) and a basic set of UNIBUS peripherals (DL11, LP11, PC11), and last but not least a cache and memory controllers for SRAM and PSRAM. The design is FPGA proven, runs currently on Digilent Arty, Basys3, Nexys4, Nexys3, Nexys2 and S3board boards and boots 5th Edition UNIX and 2.11BSD UNIX.
For more information look into:
- w11 project home page and blog
- change log and installation notes
- guides to build bit files and test benches with Xilinx Vivado and Xilinx ISE
- guides to run test benches and to boot operating systems
- known issues general and w11a CPU
A short description of the directory layout is provided separately, the top level directories are
| Directory | Content |
|---|---|
| doc | documentation |
| rtl | HDL sources (mostly vhdl) |
| tools | many tools |
Note on freecores/w11
The freecores team created in 2014 a copy of almost all OpenCores cores in Github under freecores. This created freecores/w11 which is outdated and not maintained. Only wfjm/w11 is maintained.