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0c395856d7
- add fifo_simple_dram: simple fifo with CE/WE interface, dram based - add test benches for fifo_simple_dram, fifo_2c_dram, and fifo_2c_dram2 - add simclkv: test bench clock generator with variable period
25 lines
903 B
YAML
25 lines
903 B
YAML
# $Id: tbrun.yml 1099 2018-12-31 09:07:36Z mueller $
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#
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# Revision History:
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# Date Rev Version Comment
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# 2018-12-30 1099 1.0.1 add tst_mig, bplib/mig
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# 2016-08-27 802 1.0 Initial version
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#
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- include: rtl/vlib/memlib/tb/tbrun.yml
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- include: rtl/vlib/comlib/tb/tbrun.yml
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- include: rtl/vlib/serport/tb/tbrun.yml
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- include: rtl/vlib/rlink/tb/tbrun.yml
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- include: rtl/bplib/issi/tb/tbrun.yml
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- include: rtl/bplib/micron/tb/tbrun.yml
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- include: rtl/bplib/nxcramlib/tb/tbrun.yml
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- include: rtl/bplib/s3board/tb/tbrun.yml
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- include: rtl/bplib/cmoda7/tb/tbrun.yml
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- include: rtl/bplib/mig/tb/tbrun.yml
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- include: rtl/w11a/tb/tbrun.yml
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- include: rtl/sys_gen/tst_serloop/tbrun.yml
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- include: rtl/sys_gen/tst_rlink/tbrun.yml
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- include: rtl/sys_gen/tst_rlink_cuff/tbrun.yml
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- include: rtl/sys_gen/tst_mig/tbrun.yml
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- include: rtl/sys_gen/tst_sram/tbrun.yml
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- include: rtl/sys_gen/w11a/tbrun.yml
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