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563e230a6a
- rtl/bplib
- arty/migui_arty_gsim.vhd: cosmetics
- nexys4d/mig_a.prj: BUGFIX: SysResetPolarity ACTIVE HIGH; InputClk 100 MHz
- nexys4d/migui_nexys4d_gsim.vhd: cosmetics
- rtl/sys_gen
- tst_mig/nexys4d/sys_tst_mig_n4d: use 100 MHz MIG SYS_CLK; add clock monitor
- tst_sram/nexys4d/sys_tst_sram_n4d: use 100 MHz MIG SYS_CLK
- w11a/nexys4d/sys_w11a_n4d: use 100 MHz MIG SYS_CLK
- */nexys4*/tb/tbrun.yml: drop n4 from, add n4d to default
- tools/exptest/sys
- sys_w11a_arty_setup.tcl: add missing memsize definition
- sys_w11a_{br_arty,br_n4d,n4d}_setup.tcl: added
138 lines
5.5 KiB
VHDL
138 lines
5.5 KiB
VHDL
-- $Id: migui_arty_gsim.vhd 1201 2019-08-10 16:51:22Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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------------------------------------------------------------------------------
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-- Module Name: migui_arty - sim
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-- Description: MIG generated for arty - simple simulator
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--
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-- Dependencies: bplib/mig/migui_core_gsim
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-- Test bench: tb_tst_sram_arty
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-- Target Devices: arty board
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-- Tool versions: viv 2017.2; ghdl 0.34
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2018-12-25 1093 1.0 Initial version
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-- 2018-11-17 1071 0.1 First draft
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--
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.miglib.all;
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use work.miglib_arty.all;
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entity migui_arty is -- MIG generated for arty
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port (
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DDR3_DQ : inout slv16; -- dram: data in/out
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DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p)
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DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n)
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DDR3_ADDR : out slv14; -- dram: address
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DDR3_BA : out slv3; -- dram: bank address
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DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low)
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DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low)
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DDR3_WE_N : out slbit; -- dram: write enable (act.low)
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DDR3_RESET_N : out slbit; -- dram: reset (act.low)
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DDR3_CK_P : out slv1; -- dram: clock (diff-p)
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DDR3_CK_N : out slv1; -- dram: clock (diff-n)
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DDR3_CKE : out slv1; -- dram: clock enable
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DDR3_CS_N : out slv1; -- dram: chip select (act.low)
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DDR3_DM : out slv2; -- dram: data input mask
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DDR3_ODT : out slv1; -- dram: on-die termination
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APP_ADDR : in slv(mig_mawidth-1 downto 0); -- MIGUI address
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APP_CMD : in slv3; -- MIGUI command
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APP_EN : in slbit; -- MIGUI command enable
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APP_WDF_DATA : in slv(mig_dwidth-1 downto 0);-- MIGUI write data
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APP_WDF_END : in slbit; -- MIGUI write end
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APP_WDF_MASK : in slv(mig_mwidth-1 downto 0); -- MIGUI write mask
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APP_WDF_WREN : in slbit; -- MIGUI data write enable
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APP_RD_DATA : out slv(mig_dwidth-1 downto 0); -- MIGUI read data
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APP_RD_DATA_END : out slbit; -- MIGUI read end
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APP_RD_DATA_VALID : out slbit; -- MIGUI read valid
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APP_RDY : out slbit; -- MIGUI ready for cmd
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APP_WDF_RDY : out slbit; -- MIGUI ready for data write
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APP_SR_REQ : in slbit; -- MIGUI reserved (tie to 0)
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APP_REF_REQ : in slbit; -- MIGUI refresh request
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APP_ZQ_REQ : in slbit; -- MIGUI ZQ calibrate request
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APP_SR_ACTIVE : out slbit; -- MIGUI reserved (ignore)
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APP_REF_ACK : out slbit; -- MIGUI refresh acknowledge
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APP_ZQ_ACK : out slbit; -- MIGUI ZQ calibrate acknowledge
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UI_CLK : out slbit; -- MIGUI clock
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UI_CLK_SYNC_RST : out slbit; -- MIGUI reset
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INIT_CALIB_COMPLETE : out slbit; -- MIGUI inital calibration complete
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SYS_CLK_I : in slbit; -- MIGUI system clock
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CLK_REF_I : in slbit; -- MIGUI reference clock
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DEVICE_TEMP_I : in slv12; -- MIGUI xadc temperature
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SYS_RST : in slbit -- MIGUI system reset
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);
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end migui_arty;
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architecture sim of migui_arty is
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begin
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-- On Arty we have
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-- SYS_CLK_I 166.6 Mhz
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-- controller 333.3 MHz
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-- UI_CLK 83.3 MHz (4:1)
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-- therefore for simulation
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-- f_vco 1000 MHz
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-- --> mul 6 (f_vco/SYS_CLK)
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-- --> div 12 (f_vco/UI_CLK)
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MIG_SIM : migui_core_gsim
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generic map (
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BAWIDTH => mig_bawidth,
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MAWIDTH => mig_mawidth,
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SAWIDTH => 24,
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CLKMUI_MUL => 6,
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CLKMUI_DIV => 12)
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port map (
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SYS_CLK => SYS_CLK_I,
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SYS_RST => SYS_RST,
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UI_CLK => UI_CLK,
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UI_CLK_SYNC_RST => UI_CLK_SYNC_RST,
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INIT_CALIB_COMPLETE => INIT_CALIB_COMPLETE,
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APP_RDY => APP_RDY,
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APP_EN => APP_EN,
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APP_CMD => APP_CMD,
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APP_ADDR => APP_ADDR,
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APP_WDF_RDY => APP_WDF_RDY,
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APP_WDF_WREN => APP_WDF_WREN,
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APP_WDF_DATA => APP_WDF_DATA,
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APP_WDF_MASK => APP_WDF_MASK,
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APP_WDF_END => APP_WDF_END,
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APP_RD_DATA_VALID => APP_RD_DATA_VALID,
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APP_RD_DATA => APP_RD_DATA,
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APP_RD_DATA_END => APP_RD_DATA_END,
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APP_REF_REQ => APP_REF_REQ,
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APP_ZQ_REQ => APP_ZQ_REQ,
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APP_REF_ACK => APP_REF_ACK,
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APP_ZQ_ACK => APP_ZQ_ACK
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);
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DDR3_DQ <= (others=>'Z');
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DDR3_DQS_P <= (others=>'Z');
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DDR3_DQS_N <= (others=>'Z');
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DDR3_ADDR <= (others=>'0');
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DDR3_BA <= (others=>'0');
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DDR3_RAS_N <= '1';
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DDR3_CAS_N <= '1';
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DDR3_WE_N <= '1';
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DDR3_RESET_N <= '1';
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DDR3_CK_P <= (others=>'0');
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DDR3_CK_N <= (others=>'1');
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DDR3_CKE <= (others=>'0');
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DDR3_CS_N <= (others=>'1');
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DDR3_DM <= (others=>'0');
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DDR3_ODT <= (others=>'0');
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APP_SR_ACTIVE <= '0';
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end sim;
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