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cb7b906089
- sys_tst_sram_arty: add system and tb - sramif_mig_arty: add SRAM to DDR via MIG adapter for arty - cdc_pulse: add clock domain crossing for a slowly changing value - cdc_vector_s0: add ENA port (now used in cdc_pulse) - tst_mig/util.tcl: test_rwait: add optional lena argument - viv_tools_build.tcl: downgrade SSN critical warnings to warnings
14 lines
284 B
Plaintext
14 lines
284 B
Plaintext
# libs
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../../vlib/slvtypes.vhd
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../../vlib/cdclib/cdclib.vhd
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../mig/miglib.vbom
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miglib_arty.vbom
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# components
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../mig/sramif2migui_core.vbom
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../../vlib/cdclib/cdc_pulse.vbom
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../../vlib/cdclib/cdc_value.vbom
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@tcl:mig_arty.tcl
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[ghdl,vsim]migui_arty_gsim.vbom
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# design
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sramif_mig_arty.vhd
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