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wfjm.w11/rtl/sys_gen
Walter F.J. Mueller 0e96fa106b added preliminary and FPFA untested(!) support for nexys4 DDR board
- rtl/bplib/nexys4d: added board support
- rtl/sys_gen
  - tst_rlink/nexys4d: rlink tester design
  - tst_serloop/nexys4d: serial port tester design
  - tst_snhumanio/nexys4d: human IO tester design
  - w11a/nexys4d_bram: w11 design using BRAM only
2017-01-04 22:12:29 +01:00
..
2016-12-17 16:28:37 +01:00
2016-12-23 15:51:48 +01:00

This directory sub-tree contains HDL sources for top level designs and is organized in

Directory Content
tst_rlink rlink tester (over serial links)
tst_rlink_cuff rlink tester (over Cypress FX2 USB)
tst_serloop serial port loop back tester
tst_snhumanio Digilent board human IO tester
tst_sram memory tester (SRAM or CRAM)
w11a w11a systems