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16ce5b2091
- migrate to ibus protocol verion 2 - nexys2 systems now with DCM derived system clock supported - sys_w11a_n2 now runs with 58 MHz clksys
80 lines
2.7 KiB
VHDL
80 lines
2.7 KiB
VHDL
-- $Id: simclk.vhd 338 2010-11-13 22:19:25Z mueller $
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--
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-- Copyright 2007-2008 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: simclk - sim
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-- Description: Clock generator for test benches
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--
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-- Dependencies: -
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-- Test bench: -
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-- Target Devices: generic
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2008-03-24 129 1.0.2 CLK_CYCLE now 31 bits
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-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
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-- 2007-08-10 72 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use work.slvtypes.all;
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entity simclk is -- test bench clock generator
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generic (
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PERIOD : time := 20 ns; -- clock period
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OFFSET : time := 200 ns); -- clock offset (first up transition)
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port (
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CLK : out slbit; -- clock
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CLK_CYCLE : out slv31; -- clock cycle number
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CLK_STOP : in slbit -- clock stop trigger
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);
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end entity simclk;
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architecture sim of simclk is
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begin
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proc_clk: process
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constant clock_halfperiod : time := PERIOD/2;
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variable icycle : slv31 := (others=>'0');
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begin
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CLK <= '0';
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CLK_CYCLE <= (others=>'0');
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wait for OFFSET;
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clk_loop: loop
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CLK <= '1';
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wait for 0 ns; -- make a delta cycle so that clock
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icycle := unsigned(icycle) + 1; -- cycle number is updated after the
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CLK_CYCLE <= icycle; -- clock transition. all edge triggered
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-- proc's will thus read old value.
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wait for clock_halfperiod;
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CLK <= '0';
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wait for clock_halfperiod;
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exit clk_loop when CLK_STOP = '1';
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end loop;
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CLK <= '1'; -- final clock cycle for clk_sim
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wait for clock_halfperiod;
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CLK <= '0';
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wait for clock_halfperiod;
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wait; -- endless wait, simulator will stop
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end process proc_clk;
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end sim;
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