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120 lines
3.5 KiB
VHDL
120 lines
3.5 KiB
VHDL
-- $Id: cdc_pulse.vhd 1181 2019-07-08 17:00:50Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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------------------------------------------------------------------------------
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-- Module Name: cdc_pulse - syn
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-- Description: clock domain crossing for a pulse
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--
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-- Dependencies: -
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-- Test bench: -
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-- Target Devices: generic
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-- Tool versions: xst 13.1-14.7; viv 2015.4-2016.2; ghdl 0.29-0.33
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-- Revision History:
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-- Date Rev Version Comment
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-- 2016-06-11 774 1.2 add INIT generic
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-- 2016-03-29 756 1.1 rename regs; add ASYNC_REG attributes
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-- 2011-11-09 422 1.0 Initial version
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--
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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entity cdc_pulse is -- clock domain cross for pulse
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generic (
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POUT_SINGLE : boolean := false; -- if true: single cycle pout
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BUSY_WACK : boolean := false; -- if true: busy waits for ack
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INIT : slbit := '0'); -- initial state
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port (
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CLKM : in slbit; -- M|clock master
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RESET : in slbit := '0'; -- M|reset
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CLKS : in slbit; -- S|clock slave
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PIN : in slbit; -- M|pulse in
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BUSY : out slbit; -- M|busy
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POUT : out slbit -- S|pulse out
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);
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end entity cdc_pulse;
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architecture syn of cdc_pulse is
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signal RM_REQ : slbit := INIT; -- request active
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signal RS_REQ_S0 : slbit := INIT; -- request: CLKM->CLKS
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signal RS_REQ_S1 : slbit := INIT; -- request: CLKS->CLKS
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signal RM_ACK_S0 : slbit := '0'; -- acknowledge: CLKS->CLKM
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signal RM_ACK_S1 : slbit := '0'; -- acknowledge: CLKM->CLKM
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attribute ASYNC_REG: string;
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attribute ASYNC_REG of RS_REQ_S0 : signal is "true";
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attribute ASYNC_REG of RS_REQ_S1 : signal is "true";
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attribute ASYNC_REG of RM_ACK_S0 : signal is "true";
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attribute ASYNC_REG of RM_ACK_S1 : signal is "true";
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begin
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proc_master: process (CLKM)
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begin
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if rising_edge(CLKM) then
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if RESET = '1' then
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RM_REQ <= '0';
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else
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if PIN = '1' then
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RM_REQ <= '1';
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elsif RM_ACK_S1 = '1' then
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RM_REQ <= '0';
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end if;
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end if;
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RM_ACK_S0 <= RS_REQ_S1; -- synch 0: CLKS->CLKM
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RM_ACK_S1 <= RM_ACK_S0; -- synch 1: CLKM
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end if;
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end process proc_master;
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proc_slave: process (CLKS)
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begin
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if rising_edge(CLKS) then
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RS_REQ_S0 <= RM_REQ; -- synch 0: CLKM->CLKS
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RS_REQ_S1 <= RS_REQ_S0; -- synch 1: CLKS
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end if;
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end process proc_slave;
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-- Note: no pulse at startup when POUT_SINGLE=true, INIT=1 and PIN=1 initially
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SINGLE1: if POUT_SINGLE = true generate
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signal RS_ACK_1 : slbit := INIT;
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signal RS_POUT : slbit := '0';
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begin
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proc_pout: process (CLKS)
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begin
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if rising_edge(CLKS) then
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RS_ACK_1 <= RS_REQ_S1;
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if RS_REQ_S1='1' and RS_ACK_1='0' then
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RS_POUT <= '1';
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else
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RS_POUT <= '0';
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end if;
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end if;
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end process proc_pout;
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POUT <= RS_POUT;
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end generate SINGLE1;
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SINGLE0: if POUT_SINGLE = false generate
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begin
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POUT <= RS_REQ_S1;
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end generate SINGLE0;
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BUSY1: if BUSY_WACK = true generate
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begin
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BUSY <= RM_REQ or RM_ACK_S1;
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end generate BUSY1;
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BUSY0: if BUSY_WACK = false generate
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begin
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BUSY <= RM_REQ;
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end generate BUSY0;
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end syn;
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