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62 lines
1.6 KiB
VHDL
62 lines
1.6 KiB
VHDL
-- $Id: cdc_vector_s0.vhd 1181 2019-07-08 17:00:50Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2016-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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------------------------------------------------------------------------------
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-- Module Name: cdc_vector_s0 - syn
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-- Description: clock domain crossing for a vector, 1 stage
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--
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-- Dependencies: -
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-- Test bench: -
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-- Target Devices: generic
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-- Tool versions: viv 2015.4-2017.2; ghdl 0.33-0.34
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-- Revision History:
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-- Date Rev Version Comment
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-- 2019-01-02 1101 1.1 add ENA port
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-- 2016-04-08 459 1.0 Initial version
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--
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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entity cdc_vector_s0 is -- cdc for vector (1 stage)
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generic (
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DWIDTH : positive := 16); -- data port width
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port (
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CLKO : in slbit; -- O|output clock
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ENA : in slbit := '1'; -- O|capture enable
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DI : in slv(DWIDTH-1 downto 0); -- I|input data
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DO : out slv(DWIDTH-1 downto 0) -- O|output data
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);
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end entity cdc_vector_s0;
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architecture syn of cdc_vector_s0 is
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subtype d_range is integer range DWIDTH-1 downto 0;
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signal R_DO_S0 : slv(d_range) := (others=>'0');
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attribute ASYNC_REG: string;
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attribute ASYNC_REG of R_DO_S0 : signal is "true";
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begin
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proc_regs: process (CLKO)
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begin
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if rising_edge(CLKO) then
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if ENA = '1' then
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R_DO_S0 <= DI; -- synch 0: CLKI->CLKO
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end if;
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end if;
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end process proc_regs;
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DO <= R_DO_S0;
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end syn;
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