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39 lines
1.6 KiB
VHDL
39 lines
1.6 KiB
VHDL
-- $Id: simbus.vhd 1181 2019-07-08 17:00:50Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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------------------------------------------------------------------------------
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-- Package Name: simbus
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-- Description: Global signals for support control in test benches
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--
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-- Dependencies: -
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-- Tool versions: xst 8.2-14.7; viv 2016.2; ghdl 0.18-0.33
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-- Revision History:
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-- Date Rev Version Comment
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-- 2016-09-02 805 2.1 rename SB_CLKSTOP > SB_SIMSTOP; init with 'L'
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-- 2011-12-23 444 2.0 remove global clock cycle signal SB_CLKCYCLE
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-- 2010-04-24 282 1.1 add SB_(VAL|ADDR|DATA)
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-- 2008-03-24 129 1.0.1 use 31 bits for SB_CLKCYCLE
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-- 2007-08-27 76 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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package simbus is
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signal SB_SIMSTOP : slbit := 'L'; -- global simulation stop
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signal SB_CNTL : slv16 := (others=>'L'); -- global signals tb -> uut
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signal SB_STAT : slv16 := (others=>'0'); -- global signals uut -> tb
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signal SB_VAL : slbit := 'L'; -- init bcast valid
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signal SB_ADDR : slv8 := (others=>'L'); -- init bcast address
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signal SB_DATA : slv16 := (others=>'L'); -- init bcast data
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-- Note: SB_SIMSTOP, SB_CNTL, SB_VAL, SB_ADDR, SB_DATA can have weak
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-- ('L','H') and strong ('0','1') drivers. Therefore always remove
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-- strenght before using, e.g. with to_x01()
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end package simbus;
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